Digital signal demodulation method and system based on multi-sequence closed-loop estimation

Abstract

The invention provides a digital signal demodulation method and system based on multi-sequence closed-loop estimation, and the method comprises the steps: receiving an intermediate frequency (IF) signal, processing the IF signal through carrier recovery based on multi-sequence closed-loop estimation, and obtaining a coherent carrier; carrying out frequency mixing on the IF signal and the in-phase component and the orthogonal component of the coherent carrier, and carrying out low-pass filtering to obtain an I-path baseband signal and a Q-path baseband signal; processing the I-path baseband signal and the Q-path baseband signal by adopting timing recovery based on multi-sequence closed-loop estimation to obtain a signal peak moment, and performing baseband signal extraction on the signal peak moment to obtain baseband data after peak extraction; and carrying out symbol judgment and mapping on the baseband data subjected to peak value extraction to obtain a demodulation output signal.

Description

Technical Field

[0001] This invention relates to the field of signal estimation technology, and in particular to a digital signal demodulation method and system based on multi-sequence closed-loop estimation. Background Technology

[0002] In the field of communication, the Turbo Code, proposed 30 years ago, achieved decoding performance close to the Shannon theoretical limit for the first time, undoubtedly a significant theoretical breakthrough in recent years. However, in the field of modulation and demodulation, digital demodulation performance has always lagged behind the theoretical limit, especially in complex electromagnetic environments with high dynamics and low signal-to-noise ratios.

[0003] Therefore, it is necessary to propose a digital signal demodulation method that can achieve ultra-low loss and significantly improve the accuracy of digital demodulation. Summary of the Invention

[0004] This invention provides a digital signal demodulation method and system based on multi-sequence closed-loop estimation to address the deficiencies in the prior art.

[0005] In a first aspect, the present invention provides a digital signal demodulation method based on multi-sequence closed-loop estimation, comprising: The intermediate frequency (IF) signal is received, and carrier recovery based on multi-sequence closed-loop estimation is used to process the IF signal to obtain a coherent carrier. The IF signal is mixed with the in-phase and quadrature components of the coherent carrier, and after low-pass filtering, I-channel baseband signal and Q-channel baseband signal are obtained. The I-channel baseband signal and the Q-channel baseband signal are processed by timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time. Baseband signal extraction is performed on the signal peak time to obtain the baseband data after peak extraction. The baseband data after peak extraction is subjected to symbol decision and mapping to obtain the demodulated output signal.

[0006] According to the present invention, a digital signal demodulation method based on multi-sequence closed-loop estimation receives an intermediate frequency (IF) signal and processes the IF signal using carrier recovery based on multi-sequence closed-loop estimation to obtain a coherent carrier, comprising: Receive the IF signal, perform positive closed-loop estimation on the IF signal, and output the first output signal; Receive the first output signal, reverse sort the IF signal, perform reverse closed-loop estimation, and output the second output signal; The system receives the second output signal and the forward-ordered IF signal respectively, performs forward closed-loop estimation on the second output signal and the forward-ordered IF signal, and outputs the third output signal. The acquisition process of the second output signal and the third output signal is repeated multiple times, and the processing speed of the second output signal and the third output signal is greater than the processing speed of the first output signal.

[0007] According to the present invention, a digital signal demodulation method based on multi-sequence closed-loop estimation receives an IF signal, performs forward closed-loop estimation on the IF signal, and outputs a first output signal, comprising: The IF signal is passed through the first down-conversion module and the first low-pass and matched filter module group to obtain the first I-channel baseband signal and the first Q-channel baseband signal. The output signal obtained by closed-loop estimation of the first I-channel baseband signal and the first Q-channel baseband signal is used to obtain the first phase error by the first phase detector module. The first phase error is filtered out for interference and noise by the first loop filter to obtain the processed first phase error. The processed first phase error is processed by the first NCO module to obtain the first output signal. At the last moment of the forward closed-loop estimation, the integer delay 1 output result of the storage unit in the first loop filter and the integer delay 3 output result of the storage unit in the first NCO module are obtained. The cosine portion of the first output signal and the negative value of the sine portion of the first output signal are used for mixing the in-phase component and the quadrature component, respectively.

[0008] According to the present invention, a digital signal demodulation method based on multi-sequence closed-loop estimation receives a first output signal, reverse-sorts the IF signals, performs reverse closed-loop estimation, and outputs a second output signal, comprising: The IF signal is reverse sorted to obtain the reverse-order received signal. The reverse-order received signal is passed through the second down-conversion module and the second low-pass and matched filter module group to obtain the second I-channel baseband signal and the second Q-channel baseband signal. The output signal obtained by closed-loop estimation of the second I-channel baseband signal and the second Q-channel baseband signal is used by the second phase detector module to obtain the second phase error. The second phase error is processed sequentially through the second loop filter and the second NCO module to obtain the second output signal.

[0009] According to the present invention, a digital signal demodulation method based on multi-sequence closed-loop estimation receives a second output signal and a forward-ordered IF signal, performs forward closed-loop estimation on the second output signal and the forward-ordered IF signal, and outputs a third output signal, comprising: The second output signal and the forward sorted IF signal are passed through the third down-conversion module and the third low-pass and matched filter module group to obtain the third I-channel baseband signal and the third Q-channel baseband signal. The output signal obtained by closed-loop estimation of the third I-channel baseband signal and the third Q-channel baseband signal is processed by the third phase detector module to obtain the third phase error. The third phase error is processed sequentially through the third loop filter and the third NCO module to obtain the third output signal; Specifically, the accumulator in the second NCO module of the reverse closed-loop estimation performs a subtraction operation, while the accumulators in the first and third NCO modules of the forward closed-loop estimation perform an addition operation.

[0010] According to the present invention, a digital signal demodulation method based on multi-sequence closed-loop estimation is provided, which processes the I-channel baseband signal and the Q-channel baseband signal using timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time, and performs baseband signal decimation on the signal peak time to obtain baseband data after peak decimation, including: Receive the I-channel baseband signal and the Q-channel baseband signal, perform forward closed-loop estimation on the I-channel baseband signal and the Q-channel baseband signal, and output a fourth output signal; Receive the fourth output signal, reverse sort the I-path baseband signal and the Q-path baseband signal, perform reverse closed-loop estimation, and output the fifth output signal; The fifth output signal, as well as the forward-ordered I-path baseband signal and the Q-path baseband signal, are received respectively. A forward closed-loop estimation is performed on the fifth output signal and the forward-ordered I-path baseband signal and the Q-path baseband signal, and a sixth output signal is output. The acquisition process of the fifth and sixth output signals is repeated multiple times, and the processing speed of the fifth and sixth output signals is greater than that of the fourth output signal.

[0011] A digital signal demodulation method based on multi-sequence closed-loop estimation provided by the present invention receives the I-channel baseband signal and the Q-channel baseband signal, performs forward closed-loop estimation on the I-channel baseband signal and the Q-channel baseband signal, and outputs a fourth output signal, including: The I-channel baseband signal and the Q-channel baseband signal are passed through the first timing error detection module to obtain the fourth phase error; The fourth phase error is filtered out for interference and noise by the fourth loop filter in the error estimation module to obtain the processed fourth phase error. The processed fourth phase error is processed by the fourth NCO module to obtain the fourth output signal. At the last moment of the forward closed-loop estimation, the integer delay 1 output result of the storage unit in the fourth loop filter and the integer delay 3 output result of the storage unit in the fourth NCO module are obtained. The peak time output by the fourth NCO module corresponds to the time corresponding to the peak value of the baseband signal, and the transition value time output by the fourth NCO module corresponds to the time corresponding to the transition value between the two peak values ​​of the baseband signal. These are used to extract phase error and extract peak data for decision-making.

[0012] According to a digital signal demodulation method based on multi-sequence closed-loop estimation provided by the present invention, a fourth output signal is received, the I-channel baseband signal and the Q-channel baseband signal are reverse-ordered, and reverse closed-loop estimation is performed to output a fifth output signal, comprising: The I-channel baseband signal and the Q-channel baseband signal are arranged in reverse order to obtain the reversed I-channel baseband signal and Q-channel baseband signal; The reverse-ordered I-path baseband signal and Q-path baseband signal are passed through the second timing error detection module to obtain the fifth phase error; The fifth phase error is processed sequentially through the fifth loop filter and the fifth NCO module to obtain the fifth output signal.

[0013] According to a digital signal demodulation method based on multi-sequence closed-loop estimation provided by the present invention, the fifth output signal, as well as the forward-ordered I-channel baseband signal and the Q-channel baseband signal, are received respectively. Forward closed-loop estimation is performed on the fifth output signal and the forward-ordered I-channel baseband signal and the Q-channel baseband signal to output a sixth output signal, including: The fifth output signal, the forward-ordered I-path baseband signal, and the Q-path baseband signal are processed by the third timing error detection module to obtain the sixth phase error. The sixth phase error is passed sequentially through the sixth loop filter and the sixth NCO module to obtain the estimated results of the peak value and transition value of the baseband signal after adjustment based on the phase error, which are used as the sixth output signal; Specifically, the mod-1 operation in the fifth NCO module of the reverse closed-loop estimation is preceded by a subtraction operation, while the mod-1 operation in the fourth and sixth NCO modules of the forward closed-loop estimation is preceded by an addition operation.

[0014] Secondly, the present invention also provides a digital signal demodulation system based on multi-sequence closed-loop estimation, comprising: The first processing module is used to receive the intermediate frequency (IF) signal and process the IF signal using carrier recovery based on multi-sequence closed-loop estimation to obtain a coherent carrier. The second processing module is used to mix the IF signal with the in-phase component and quadrature component of the coherent carrier, and obtain the I-channel baseband signal and the Q-channel baseband signal after low-pass filtering. The third processing module is used to process the I-channel baseband signal and the Q-channel baseband signal using timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time, and to extract the baseband signal from the signal peak time to obtain the baseband data after peak extraction. The fourth processing module is used to perform symbol decision and mapping on the baseband data after peak extraction to obtain the demodulated output signal.

[0015] The digital signal demodulation method and system based on multi-sequence closed-loop estimation provided by this invention improves estimation performance, reduces demodulation loss, and enhances bit error rate demodulation performance by applying multi-sequence closed-loop estimation to carrier recovery and timing recovery in digital signal demodulation, thereby achieving ultra-low loss digital demodulation. In this invention, the carrier recovery and timing recovery in digital demodulation are changed from the existing closed-loop estimation structure to multi-sequence closed-loop estimation, which improves the estimation accuracy by about three orders of magnitude. Thus, for the first time in simulation, QPSK and GMSK demodulation reaching the theoretical limit of BER are achieved. Simulation of 16APSK carrier recovery shows that the estimation accuracy of the multi-sequence closed-loop estimation method is also improved by more than three orders of magnitude compared with the existing closed-loop estimation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the digital signal demodulation method based on multi-sequence closed-loop estimation provided by the present invention. Figure 2 This is a simulation structure diagram of the bit error rate (BER) of the forward closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention; Figure 3 This is a structural diagram of the demodulation module for forward closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention; Figure 4 This is a structural diagram of the down-convert module for forward closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention; Figure 5This is a structural diagram of the carrier recovery module for forward closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention; Figure 6 This is a diagram of the Costas ring carrier recovery structure for reverse closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention; Figure 7 This is a structural diagram of the carrier recovery module for reverse closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention; Figure 8 This is a diagram of the QPSK demodulation structure for timing recovery of the positive closed loop provided by the present invention. Figure 9 This is a structural diagram of the timing error detection (Gardner_TED) module for QPSK demodulation timing recovery positive closed loop provided by the present invention; Figure 10 This is a structural diagram of the error estimation (estimate_value) module for QPSK demodulation timing recovery of the positive closed loop provided by the present invention; Figure 11 This is a structural diagram of the Gardner symbol timing recovery module for QPSK demodulation timing recovery reverse closed loop provided by the present invention; Figure 12 This is a structural diagram of the error estimation module for QPSK demodulation timing recovery reverse closed loop provided by the present invention; Figure 13 This is a comparison chart of the BPSK demodulation estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention; Figure 14 This is a comparison chart of the QPSK demodulation estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention; Figure 15 This is a comparison chart of the MSK demodulation 2f+ estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention; Figure 16 This is a comparison chart of the MSK demodulation 2f-estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention; Figure 17 This is a comparison chart of the BPSK demodulation performance of multi-sequence closed-loop estimation digital demodulation provided by the present invention; Figure 18 This is a comparison chart of the QPSK demodulation performance of multi-sequence closed-loop estimation digital demodulation provided by the present invention; Figure 19 This is a comparison chart of the MSK demodulation performance of the multi-sequence closed-loop estimation digital demodulation provided by the present invention; Figure 20 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0019] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0020] To address the problems existing in the prior art, the technical problem to be solved by the present invention is: how to use a multi-sequence closed-loop estimation method to achieve carrier recovery and timing recovery in digital demodulation, thereby greatly improving the estimation performance and achieving ultra-low loss BER performance.

[0021] In this invention, for ease of explanation of the implementation scheme, the following embodiments are described using the intermediate frequency (IF) quadrature phase shift keying (QPSK) modulation method. Timing recovery can be performed using the Gardner algorithm, while carrier recovery uses the classical closed-loop estimation method. Simulation results of several modulation methods are also given.

[0022] Figure 1 This is a flowchart illustrating the digital signal demodulation method based on multi-sequence loop closure estimation provided in an embodiment of the present invention, as shown below. Figure 1 As shown, it includes: Step 100: Receive the intermediate frequency (IF) signal, and process the IF signal using carrier recovery based on multi-sequence closed-loop estimation to obtain a coherent carrier; Step 200: Mix the IF signal with the in-phase component and quadrature component of the coherent carrier, and obtain the I-channel baseband signal and Q-channel baseband signal after low-pass filtering; Step 300: The I-channel baseband signal and the Q-channel baseband signal are processed by timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time. Baseband signal extraction is performed on the signal peak time to obtain the baseband data after peak extraction. Step 400: Perform symbol decision and mapping on the baseband data after peak extraction to obtain the demodulated output signal.

[0023] Specifically, the embodiments of the present invention adopt the following technical solutions: The IF signal is received and mixed with the in-phase and quadrature components of the coherent carrier. After low-pass filtering, the I and Q baseband signals are obtained. The I and Q baseband signals are processed by a phase detector, a loop filter, and an NCO to obtain a coherent carrier output, which is the carrier estimation result of the received IF signal. The in-phase (cos) and quadrature (-sin) components of the coherent carrier are used for mixing. The closed-loop estimation here adopts a multi-sequence closed-loop estimation method. The peak times of the I and Q baseband signals are estimated through timing recovery, and then the baseband signals are extracted. The timing recovery also uses a multi-sequence closed-loop estimation method. After peak extraction, the baseband data undergoes symbol determination and mapping to obtain the demodulated output signal.

[0024] In one embodiment, step 100 includes: Receive the IF signal, perform positive closed-loop estimation on the IF signal, and output the first output signal; Receive the first output signal, reverse sort the IF signal, perform reverse closed-loop estimation, and output the second output signal; The system receives the second output signal and the forward-ordered IF signal respectively, performs forward closed-loop estimation on the second output signal and the forward-ordered IF signal, and outputs the third output signal. The acquisition process of the second output signal and the third output signal is repeated multiple times, and the processing speed of the second output signal and the third output signal is greater than the processing speed of the first output signal.

[0025] It is understandable that the coherent carrier required for mixing is obtained after multi-sequence closed-loop estimation based on carrier recovery, including: While performing positive closed-loop estimation, the received intermediate frequency (IF) signal is stored; The reverse closed-loop estimation is for received IF signals arranged in reverse order. The NCO module is slightly different from the forward closed-loop estimation, but the other parts are the same. The loop parameters of different closed-loop estimates are also different. By inheriting and combining the corresponding results of different closed-loop estimates, and performing multiple closed-loop estimates in the forward → reverse → forward → reverse → forward, the final estimation result is obtained.

[0026] The specific steps of the first positive loop closure estimation include: The system receives the IF input signal, performs down-conversion, low-pass filtering, and matched filtering (LPF&SRRC1, LPF&SRRC2) to obtain the I and Q baseband signals, and then obtains the phase error by the "phase detector" module based on the output signal estimated by the closed loop. The phase error is filtered out by a "loop filter" to remove interference noise, resulting in a more accurate phase error. The closed-loop estimated output signal is then obtained by passing it through the "NCO" module. The cosine output cos and the sine output -sin of the NCO are used to mix the in-phase and quadrature components, respectively.

[0027] Here, receiving the first output signal means recording the results of the loop filter and the storage units (Integer Delay1, Integer Delay3) in the NCO module at the last moment.

[0028] The specific steps of reverse loop closure estimation include: The received IF signal is reverse-ordered to obtain the reverse-ordered received signal revIF_data. After down-conversion, low-pass filtering, and matched filtering (LPF&SRRC1, LPF&SRRC2), the baseband signals of the I and Q channels (in-phase and quadrature channels) are obtained. The phase error is obtained by the phase detector module, and then the output result of the reverse closed-loop estimation is obtained by passing through the loop filter and NCO.

[0029] Because the NCO outputs the results in reverse order during the reverse loop estimation, its structure differs from that of the forward loop estimation. In the forward loop estimation, the accumulator of the NCO module performs addition, while in the reverse loop estimation, it performs subtraction.

[0030] The specific steps of the second positive loop closure estimation include: Based on the forward-ordered received signal and the NCO output, the phase error is obtained by the "phase detector" module after down-conversion, low-pass filtering, and matched filtering (LPF&SRRC1, LPF&SRRC2). After passing through the "loop filter" and "NCO", the estimated result adjusted according to the phase error is obtained and used as the output signal.

[0031] Furthermore, the acquisition of the second and third output signals is repeated N times, and the final output signal is the third output signal, which is the final estimated signal.

[0032] In this embodiment of the invention, the processing speed of the second and third output signals is greater than the processing speed of the first output signal, and the data reception rate is defined as... The number of data sequence points is The data processing rate of the second and third signals is improved. The total processing latency is approximately (1+ times). .

[0033] Figure 2 This invention presents a simulation structure diagram of the bit error rate (BER) for forward closed-loop estimation of QPSK demodulation carrier recovery. The BER simulation program consists of a signal source, modulation module, white Gaussian noise channel, demodulation module, parallel-to-serial conversion module, and BER calculation module. The signal source module generates pseudo-random data, the modulation module implements QPSK modulation, the white Gaussian noise channel is used to superimpose white noise, the demodulation module implements QPSK demodulation, and the parallel-to-serial conversion module is implemented using a selector. The I and Q channels output from the signal source are time-aligned with the I and Q channels output from the demodulation after integer delays, and both are sent to the BER calculation module after parallel-to-serial conversion, thus simulating the BER performance of the demodulation algorithm. The multi-sequence closed-loop estimation method in this invention is used for... Figure 2 In the demodulation module shown.

[0034] Figure 3 This is a structural diagram of the demodulation module for forward closed-loop estimation of QPSK demodulation carrier recovery provided by this invention. It mainly consists of a down-conversion module, a low-pass filter, carrier recovery, Gardner timing recovery, error estimation, and an intermediate frequency signal acquisition module. Specifically, the down-conversion module, low-pass filter, and carrier recovery form the Costas loop carrier recovery, used to obtain the coherent carrier required for demodulation; the Gardner timing recovery and error estimation constitute the Gardner symbol timing recovery loop, used to obtain the symbol clock required for sampling decision; the multi-sequence closed-loop estimation method in this invention is used in the loops of these two closed-loop structures.

[0035] Figure 4 This is a structural diagram of the down-convert module for forward closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention. The input intermediate frequency signal is multiplied by the cosine and -sin values ​​of the related carrier obtained by carrier recovery to obtain the I and Q signals.

[0036] Figure 5This diagram illustrates the carrier recovery module structure for forward closed-loop estimation of QPSK demodulation carrier recovery provided by this invention. The input intermediate frequency (IF) signal, after down-conversion and a low-pass filter, is sent to the carrier recovery module. There, it passes through a phase detector, loop filter, and NCO to obtain a coherent carrier. The diagram shows the structure for forward closed-loop estimation. The frequency and phase acquisition modules are used to obtain the frequency and phase for forward closed-loop estimation. The standard deviation acquisition module is used to obtain the standard deviation of the relative frequency offset, which measures the accuracy of the closed-loop estimation.

[0037] Figure 6 This is a diagram of the Costas ring carrier recovery structure for reverse closed-loop estimation of QPSK demodulation carrier recovery provided by the present invention. Figure 7 This is a structural diagram of the carrier recovery module for QPSK demodulation carrier recovery reverse closed-loop estimation provided by the present invention. Figure 6 In the code, `revIF_data` represents the reverse order of the received intermediate frequency (IF) signal data, and the `get_stdDev` module calculates the standard deviation of the relative deviation to represent the estimation performance. The main differences between reverse and forward closed-loop estimation are: different input data, slight differences in the NCO module, and different loop filter parameters.

[0038] Figure 6 The intermediate frequency signal in the middle frequency is reversed, and then down-converted, low-pass filtered and carrier recovered to obtain a reversed coherent carrier. Figure 7 The carrier recovery in the system also consists of a phase detector, a loop filter, and an NCO.

[0039] In one embodiment, step 300 includes: Receive the I-channel baseband signal and the Q-channel baseband signal, perform forward closed-loop estimation on the I-channel baseband signal and the Q-channel baseband signal, and output a fourth output signal; Receive the fourth output signal, reverse sort the I-path baseband signal and the Q-path baseband signal, perform reverse closed-loop estimation, and output the fifth output signal; The fifth output signal, as well as the forward-ordered I-path baseband signal and the Q-path baseband signal, are received respectively. A forward closed-loop estimation is performed on the fifth output signal and the forward-ordered I-path baseband signal and the Q-path baseband signal, and a sixth output signal is output. The acquisition process of the fifth and sixth output signals is repeated multiple times, and the processing speed of the fifth and sixth output signals is greater than that of the fourth output signal.

[0040] Understandably, timing recovery employs a multi-sequence closed-loop estimation method. During conventional (forward) closed-loop estimation, the received baseband I and Q signals are stored. Reverse closed-loop estimation targets the baseband I and Q signals arranged in reverse order. Gardner's timing recovery NCO (which differs from carrier recovery) differs slightly from the forward closed-loop estimation. The loop parameters also differ between different closed-loop estimations. By inheriting and combining the results of different closed-loop estimations, multiple closed-loop estimations are performed (forward → reverse → forward → reverse → forward…) to obtain the final estimation result. Similar to the conventional closed-loop estimation method, the timing error detection (TED) module differs for different modulation schemes.

[0041] The specific steps of the first positive loop closure estimation include: The system receives input I and Q baseband signals and obtains the phase error through the "Timing Error Detection" (Gardner TED) module. The phase error is filtered out by the loop filter in the "error estimation" (estimate_value) module to remove interference noise, resulting in a more accurate phase error. This is then passed through the "NCO" module to obtain the closed-loop estimation output signal. The peak time (Sym_clock) of the NCO output corresponds to the time corresponding to the peak value of the baseband signal, while the transition time (tran_clk) corresponds to the time corresponding to the transition value between the two peak values ​​of the baseband signal. These are used to extract the phase error and extract peak data for decision-making. To simplify the description of the Gardner timing recovery module for multi-sequence closed-loop estimation, a sampling rate of 16 times the symbol rate is selected here, thus omitting the "cubic interpolation" module.

[0042] Here, receiving the fourth output signal refers to recording the results of the loop filter and the storage units (Integer Delay1, Integer Delay3) in the NCO module at the last moment.

[0043] The specific steps of reverse loop closure estimation include: The received I and Q baseband signals are reverse-sorted to obtain the reverse-ordered I and Q baseband signals revI_base and revQ_base. The phase error is then obtained through the "Timing Error Detection" (Gardner TED) module, followed by a "Loop Filter" and "NCO" to obtain the output of the reverse closed-loop estimation. Because the NCO output in the reverse closed-loop estimation is a reverse-sorted result, its structure differs from that in the forward closed-loop estimation.

[0044] In forward loop closure estimation, the mod-1 operation in the NCO module is preceded by a subtraction operation, while in reverse loop closure estimation, the mod-1 operation is preceded by an addition operation.

[0045] The specific steps of the second positive loop closure estimation include: Based on the forward-ordered received I and Q baseband signals and the NCO output, the phase error is obtained through the "Timing Error Detection" (Gardner TED) module. After passing through the "Loop Filter" and "NCO", the estimated results of the peak and transition times of the baseband signal after adjustment according to the phase error are obtained as the output signal.

[0046] Furthermore, the acquisition of the fifth and sixth output signals is repeated N times, and the final output signal, the sixth output signal, is the final estimated signal.

[0047] In this embodiment of the invention, the processing speed of the fifth and sixth output signals is greater than the processing speed of the fourth output signal, and the data reception rate is defined as... The number of data sequence points is The data processing rate of the second and third signals is improved. The total processing latency is approximately (1+ times). .

[0048] Figure 8 This is a QPSK demodulation structure diagram of the positive closed loop of QPSK demodulation timing recovery provided by the present invention. It consists of Costas ring carrier recovery and Gardner timing recovery. The intermediate frequency signal from the working area is the previously stored data. The baseband signal acquisition module is used to store the I and Q path baseband signals. Figure 9 This is a structural diagram of the timing error detection (Gardner_TED) module for QPSK demodulation timing recovery in a positive closed loop provided by this invention. The I and Q inputs are fed by a peak clock to obtain the symbol values ​​of the current symbol period and the previous symbol period. The difference between these two values ​​is then multiplied by the transition value obtained from the transition time clock. Finally, the I and Q multiplication outputs are added together to obtain the timing error. After the I and Q peak symbols are sampled by the symbol clock, the corresponding decision result can be obtained. Figure 10 This is a structural diagram of the error estimation module for QPSK demodulation timing recovery positive closed loop provided by the present invention. It consists of a loop filter and an NCO. For the implementation principle of the NCO, please refer to the references of Gardner's timing recovery. The timing frequency difference and timing phase acquisition modules are used to obtain the frequency difference and phase estimation results.

[0049] Figure 11 This is a structural diagram of the Gardner symbol timing recovery module for QPSK demodulation timing recovery in reverse closed loop provided by the present invention. It consists of a Gardner timing recovery module and an error estimation module. revI_base and revQ_base are the reverse-order data of the I and Q baseband signals. The structure of the Gardner timing recovery module is similar to... Figure 3 same. Figure 12This is a structural diagram of the error estimation module for QPSK demodulation timing recovery reverse closed loop provided by the present invention. It is also composed of a loop filter and an NCO. The timing frequency difference and timing phase acquisition modules are used to obtain the frequency difference and phase estimation results.

[0050] Figure 11 In the diagram, IF_signal represents the received intermediate frequency signal, revI_base is the reverse order of the baseband signal I_base received by the get_base module, and revQ_base is the reverse order of the received baseband signal Q_base. The main differences between the reverse and forward closed-loop estimation are: different input data (reverse order), slight differences in the NCO module, and different loop filter parameters.

[0051] In one embodiment, step 400 includes: Symbol decision and mapping specifically include peak data extraction, symbol decision and mapping, which correspond to the corresponding modulation scheme. For example, in QPSK demodulation, the extracted I and Q peak data are subjected to symbol decision, with positive numbers being decided as +1 and negative numbers as -1. Then, +1 and -1 are mapped to 1 and 0 respectively, thus obtaining the demodulated output.

[0052] It should be noted that the carrier recovery and timing recovery structures for multi-sequence closed-loop estimation in other MSK and APSK modulation schemes are similar, and will not be elaborated further here.

[0053] The simulation results for different modulation methods are given below. Figure 13 This is a comparison chart of the BPSK demodulation estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention. Figure 14 This is a comparison chart of the QPSK demodulation estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention. Figure 15 This is a comparison chart of the MSK demodulation 2f+ estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention. Figure 16 This is a comparison chart of the MSK demodulation 2f-estimation performance of multi-sequence closed-loop estimation carrier recovery provided by the present invention. Figure 17 This is a comparison chart of the BPSK demodulation performance of multi-sequence closed-loop estimation digital demodulation provided by the present invention. Figure 18 This is a comparison chart of the QPSK demodulation performance of multi-sequence closed-loop estimation digital demodulation provided by the present invention. Figure 19 This is a comparison chart of the MSK demodulation performance of the multi-sequence closed-loop estimation digital demodulation provided by the present invention.

[0054] Figures 13 to 16 The optimal estimate is the multi-sequence closed-loop estimate, with the blue, green, and red curves corresponding to the existing closed-loop estimate, the 2-sequence closed-loop estimate, and the 3-sequence closed-loop estimate, respectively. Figures 13 to 16It is evident that the estimation performance of the 3-sequence loop closure estimation is improved by three orders of magnitude compared to existing loop closure estimation methods.

[0055] In the 16APSK carrier recovery simulation, the symbol rate fsymbol = 400MHz, the sampling rate fs = 1.6GSPS, the carrier frequency fc = 1.2GHz, the Doppler frequency shift fd = 1.2MHz, and the frequency shift rate is negligible. Eb / n0 = 5~6dB @ symbol rate 400MHz. 16APSK uses the QPD carrier recovery (DVB Blue Book) algorithm, Q = 3. Eb / n0 = 6~5dB, and the relative frequency offset standard performance improvement of conventional closed-loop estimation and (3-sequence) multi-sequence closed-loop estimation exceeds 3.6 orders of magnitude.

[0056] Figures 17 to 19 The best estimate is the multi-sequence closed-loop estimate. The green, blue, and red curves correspond to the existing closed-loop estimate, the multi-sequence closed-loop estimate (best estimate), and the theoretical limit BER performance, respectively.

[0057] To avoid fluctuations in BER results due to variations in pseudo-random seeds and simulation durations, ideal carrier and timing values ​​(i.e., setpoints) are selected in the simulation. Appropriate durations and seeds are chosen to ensure that the simulated BER results exactly match the theoretical BER values—this is achievable. BER performance simulations are then conducted and compared under the corresponding simulation duration and seed settings.

[0058] Depend on Figures 17 to 19 As can be seen, the BER demodulation performance is significantly improved, reaching the theoretical limit of BER. In particular, under the low signal-to-noise ratio condition of Eb / N0 < 6dB, the performance of MSK demodulation using the existing closed-loop estimation (which cannot work properly) deteriorates sharply, while the multi-sequence closed-loop estimation still reaches the theoretical performance of BER.

[0059] Figure 20 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 20As shown, the electronic device may include: a processor 2010, a communications interface 2020, a memory 2030, and a communication bus 2040, wherein the processor 2010, the communications interface 2020, and the memory 2030 communicate with each other through the communication bus 2040. The processor 2010 can call logic instructions in the memory 2030 to execute a digital signal demodulation method based on multi-sequence closed-loop estimation. This method includes: receiving an intermediate frequency (IF) signal; processing the IF signal using carrier recovery based on multi-sequence closed-loop estimation to obtain a coherent carrier; mixing the IF signal with the in-phase and quadrature components of the coherent carrier, and obtaining I-channel and Q-channel baseband signals after low-pass filtering; processing the I-channel and Q-channel baseband signals using timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time; decimating the baseband signal at the signal peak time to obtain peak-decimated baseband data; and performing symbol decision and mapping on the peak-decimated baseband data to obtain a demodulated output signal.

[0060] Furthermore, the logical instructions in the aforementioned memory 2030 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0061] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0062] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital signal demodulation method based on multi-sequence closed-loop estimation, characterized in that, include: The intermediate frequency (IF) signal is received, and carrier recovery based on multi-sequence closed-loop estimation is used to process the IF signal to obtain a coherent carrier. The IF signal is mixed with the in-phase and quadrature components of the coherent carrier, and after low-pass filtering, I-channel baseband signal and Q-channel baseband signal are obtained. The I-channel baseband signal and the Q-channel baseband signal are processed by timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time. Baseband signal extraction is performed on the signal peak time to obtain the baseband data after peak extraction. The baseband data after peak extraction is subjected to symbol decision and mapping to obtain the demodulated output signal.

2. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 1, characterized in that, The intermediate frequency (IF) signal is received, and carrier recovery based on multi-sequence closed-loop estimation is used to process the IF signal to obtain a coherent carrier, including: Receive the IF signal, perform positive closed-loop estimation on the IF signal, and output the first output signal; Receive the first output signal, reverse sort the IF signal, perform reverse closed-loop estimation, and output the second output signal; The system receives the second output signal and the forward-ordered IF signal respectively, performs forward closed-loop estimation on the second output signal and the forward-ordered IF signal, and outputs the third output signal. The acquisition process of the second output signal and the third output signal is repeated multiple times, and the processing speed of the second output signal and the third output signal is greater than the processing speed of the first output signal.

3. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 2, characterized in that, Receive an IF signal, perform forward closed-loop estimation on the IF signal, and output a first output signal, including: The IF signal is passed through the first down-conversion module and the first low-pass and matched filter module group to obtain the first I-channel baseband signal and the first Q-channel baseband signal. The output signal obtained by closed-loop estimation of the first I-channel baseband signal and the first Q-channel baseband signal is used to obtain the first phase error by the first phase detector module. The first phase error is filtered out for interference and noise by the first loop filter to obtain the processed first phase error. The processed first phase error is processed by the first NCO module to obtain the first output signal. At the last moment of the forward closed-loop estimation, the integer delay 1 output result of the storage unit in the first loop filter and the integer delay 3 output result of the storage unit in the first NCO module are obtained. The cosine portion of the first output signal and the negative value of the sine portion of the first output signal are used for mixing the in-phase component and the quadrature component, respectively.

4. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 3, characterized in that, Receive the first output signal, reverse-sort the IF signal, perform reverse closed-loop estimation, and output the second output signal, including: The IF signal is reverse sorted to obtain the reverse-order received signal. The reverse-order received signal is passed through the second down-conversion module and the second low-pass and matched filter module group to obtain the second I-channel baseband signal and the second Q-channel baseband signal. The output signal obtained by closed-loop estimation of the second I-channel baseband signal and the second Q-channel baseband signal is used by the second phase detector module to obtain the second phase error. The second phase error is processed sequentially through the second loop filter and the second NCO module to obtain the second output signal.

5. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 4, characterized in that, The system receives the second output signal and the forward-ordered IF signal, performs forward closed-loop estimation on the second output signal and the forward-ordered IF signal, and outputs a third output signal, including: The second output signal and the forward sorted IF signal are passed through the third down-conversion module and the third low-pass and matched filter module group to obtain the third I-channel baseband signal and the third Q-channel baseband signal. The output signal obtained by closed-loop estimation of the third I-channel baseband signal and the third Q-channel baseband signal is processed by the third phase detector module to obtain the third phase error. The third phase error is processed sequentially through the third loop filter and the third NCO module to obtain the third output signal; Specifically, the accumulator in the second NCO module of the reverse closed-loop estimation performs a subtraction operation, while the accumulators in the first and third NCO modules of the forward closed-loop estimation perform an addition operation.

6. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 1, characterized in that, Timing recovery based on multi-sequence closed-loop estimation is used to process the I-channel baseband signal and the Q-channel baseband signal to obtain the signal peak time. Baseband signal decimation is then performed on the signal peak time to obtain the baseband data after peak decimation, including: Receive the I-channel baseband signal and the Q-channel baseband signal, perform forward closed-loop estimation on the I-channel baseband signal and the Q-channel baseband signal, and output a fourth output signal; Receive the fourth output signal, reverse sort the I-path baseband signal and the Q-path baseband signal, perform reverse closed-loop estimation, and output the fifth output signal; The fifth output signal, as well as the forward-ordered I-path baseband signal and the Q-path baseband signal, are received respectively. A forward closed-loop estimation is performed on the fifth output signal and the forward-ordered I-path baseband signal and the Q-path baseband signal, and a sixth output signal is output. The acquisition process of the fifth and sixth output signals is repeated multiple times, and the processing speed of the fifth and sixth output signals is greater than that of the fourth output signal.

7. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 6, characterized in that, Receive the I-channel baseband signal and the Q-channel baseband signal, perform forward closed-loop estimation on the I-channel baseband signal and the Q-channel baseband signal, and output a fourth output signal, including: The I-channel baseband signal and the Q-channel baseband signal are passed through the first timing error detection module to obtain the fourth phase error; The fourth phase error is filtered out for interference and noise by the fourth loop filter in the error estimation module to obtain the processed fourth phase error. The processed fourth phase error is processed by the fourth NCO module to obtain the fourth output signal. At the last moment of the forward closed-loop estimation, the integer delay 1 output result of the storage unit in the fourth loop filter and the integer delay 3 output result of the storage unit in the fourth NCO module are obtained. The peak time output by the fourth NCO module corresponds to the time corresponding to the peak value of the baseband signal, and the transition value time output by the fourth NCO module corresponds to the time corresponding to the transition value between the two peak values ​​of the baseband signal. These are used to extract phase error and extract peak data for decision-making.

8. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 7, characterized in that, Receive the fourth output signal, reverse sort the I-channel baseband signal and the Q-channel baseband signal, perform reverse closed-loop estimation, and output the fifth output signal, including: The I-channel baseband signal and the Q-channel baseband signal are arranged in reverse order to obtain the reversed I-channel baseband signal and Q-channel baseband signal; The reverse-ordered I-path baseband signal and Q-path baseband signal are passed through the second timing error detection module to obtain the fifth phase error; The fifth phase error is processed sequentially through the fifth loop filter and the fifth NCO module to obtain the fifth output signal.

9. The digital signal demodulation method based on multi-sequence closed-loop estimation according to claim 8, characterized in that, The system receives the fifth output signal, as well as the forward-ordered I-path baseband signal and the Q-path baseband signal, respectively. It then performs a forward closed-loop estimation on the fifth output signal and the forward-ordered I-path and Q-path baseband signals, and outputs a sixth output signal, including: The fifth output signal, the forward-ordered I-path baseband signal, and the Q-path baseband signal are processed by the third timing error detection module to obtain the sixth phase error. The sixth phase error is passed sequentially through the sixth loop filter and the sixth NCO module to obtain the estimated results of the peak value and transition value of the baseband signal after adjustment based on the phase error, which are used as the sixth output signal; Specifically, the mod-1 operation in the fifth NCO module of the reverse closed-loop estimation is preceded by a subtraction operation, while the mod-1 operation in the fourth and sixth NCO modules of the forward closed-loop estimation is preceded by an addition operation.

10. A digital signal demodulation system based on multi-sequence closed-loop estimation, characterized in that, include: The first processing module is used to receive the intermediate frequency (IF) signal and process the IF signal using carrier recovery based on multi-sequence closed-loop estimation to obtain a coherent carrier. The second processing module is used to mix the IF signal with the in-phase component and quadrature component of the coherent carrier, and obtain the I-channel baseband signal and the Q-channel baseband signal after low-pass filtering. The third processing module is used to process the I-channel baseband signal and the Q-channel baseband signal using timing recovery based on multi-sequence closed-loop estimation to obtain the signal peak time, and to extract the baseband signal from the signal peak time to obtain the baseband data after peak extraction. The fourth processing module is used to perform symbol decision and mapping on the baseband data after peak extraction to obtain the demodulated output signal.

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