Semiconductor structure and method of manufacturing the same

Abstract

This application relates to a semiconductor structure and its fabrication method, comprising: an active region; a termination region circumferentially surrounding the active region; an extended junction within a substrate of the termination region, and a local field oxide layer and a polysilicon field plate on the substrate; the polysilicon field plate being located on the local field oxide layer and a portion of the top surface of the substrate near the active region; a metal layer including a source metal located on the active region, and conductive plugs with the same potential as the source metal, arranged circumferentially at intervals on the termination region; a dielectric layer being included between the metal layer and the polysilicon field plate, the active region, and the local field oxide layer; wherein, the substrate of the active region includes a well region of a first conductivity type extending in the direction toward the termination region to contact the extended junction; the conductive plugs extending in the direction toward the substrate to contact the well region. This improves the device's UIS capability without affecting the function of the gate field plate, the characteristics of the active region, and its reliability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of modern electronic technology, higher requirements are being placed on semiconductor materials, especially in fields such as high voltage, high frequency, high power, high temperature, and radiation resistance. Silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] Ultra-high voltage SiC power devices are mainly divided into two parts: cells and terminals. In the cell region, the cell structures are all the same, the mutual potentials are equal, and the breakdown voltage is relatively uniform. The terminal region can control and disperse the electric field and reduce electric field concentration by changing the geometry of the edge region of the power device or introducing specific doping profiles at the edge of the device to address the curvature effect of the chip's main junction.

[0004] When SiC is used as a switching device, it will experience frequent voltage and current surges during application. Under high dV / dt conditions, some areas of the device's terminal region will face extreme overcurrent and overvoltage conditions, which can easily lead to thermal failure and result in poor robustness of the end product. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the technical problems in the existing technology, so as to at least avoid thermal failure caused by extreme overcurrent and overvoltage conditions when SiC is used as a switching device, thereby improving the robustness of the end product.

[0006] In a first aspect, this application provides a semiconductor structure, comprising:

[0007] Active region;

[0008] The terminal region surrounds the active region circumferentially; the substrate of the terminal region includes an extended junction, and the substrate includes a local field oxide layer and a polysilicon field plate; the polysilicon field plate is located on the local field oxide layer and a portion of the top surface of the substrate near the active region.

[0009] The metal layer includes a source metal located on the active region and conductive plugs with the same potential as the source metal, which are arranged circumferentially on the terminal region; a dielectric layer is included between the metal layer and the polysilicon field plate, the active region and the local field oxide layer.

[0010] The active region includes a first conductivity type well region extending in the direction toward the terminal region to contact the extended junction; a conductive plug extends in the direction toward the substrate to contact the well region.

[0011] In some embodiments, the metal layer includes gate metal located on the termination region and spaced apart from the source metal;

[0012] The gate metal extends in the direction toward the substrate to contact the polysilicon field plate.

[0013] In some embodiments, a gate oxide layer is included between the polysilicon field plate and the substrate of the terminal region.

[0014] In some embodiments, the first spacing is less than or equal to the second spacing, and the second spacing is less than twice the first spacing;

[0015] The first spacing represents the distance between the conductive plug and the active region; the second spacing represents the distance between the conductive plug and the extended junction.

[0016] In some embodiments, the active region includes a plurality of trench transistors or planar gate transistors.

[0017] In some embodiments, the spacing between circumferentially adjacent conductive plugs is the same; and

[0018] The spacing between adjacent conductive plugs along the first direction and the second direction is the same;

[0019] Both the first and second directions are perpendicular to the circumference.

[0020] In some embodiments, the substrate of the active region and the terminal region is of a second conductivity type;

[0021] The conductivity type of the extended junction is opposite to that of the substrate, but the same as that of the well region.

[0022] Secondly, this application also provides a method for fabricating a semiconductor structure to form a semiconductor structure as described in any of the above embodiments. The method includes: providing a substrate; the substrate includes an active region and a terminal region circumferentially surrounding the active region;

[0023] A local field oxide layer and a polysilicon field plate are formed on the terminal region; the polysilicon field plate is located on the local field oxide layer and on a portion of the top surface of the substrate near the active region.

[0024] A dielectric layer and a metal layer are formed; the metal layer includes a source metal located on the active region and conductive plugs with the same potential as the source metal, which are arranged circumferentially on the terminal region; the dielectric layer is located between the metal layer and the polysilicon field plate, the active region and the local field oxide layer;

[0025] The substrate of the terminal region includes an extended junction; the substrate of the active region includes a first conductivity type well region extending in the direction toward the terminal region to contact the extended junction; and a conductive plug extending in the direction toward the substrate to contact the well region.

[0026] In some embodiments, the metal layer includes gate metal located on the termination region and spaced apart from the source metal;

[0027] The gate metal extends along the direction toward the substrate to contact the polysilicon field plate;

[0028] A gate oxide layer is included between the polycrystalline silicon field plate and the substrate of the terminal region.

[0029] In some embodiments, the first spacing is less than or equal to the second spacing, and the second spacing is less than twice the first spacing;

[0030] The first spacing represents the distance between the conductive plug and the active region; the second spacing represents the distance between the conductive plug and the extended junction.

[0031] The semiconductor structure and its fabrication method provided in this application have the following unexpected technical effects:

[0032] Compared to classic ultra-high voltage SiC power devices, conductive plugs are spaced and filled in the terminal region of the integrated polycrystalline silicon field plate and junction-extended semiconductor structure. Since the conductive plugs are electrically isolated from the polycrystalline silicon field plate through the dielectric layer, the conductive plugs are made to be at the same potential as the source metal without affecting the function of the polycrystalline silicon field plate, thus constructing a displacement current output path from the terminal region to the source.

[0033] Under extreme dynamic conditions such as high dV / dt, the displacement current generated in the terminal area can be quickly guided to the source metal through the conductive plug, significantly shortening the current path. By utilizing the generally superior heat dissipation capability of the active area, the heat concentration problem of the terminal structure can be alleviated, reducing the risk of thermal failure caused by overvoltage, overcurrent or high-speed switching, and enhancing the long-term reliability of the terminal product under extreme conditions.

[0034] Furthermore, by rationally designing the spacing and position of the conductive plugs (i.e., the first spacing ≤ the second spacing < twice the first spacing), effective heat dissipation and potential uniformity can be ensured while also taking into account device area efficiency, resulting in good process compatibility and scalability. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a classic high-voltage SiC power device in related technologies;

[0037] Figure 2This is a top view of a semiconductor structure provided in one embodiment of this application;

[0038] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in one embodiment of this application;

[0039] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of this application;

[0040] Figure 5 This is a flowchart of a semiconductor structure fabrication method provided in one embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the structure obtained after steps S20 to S40 in the preparation method provided in one embodiment;

[0042] Figure 7 This is a schematic diagram of the structure obtained after step S60 of the fabrication method provided in one embodiment forms the source contact hole, the inner equipotential hole and the gate contact hole;

[0043] Figure 8 for Figure 7 A schematic diagram of the structure obtained after the formation of the contact improvement layer and the metal layer;

[0044] Figure 9 for Figure 8 A schematic diagram of the structure obtained after removing part of the contact improvement layer and the metal layer.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1. Substrate; 10. Well region; 21. Extended junction; 22. Local field oxide layer; 23. Dielectric layer; 24. Polysilicon field plate; 25. Gate oxide layer; 26. Contact improvement layer; 30. Metal layer; 31. Source metal; 32. Conductive plug; 33. Gate metal; 41. Source contact hole; 42. Internal equipotential hole; 43. Gate contact hole. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0053] Figure 1 The demonstration showcased a high-voltage SiC power device with a termination region in related technologies. In this device, the displacement current generated in the termination region under high dV / dt conditions has a long path, requiring it to traverse the entire transition region before flowing out through the source metal. The active region cannot adequately absorb the heat generated by this displacement current, leading to high electric field spikes in the transition region and heat generation from the displacement current, ultimately causing the chip structure to break down and burn out. This also highlights the poor switching performance (UIS) and dynamic reverse bias (DRB) capabilities under unclamped inductive loads.

[0054] Based on this, please refer to the following: Figure 2 , Figure 2 This application provides an exemplary semiconductor structure, illustrated in a top view, including an active region and a terminal region circumferentially surrounding the active region. For ease of understanding, the substrate in this embodiment may include a first surface on the front side and a back surface, i.e., a second surface, opposite the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and directions toward the substrate include a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the Y-axis direction, the second direction as the X-axis direction, and the third direction as the Z-axis direction.

[0055] Figure 2 Multiple trench transistors or planar gate transistors can be formed within the active region. Figure 3 Figure 'a' shows a cross-sectional view of the semiconductor structure along line A-A' when the active region forms a planar gate transistor. Figure 3Figure b shows a cross-sectional view along line A-A' of the semiconductor structure obtained when the active region forms a trench gate transistor. When this application is used in other power devices such as IGBTs, the above-mentioned active region can be adjusted accordingly based on the device structure. For example, the source region can also be called the emitter region, and the source metal can also be called the emitter metal. In addition, it should be understood that the figures are not drawn to the actual scale of the device and are only for illustrative purposes.

[0056] In this embodiment, a planar gate transistor is formed in the active region, and the first conductivity type is defined as P-type and the second conductivity type as N-type. Further, P+ type represents heavily doped P-type, and P- type represents lightly doped P-type. The planar gate transistor mainly includes some core structures, such as an N+ type source region, a P-type base region, and a P+ type well region 10 formed by ion implantation in the epitaxial layer or substrate 1, and a gate located on the top surface. Specifically, in embodiments where substrate 1 includes a P-type substrate 1, the source region can be formed by implanting N-type ions; correspondingly, in embodiments where substrate 1 includes an N-type substrate 1, the source region can be formed by implanting P-type ions. Figure 4 In the diagram, 'a' shows a cross-sectional view of the semiconductor structure along line A-A'. Figure 4 In Figure 'b', a cross-sectional view of the semiconductor structure along line B-B' is shown. It should be understood that, except for... Figure 3 In addition, 'a' and 'b' in other views also correspond to the sectional views of the devices along lines A-A' and B-B' in the corresponding steps, respectively, which will not be elaborated on further.

[0057] Please combine Figure 2 , Figure 4 The active region edge design is the same. The well region 10 of the planar gate transistor near the terminal region extends towards the terminal region (i.e., the OY direction or OX direction) and contacts the extended junction 21 in the terminal region.

[0058] The termination region includes two types of termination designs: a polysilicon field plate 24 and an extended junction 21. Specifically, the polysilicon field plate 24 covers the top surface of the local field oxide layer 22 near the active region, and a gate oxide layer 25 is disposed between it and the substrate 1. Within the termination region, the well region 10 located between the gate oxide layer 25 and the extended junction 21 is referred to as the transition region. Compared to field-limited ring (FLR) termination, which has significant limitations on chip area reduction, the field plate-extended junction (JTE) termination can achieve the same stress resistance through optimized design, with a significantly reduced transition region size. Furthermore, the field plate-extended junction (JTE) termination has been repeatedly verified and has shown strong reliability. If the problem of UIS failure weak points being concentrated in the transition region can be solved, it will be beneficial for chip size reduction and improved economic efficiency.

[0059] In addition, the depth of the extended junction 21 is greater than the depth of the well region 10, which increases the radius of curvature of the terminal region and alleviates the electric field concentration.

[0060] Furthermore, a metal layer 30 is provided on the top surface of the active region and the terminal region for connecting the corresponding potentials. The metal layer 30 includes a source metal 31 located on the active region and conductive plugs 32 with the same potential as the source metal 31, which are arranged circumferentially (i.e., in the OY direction and OX direction) at intervals on the transition region.

[0061] In some embodiments, the metal layer 30 further includes gate metal 33 located on the termination region and spaced apart from the source metal 31. Specific structures are as follows: Figure 4 As shown, the source metal 31 is connected to the dummy source, and the gate metal 33 is used to apply voltage to the polycrystalline field plate while working together with the polycrystalline silicon field plate 24 to regulate the surface electric field distribution. Since the polycrystalline silicon field plate 24 is not cut off by the conductive plug 32, it can still maintain the same potential. The conductive plug 32 extends along the OZ direction to connect with the well region 10, which can extract the current flowing through the transition region in a timely manner without affecting the polycrystalline silicon field plate 24, shortening the displacement current output path of the transition region and the terminal region under high dV / dt conditions.

[0062] To further optimize the potential distribution and current extraction efficiency of the conductive plug 32, the position of the conductive plug 32 is further limited. In this embodiment, the first spacing is defined as D1 (i.e., the spacing between the conductive plug 32 and the active region), and the second spacing (i.e., the spacing between the conductive plug 32 and the extended junction 21) is defined as D2. When the conductive plug 32 is arranged closer to the extended junction 21, the extraction path of the displacement current in the terminal region can be significantly shortened, thereby improving the current extraction efficiency and heat dissipation capacity; however, this usually requires a wider area to be reserved between the extended junction 21 and the active region, resulting in an increase in the lateral dimension of the terminal region along the OX direction, which is not conducive to chip miniaturization and cost control. Therefore, this embodiment limits the spacing relationship by first spacing D1 < second spacing D2 ≤ 2 times the first spacing D1. While ensuring that the current extraction efficiency is close to optimal, the area expansion of the terminal region is effectively constrained, achieving a good balance between performance and size.

[0063] Furthermore, the conductive plugs 32 are spaced evenly along both the OX and OY directions, ensuring the uniformity of the semiconductor structure layout in the terminal region and avoiding localized electric field concentration. The cross-sectional shape of the conductive plugs 32 in the top view can be, but is not limited to, rectangular or circular. Their specific design can be flexibly chosen while meeting process compatibility and electrical performance requirements, and is not restricted here.

[0064] In some embodiments, to reduce the contact resistance during metal contact hole filling and enhance the interfacial adhesion between the contact hole sidewall and the metal layer 30, this solution adds a titanium / titanium nitride (Ti / TiN) composite layer as a contact improvement layer 26 above the dielectric layer 23 and between the metal layer 30 and the underlying structure (including the well region 10, the polysilicon field plate 24, the active region, and the local field oxide layer 22). This optimizes ohmic contact performance, reduces contact resistance, and reduces localized heat generation during current transmission. This further optimizes the conductivity and reliability of the current path from the transition region to the active region, and enhances the heat dissipation capability and mechanical stability of the terminal structure under extreme operating conditions.

[0065] The method for fabricating the above-mentioned semiconductor structure is described below. For some embodiments, please refer to... Figure 5 The method includes steps S20-S60.

[0066] Step S20: Provide substrate 1; substrate 1 includes an active region and a terminal region circumferentially surrounding the active region.

[0067] Step S40: A local field oxide layer 22 and a polysilicon field plate 24 are formed on the terminal region; the polysilicon field plate 24 is located on the local field oxide layer 22 and on a portion of the top surface of the substrate 1 near the active region.

[0068] Step S60: Forming a dielectric layer 23 and a metal layer 30; the metal layer 30 includes a source metal 31 located on the active region and conductive plugs 32 with the same potential as the source metal 31, arranged circumferentially on the terminal region; the dielectric layer 23 is located between the metal layer 30 and the polysilicon field plate 24, the active region and the local field oxide layer 22.

[0069] The substrate 1 of the terminal region includes an extended junction 21; the substrate 1 of the active region includes a first conductivity type well region 10 extending in the direction toward the terminal region to contact the extended junction 21; and a conductive plug 32 extending in the direction toward the substrate 1 to contact the well region 10.

[0070] It should be understood that, although Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0071] First, it should be noted that photolithography and etching may be involved in each of the following steps. For example, in step S20 or S40, a planar gate partially covering the top surface of the active region is formed, or in step S40, a polysilicon field plate 24 is formed on the top surface of the terminal region. Specifically, polysilicon material is deposited on the entire wafer, and then the polysilicon outside the predetermined position is removed by photolithography and etching. This type of operation is similar to the fabrication process of a planar gate MOSFET, and is a conventional process. Describing it in detail would be cumbersome, and those skilled in the art will know how to implement the process without any creative effort. Therefore, conventional processes will not be described in detail. The structure obtained after steps S20 to S40 is as follows... Figure 6 As shown, at this time, the semiconductor structure cross section obtained along line A-A' is the same as the semiconductor structure cross section along line B-B'.

[0072] Please see Figures 7-9 In the extended step of step S60, the following steps are included: performing photolithography and etching processes to form a source contact hole 41 located in the active region, and an inner equipotential hole 42 and a gate contact hole 43 located in the transition region, resulting in the structure shown below. Figure 7 As shown; using any deposition process, the contact improvement layer 26 and the metal layer 30 are formed sequentially, resulting in the structure shown. Figure 8 As shown.

[0073] Photoresist is recoated and patterned. Part of the metal layer 30 and contact improvement layer 26 on the side of the inner equipotential hole away from the active region are removed. At this point, the metal layer 30 within the source contact hole forms the source metal 31, the metal layer 30 within the inner equipotential hole forms the conductive plug 32, and the metal layer 30 within the gate contact hole forms the gate metal 33. The specific structure is as follows: Figure 9 As shown. Of course, before forming the contact improvement layer 26, the substrate 1 exposed by the contact hole can be further processed, but since this is not the point of invention of this application, it will not be discussed here.

[0074] For example, the material of the metal layer 30 includes, but is not limited to, conductive materials such as aluminum (Al), tungsten (W), or copper (Cu).

[0075] In the above embodiments, the unexpected technical effect of this application is:

[0076] Compared to field-limiting ring terminations, which are not conducive to chip area reduction and whose ring width / spacing is easily affected by process fluctuations, resulting in a narrow process window and hindering mass production control, this invention, based on the high reliability, process stability, and unaffected dynamic and static characteristic parameters of polysilicon field plate-extended junction (JTE) terminations, combines the polysilicon field plate-extended junction (JTE) termination design with the conductive plug design in the internal equipotential via. This solves the problem that the displacement current generated in the termination and transition region under high dV / dt conditions must cross the entire transition region to flow out through the source metal, effectively improving the device's UIS / DRB capability.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Active region; The terminal region surrounds the active region circumferentially; the substrate of the terminal region includes an extended junction, and the substrate includes a local field oxide layer and a polysilicon field plate; the polysilicon field plate is located on the local field oxide layer and a portion of the top surface of the substrate near the active region. The metal layer includes a source metal located on the active region and conductive plugs that have the same potential as the source metal and are arranged circumferentially at intervals on the terminal region. A dielectric layer is included between the metal layer and the polycrystalline silicon field plate, the active region and the local field oxide layer; The active region includes a first conductivity type well region extending in the direction toward the terminal region to contact the extended junction; the conductive plug extends in the direction toward the substrate to contact the well region.

2. The semiconductor structure according to claim 1, characterized in that, The metal layer includes a gate metal located on the terminal region and spaced apart from the source metal; The gate metal extends in a direction toward the substrate to contact the polycrystalline silicon field plate.

3. The semiconductor structure according to claim 2, characterized in that, A gate oxide layer is included between the polycrystalline silicon field plate and the substrate of the terminal region.

4. The semiconductor structure according to claim 1, characterized in that, The first spacing is less than or equal to the second spacing, and the second spacing is less than twice the first spacing; The first spacing represents the distance between the conductive plug and the active region; the second spacing represents the distance between the conductive plug and the extended junction.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The active region includes multiple trench transistors or planar gate transistors.

6. The semiconductor structure according to any one of claims 1-4, characterized in that, The spacing between adjacent conductive plugs along the circumferential direction is the same; and The spacing between adjacent conductive plugs along the first direction and the second direction is the same; Both the first direction and the second direction are perpendicular to the circumferential direction.

7. The semiconductor structure according to any one of claims 1-4, characterized in that, The substrates of the active region and the terminal region are of a second conductivity type; The conductivity type of the extended junction is opposite to that of the substrate, but the same as that of the well region.

8. A method for fabricating a semiconductor structure, characterized in that, A method for forming a semiconductor structure as described in any one of claims 1-6 includes: providing a substrate; the substrate including an active region and a terminal region circumferentially surrounding the active region; A local field oxide layer and a polysilicon field plate are formed on the terminal region; the polysilicon field plate is located on the local field oxide layer and on a portion of the top surface of the substrate near the active region. A dielectric layer and a metal layer are formed; the metal layer includes a source metal located on the active region and conductive plugs with the same potential as the source metal, arranged circumferentially on the terminal region; the dielectric layer is located between the metal layer and the polysilicon field plate, the active region and the local field oxide layer; The terminal region includes an extended junction within its substrate; the active region includes a first conductivity type well region extending toward the terminal region to contact the extended junction within its substrate; and the conductive plug extends toward the substrate to contact the well region.

9. The preparation method according to claim 8, characterized in that, The metal layer includes a gate metal located on the terminal region and spaced apart from the source metal; The gate metal extends in a direction toward the substrate to contact the polysilicon field plate; A gate oxide layer is included between the polycrystalline silicon field plate and the substrate of the terminal region.

10. The preparation method according to claim 9, characterized in that, The first spacing is less than or equal to the second spacing, and the second spacing is less than twice the first spacing; The first spacing is used to represent the spacing between the conductive plug and the active region; The second spacing represents the distance between the conductive plug and the extended junction.

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