SiC MOSFET device and manufacturing method

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method, and the device comprises at least two first grooves which are located in an N-type drift region; the at least two second grooves are respectively positioned at the bottoms of the first grooves; the P-type doped buried layer is located in the N-type drift region under the second groove; an N-type carrier storage region; the P well region is located in the N-type drift region between the two first trenches; the N + doped region is located in the P well region; the shield gate polycrystalline silicon is positioned on the gate oxide layer in the second groove; and the control gate polycrystalline silicon is positioned on the gate oxide layer close to the side walls and the bottoms of the P well region and the N + doped region in the first groove. Through the structure of the first groove and the second groove, the Schottky diode is introduced to the side wall of the groove, so that the area of a Schottky junction is large, the forward conduction voltage drop of the Schottky diode is reduced, the forward conduction current is improved, an electric field can be shielded below the groove structure through the P-type doped buried layer, and reverse electric leakage is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a SiC MOSFET device and its manufacturing method. Background Technology

[0002] Existing SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) devices typically rely on their internal parasitic PN junction as a body diode to achieve reverse freewheeling functionality. This parasitic body diode is essentially a SiC PIN diode structure. However, this structure has significant drawbacks: its forward voltage drop is relatively high, typically between 3V and 5V, leading to substantial conduction losses during reverse freewheeling and reducing system efficiency. Simultaneously, since SiC PIN diodes are bipolar devices, they need to extract non-equilibrium minority carriers accumulated in the drift region during turn-off, generating significant reverse recovery current and resulting in substantial reverse recovery losses. Furthermore, under prolonged on-state operation, the energy released by continuous electron-hole recombination in the PN junction region can induce the expansion of lattice defects, leading to bipolar degradation and reducing the reliability of the SiC MOSFET.

[0003] Current technologies commonly employ an independent SiC SBD (Silicon Carbide Schottky Barrier Diode) connected in anti-parallel to the SiC MOSFET as a freewheeling element. SiC SBDs are unipolar devices with a low on-state voltage drop of approximately 1V, significantly reducing freewheeling conduction losses. They exhibit no minority carrier storage effect, excellent reverse recovery characteristics, minimal recovery charge, and no bipolar degradation issues, resulting in high reliability. However, this approach requires additional packaging and bonding processes, increasing system cost. Furthermore, the bonding wires introduce significant parasitic inductance, limiting device performance in high-frequency switching scenarios and impacting overall efficiency. To address this, a MOSFET structure integrating a monolithic SiC SBD has been developed. By integrating the SBD on a single chip, external bonding wires are eliminated, parasitic inductance is reduced, and power density and switching speed are improved. However, currently integrated SBDs exhibit low forward conduction current and high reverse leakage current, severely affecting device performance. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a SiC MOSFET device and manufacturing method that overcome or at least partially solve the above problems.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows: In a first aspect, embodiments of the present invention provide a SiC MOSFET device, wherein the SiC MOSFET device comprises: N-type drift zone; At least two first trenches are located within the N-type drift region; At least two second trenches are located at the bottom of the corresponding first trenches; The P-type doped buried layer is located in the N-type drift region directly below the second trench and extends to the left and right sides; The N-type carrier storage region has a top surface that is flush with the top surface of the P-type doped buried layer, a bottom surface that is flush with the bottom surface of the P-type doped buried layer, and a side surface that is connected to the side surface of the P-type doped buried layer. The P-well region is located within the N-type drift region between the two first trenches, and the depth of the P-well region is less than the depth of the first trenches. The N+ doped region is located within the P-well region; A gate oxide layer is located on the sidewalls and bottom of the second trench, on the sidewalls and bottom of the first trench near the P-well region and the N+ doped region, and on a portion of the surface of the N+ doped region. The shielding gate polysilicon is located on the gate oxide layer within the second trench; The control gate polysilicon is located on the gate oxide layer within the first trench, near the sidewalls and bottom of the P-well region and the N+ doped region.

[0006] Optionally, the SiC MOSFET device further includes: An insulating passivation layer is located on the side and surface of the control gate polysilicon and on the gate oxide layer on a portion of the surface of the N+ doped region; The source metal is located on the surface of the N-type drift region, inside the first trench, on the surface of the shielding gate polysilicon, on the surface of the insulating passivation layer, and on a portion of the surface of the N+ doped region. The drain metal is located on the back side of the N-type drift region.

[0007] Optionally, the SiC MOSFET device further includes: The P-type implantation region is located within the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon, and the depth of the P-type implantation region is less than the depth of the first trench.

[0008] Optionally, the SiC MOSFET device further includes: The deep P-pillar is located in the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon, and the depth of the deep P-pillar is greater than the depth of the first trench.

[0009] Secondly, embodiments of the present invention provide a method for manufacturing a SiC MOSFET device, the method comprising: Provides N-type drift zones; Etching is performed within the N-type drift region to form at least two first trenches; Etching is performed at the bottom of the at least two first trenches to form at least two second trenches at the bottom of the first trenches that correspond one-to-one. P-type ions are injected directly below the second trench to form a P-type doped buried layer; the P-type doped buried layer extends to the left and right sides. N-type ions are injected into the N-type drift region to form an N-type carrier storage region; the top surface of the N-type carrier storage region is flush with the top surface of the P-type doped buried layer, the bottom surface is flush with the bottom surface of the P-type doped buried layer, and the side surface is connected to the side surface of the P-type doped buried layer. P-type ions are injected into the N-type drift region between the two first trenches to form a P-well region; the depth of the P-well region is less than the depth of the first trench. N-type ions are implanted into the P-well region to form an N+ doped region. Thermal oxidation is performed on the surface of the N-type drift region, the surface of the first trench, the surface of the second trench, a portion of the surface of the P-type doped buried layer, and the surface of the N+ doped region to form a gate oxide layer; Polysilicon is deposited on the gate oxide layer of the first trench and the second trench, and the polysilicon fills the first trench and the second trench; the polysilicon is etched, and the polysilicon in the second trench is retained to form a shielding gate polysilicon, and the polysilicon in the first trench near the P-well region and the N+ doped region is retained to form a control gate polysilicon. The gate oxide layer is etched, while retaining the gate oxide layers on the bottom and sides of the shielding gate polysilicon, the gate oxide layers on the bottom and sides of the control gate polysilicon, and the gate oxide layer on the surface of the N+ doped region.

[0010] Optionally, the manufacturing method further includes: An insulating passivation layer is formed on the surface of the gate oxide layer, the surface of the shielding gate polysilicon, and the surface of the control gate polysilicon; the insulating passivation layer is etched, while retaining the insulating passivation layer on the gate oxide layer of the control gate polysilicon side surface, surface, and part of the surface of the N+ doped region; Source metal is formed on the surface of the N-type drift region, inside the first trench, on the surface of the shielding gate polysilicon, on the surface of the insulating passivation layer, and on a portion of the surface of the N+ doped region. Drain metal is formed on the back side of the N-type drift region.

[0011] Optionally, the manufacturing method further includes: Thermal oxidation is performed on the surface of the N-type drift region, the surface of the first trench, the surface of the second trench, a portion of the surface of the P-type doped buried layer, and the surface of the N+ doped region to form a sacrificial oxide layer, and the sacrificial oxide layer is then removed.

[0012] Optionally, the manufacturing method further includes: P-type ions are implanted in the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon to form a P-type implantation region, the depth of which is less than the depth of the first trench.

[0013] Optionally, the manufacturing method further includes: P-type ions are implanted in the N-type drift region of the unetched trench connecting the first trench to the control gate polysilicon to form a deep P-pillar, the depth of which is greater than the depth of the first trench.

[0014] Optionally, the manufacturing method further includes: The P-type doped buried layer, the N-type carrier storage region, the P-well region, and the N+ doped region are activated at high temperature.

[0015] The SiC MOSFET device according to embodiments of the present invention includes: an N-type drift region; at least two first trenches located within the N-type drift region; at least two second trenches located at the bottom of corresponding first trenches; a P-type doped buried layer located within the N-type drift region directly below the second trenches and extending to the left and right sides; an N-type carrier storage region having a top surface flush with the top surface of the P-type doped buried layer, a bottom surface flush with the bottom surface of the P-type doped buried layer, and a side surface connected to the side surface of the P-type doped buried layer; a P-well region located within the N-type drift region between the two first trenches, the depth of the P-well region being less than the depth of the first trenches; an N+ doped region located within the P-well region; a gate oxide layer located on the sidewalls and bottom of the second trenches, on the sidewalls and bottom of the first trenches near the P-well region and the N+ doped region, and on a portion of the surface of the N+ doped region; a shielding gate polysilicon located on the gate oxide layer within the second trenches; and a control gate polysilicon located on the gate oxide layer within the first trenches near the sidewalls and bottom of the P-well region and the N+ doped region. By using the structure of the first and second trenches and introducing Schottky diodes on the sidewalls of the trenches, the area of ​​the Schottky junction is made larger, thereby reducing the forward voltage drop of the Schottky diodes and increasing the forward current. Furthermore, the electric field can be shielded below the trench structure by the P-type doped buried layer, thereby reducing reverse leakage current.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of a SiC MOSFET device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a SiC MOSFET device manufactured according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 4 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 5 This is a schematic diagram of another SiC MOSFET device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 7 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 8 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 9 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 10 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention; Figure 11 This is a schematic diagram of another SiC MOSFET device according to an embodiment of the present invention; Figure 12 This is a schematic diagram of another SiC MOSFET device according to an embodiment of the present invention; Figure 13 This is a flowchart illustrating the steps involved in manufacturing a SiC MOSFET device according to an embodiment of the present invention.

[0018] Reference numerals: N-type drift region 10, first trench 11, second trench 12, P-type doped buried layer 13, N-type carrier storage region 14, P-well region 15, N+ doped region 16, gate oxide layer 17, shielding gate polysilicon 18, control gate polysilicon 19, insulating passivation layer 20, source metal 21, drain metal 22, P-type implantation region 23, deep P-pillar 24. Detailed Implementation

[0019] Embodiments of the present invention will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0020] Existing SiC MOSFET devices typically rely on their internal parasitic PN junction as a body diode to achieve reverse freewheeling functionality. This parasitic body diode is essentially a SiC PIN diode structure. However, this structure has significant drawbacks: its forward voltage drop is relatively high, typically between 3V and 5V, leading to substantial conduction losses during reverse freewheeling and reducing system efficiency. Simultaneously, since SiC PIN diodes are bipolar devices, they require the extraction of non-equilibrium minority carriers accumulated in the drift region during turn-off, generating significant reverse recovery current and resulting in substantial reverse recovery losses. Furthermore, under prolonged on-state operation, the energy released by continuous electron-hole recombination in the PN junction region can induce the expansion of lattice defects, leading to bipolar degradation and reducing the reliability of the SiC MOSFET.

[0021] Current technologies commonly employ an independent SiC SBD connected in anti-parallel to the SiC MOSFET as a freewheeling element. SiC SBDs are unipolar devices with a low on-state voltage drop of approximately 1V, significantly reducing freewheeling conduction losses. They exhibit no minority carrier storage effect, excellent reverse recovery characteristics, minimal recovery charge, and no bipolar degradation issues, resulting in high reliability. However, this approach requires additional packaging and bonding processes, increasing system cost. Furthermore, the bonding wires introduce significant parasitic inductance, limiting device performance in high-frequency switching scenarios and impacting overall efficiency. To address this, a MOSFET structure integrating a monolithic SiC SBD has been developed. By integrating the SBD on a single chip, external bonding wires are eliminated, parasitic inductance is reduced, and power density and switching speed are improved. However, currently integrated SBDs exhibit low forward conduction current and high reverse leakage current, severely affecting device performance.

[0022] One of the core concepts of this invention is that by using the structure of the first trench and the second trench and introducing a Schottky diode on the sidewall of the trench, the area of ​​the Schottky junction is made larger, thereby reducing the forward conduction voltage drop of the Schottky diode and increasing the forward conduction current. Furthermore, the electric field can be shielded below the trench structure by the P-type doped buried layer, thereby reducing the reverse leakage current.

[0023] Reference Figure 1The diagram illustrates a structural schematic of a SiC MOSFET device according to an embodiment of the present invention. The SiC MOSFET device includes: N-type drift zone 10.

[0024] The N-type drift region 10 includes an N-type epitaxial layer and an N-type substrate layer.

[0025] At least two first grooves 11 are located within the N-type drift region 10.

[0026] Reference Figure 2 The first trench 11 is formed by etching within the N-type drift region 10.

[0027] At least two second grooves 12 are located at the bottom of the corresponding first grooves 11.

[0028] Reference Figure 3 The bottom of each first trench 11 is etched to form a second trench 12.

[0029] The P-type doped buried layer 13 is located in the N-type drift region 10 directly below the second trench 12 and extends to the left and right sides.

[0030] Reference Figure 4 P-type ions are injected at the bottom of the second trench 12 to form a P-type doped buried layer 13. The P-type doped buried layer 13 is located directly below the second trench 12 and extends to the left and right sides.

[0031] The N-type carrier storage region 14 has a top surface flush with the top surface of the P-type doped buried layer 13, a bottom surface flush with the bottom surface of the P-type doped buried layer 13, and a side surface connected to the side surface of the P-type doped buried layer 13.

[0032] The N-type carrier storage region 14 and the P-type doped buried layer 13 are located within the same lateral depth range, and the N-type carrier storage region 14 and the P-type doped buried layer 13 are alternately distributed. The doping concentration of the N-type carrier storage region 14 is greater than that of the N-type epitaxial layer, which can reduce the JFET region resistance formed between the P-type doped buried layers 13.

[0033] P-well region 15 is located within the N-type drift region 10 between the two first trenches 11, and the depth of P-well region 15 is less than the depth of the first trenches 11.

[0034] On the surface of the N-type drift region 10 of the unetched trench between the two first trenches 11, P-type ions are implanted inward to form a P-well region 15. The depth of the P-well region 15 is less than the depth of the first trench 11. The P-well region 15 is base region doped, and the channel is formed here.

[0035] N+ doped region 16 is located within P well region 15.

[0036] N-type ions are implanted into the P-well region 15 to form an N+ doped region 16, which provides electrons during forward conduction.

[0037] Gate oxide layer 17 is located on the sidewall and bottom of the second trench 12, the sidewall and bottom of the first trench 11 near the P-well region 15 and the N+ doped region 16, and a portion of the surface of the N+ doped region 16.

[0038] Thermal oxidation is performed on the sidewalls and bottom of the second trench 12, the sidewalls and bottom of the first trench 11 near the P-well region 15 and the N+ doped region 16, and a portion of the surface of the N+ doped region 16 to form a gate oxide layer 17. The gate oxide layer 17 is used to insulate and isolate the polysilicon and SiC, and forms a gate structure with the polysilicon.

[0039] The shielding gate polysilicon 18 is located on the gate oxide layer 16 within the second trench 12.

[0040] The shielding gate polysilicon 18 is located on the gate oxide layer 16 in the second trench 12, filling the internal space of the second trench 12. The shielding gate polysilicon 18 can be connected to the source metal to form a shielding gate.

[0041] The control gate polysilicon 19 is located on the gate oxide layer 16 within the first trench 11, near the sidewalls and bottom of the P-well region 15 and the N+ doped region 16.

[0042] The control gate polysilicon 19 is located on the gate oxide layer 16 near the sidewalls and bottom of the P-well region 15 and the N+ doped region 16 in the first trench 11. The control gate polysilicon 19 can be connected to the gate metal to form a control gate.

[0043] Through the first trench 11 and the second trench 12, this two-stage trench structure fabricates two gate structures: a shielding gate polysilicon 18 and a control gate polysilicon 19, formed by polysilicon with different electrodes. The shielding gate polysilicon 18 can be connected to the source metal to form a shielding gate, shielding part of the gate-drain capacitance and converting it into a gate-source capacitance. That is, this structure can increase the gate-source capacitance and decrease the gate-drain capacitance, reducing the ratio of input capacitance to feedback capacitance, improving the dv / dt handling capability during switching, improving the switching stability of the device, and improving its EMI capability. The control gate polysilicon 19 is connected to the source metal to form a control gate, and together with the P-well region 15 and the N+ doped region 16, forms the channel region of the MOS, controlling the turn-on and turn-off of the device.

[0044] The source metal can be connected to the shielding gate polysilicon 18 of the second trench 12 and the trench sidewalls, bottom, and unetched SiC surface of the first trench 11 away from the control gate polysilicon 19, wherein the portion connected to the trench sidewalls, bottom, and unetched SiC surface of the first trench 11 away from the control gate polysilicon 19 forms a Schottky barrier, thereby integrating the Schottky diode into the SiC MOSFET.

[0045] By implanting a P-type doped buried layer 13 connected to the bottom of the second trench 12, the electric field strength at the trench corner can be reduced when the SiC MOSFET is subjected to reverse breakdown voltage, thereby improving the reliability of the chip. The N-type carrier storage region 14, which is formed by implantation and alternately distributed with the P-type doped buried layer 13, has a higher doping concentration than the N-type epitaxial layer, which can reduce the resistance of the JFET region formed between the P-type doped buried layers 13.

[0046] The SiC MOSFET device according to embodiments of the present invention includes: an N-type drift region; at least two first trenches located within the N-type drift region; at least two second trenches located at the bottom of corresponding first trenches; a P-type doped buried layer located within the N-type drift region directly below the second trenches and extending to the left and right sides; an N-type carrier storage region having a top surface flush with the top surface of the P-type doped buried layer, a bottom surface flush with the bottom surface of the P-type doped buried layer, and a side surface connected to the side surface of the P-type doped buried layer; a P-well region located within the N-type drift region between the two first trenches, the depth of the P-well region being less than the depth of the first trenches; an N+ doped region located within the P-well region; a gate oxide layer located on the sidewalls and bottom of the second trenches, on the sidewalls and bottom of the first trenches near the P-well region and the N+ doped region, and on a portion of the surface of the N+ doped region; a shielding gate polysilicon located on the gate oxide layer within the second trenches; and a control gate polysilicon located on the gate oxide layer within the first trenches near the sidewalls and bottom of the P-well region and the N+ doped region. By using the structure of the first and second trenches and introducing Schottky diodes on the sidewalls of the trenches, the area of ​​the Schottky junction is made larger, thereby reducing the forward voltage drop of the Schottky diodes and increasing the forward current. Furthermore, the electric field can be shielded below the trench structure by the P-type doped buried layer, thereby reducing reverse leakage current.

[0047] Reference Figure 5 The diagram illustrates a structural schematic of another SiC MOSFET device according to an embodiment of the present invention. The SiC MOSFET device further includes: An insulating passivation layer 20 is located on the side and surface of the control gate polysilicon 19 and on the gate oxide layer 17 on a portion of the surface of the N+ doped region 16.

[0048] For example, refer to Figure 6 Thermal oxidation is performed on the surfaces of the N-type drift region 10, the first trench 11, the second trench 12, a portion of the surface of the P-type doped buried layer 13, and the surface of the N+ doped region 16 to form a gate oxide layer 17. (Refer to...) Figure 7 Polysilicon is deposited on the gate oxide layer 17 of the first trench 11 and the second trench 12, and the polysilicon fills the first trench 11 and the second trench 12. (Refer to...) Figure 8The polysilicon is etched, retaining the polysilicon within the second trench 12 to form the shielding gate polysilicon 18, and retaining the polysilicon within the first trench 11 near the P-well region 15 and the N+ doped region 16 to form the control gate polysilicon 19. (Refer to...) Figure 9 An insulating passivation layer 20 is formed on the surface of the gate oxide layer 17, the surface of the shielding gate polysilicon 18, and the surface of the control gate polysilicon 19. (Refer to...) Figure 10 The portion requiring connection to the source metal 21 is etched with an insulating passivation layer 20 and a gate oxide layer 17. The gate oxide layer 17 is etched, retaining the gate oxide layers 17 on the bottom and sides of the shielding gate polysilicon 18, the gate oxide layers 17 on the bottom and sides of the control gate polysilicon 19, and the gate oxide layer 17 on a portion of the surface of the N+ doped region 16. The insulating passivation layer 20 is etched, retaining the insulating passivation layer 20 on the gate oxide layers 17 on the sides, surface, and a portion of the surface of the N+ doped region 16 of the control gate polysilicon 19. The insulating passivation layer 20 can be a combination of an oxide layer and borosilicate glass (BPSG), serving as an insulating passivation layer.

[0049] The source metal 21 is located on the surface of the N-type drift region 10, inside the first trench 11, on the surface of the shielding gate polysilicon 18, on the surface of the insulating passivation layer 20, and on part of the surface of the N+ doped region 16.

[0050] The source metal 21 is formed by front-side sputtering and filling.

[0051] Drain metal 22 is located on the back side of the N-type drift region 10.

[0052] The back-side process is performed, and the back side of the N-type drift region 10 is thinned to a suitable thickness in sequence. The back-side drain metal is sputtered to form drain metal 22.

[0053] The source metal 22 can be connected to the shielding gate polysilicon 18 of the second trench 12 and the trench sidewalls, bottom, and unetched SiC surface of the first trench 11 away from the control gate polysilicon 19. The portion connected to the trench sidewalls, bottom, and unetched SiC surface of the first trench 11 away from the control gate polysilicon 19 forms a Schottky barrier, thereby integrating the Schottky diode into the SiC MOSFET. Furthermore, through the structure of the first trench 11 and the second trench 12, and by introducing the Schottky diode on the trench sidewall, the area of ​​the Schottky junction is made larger, thereby reducing the forward conduction voltage drop of the Schottky diode and increasing the forward conduction current.

[0054] Through the first trench 11 and the second trench 12, this two-stage trench structure fabricates two gate structures: a shielding gate polysilicon 18 and a control gate polysilicon 19, formed by polysilicon with different electrodes. The shielding gate polysilicon 18 can be connected to the source metal 22 to form a shielding gate, shielding part of the gate-drain capacitance and converting it into a gate-source capacitance. That is, this structure can increase the gate-source capacitance and decrease the gate-drain capacitance, reducing the ratio of input capacitance to feedback capacitance, improving the dv / dt handling capability during switching, improving the switching stability of the device, and improving its EMI capability. The control gate polysilicon 19 is connected to the source metal 22 to form a control gate, and together with the P-well region 15 and the N+ doped region 16, forms the channel region of the MOS, controlling the turn-on and turn-off of the device.

[0055] Reference Figure 11 The diagram illustrates a structural schematic of another SiC MOSFET device according to an embodiment of the present invention. The SiC MOSFET device further includes: The P-type implantation region 23 is located within the N-type drift region 10 of the unetched trench connecting the first trench 11 away from the control gate polysilicon 19, and the depth of the P-type implantation region 23 is less than the depth of the first trench.

[0056] On the surface of the N-type drift region 10 of the first trench 11 away from the control gate polysilicon 19, N-type ions are implanted inward to form a P-type implantation region 23. The P-type implantation region 23 and the N-type drift region 10 form a PIN diode. The PIN diode, together with the trench sidewall of the first trench 11 away from the control gate polysilicon 19 and the bottom Schottky diode directly connected to the source metal 21, form a JBS structure, thereby reducing its leakage current and improving its reverse withstand voltage capability.

[0057] Reference Figure 12 The diagram illustrates a structural schematic of another SiC MOSFET device according to an embodiment of the present invention. The SiC MOSFET device further includes: The deep P-pillar 24 is located in the N-type drift region 10 of the unetched trench connecting the first trench 11 away from the control gate polysilicon 19, and the depth of the deep P-pillar 24 is greater than the depth of the first trench.

[0058] On the surface of the N-type drift region 10 of the first trench 11 away from the unetched trench of the control gate polysilicon 19, N-type ions are injected inward, and the N-type carrier storage region 14 directly below it is removed, thereby forming a superjunction structure deep P-pillar 24. Alternatively, on the surface of the N-type drift region 10 of the first trench 11 away from the unetched trench of the control gate polysilicon 19, trenches are etched inward and filled with P-type ions, thereby forming a superjunction structure deep P-pillar 24. This can further ensure the device withstand voltage and reduce the on-resistance of the SiC MOSFET.

[0059] In this embodiment of the invention, a Schottky diode is introduced into the sidewall of a multi-level trench, and a shielding gate polysilicon 18 in contact with the source metal 21 is introduced in the second trench 12 to act as a capacitor shield, thereby reducing its gate leakage capacitance. This achieves optimized on-state voltage drop when the device is forward and reverse conducting without sacrificing forward withstand voltage. Furthermore, by introducing the shielding gate polysilicon 18 in the second trench 12 in contact with the source metal 21, capacitor shielding is provided, thereby reducing its gate leakage capacitance, reducing oscillations during switching, and improving its EMI characteristics.

[0060] Reference Figure 13 The diagram illustrates a flowchart of the manufacturing process of a SiC MOSFET device according to an embodiment of the present invention, which may specifically include the following steps: Step 101, provide the N-type drift zone.

[0061] Step 102: Etch within the N-type drift region to form at least two first trenches.

[0062] Step 103: Etch at the bottom of at least two first trenches to form at least two second trenches at the bottom of the corresponding first trenches.

[0063] Step 104: P-type ions are injected directly below the second trench to form a P-type doped buried layer; the P-type doped buried layer extends to the left and right sides.

[0064] Step 105: Inject N-type ions into the N-type drift region to form an N-type carrier storage region; the top surface of the N-type carrier storage region is flush with the top surface of the P-type doped buried layer, the bottom surface is flush with the bottom surface of the P-type doped buried layer, and the side surface is connected to the side surface of the P-type doped buried layer.

[0065] Step 106: P-type ions are injected into the N-type drift region between the two first trenches to form a P-well region; the depth of the P-well region is less than the depth of the first trench.

[0066] Step 107: Implant N-type ions into the P-well region to form an N+ doped region.

[0067] Step 108: Thermal oxidation is performed on the surface of the N-type drift region, the surface of the first trench, the surface of the second trench, a portion of the surface of the P-type doped buried layer, and the surface of the N+ doped region to form a gate oxide layer.

[0068] Step 109: Deposit polysilicon on the gate oxide layer of the first trench and the second trench, and fill the first trench and the second trench with polysilicon; etch the polysilicon, retain the polysilicon in the second trench to form the shielding gate polysilicon, and retain the polysilicon in the first trench near the P-well region and the N+ doped region to form the control gate polysilicon.

[0069] Step 110: Etch the gate oxide layer, retaining the gate oxide layers on the bottom and sides of the shielding gate polysilicon, the gate oxide layers on the bottom and sides of the control gate polysilicon, and the gate oxide layer on the surface of the N+ doped region.

[0070] For example, a first trench 11 is formed by etching within the N-type drift region 10; a second trench 12 is formed by etching at the bottom of each first trench 11; P-type ions are implanted at the bottom of the second trench 12 to form a P-type doped buried layer 13, which is located directly below the second trench 12 and extends to the left and right sides; N-type ions are implanted within the N-type drift region 10 to form an N-type carrier storage region 14, which is located at the same lateral depth as the P-type doped buried layer 13, and the N-type carrier storage region 14 and the P-type doped buried layer 13 are alternately distributed; P-type ions are implanted inward on the surface of the unetched trench of the N-type drift region 10 between the two first trenches 11 to form a P-well region 15, the depth of which is less than the depth of the first trench 11, and the P-well region 15 is base-doped, where the channel is formed; N-type ions are implanted within the P-well region 15. An N+ doped region 16 is formed, which provides electrons during forward conduction. Thermal oxidation is performed on the surface of the N-type drift region 10, the surface of the first trench 11, the surface of the second trench 12, a portion of the surface of the P-type doped buried layer 13, and the surface of the N+ doped region 16 to form a gate oxide layer 17. Polysilicon is deposited on the gate oxide layer 17 of the first trench 11 and the second trench 12, filling the first trench 11 and the second trench 12. The polysilicon is etched, retaining the polysilicon within the second trench 12 to form a shielding gate polysilicon 18, and retaining the polysilicon within the first trench 11 near the P-well region 15 and the N+ doped region 16 to form a control gate polysilicon 19. The gate oxide layer 17 is etched, retaining the gate oxide layers 17 at the bottom and sides of the shielding gate polysilicon 18, the gate oxide layers 17 at the bottom and sides of the control gate polysilicon 19, and the gate oxide layer 17 on a portion of the surface of the N+ doped region 16.

[0071] The SiC MOSFET device according to embodiments of the present invention includes: an N-type drift region; at least two first trenches located within the N-type drift region; at least two second trenches located at the bottom of corresponding first trenches; a P-type doped buried layer located within the N-type drift region directly below the second trenches and extending to the left and right sides; an N-type carrier storage region having a top surface flush with the top surface of the P-type doped buried layer, a bottom surface flush with the bottom surface of the P-type doped buried layer, and a side surface connected to the side surface of the P-type doped buried layer; a P-well region located within the N-type drift region between the two first trenches, the depth of the P-well region being less than the depth of the first trenches; an N+ doped region located within the P-well region; a gate oxide layer located on the sidewalls and bottom of the second trenches, on the sidewalls and bottom of the first trenches near the P-well region and the N+ doped region, and on a portion of the surface of the N+ doped region; a shielding gate polysilicon located on the gate oxide layer within the second trenches; and a control gate polysilicon located on the gate oxide layer within the first trenches near the sidewalls and bottom of the P-well region and the N+ doped region. By using the structure of the first and second trenches and introducing Schottky diodes on the sidewalls of the trenches, the area of ​​the Schottky junction is made larger, thereby reducing the forward voltage drop of the Schottky diodes and increasing the forward current. Furthermore, the electric field can be shielded below the trench structure by the P-type doped buried layer, thereby reducing reverse leakage current.

[0072] In this embodiment of the invention, the manufacturing method further includes: An insulating passivation layer is formed on the surface of the gate oxide layer, the surface of the shielding gate polysilicon, and the surface of the control gate polysilicon; the insulating passivation layer is etched, while retaining the insulating passivation layer on the gate oxide layer of the control gate polysilicon side surface, surface, and part of the surface of the N+ doped region; Source metal is formed on the surface of the N-type drift region, inside the first trench, on the surface of the shielding gate polysilicon, on the surface of the insulating passivation layer, and on a portion of the surface of the N+ doped region. Drain metal is formed on the back side of the N-type drift region.

[0073] For example, before etching the gate oxide layer 17, an insulating passivation layer 20 is formed on the surface of the gate oxide layer 17, the surface of the shielding gate polysilicon 18, and the surface of the control gate polysilicon 19; the insulating passivation layer 20 and the gate oxide layer 17 are etched on the portions that need to be connected to the source metal 21, the gate oxide layer 17 is etched, and the gate oxide layer 17 on the bottom and sides of the shielding gate polysilicon 18, the gate oxide layer 17 on the bottom and sides of the control gate polysilicon 19, and the gate oxide layer 17 on the surface of the N+ doped region 16 are retained; the insulating passivation layer 20 is etched. An insulating passivation layer 20 is retained on the gate oxide layer 17 on the side, surface, and part of the surface of the N+ doped region 16 of the control gate polysilicon 19; front-side source metal is sputtered and filled on the surface of the N-type drift region 10, inside the first trench 11, on the surface of the shielding gate polysilicon 18, on the surface of the insulating passivation layer 20, and on part of the surface of the N+ doped region 16 to form source metal 21; back-side processing is performed on the back side of the N-type drift region 10, and the back side of the N-type drift region 10 is sequentially thinned to a suitable thickness, and back-side drain metal is sputtered to form drain metal 22.

[0074] In this embodiment of the invention, the manufacturing method further includes: Thermal oxidation is performed on the surface of the N-type drift region, the surface of the first trench, the surface of the second trench, a portion of the surface of the P-type doped buried layer, and the surface of the N+ doped region to form a sacrificial oxide layer, and the sacrificial oxide layer is then removed.

[0075] In this embodiment of the invention, the manufacturing method further includes: P-type ions are implanted in the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon to form a P-type implantation region, the depth of which is less than the depth of the first trench.

[0076] The P-type injection region 23 and the N-type drift region 10 form a PIN diode. The PIN diode, together with the trench sidewall of the first trench 11 directly connected to the source metal 21 away from the control gate polysilicon 19 and the bottom Schottky diode, form a JBS structure, thereby reducing its leakage current and improving its reverse withstand voltage capability.

[0077] In this embodiment of the invention, the manufacturing method further includes: P-type ions are implanted in the N-type drift region of the unetched trench connecting the first trench to the control gate polysilicon to form a deep P-pillar, the depth of which is greater than the depth of the first trench.

[0078] The superjunction structure with deep P-pillars 24 further ensures the device's withstand voltage and reduces the on-resistance of the SiC MOSFET.

[0079] In this embodiment of the invention, the manufacturing method further includes: The P-type doped buried layer, the N-type carrier storage region, the P-well region, and the N+ doped region are activated at high temperature.

[0080] The manufacturing method embodiments of the present invention correspond to the structural embodiments, and will not be described in detail here.

[0081] The SiC MOSFET device according to embodiments of the present invention includes: an N-type drift region; at least two first trenches located within the N-type drift region; at least two second trenches located at the bottom of corresponding first trenches; a P-type doped buried layer located within the N-type drift region directly below the second trenches and extending to the left and right sides; an N-type carrier storage region having a top surface flush with the top surface of the P-type doped buried layer, a bottom surface flush with the bottom surface of the P-type doped buried layer, and a side surface connected to the side surface of the P-type doped buried layer; a P-well region located within the N-type drift region between the two first trenches, the depth of the P-well region being less than the depth of the first trenches; an N+ doped region located within the P-well region; a gate oxide layer located on the sidewalls and bottom of the second trenches, on the sidewalls and bottom of the first trenches near the P-well region and the N+ doped region, and on a portion of the surface of the N+ doped region; a shielding gate polysilicon located on the gate oxide layer within the second trenches; and a control gate polysilicon located on the gate oxide layer within the first trenches near the sidewalls and bottom of the P-well region and the N+ doped region. By using the structure of the first and second trenches and introducing Schottky diodes on the sidewalls of the trenches, the area of ​​the Schottky junction is made larger, thereby reducing the forward voltage drop of the Schottky diodes and increasing the forward current. Furthermore, the electric field can be shielded below the trench structure by the P-type doped buried layer, thereby reducing reverse leakage current.

[0082] In this embodiment of the invention, a Schottky diode is introduced into the sidewall of a multi-level trench, and a shielding gate polysilicon 18 in contact with the source metal 21 is introduced in the second trench 12 to act as a capacitor shield, thereby reducing its gate leakage capacitance. This achieves optimized on-state voltage drop when the device is forward and reverse conducting without sacrificing forward withstand voltage. Furthermore, by introducing the shielding gate polysilicon 18 in the second trench 12 in contact with the source metal 21, capacitor shielding is provided, thereby reducing its gate leakage capacitance, reducing oscillations during switching, and improving its EMI characteristics.

[0083] The terms "first" and "second" in the specification and claims of this invention may explicitly or implicitly include one or more of those features. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0084] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0085] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0086] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0087] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A SiC MOSFET device, characterized in that, The SiC MOSFET device includes: N-type drift zone; At least two first trenches are located within the N-type drift region; At least two second trenches are located at the bottom of the corresponding first trenches; The P-type doped buried layer is located in the N-type drift region directly below the second trench and extends to the left and right sides; The N-type carrier storage region has a top surface that is flush with the top surface of the P-type doped buried layer, a bottom surface that is flush with the bottom surface of the P-type doped buried layer, and a side surface that is connected to the side surface of the P-type doped buried layer. The P-well region is located within the N-type drift region between the two first trenches, and the depth of the P-well region is less than the depth of the first trenches. The N+ doped region is located within the P-well region; A gate oxide layer is located on the sidewalls and bottom of the second trench, on the sidewalls and bottom of the first trench near the P-well region and the N+ doped region, and on a portion of the surface of the N+ doped region. The shielding gate polysilicon is located on the gate oxide layer within the second trench; The control gate polysilicon is located on the gate oxide layer within the first trench, near the sidewalls and bottom of the P-well region and the N+ doped region.

2. The SiC MOSFET device according to claim 1, characterized in that, The SiC MOSFET device also includes: An insulating passivation layer is located on the side and surface of the control gate polysilicon and on the gate oxide layer on a portion of the surface of the N+ doped region; The source metal is located on the surface of the N-type drift region, inside the first trench, on the surface of the shielding gate polysilicon, on the surface of the insulating passivation layer, and on a portion of the surface of the N+ doped region. The drain metal is located on the back side of the N-type drift region.

3. The SiC MOSFET device according to claim 1, characterized in that, The SiC MOSFET device also includes: The P-type implantation region is located within the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon, and the depth of the P-type implantation region is less than the depth of the first trench.

4. The SiC MOSFET device according to claim 1, characterized in that, The SiC MOSFET device also includes: The deep P-pillar is located in the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon, and the depth of the deep P-pillar is greater than the depth of the first trench.

5. A method for manufacturing a SiC MOSFET device, characterized in that, The manufacturing method includes: Provides N-type drift zones; Etching is performed within the N-type drift region to form at least two first trenches; Etching is performed at the bottom of the at least two first trenches to form at least two second trenches at the bottom of the first trenches that correspond one-to-one. P-type ions are injected directly below the second trench to form a P-type doped buried layer; the P-type doped buried layer extends to the left and right sides. N-type ions are injected into the N-type drift region to form an N-type carrier storage region; the top surface of the N-type carrier storage region is flush with the top surface of the P-type doped buried layer, the bottom surface is flush with the bottom surface of the P-type doped buried layer, and the side surface is connected to the side surface of the P-type doped buried layer. P-type ions are injected into the N-type drift region between the two first trenches to form a P-well region; the depth of the P-well region is less than the depth of the first trench. N-type ions are implanted into the P-well region to form an N+ doped region. Thermal oxidation is performed on the surface of the N-type drift region, the surface of the first trench, the surface of the second trench, a portion of the surface of the P-type doped buried layer, and the surface of the N+ doped region to form a gate oxide layer; Polysilicon is deposited on the gate oxide layer of the first trench and the second trench, and the polysilicon fills the first trench and the second trench; the polysilicon is etched, and the polysilicon in the second trench is retained to form a shielding gate polysilicon, and the polysilicon in the first trench near the P-well region and the N+ doped region is retained to form a control gate polysilicon. The gate oxide layer is etched, while retaining the gate oxide layers on the bottom and sides of the shielding gate polysilicon, the gate oxide layers on the bottom and sides of the control gate polysilicon, and the gate oxide layer on the surface of the N+ doped region.

6. The method for manufacturing a SiC MOSFET device according to claim 5, characterized in that, The manufacturing method further includes: An insulating passivation layer is formed on the surface of the gate oxide layer, the surface of the shielding gate polysilicon, and the surface of the control gate polysilicon; the insulating passivation layer is etched, while retaining the insulating passivation layer on the gate oxide layer of the control gate polysilicon side surface, surface, and part of the surface of the N+ doped region; Source metal is formed on the surface of the N-type drift region, inside the first trench, on the surface of the shielding gate polysilicon, on the surface of the insulating passivation layer, and on a portion of the surface of the N+ doped region. Drain metal is formed on the back side of the N-type drift region.

7. The method for manufacturing a SiC MOSFET device according to claim 5, characterized in that, The manufacturing method further includes: Thermal oxidation is performed on the surface of the N-type drift region, the surface of the first trench, the surface of the second trench, a portion of the surface of the P-type doped buried layer, and the surface of the N+ doped region to form a sacrificial oxide layer, and the sacrificial oxide layer is then removed.

8. The method for manufacturing a SiC MOSFET device according to claim 5, characterized in that, The manufacturing method further includes: P-type ions are implanted in the N-type drift region of the unetched trench connecting the first trench away from the control gate polysilicon to form a P-type implantation region, the depth of which is less than the depth of the first trench.

9. The method for manufacturing a SiC MOSFET device according to claim 5, characterized in that, The manufacturing method further includes: P-type ions are implanted in the N-type drift region of the unetched trench connecting the first trench to the control gate polysilicon to form a deep P-pillar, the depth of which is greater than the depth of the first trench.

10. The method for manufacturing a SiC MOSFET device according to claim 5, characterized in that, The manufacturing method further includes: The P-type doped buried layer, the N-type carrier storage region, the P-well region, and the N+ doped region are activated at high temperature.

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