Current type micro-display device pixel point and drive circuit design thereof

Abstract

The invention discloses a current type micro-display device pixel point and a driving circuit design thereof, and provides a corresponding driving method at the same time. The pixel point circuit comprises four metal-oxide-semiconductor field effect transistors (MOSFETs), a storage capacitor and a light emitting diode load; the four MOSFETs are regulated and controlled by two driving signals, one pixel enable signal and one data input signal, and functions of the four MOSFETs are realized by combining a driving circuit and a driving method. According to the line scanning driving circuit disclosed by the invention, the scanning input signal, the enabling input signal, the line control input signal, the line scanning clock and the frame cutting clock are combined to obtain the driving signal and the pixel enabling signal required by a pixel point circuit, and the power consumption of a current type micro display device is reduced. According to the driving method disclosed by the invention, the pixel point circuit has three working stages in a frame of light emitting period, and the threshold voltage is extracted and stored in the capacitor, so that the current stability of the pixel point circuit in the light emitting stage is improved, and normal light emitting of the micro-display device is realized.

Description

Technical Field

[0001] This invention discloses a pixel design for a current-driven microdisplay device and its driving circuit, and proposes a corresponding driving method. Background Technology

[0002] Microdisplay technology is a novel display technology that integrates optics, microelectronics, and image processing. Compared to traditional flat panel displays, it features smaller size and higher resolution. Active-emitting microdisplays combine display devices with a CMOS (Complementary Metal-Oxide-Semiconductor) driving backplane, resulting in smaller size and faster response times compared to light-modulated microdisplays, making them more suitable for future microdisplay development. Based on whether the input data signal is current or voltage, active-emitting microdisplays can be divided into current-driven and voltage-driven types, both of which enable the operation of the microdisplay device.

[0003] However, as the resolution requirements of microdisplays increase, it is necessary to use smaller transistors to build smaller pixel circuits. Smaller transistors generally have lower voltage ratings and smaller absolute drive currents compared to high-voltage transistors, which may lead to stability issues with the drive current. This is because the shift in the threshold voltage of the transistors in the pixel circuit means that, under the same conditions, the drive current of each pixel circuit will differ, thus affecting the uniformity of the display. Figure 1 The diagram shows a traditional 2T1C (2-Transistor-1-Capacitor) pixel circuit. This circuit can drive the load using the leakage current of the transistor, but the current is highly susceptible to changes in the threshold voltage, resulting in poor stability and making it unsuitable for practical applications.

[0004] Meanwhile, the switching and brightness of the pixel circuit are controlled by several control signals. These control signals originate from the driving circuit of the microdisplay device, while the data input signals determining the brightness originate from the microdisplay device's digital-to-analog converter circuit. The driving circuit, according to a specific scanning method, combines several clock signals with the input level signals within one frame, outputting control signals that can be directly used by the pixel circuit, thus controlling it. For different pixel circuit structures, the principle of the digital-to-analog converter is roughly the same, but the required control signals often differ, i.e., the driving circuit and method differ. Therefore, to make the pixel circuit have practical engineering significance and implementation value, it is necessary to design matching driving circuits and corresponding driving methods for specific pixel circuit structures. Summary of the Invention

[0005] This invention aims to provide a pixel circuit suitable for current-driven microdisplay devices, which has high current stability and solves the problem of display current deviation caused by threshold voltage deviation of the pixel circuit driver transistor. At the same time, it proposes a driving circuit and driving method to match the pixel circuit, so as to improve the practical engineering significance of the designed pixel circuit.

[0006] In view of the problems encountered in the development of the aforementioned current-type microdisplay devices, the technical solution adopted by the present invention is as follows.

[0007] Technical Solution 1: A 4T1C (4-Transistor-1-Capacitor) type pixel circuit suitable for current-mode micro-display devices, to solve the problem that transistor threshold voltage drift in existing pixel circuits affects the operating current of micro-displays and thus affects display quality.

[0008] The 4T1C type pixel circuit proposed in this patent, suitable for current-mode microdisplays, consists of five P-type metal-oxide-semiconductor field-effect transistors using a low-voltage 5V process and four external signal lines.

[0009] The five metal-oxide-semiconductor field-effect transistors are a first switching metal-oxide-semiconductor field-effect transistor, a second switching metal-oxide-semiconductor field-effect transistor, a third switching metal-oxide-semiconductor field-effect transistor, a driving metal-oxide-semiconductor field-effect transistor, a storage capacitor, and a light-emitting load.

[0010] The six external signal lines include a data input signal, a first drive signal, a second drive signal, a pixel enable signal, a common power supply, and a common ground. The first drive signal, the second drive signal, and the pixel enable signal are DC square wave signals provided by an external level shifter, etc.; the data input signal is a variable-range square wave signal provided by an external digital-to-analog converter, etc., depending on the actual input data size. The common power supply and common ground are both constant DC level signals.

[0011] The gate of the first switching metal-oxide-semiconductor field-effect transistor is connected to a data input signal, its drain and substrate are connected to a common ground line, and its source is connected to a first node; the gate of the second switching metal-oxide-semiconductor field-effect transistor is connected to a pixel enable signal, its source is connected to a second node, and its drain and substrate are connected to a common ground line; the gate of the third switching metal-oxide-semiconductor field-effect transistor is connected to a first driving signal, its source is connected to a second driving signal, and its drain and substrate are connected to a second node; the gate of the driving metal-oxide-semiconductor field-effect transistor is electrically connected to a second node, its source is connected to the pixel enable signal, and its drain and substrate are electrically connected to the positive terminal of the light-emitting load; one end of the storage capacitor is electrically connected to a second node, and its other end is connected to a common ground line; the anode of the light-emitting load is connected to a third node, and its cathode is connected to a common ground line.

[0012] Technical Solution 2: A driving circuit for current-mode microdisplay devices. Due to the limitations of power consumption and area of ​​microdisplay chips, a dedicated driving circuit is required to generate the control signals needed by the pixel circuits, thereby controlling the working state of the pixel circuits, meeting the low power consumption requirements of microdisplay driving chips, and reducing the chip design area.

[0013] The driving circuit designed in this patent consists of a first register, a second register, a third register, a first logic NAND gate, a second logic NAND gate, a standard inverter, and a level shifting module; a scan input signal, an enable input signal, a line control input signal, a driving clock, a frame cutting clock; a first driving signal for the pixel circuit, a second driving signal for the pixel circuit, and a driving signal for the pixel circuit.

[0014] The first register F1 has an external scan input signal at its data input terminal, a frame cutting clock at its clock input terminal, and a basic scan level at its data output terminal. The second register has an external row control input signal at its data input terminal, a clock signal at its clock input terminal, and a basic row control level at its data output terminal. The first register also has an external enable input signal at its data input terminal, a frame cutting clock at its clock input terminal, and a basic enable level at its data output terminal. The first logic NAND gate has inputs to the basic scan level and the basic row control level, and outputs a low-voltage first signal. The second logic NAND gate has inputs to the basic row control level and the basic enable level, and outputs a low-voltage pixel circuit enable signal. The standard inverter has an input to a low-voltage first drive signal and outputs a low-voltage second drive signal. The level shifting module of the unit circuit has three signal input ports: a low-voltage first drive signal, a low-voltage second drive signal, and a low-voltage pixel circuit enable signal; and three signal output ports: a pixel circuit first drive signal, a pixel circuit second drive signal, and a pixel circuit enable signal. The output signal of each port is connected to the corresponding signal input port of the pixel circuit on a scan link in the active matrix panel.

[0015] Technical Solution 3: A driving method applicable to the pixel circuit described in Technical Solution 1 and the driving circuit described in Technical Solution 2. This driving method can be applied to current-type microdisplay devices, realizing the driving control of the microdisplay array of the pixel circuit. The driving circuit described in Technical Solution 2 outputs the signals required by the pixel circuit described in Technical Solution 1, realizing the normal operation of the pixel circuit described in Technical Solution 1. At the same time, it compensates for the threshold voltage offset of the pixel circuit transistor and improves the current stability.

[0016] To achieve the aforementioned function, the driving method proposed in this patent mainly includes the following three working stages:

[0017] Pre-charging and reset phase: The first driving signal of the pixel circuit is high, the second driving signal of the pixel circuit is low, and the power signal of the pixel circuit is low; Threshold voltage storage phase: The first driving signal of the pixel circuit is low, the second driving signal of the pixel circuit is high, and the power signal of the pixel circuit is low; Compensation and emission phase: The first driving signal of the pixel circuit is high, the second driving signal of the pixel circuit is low, and the power signal of the pixel circuit is high.

[0018] Compared with the prior art, the present invention has the following beneficial effects.

[0019] First, the pixel circuit disclosed in this invention consists of four low-voltage metal-oxide-semiconductor field-effect transistors, one storage capacitor, and one light-emitting diode load. It has a simple structure, small size, and versatility, and is suitable for a variety of different current-type micro-display devices.

[0020] Secondly, the driving circuit disclosed in this invention simplifies chip design and reduces power consumption. Utilizing the common scan clock, frame clock, and several low-level signals with a maximum level of 3.3V in the microdisplay driver chip, a highly stable pixel control signal is output through D flip-flops, logic gates, and level shifting circuits. The signal's maximum level is 5V, achieving scan control of the microdisplay matrix without requiring an additional 5V pulse signal, thus reducing static power consumption. Furthermore, it avoids invalid flips caused by pixel clocks in the shift register, thereby reducing dynamic power consumption caused by invalid clock flips in the microdisplay chip. Simultaneously, due to its pipelined operation principle, it can be applied in high refresh rate microdisplay devices.

[0021] Third, the driving method disclosed in this invention solves the key technical problem of the offset of the transistor threshold voltage in the pixel circuit, builds a bridge between the pixel circuit and the driving circuit, does not change the structure of the pixel circuit, the scanning scheme is simple to implement, meets the normal operation requirements of the pixel circuit proposed in this invention, and can meet the needs of high-stability display, effectively solving the problems of uneven display and low brightness caused by the unstable light-emitting current of traditional pixel circuit. Attached Figure Description

[0022] Figure 1 It is the structure of a traditional microdisplay pixel circuit.

[0023] Figure 2 This is a circuit structure diagram of a pixel circuit suitable for current-mode microdisplay devices disclosed in this invention.

[0024] Figure 3 This is a circuit structure diagram of the driving circuit applicable to the proposed pixel circuit disclosed in this invention.

[0025] Figure 4 This is a timing diagram of the driving method for the pixel circuit and driving circuit of the current-type microdisplay device disclosed in this invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Obviously, the described embodiments are merely preferred embodiments of the present invention, and not all embodiments. For example, the transistor in this application can refer to a transistor of any structure, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). In the preferred embodiment shown in this invention, to illustrate the application effect of this patent in high-resolution microdisplays, the transistor in the microdisplay is selected as a metal-oxide-semiconductor field-effect transistor (MOSFET). Meanwhile, depending on the different structures and principles of different microdisplay devices, the light-emitting device in this application can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), other inorganic light-emitting diodes (LEDs), or other light-emitting elements. In the preferred embodiment shown in this invention, the light-emitting diode load is selected as an illustrative example. The component designations used herein, such as "first," "second," etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0027] Therefore, although the present invention is shown below with preferred embodiments, these preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention, and all such modifications and refinements should fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

[0028] like Figure 2 The diagram shown is a circuit diagram of a pixel circuit for a current-mode microdisplay device according to an embodiment of the present invention. In this preferred embodiment, a P-type metal-oxide-semiconductor transistor (MOSFET) with a low-voltage 0.35μm, 3.3-5V process is selected as the driving and switching transistors of the pixel circuit to meet the microdisplay requirements of low operating voltage and high display resolution. This pixel circuit consists of control signals and circuit elements. Specifically, it includes a first switching MOSFET M... sw0 The second switching metal-oxide-semiconductor field-effect transistor M sw1 The third switch, metal-oxide-semiconductor field-effect transistor M sw2 , drive metal-oxide-semiconductor field-effect transistor M dr Storage capacitor C s and light-emitting diode load (LED); including data input signal V DATA First drive signal V SCAN1 The second driving signal V SCAN2 Pixel enable signal V EN .

[0029] Specifically, the first switching metal-oxide-semiconductor field-effect transistor Msw0 The gate is connected to the data input signal V DATA Its drain and substrate are connected to the common ground line GND, and its source is connected to the first node A; the second switching metal-oxide-semiconductor field-effect transistor M sw1 The gate access pixel enable signal V EN Its source is connected to the second node B, and its drain and substrate are connected to the common ground line GND; the third switching metal-oxide-semiconductor field-effect transistor M sw2 The gate is connected to the first drive signal V SCAN1 Its source is connected to the second driving signal V. SCAN2 Its drain and substrate are connected to the second node B; the driving metal-oxide-semiconductor field-effect transistor M dr Its gate is electrically connected to the second node B, and its source is connected to the pixel enable signal V. EN Its drain and substrate are electrically connected to the positive electrode of the LED; one end of the storage capacitor is electrically connected to the second node B, and the other end is connected to the common ground GND; the anode of the light-emitting diode load LED is connected to the third node C, and its cathode is connected to the common ground GND.

[0030] The first driving signal V SCAN1 The second driving signal V SCAN2 Pixel enable signal V EN This is the control signal output by the following drive unit circuit. Data input signal V DATA This is a square wave signal with a variable range, provided to external digital-to-analog converters, etc., based on the actual input data DATA. The duty cycle of this signal should be determined according to the actual frame count requirements.

[0031] Figure 3 This is a circuit diagram of a row scanning unit applicable to a microdisplay driver chip according to an embodiment of the present invention. In this preferred embodiment, the timing components are conventional single-bit D flip-flops, and the logic components include two-input NAND gates, inverters, and level shifter modules, all manufactured using low-voltage 0.35μm, 3.3–5V processes.

[0032] Specifically, the row scanning unit circuit includes a first register F1, a second register F2, a third register F3, a first logic NAND gate NAND1, a second logic NAND gate NAND2, a standard inverter N1, a level shifting module MDC consisting of three parallel 3.3V-5V level shifting circuits; a scan input signal scan_in, an enable input signal en_clk, a row control input signal din, a row scan clock row_scan_clk, and a frame cutting clock scan_ctr; a first drive signal SCAN1 for the pixel circuit, a second drive signal SCAN2 for the pixel circuit, and an enable signal EN for the pixel circuit.

[0033] The first register F1 has an external scan input signal scan_in at its data input terminal, a frame cutting clock signal scan_ctr at its clock input terminal, and a basic scan level DFF_scan at its data output terminal. The second register F2 has an external row control input signal din at its data input terminal, a row scan clock signal row_scan_clk at its clock input terminal, and a basic row control level DFF_Q at its data output terminal. The first register F1 has an external enable input signal en_clk at its data input terminal, a frame cutting clock signal scan_ctr at its clock input terminal, and a basic enable level DFF_en at its data output terminal.

[0034] The inputs of the first logic NAND gate NAND1 are the basic scan level DFF_scan and the basic row control level DFF_Q, and the output is the low-voltage first row scan signal scan1_low; the inputs of the second logic NAND gate NAND2 are the basic row control level DFF_Q and the basic enable level DFF_en, and the output is the low-voltage pixel circuit enable signal en_low.

[0035] The input of the standard inverter N1 is the low-voltage first row scan signal scan1_low, and the output is the low-voltage second row scan signal scan2_low.

[0036] The level shifting module (MDC) of the row scanning unit circuit has three signal input ports: a low-voltage first row scanning signal scan1_low, a low-voltage second row scanning signal scan2_low, and a low-voltage pixel circuit enable signal en_low; and three signal output ports: a pixel circuit first drive signal SCAN1, a pixel circuit second drive signal SCAN2, and a pixel circuit enable signal EN. The output signal of each port is connected to the corresponding signal input port of the pixel circuit on one of the scanning links in the active matrix panel.

[0037] Figure 4 This is a timing diagram of the driving method according to an embodiment of the present invention. The driving method disclosed in this invention achieves normal operation of the pixel circuit through the connection between the row scanning circuit and the pixel circuit, while compensating for the threshold voltage offset of the pixel circuit transistors and improving current stability. The method described in this diagram is explained below;

[0038] First, the first row scan signal SCAN1 in the row scan unit circuit and the first drive signal V in the pixel circuit are connected. SCAN1 Connected, the second row scan signal SCAN2 is connected to the second drive signal V of the pixel circuit. SCAN2 Connect the power signal EN and the pixel enable signal V. EN Connected. The data input signal V of the pixel circuit.DATA The signal is provided by an external digital-to-analog converter and other circuits. The above signal combination constitutes three working stages for unified control of the pixel circuit. This timing control is based on the row scanning method, therefore the pixel circuit and the row scanning unit have the same timing. The three working stages are the pre-charging and reset stage, the threshold voltage storage stage, and the compensation and emission stage.

[0039] Pre-charge and reset phase: When the first pulse signal of the frame cutting clock scan_ctr arrives, the first row pixel circuit of the microdisplay device is selected to emit light, and the row input control signal din for this row is high. The row scanning circuit enters the first timing phase, namely the pre-charge and reset phase. The scan input signal scan_in is high, and after NAND and level shifting with the row control input signal din, the first drive signal SCAN1 of the pixel circuit is high, and the second drive signal SCAN2 of the pixel circuit is low. The enable input signal en_clk is low, and after NAND and level shifting with the row control input signal din, the enable signal EN of the pixel circuit is low. The data input signal V DATA Set to high level, first drive signal V SCAN1 Set to low level, second drive signal V SCAN2 Set to high level, pixel enable signal V EN Set to low level; the first switch, metal-oxide-semiconductor field-effect transistor M sw0 Turn off, second switch metal-oxide-semiconductor field-effect transistor M sw1 Turn on, third switch metal-oxide-semiconductor field-effect transistor M sw2 Turn on and drive the metal-oxide-semiconductor field-effect transistor M dr The LED load is off; the voltage V at the first node A is [value missing]. A The voltage V at the second node B is 5V. B It is 0V.

[0040] Threshold voltage storage stage: When the second pulse signal of the frame cutting clock scan_ctr arrives, the row input control signal din of the first row of the microdisplay device is high. The row scanning circuit enters the second timing stage, namely the threshold voltage storage stage. The scan input signal scan_in is low, and after NAND and level shifting with the row control input signal din, the first drive signal SCAN1 of the pixel circuit is low, and the second drive signal SCAN2 of the pixel circuit is high. The enable input signal en_clk is low, and after NAND and level shifting with the row control input signal din, the enable signal EN of the pixel circuit is low. The data input signal V DATA Set to low level, first drive signal VSCAN1 Set to high level, second drive signal V SCAN2 Set to low level, pixel enable signal V EN Set to low level; the first switch metal-oxide-semiconductor field-effect transistor M sw0 Turn on, second switch metal-oxide-semiconductor field-effect transistor M sw1 Turn on, third switch metal-oxide-semiconductor field-effect transistor M sw2 Turn off / drive the metal-oxide-semiconductor field-effect transistor M dr The LED load is off; the voltage V at the first node A is off. A For DATA+|V thp0 |, where |V thp0 | is the first switching metal-oxide-semiconductor field-effect transistor M sw0 The absolute value of the threshold voltage, the voltage V of the second node B. B It is 0V.

[0041] Compensation and Emission Stage: When the third pulse signal of the frame cutting clock scan_ctr arrives, the row input control signal din of the first row of the microdisplay device is high. The row scanning circuit enters the third timing stage, namely the compensation and emission stage. The scan input signal scan_in is high, and after NAND and level shifting with the row control input signal din, the first drive signal SCAN1 of the pixel circuit is high, and the second drive signal SCAN2 of the pixel circuit is low. The enable input signal en_clk is high, and after NAND and level shifting with the row control input signal din, the enable signal EN of the pixel circuit is high. The data input signal V DATA Set to high level, first drive signal V SCAN1 Set to low level, second drive signal V SCAN2 Set to high level, pixel enable signal V EN Set to high level; the first switch, metal-oxide-semiconductor field-effect transistor M sw0 Turn off, second switch metal-oxide-semiconductor field-effect transistor M sw1 Turn off, third switch metal-oxide-semiconductor field-effect transistor M sw2 Turn on and drive the metal-oxide-semiconductor field-effect transistor M dr The LED load is turned on. Then, for one scan frame, all signals remain unchanged, driving the metal-oxide-semiconductor field-effect transistor M. dr The leakage current, i.e., the driving current of the pixel circuit, remains constant, and the LED will continue to emit light. The voltage V of the first node A. A The voltage V at the second node B is 5V.B (5-DATA-|V) thp0 |)V. Utilizing the current flowing through the fourth metal-oxide-semiconductor field-effect transistor M ar The leakage current serves as the driving current for the LED load, thereby causing it to emit light. This current satisfies...

[0042]

[0043] Among them, I dr To drive the metal-oxide-semiconductor field-effect transistor M dr The leakage current, parameter k = μC ox W / L, μ is the driving M of the metal-oxide-semiconductor field-effect transistor. dr The carrier mobility, C ox To drive the metal-oxide-semiconductor field-effect transistor M dr The capacitance, W / L, is the driving capacitance of the metal-oxide-semiconductor field-effect transistor M. dr The aspect ratio of the driving metal-oxide-semiconductor field-effect transistor M. dr The leakage current, i.e. the driving current of the pixel circuit, is independent of the threshold voltage of the first to third switching metal-oxide-semiconductor field-effect transistors and the driving metal-oxide-semiconductor field-effect transistors.

Claims

1. A pixel circuit suitable for current-mode microdisplay devices. Its features are, It consists of five low-voltage 5V P-type metal-oxide-semiconductor field-effect transistors and four external signal lines. The five metal-oxide-semiconductor field-effect transistors are a first switching metal-oxide-semiconductor field-effect transistor, a second switching metal-oxide-semiconductor field-effect transistor, a third switching metal-oxide-semiconductor field-effect transistor, a driving metal-oxide-semiconductor field-effect transistor, a storage capacitor, and a light-emitting load. The six external signal lines include a data input signal, a first drive signal, a second drive signal, a pixel enable signal, a common power supply, and a common ground. The first drive signal, the second drive signal, and the pixel enable signal are DC square wave signals provided by an external level shifter, etc.; the data input signal is a variable-range square wave signal provided by an external digital-to-analog converter, etc., depending on the actual input data size. The common power supply and common ground are both constant DC level signals. The gate of the first switching metal-oxide-semiconductor field-effect transistor is connected to a data input signal, its drain and substrate are connected to a common ground line, and its source is connected to a first node; the gate of the second switching metal-oxide-semiconductor field-effect transistor is connected to a pixel enable signal, its source is connected to a second node, and its drain and substrate are connected to a common ground line; the gate of the third switching metal-oxide-semiconductor field-effect transistor is connected to a first driving signal, its source is connected to a second driving signal, and its drain and substrate are connected to a second node; the gate of the driving metal-oxide-semiconductor field-effect transistor is electrically connected to a second node, its source is connected to the pixel enable signal, and its drain and substrate are electrically connected to the positive terminal of the light-emitting load; one end of the storage capacitor is electrically connected to a second node, and its other end is connected to a common ground line; the anode of the light-emitting load is connected to a third node, and its cathode is connected to a common ground line.

2. A row scanning drive circuit for use in a digital driver chip of a current-mode microdisplay device, applicable to the pixel circuit of claim 1. Its features are, The row scan driving circuit consists of a first register, a second register, a third register, a first logic NAND gate, a second logic NAND gate, a standard inverter, and a level shifting module; and includes a scan input signal, an enable input signal, a row control input signal, a row scan clock, and a frame cutting clock. First drive signal for pixel circuit, second drive signal for pixel circuit, and power signal for pixel circuit. The first register F1 has an external scan input signal at its data input terminal, a frame cutting clock at its clock input terminal, and a basic scan level at its data output terminal; the second register has an external row control input signal at its data input terminal, a row scan clock at its clock input terminal, and a basic row control level at its data output terminal. The first register has an external enable input signal at its data input terminal, a frame cutting clock at its clock input terminal, and a basic enable level at its data output terminal. The first NAND gate's inputs are the basic scan level and the basic row control level, and its output is a low-voltage first row scan signal. The second NAND gate's inputs are the basic row control level and the basic enable level, and its output is a low-voltage pixel circuit enable signal. The standard inverter's input is the low-voltage first row scan signal, and its output is the low-voltage second row scan signal. The row scan unit circuit's level shifting module has three signal input ports: the low-voltage first row scan signal, the low-voltage second row scan signal, and the low-voltage pixel circuit enable signal; and three signal output ports: the pixel circuit first drive signal, the pixel circuit second drive signal, and the pixel circuit enable signal. The output signal of each port is connected to the corresponding signal input port of the pixel circuit on a scan link in the active matrix panel.

3. A driving method applicable to the pixel circuit of claim 1 and the row scanning driving circuit of claim 2. Its features are, It includes three timing operation stages: pre-charging and reset stage, threshold voltage storage stage, and compensation and emission stage. Pre-charging and reset phase: The first driving signal of the pixel circuit is high, the second driving signal of the pixel circuit is low, and the power signal of the pixel circuit is low; Threshold voltage storage phase: The first driving signal of the pixel circuit is low, the second driving signal of the pixel circuit is high, and the power signal of the pixel circuit is low; Compensation and emission phase: The first driving signal of the pixel circuit is high, the second driving signal of the pixel circuit is low, and the power signal of the pixel circuit is high.

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