Trench gate sic mosfet and method of manufacturing the same

Abstract

The present application belongs to the technical field of semiconductor, and particularly relates to a trench gate SiC MOSFET and a preparation method thereof. The preparation method of the trench gate SiC MOSFET forms a relatively thick N-type doping layer below the groove bottom of the gate groove. In the subsequent gate oxide process, the relatively thick N-type doping layer generates more electrons, which accelerates the oxidation of SiC. After the gate oxide process, the thickness of the gate oxide formed at the bottom of the gate groove is obviously thicker than that at the channel sidewall position. The relatively thick gate oxide enhances the tolerance of the device to high voltage, and reduces Qgd (the charge amount of the gate-drain), thereby improving the switching speed of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a trench gate SiC MOSFET and its fabrication method. Background Technology

[0002] Compared to silicon, silicon carbide has a critical breakdown electric field strength that is ten times higher. Therefore, when developing MOSFETs of the same voltage level, the drift region thickness can be significantly reduced and the doping concentration increased, thereby reducing the drift region resistance by about a thousand times. This makes SiC a highly promising semiconductor material for high-voltage power MOSFET structure design.

[0003] Currently, SiC power MOSFET devices mainly include planar MOSFETs and trench MOSFETs. For current trench MOSFETs, due to the large electric field strength experienced by the gate oxide at the bottom of the trench under high drain-source voltage, the gate oxide layer is prone to burn-out during operation. Therefore, there are two main commercial implementation structures: one is a double-trench structure (…). Figure 1 The deep trench utilizes the P-type pins around the deep trench to pre-pinch off during blocking, protecting the gate of the shallow trench. The dual-trench structure increases the on-resistance, and the exposed bottom of the gate trench increases Qgd (gate-drain charge), potentially impacting device reliability. Secondly, there is the asymmetric cell structure (…). Figure 2 One approach involves retaining a channel on one side and surrounding the other side with a deeper P+ ring. This allows adjacent P+ rings to be pinched off in advance during blocking, protecting the gate on one side of the channel. However, this significantly reduces the channel density and increases the on-resistance.

[0004] Therefore, it can be seen that in order to ensure the reliability of the gate oxide, it is often necessary to sacrifice some advantages of the on-resistance. How to improve the gate oxide reliability of trench gate SiC MOSFETs while reducing the on-resistance is of great significance for the application of SiC MOSFETs. Summary of the Invention

[0005] The purpose of this invention is to provide a trench gate SiC MOSFET and its fabrication method.

[0006] This application provides a method for fabricating a trench-gate SiC MOSFET, comprising: Forming gate trenches; A layer with an implantation concentration of [missing information] is formed below the bottom of the gate trench. The heavily doped N-doped region; Sacrificial oxidation; Remove sacrificial oxidation ; Gate oxide growth is performed.

[0007] In one embodiment of this application, the upper end of the heavily doped N-doped region is 50 Å to 200 Å below the bottom of the gate trench.

[0008] In one embodiment of this application, the distance from the upper end to the lower end of the heavily doped N-doped region is 330 Å to 1000 Å.

[0009] In one embodiment of this application, the method for forming a gate trench includes: substrate preparation, epitaxial growth, trench etching, and ion implantation and annealing.

[0010] In one embodiment of this application, after gate oxide growth, the process further includes: gate deposition and patterning, source / drain region ion implantation and annealing, isolation dielectric layer growth, contact hole etching, metallization and interconnection, backside processing, and passivation layer deposition.

[0011] Accordingly, one embodiment of this application provides a trench gate SiC MOSFET fabricated by the method described above, comprising: The drain, substrate, epitaxial layer, trench layer and source are arranged sequentially from bottom to top; The trench layer includes source trenches and gate trenches located between adjacent source trenches; The sidewalls of the gate trench are provided with a side gate oxide layer, and the bottom is provided with a bottom gate oxide layer. The thickness of the bottom gate oxide layer is 1.5 to 3 times the thickness of the side gate oxide layer.

[0012] In one embodiment of this application, the thickness of the bottom gate oxide layer is 600 Å to 1200 Å; The thickness of the side gate oxide layer is 400 Å to 600 Å.

[0013] The beneficial effects of this invention are: This invention forms a denser N-type doped layer below the bottom of the gate trench. In subsequent gate oxide processes, the heavily doped N-type generates more electrons, which accelerates the oxidation of SiC. Ultimately, after the gate oxide process, the gate oxide thickness at the bottom of the gate trench is significantly thicker than that at the channel sidewall. The thicker gate oxide enhances the device's tolerance to high voltages, while also reducing Qgd (gate-drain charge), thus improving the device's switching speed.

[0014] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 and Figure 2 This is a schematic diagram of existing technology; Figure 3 This is a schematic diagram of a trench gate SiC MOSFET according to a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the formation of a heavily doped N-doped region according to a preferred embodiment of the present invention; Figure 5 This is a preferred embodiment of the invention, generated before sacrificial oxidation. A schematic diagram; Figure 6 This is a schematic diagram of a preferred embodiment of the present invention after sacrificial oxidation; Figure 7 This is a schematic diagram of the gate oxide growth according to a preferred embodiment of the present invention.

[0018] In the picture: Drain 1, Substrate 2, Epitaxial layer 3, Trench layer 4, Source trench 41, Gate trench 42, Side gate oxide layer 421, Bottom gate oxide layer 422, Source 5, Heavily doped N-doped region 6. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This application provides a trench-gate SiC MOSFET and its fabrication method, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0021] See Figure 1 In one embodiment, the trench gate SiC MOSFET includes, from bottom to top, a drain 1, a substrate layer 2, an epitaxial layer 3, a trench layer 4, and a source 5; the trench layer 4 includes a source trench 41 and a gate trench 42 located between adjacent source trenches 41; the sidewalls of the gate trench 42 are provided with a side gate oxide layer 421, and the bottom is provided with a bottom gate oxide layer 422; the thickness of the bottom gate oxide layer 422 is 1.5 to 3 times the thickness of the side gate oxide layer 421.

[0022] In this embodiment, by increasing the thickness of the bottom gate oxide layer 422, the device's tolerance to high voltage is enhanced, thereby significantly improving the reliability of the gate oxide; at the same time, the thicker gate oxide reduces Qgd (gate-drain charge), improving the device's switching speed.

[0023] Optionally, the thickness of the bottom gate oxide layer 422 is 600 Å to 1200 Å; the thickness of the side gate oxide layer 421 is 400 Å to 600 Å.

[0024] Accordingly, one embodiment of this application provides a method for fabricating a trench-gate SiC MOSFET, which includes the following steps: A gate trench 42 is formed. Optionally, the method for forming the gate trench 42 includes: substrate preparation, epitaxial growth, trench etching, and ion implantation and annealing, all of which can be implemented using existing fabrication processes.

[0025] In some embodiments, for example: Substrate preparation may include: selecting a SiC single crystal substrate with a suitable crystal orientation, and obtaining a wafer with a flat surface and low defect density through processes such as cutting, grinding, and polishing.

[0026] Epitaxial growth can include growing one or more epitaxial layers on a substrate using methods such as chemical vapor deposition (CVD), typically including n-type drift layers, to form the active region structure of a device.

[0027] Trench etching can include using processes such as photolithography and dry etching (e.g., reactive ion etching, RIE) to etch a double-trench structure on an epitaxial layer, defining the gate and channel regions. During the etching process, the morphology, depth, and sidewall angle of the trenches must be controlled to ensure trench quality.

[0028] Ion implantation and annealing: Ion implantation is performed according to the device design to form doped regions such as p-type body regions and n+ source regions. After implantation, high-temperature annealing (usually 1600-18000℃) is required to activate the doped ions and repair lattice damage, ensuring that the doping distribution and electrical performance meet the requirements.

[0029] Further, see Figure 4 A layer with an implantation concentration of [missing information] is formed below the bottom of the gate trench 42. The heavily doped N-doped region 6.

[0030] Optionally, the upper end of the heavily doped N-doped region 6 is 50 Å to 200 Å below the bottom of the gate trench 42.

[0031] Optionally, the distance from the upper end to the lower end of the heavily doped N-doped region 6 is 330 Å to 1000 Å.

[0032] It is understandable that the distance from the upper end of the heavily doped N-doped region 6 to the bottom of the gate trench 42, and the size of the heavily doped N-doped region 6, can be adjusted according to process requirements.

[0033] In one embodiment, the implantation of the heavily doped N-doped region 6 can be achieved using a deposition and photolithography etching process followed by implantation.

[0034] In one embodiment, specifically, the heavily doped N-doped region 6 can be a range of 150 Å to 480 Å below the bottom of the gate trench 42 (the top 150 Å depth is not doped with N), that is, the upper end of the heavily doped N-doped region 6 is 150 Å below the bottom of the gate trench 42, and the distance from the upper end to the lower end of the heavily doped N-doped region 6 is 330 Å.

[0035] Next, sacrificial oxidation is performed. To prepare for gate oxide growth, a sacrificial oxidation layer is first applied to remove contaminants caused by previous processes on the SiC surface, ensuring the quality of the subsequent gate oxide.

[0036] In one embodiment, specifically, sacrificial oxidation generates The thickness is 300 Å, at which point the consumed SiC surface area is approximately 140 Å. The sacrificial oxidation conditions can be dry oxidation: oxidation for 60 minutes at atmospheric pressure, 1300℃, and in an oxygen atmosphere, resulting in a sacrificial oxidized SiO2 thickness of 300 Å. After oxidation, the thickness is as follows... Figure 5 As shown (at this time, the heavily doped N-doped region 6 is not consumed).

[0037] Furthermore, the sacrificial oxidation formed .

[0038] In one embodiment, specifically, wet etching can be used, employing an HF etching solution for 5 minutes to remove the sacrificial oxidation formed. After removal, as Figure 6 As shown.

[0039] Further, gate oxide growth is carried out.

[0040] In one embodiment, specifically, the growth target is a gate oxide thickness of 400 Å on the sidewalls. Therefore, the SiC consumption at the channel location is expected to be approximately 185 Å, and the gate oxide thickness at the bottom of the gate is expected to be approximately 800 Å, with approximately 370 Å of SiC consumed at that location. This completely consumes the SiC in the heavily doped N-doped region 6. After the gate oxide is completed, as... Figure 7 As shown.

[0041] Furthermore, subsequent processes are carried out according to existing industry standard processes until the device is manufactured. After manufacturing, as follows... Figure 3 As shown.

[0042] For example, the following steps may also be included after gate oxide growth is complete: Gate deposition and patterning: Polysilicon or metal gate material is deposited on the gate oxide layer (e.g., via LPCVD or PVD processes). The gate pattern is transferred onto the wafer through photolithography, development, and etching processes to form a double-trench gate structure, ensuring good contact between the gate and the trench sidewalls and bottom.

[0043] Source / drain ion implantation and annealing: Ion implantation is performed on both sides of the gate to form heavily doped regions in the source and drain regions (e.g., N+ implantation for n-channel devices). High-temperature annealing (typically 1600-18000℃) is then performed to activate the implanted ions, repair lattice damage, and achieve good electrical performance.

[0044] Growth of isolation dielectric layer: An insulating dielectric layer (such as SiO2 or Si3N4) is grown around the source / drain region and the gate for electrical isolation to prevent leakage between the source / drain region and the gate.

[0045] Contact hole etching: Through photolithography and etching processes, contact holes are formed on the isolation dielectric layer to expose the contact points of the source region, drain region and gate, in preparation for subsequent metallization.

[0046] Metallization and interconnection: Metal (such as Ti / Ni / Ag) is deposited within the contact holes to form ohmic contacts for the source, drain, and gate. The metal layers are patterned using photolithography and etching processes to form interconnect lines, enabling the connection between the device and external circuits.

[0047] Backside processing: The backside of the wafer is thinned and metallized to form drain contacts, ensuring electrical connections of devices in the vertical direction.

[0048] Passivation layer deposition: Depositing a passivation layer (such as Si3N4 or polyimide) on the surface of a device to protect the device from environmental factors and improve reliability and stability.

[0049] The above steps need to be adjusted according to the specific process design and device requirements to ensure the performance and reliability of the dual-trench SiC MOSFET.

[0050] It should be noted that all the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0051] In the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0052] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for fabricating a trench-gate SiC MOSFET, characterized in that, include: Form gate trench (42); A layer with an implantation concentration of [missing information] is formed below the bottom of the gate trench (42). The heavily doped N-doped region (6); Sacrificial oxidation; Remove sacrificial oxidation ; Gate oxide growth is performed.

2. The method for fabricating a trench-gate SiC MOSFET as described in claim 1, characterized in that, include: The upper end of the heavily doped N-doped region (6) is 50 Å to 200 Å below the bottom of the gate trench (42).

3. The method for fabricating a trench-gate SiC MOSFET as described in claim 1, characterized in that, include: The distance from the upper end to the lower end of the heavily doped N-doped region (6) is 330 Å to 1000 Å.

4. The method for fabricating a trench-gate SiC MOSFET as described in claim 1, characterized in that, include: The method for forming the gate trench (42) includes: substrate preparation, epitaxial growth, trench etching, and ion implantation and annealing.

5. The method for fabricating a trench-gate SiC MOSFET as described in claim 1, characterized in that, After gate oxide growth, the process also includes: gate deposition and patterning, source / drain ion implantation and annealing, isolation dielectric layer growth, contact hole etching, metallization and interconnection, backside processing, and passivation layer deposition.

6. A trench gate SiC MOSFET fabricated by the method described in any one of claims 1-5, characterized in that, include: The drain (1), substrate (2), epitaxial layer (3), trench layer (4) and source (5) are arranged sequentially from bottom to top. The trench layer (4) includes a source trench (41) and a gate trench (42) located between adjacent source trenches (41). The sidewalls of the gate trench (42) are provided with a side gate oxide layer (421), and the bottom is provided with a bottom gate oxide layer (422). The thickness of the bottom gate oxide layer (422) is 1.5 to 3 times the thickness of the side gate oxide layer (421).

7. The trench gate SiC MOSFET as described in claim 6, characterized in that, The thickness of the bottom gate oxide layer (422) is 600 Å to 1200 Å; The thickness of the side gate oxide layer (421) is 400 Å to 600 Å.

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