Semiconductor test structure and method of testing the same

Abstract

The application provides a semiconductor test structure and a preparation method thereof, and belongs to the technical field of semiconductors. A to-be-tested unit group comprises at least one to-be-tested unit. The to-be-tested unit comprises an active region, a gate structure and a source-drain epitaxial layer. The gate structure is located on a channel region of the active region, and the source-drain epitaxial layer is located in a source region and a drain region of the active region. The widths of all the active regions along a first direction are equal. The sum of the areas of all the channel regions in each to-be-tested unit group is equal. From the first to-be-tested unit group to the nth to-be-tested unit group, the widths of the active regions, the channel regions and the gate structures along a second direction gradually increase, and the widths of each source region and drain region along the second direction are equal. The application can effectively monitor edge defects of the gate structure, thereby avoiding problems in high-temperature life tests of devices and shortening the development time.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor test structure and its test method. Background Technology

[0002] With the continuous development of CMOS integrated circuit manufacturing processes, device dimensions are shrinking, and the thickness of the silicon dioxide gate dielectric layer is also decreasing. However, this thinning leads to problems such as increased leakage current, increased gate resistance, and silicon depletion effect, making it difficult for devices to meet the demands of high-performance computing and low-power applications. To solve these problems, the High-K Metal Gate (HKMG) process has emerged. This process introduces a high-k dielectric material to replace silicon dioxide as the gate dielectric layer and uses metal instead of polysilicon as the metal gate, effectively reducing leakage current and thus improving gate control capability and device performance.

[0003] However, after the metal gate structure is formed, its edges will always have some defects, such as high roughness, edge etching damage, and non-perpendicular edge morphology. These edge defects will eventually cause problems in the high-temperature operating life (HTOL) test of the device. However, monitoring edge defects of the metal gate structure using HTOL testing is time-consuming (more than 1000 hours) and requires the device to be packaged before testing, which is both time-consuming and labor-intensive. Therefore, there is an urgent need for a semiconductor test structure that can monitor edge defects of the metal gate structure. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a semiconductor test structure and test method thereon to solve the problem that monitoring edge defects of metal gate structures in the prior art is time-consuming and labor-intensive.

[0005] This application provides a semiconductor test structure, including n groups of test cells, where n is greater than or equal to 2. Each group of test cells includes at least one test cell. Each test cell includes an active region, a gate structure, and source / drain epitaxial layers. The active region includes a source region, a drain region, and a channel region located between the source region and the drain region. The gate structure is located on the channel region, and the source / drain epitaxial layers are located within the source region and the drain region.

[0006] All the active regions have equal widths along the first direction, the sum of the areas of all the channel regions in each of the test cell groups is equal, and from the 1st to the nth test cell group, the widths of the active region, the channel region, and the gate structure gradually increase along the second direction, and the widths of each source region and the drain region along the second direction are equal; and,

[0007] The first direction is parallel to the extension direction of the gate structure, and the second direction is perpendicular to the extension direction of the gate structure.

[0008] In some embodiments, the number of units under test gradually decreases from the first to the nth group of units under test;

[0009] And / or, the test unit group is fabricated simultaneously with the device unit group in the device region, and the device unit group includes at least one device unit.

[0010] In some embodiments, the device unit and the unit under test have the same structure. The gate structure of both the device unit and the unit under test includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer of both the device unit and the unit under test is made of metal oxide. The gate electrode layer of the device unit is made of metal. The gate electrode layer of the unit under test is made of polysilicon.

[0011] In some embodiments, the cell under test (DUT) is fabricated simultaneously with the gate dielectric layer of the device unit, the DUT is fabricated simultaneously with the source / drain epitaxial layer of the device unit, the gate electrode layer of the DUT is fabricated simultaneously with the dummy gate formed during the fabrication process of the device unit, and the gate electrode layer of the device unit is formed at the original position of the dummy gate after the dummy gate is removed.

[0012] In some embodiments, the area of ​​the active region in the group of units under test is equal to the area of ​​the active region in any of the device unit groups.

[0013] In some embodiments, in the group of test cells and the group of device cells with equal areas of the active region, the number of test cells in the group of test cells is greater than the number of device cells in the group of device cells.

[0014] In some embodiments, the group of cells under test further includes an interconnect metal layer for connecting all the gate structures in the group of cells under test in series.

[0015] This application also provides a semiconductor testing method, including:

[0016] Provide the aforementioned semiconductor test structure;

[0017] Obtain the breakdown voltage of each of the said test cell groups; and,

[0018] The edge defects of the gate structure are monitored based on the magnitude of the breakdown voltage of the test cell group.

[0019] In some embodiments, when the breakdown voltage of each of the test cell groups is equal, it is determined that the gate structure does not have an edge defect; when the breakdown voltage of the first to the nth test cell groups gradually increases, it is determined that the gate structure has an edge defect.

[0020] In some embodiments, the breakdown voltage of each unit under test in the unit under test group is obtained, and the breakdown voltages of all units under test in the unit under test group are fitted into a line, the line being used to characterize the breakdown voltage of the unit under test group; and...

[0021] When the lines corresponding to each of the test unit groups overlap, it is determined that the gate structure does not have edge defects. When the lines corresponding to each of the test unit groups do not overlap and the lines corresponding to the 1st to nth test unit groups are arranged at intervals, it is determined that the gate structure has edge defects.

[0022] This application provides a semiconductor test structure and its fabrication method, comprising n test cell groups, where n is greater than or equal to 2. Each test cell group includes at least one test cell, and each test cell includes an active region, a gate structure, and source / drain epitaxial layers. The active region includes a source region, a drain region, and a channel region located between the source region and the drain region. The gate structure is located on the channel region, and the source / drain epitaxial layers are located within the source region and the drain region. All active regions have equal widths along a first direction, and the sum of the areas of all channel regions in each test cell group is equal. From the 1st to the nth test cell group, the widths of the active region, the channel region, and the gate structure gradually increase along a second direction, and the widths of each source region and drain region along the second direction are equal. The first direction is parallel to the extension direction of the gate structure, and the second direction is perpendicular to the extension direction of the gate structure. An unexpected effect of this application is that the sum of the channel areas of each of the test cell groups is equal, ensuring that the test area of ​​each test cell group remains consistent. Furthermore, since the widths of each source region and drain region along the second direction are equal, the dimensions of the source and drain epitaxial layers of each test cell can be kept consistent. Therefore, the influence of the test area and the epitaxial process forming the source and drain epitaxial layers on the breakdown voltage can be eliminated. The only factor affecting the different breakdown voltages of the test cell groups is the edge defects of the gate structure. Therefore, the edge defects of the gate structure can be monitored based on the magnitude relationship of the breakdown voltages of each test cell group, thereby avoiding problems in the high-temperature life test of the device and shortening the development time. Attached Figure Description

[0023] Figure 1 The diagram shows a schematic of etch damage occurring at the edge of the gate dielectric layer.

[0024] Figure 2 and Figure 3 The diagrams show the generation of the foot and the undercut of the pseudo-gate structure.

[0025] Figure 4 This is a planar schematic diagram of a semiconductor test structure used to monitor edge defects in a metal gate structure.

[0026] Figure 5 for Figure 4 A cross-sectional schematic diagram of the semiconductor test structure.

[0027] Figure 6 This is a schematic diagram of a semiconductor test structure provided in an embodiment of this application.

[0028] Figure 7 for Figure 6 A cross-sectional schematic diagram of the unit under test.

[0029] Figure 8 This is a schematic diagram of another semiconductor test structure provided in an embodiment of this application.

[0030] Figure 9 A flowchart of a semiconductor testing method provided in an embodiment of this application.

[0031] Figure 10 This is a schematic diagram of a gate structure provided in an embodiment of this application that does not have edge defects.

[0032] Figure 11 , Figure 12 and Figure 13 Three schematic diagrams showing a gate structure with edge defects provided in an embodiment of this application.

[0033] The attached figures are labeled as follows:

[0034] 11-First group of cells under test; 12-Second group of cells under test; 13-Third group of cells under test; 100-Active region; 200-Gate structure; 300-Source / drain epitaxial layer; 400-Interconnect metal layer; X-First direction; Y-Second direction. Detailed Implementation

[0035] In advanced manufacturing processes, metal gates are typically fabricated using a gate-last process. This process requires first forming a high-k dielectric layer and a polysilicon gate as a dummy gate structure, then etching away the polysilicon gate to form the metal gate in its place. However, the high-k dielectric layer is usually made of metal oxide. Due to the material differences between polysilicon and metal oxide, the edges of the dummy gate structure (especially the dielectric layer) are often etched during patterning. Furthermore, photolithography can easily lead to high edge roughness of the dummy gate structure, resulting in polyfoot or notch poly issues. Figure 1 The diagram shows a schematic of etching damage occurring at the edge of the gate dielectric layer. Figure 2 and Figure 3 The diagrams show the generation of the foot and the undercut of the pseudo-gate structure.

[0036] It is understandable that since the metal gate is formed in the original position after the polysilicon gate is removed, the edge defects of the polysilicon gate will be replicated on the edge of the metal gate. In addition, the etching damage at the edge of the gate dielectric layer leads to more severe edge defects in the metal gate structure.

[0037] Figure 4 This is a schematic planar view of a semiconductor test structure for monitoring edge defects in a metal gate structure. Figure 5 for Figure 4 A cross-sectional schematic diagram of the semiconductor test structure. (See diagram below.) Figure 4 and Figure 5 As shown, this test structure includes an active region AA and one or at least two spaced-apart gate structures. The active region AA on both sides of the gate structure has a source / drain epitaxial layer EPI SiGe. The breakdown voltage of the semiconductor test structure is obtained by applying a voltage to the gate structure, thereby monitoring the edge defects of the gate structure (metal gate structure) of the device cell in the device region by monitoring the edge defects of the gate structure. It is understandable that in advanced processes, setting a single gate structure on the active region AA often cannot effectively monitor the edge defects of the gate structure, while setting multiple gate structures cannot eliminate the influence of the epitaxial process forming the source / drain epitaxial layer EPI SiGe on the breakdown voltage, thus also failing to effectively monitor the edge defects of the gate structure.

[0038] Based on this, this application provides a semiconductor test structure and its fabrication method. The semiconductor test structure and its fabrication method include n test cell groups, where n is greater than or equal to 2. Each test cell group includes at least one test cell. Each test cell includes an active region, a gate structure, and source / drain epitaxial layers. The active region includes a source region, a drain region, and a channel region located between the source and drain regions. The gate structure is located on the channel region, and the source / drain epitaxial layers are located within the source and drain regions. All active regions have equal widths along a first direction, and the sum of the areas of all channel regions in each test cell group is equal. From the 1st to the nth test cell group, the widths of the active region, channel region, and gate structure gradually increase along a second direction, and the widths of each source and drain region along the second direction are equal. The first direction is parallel to the extension direction of the gate structure, and the second direction is perpendicular to the extension direction of the gate structure. In this application, the sum of the channel regions of each test cell group is equal, ensuring that the test area of ​​each test cell group remains consistent. At the same time, since the width of each source and drain region along the second direction is equal, the size of the source and drain epitaxial layers of each test cell can be kept consistent. Therefore, the influence of the test area and the epitaxial process forming the source and drain epitaxial layers on the breakdown voltage can be eliminated. The only factor affecting the different breakdown voltages of the test cell groups is the edge defects of the gate structure. Therefore, the edge defects of the gate structure can be monitored based on the magnitude relationship of the breakdown voltage of each test cell group, thereby avoiding problems in the high-temperature life test of the device and shortening the development time.

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] Figure 6 This is a schematic diagram of a semiconductor test structure provided in one embodiment of this application. Figure 6 The semiconductor test structure includes n groups of test cells, where n is greater than or equal to 2. Figure 6 The diagram shows three groups of units under test (UDTs). For ease of description, the first to the third UDTs are referred to as the first UDT group 11, the second UDT group 12, and the third UDT group 13, respectively. However, it should be understood that the semiconductor test structure is not limited to including three UDTs, but may also include two, four, five, or more than six UDTs. Examples will not be provided here.

[0041] Each group of units under test includes at least one unit under test, which is a transistor. Figure 7 for Figure 6 Please refer to the cross-sectional schematic diagram of the unit under test in the diagram. Figure 6 and Figure 7 The cell under test includes an active region 100, a gate structure 200, and a source / drain epitaxial layer 300. The active region 100 includes a source region, a drain region, and a channel region located between the source and drain regions. The source, drain, and channel regions are integrated, with the source and drain regions located on opposite sides of the channel region. The gate structure 200 is located on the channel region, and the source / drain epitaxial layer 300 is located within the source and drain regions. In some embodiments, the gate structure 200 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. The gate dielectric layer is made of a high-dielectric-constant material, such as a metal oxide, while the gate electrode layer is made of polysilicon.

[0042] Furthermore, the semiconductor test structure is located within a dicing groove, which is used to separate device regions. The test cell group and the device cell group within the device region are fabricated simultaneously. Each device cell group includes at least one device cell, which is also a transistor, and the device cell has the same structure as the test cell. Specifically, the device cell also includes an active region, a gate structure, and a source / drain epitaxial layer. The gate structure of the device cell also includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. The active region, gate structure, and source / drain epitaxial layer of the device cell are referred to as the first active region, the first gate structure, and the first source / drain epitaxial layer, respectively, to distinguish them from the active region 100, gate structure 200, and source / drain epitaxial layer 300 of the test cell. The gate dielectric layer and gate electrode layer of the first gate structure are referred to as the first gate dielectric layer and the first gate electrode layer, respectively, to distinguish them from the gate dielectric layer and gate electrode layer of the test cell. The material of the first gate dielectric layer is the same as that of the gate dielectric layer, both being high-dielectric-constant materials, such as metal oxides, while the material of the first gate electrode layer is a metal. That is, the first gate electrode layer is a metal gate, while the gate electrode layer is a polysilicon gate. Furthermore, the gate dielectric layer is fabricated simultaneously with the first gate electrode layer, the source / drain epitaxial layer 300 is fabricated simultaneously with the first source / drain epitaxial layer, and the gate electrode layer is fabricated simultaneously with the dummy gate formed during the fabrication of the device unit. The first gate electrode layer is formed on the original position of the dummy gate after the dummy gate is removed.

[0043] Further, the width of the active region 100 along the first direction X is equal, the sum of the areas of all the channel regions in each group of cells to be tested is equal, and from the 1st to the nth group of cells to be tested, the widths and gradually increase along the second direction Y for the active region 100, the channel region, and the gate structure 200, so that the distance from the edge of each active region 100 extending along the first direction X to the adjacent edge of the gate structure 200 extending along the first direction X is equal (the widths of each source region and drain region along the second direction Y are equal, both being W4). That is, the widths of the active regions 100 of the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13 along the first direction X are equal, all being W1; the widths of the channels and the gate structures 200 of the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13 gradually increase along the second direction Y, that is, W31 < W32 < W33, and the widths of the active regions 100 of the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13 along the second direction Y also gradually increase, that is, W21 < W22 < W23; the distance from the edge of each active region 100 of the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13 extending along the first direction X to the adjacent edge of the gate structure 200 extending along the first direction X is equal, that is, the widths of the source regions and drain regions of the active regions 100 of the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13 along the second direction Y are equal, all being W4; the sum of the areas of all the channel regions of the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13 is equal, being W1 W31 m1 = W1 W32 m2 = W1 W33 m3, where m1, m2, and m3 are the numbers of cells to be tested in the first group of cells to be tested 11, the second group of cells to be tested 12, and the third group of cells to be tested 13, respectively.

[0044] It can be understood that since the sum of the areas of all the channel regions in each group of cells to be tested is equal, the test area of each group of cells to be tested is kept consistent; at the same time, since the widths of each source region and drain region are equal along the second direction Y from the 1st to the nth group of cells to be tested, the sizes of the source-drain epitaxial layers 300 of each cell to be tested are kept consistent. Therefore, the influence of the test area and the epitaxial process for forming the source-drain epitaxial layer 300 on the breakdown voltage can be excluded, and the only factor affecting the different breakdown voltages of the groups of cells to be tested is only the edge defects of the gate structure 200. Therefore, according to the magnitude relationship of the breakdown voltages of each group of cells to be tested, the edge defects of the gate structure 200 can be effectively monitored, and further the purpose of monitoring the edge defects of the first gate structure of the device cells can be achieved, thereby avoiding problems in the high-temperature life test of the device and shortening the development time.

[0045] Furthermore, from the 1st to the nth test unit group, the area of ​​a single channel gradually increases, but it is necessary to ensure that the sum of the areas of all channels in each test unit group is equal. Therefore, from the 1st to the nth test unit group, the number of test units gradually decreases. For example, the number of test units m1 in the first test unit group 11 can be equal to 50, the number of test units m2 in the second test unit group 12 can be equal to 30, and the number of test units m3 in the third test unit group 13 can be equal to 10, but this should not be a limitation.

[0046] It is understandable that the area of ​​the channel and the active region 100 in each test unit group is different. In order to accurately monitor the edge defects of the first gate structure 200 of the device unit group, the area of ​​the active region 100 in the test unit group can be equal to the area of ​​the active region in any device unit group. This allows the edge defects of the gate structure 200 of the test unit group to reflect the edge defects of the first gate structure of the corresponding device unit group, thus achieving the purpose of monitoring the edge defects of the first gate structure of the device unit group. Assuming there are 5 device unit groups with different active region areas, we can let n=5, that is, set 5 test unit groups, and design the area of ​​the active region 100 of the 5 test unit groups to correspond to the area of ​​the active region of the 5 device unit groups. Of course, if there are 5 device unit groups with different active region areas, we can also select 3 important device unit groups, let n=3, that is, set 3 test unit groups, and design the area of ​​the active region 100 of the 3 test unit groups to correspond to the area of ​​the active region of these 3 important device unit groups.

[0047] In some embodiments, in a group of test cells and a group of device cells with equal areas of active regions, the number of test cells in the group of test cells is greater than the number of device cells in the group of device cells. Therefore, if the gate structure 200 has edge defects, increasing the number of test cells in the group of test cells can increase the number of gate structures 200, thereby increasing the proportion of edge defects in the gate structure 200, making the edge defects of the gate structure 200 easier to detect, and thus improving the accuracy of detection.

[0048] Figure 8 This is a schematic diagram of another semiconductor test structure provided in an embodiment of this application. For example... Figure 8As shown, in some embodiments, the test cell group may further include an interconnect metal layer 400, which can be used to connect all gate structures 200 in the test cell group in series. In this way, applying a voltage to the interconnect metal layer 400 can synchronously apply a voltage to all gate structures 200 in the corresponding test cell group, thereby obtaining the breakdown voltage of the entire test cell group, without having to apply a voltage to each gate structure 200 individually to obtain the breakdown voltage of a single test cell.

[0049] It should be noted that the breakdown voltage of the entire test cell group is actually the minimum breakdown voltage of the test cell within the test cell group.

[0050] Based on this, one embodiment of this application also provides a semiconductor testing method. Figure 9 A flowchart of a semiconductor testing method provided in an embodiment of this application is shown below. Figure 9 As shown, semiconductor testing methods include:

[0051] Step S100: Provide a semiconductor test structure;

[0052] Step S200: Obtain the breakdown voltage of each test cell group; and,

[0053] Step S300: Monitor the edge defects of the gate structure based on the magnitude of the breakdown voltage of the cell group under test.

[0054] Specifically, step S100 is executed first to provide a semiconductor test structure. The specific structure of the semiconductor test structure has been described above and will not be repeated here.

[0055] Execute step S200 to obtain the breakdown voltage of each test unit group. Combined with... Figure 6 As shown, a voltage can be applied individually to the gate structure 200 of each unit under test in each unit under test group to obtain the breakdown voltage of each unit under test in each unit under test group. The breakdown voltages of all units under test in each unit under test group are fitted into a line, which can characterize the breakdown voltage of the unit under test group.

[0056] Next, step S300 is executed to monitor the edge defects of the gate structure 200 based on the magnitude relationship of the breakdown voltages of the test cell groups. Specifically, when the lines corresponding to each test cell group overlap, it indicates that the breakdown voltages of each test cell group are the same, and it can be determined that the gate structure 200 does not have edge defects; when the lines corresponding to each test cell group do not overlap and the lines corresponding to the 1st to nth test cell groups are arranged alternately, it indicates that the breakdown voltages of the 1st to nth test cell groups gradually increase, and it can be determined that the gate structure 200 has edge defects.

[0057] It should be noted that since the test area of ​​each test cell group is the same, and the size of the source / drain epitaxial layer 300 of each test cell is also the same, the influence of the test area and the epitaxial process forming the source / drain epitaxial layer 300 on the breakdown voltage of each test cell group can be eliminated. The only factor affecting the different breakdown voltages of the test cell groups is the edge defects of the gate structure 200. From the 1st to the nth test cell group, the number of test cells gradually decreases, and the proportion of the edge of the gate structure 200 also gradually decreases. If the gate structure 200 does not have edge defects, the breakdown voltage of each test cell group should theoretically be the same. If the gate structure 200 has edge defects, the breakdown voltage should gradually increase from the 1st to the nth test cell group.

[0058] Figure 10 A schematic diagram of a gate structure 200 without edge defects provided in an embodiment of this application is shown below. Figure 10 As shown, the lines corresponding to the first test unit group 11, the second test unit group 12, and the third test unit group 13 are ( Figure 10 The overlap of the green dashed line indicates that the breakdown voltages of the first test unit group 11, the second test unit group 12, and the third test unit group 13 are the same. Therefore, it can be determined that the first test unit group 11, the second test unit group 12, and the third test unit do not have edge defects.

[0059] Figure 11 , Figure 12 and Figure 13 Three schematic diagrams illustrating edge defects in a gate structure 200 provided in an embodiment of this application are shown below. Figure 11 , Figure 12 and Figure 13 As shown, the lines corresponding to the first test unit group 11, the second test unit group 12, and the third test unit group 13 are ( Figure 11 , Figure 12 and Figure 13 The green dashed lines do not overlap, and the lines corresponding to the first test unit group 11, the second test unit group 12, and the third test unit group 13 are arranged alternately, indicating that the breakdown voltage of the first test unit group 11, the second test unit group 12, and the third test unit group 13 gradually increases. Therefore, it can be determined that the first test unit group 11, the second test unit group 12, and the third test unit have edge defects.

[0060] It should be noted that, compared to Figure 11 In other words, Figure 12 and Figure 13The breakdown voltage of the test cell in the first test cell group 11 has discrete values ​​(values ​​inside the dashed circle). The discrete values ​​may be caused by the position of the test cell (e.g., if the test cell is located at the edge of the wafer, the breakdown voltage may be smaller under the same other parameters). When fitting the line, the discrete values ​​can be removed to avoid the discrete values ​​affecting the monitoring of edge defects.

[0061] Furthermore, after determining that the gate structure 200 has edge defects, the pass / failability of each test cell group can be determined based on the relationship between the breakdown voltage and a failure voltage of each test cell in the test cell group. In some embodiments, when the breakdown voltage of any test cell in the test cell group is less than the failure voltage, it indicates that the edge defect of the gate structure 200 of the test cell group is relatively serious, and the test cell group can be determined to be unqualified; when the breakdown voltage of all test cells in the test cell group is greater than the failure voltage, it indicates that although the gate structure 200 of the test cell group has edge defects, the edge defects are relatively minor, and the test cell group can be determined to be qualified. After determining that the test cell group is unqualified, it can be considered that the device is highly likely to fail the high-temperature life test, and the process can be adjusted to detect problems early, thereby shortening the development time.

[0062] In some embodiments, the failure voltage may be greater than twice the operating voltage of the unit under test, for example, the failure voltage may be equal to 2.3 times the operating voltage of the unit under test, but should not be limited thereto.

[0063] like Figures 10-12 As shown, the breakdown voltage of all test units in the first test unit group 11, the second test unit group 12, and the third test unit group 13 is greater than the failure voltage, therefore, it can be determined that the first test unit group 11, the second test unit group 12, and the third test unit group 13 are all qualified. Figure 13 As shown, the breakdown voltage of some units under test in the first unit under test group 11 is ( Figure 13 If the discrete point in the test is greater than the failure voltage, it can be determined that the first test unit group 11 is unqualified, while the second test unit group 12 and the third test unit group 13 are qualified.

[0064] Combination Figure 8 As shown, in some embodiments, a voltage can be applied to the interconnect metal layer 400 of each test cell group, so that a voltage can be applied to all gate structures 200 in the test cell group simultaneously, thereby obtaining the breakdown voltage of each test cell group.

[0065] Similarly, when the breakdown voltage of each test unit group is equal, it indicates that the breakdown voltage of each test unit group is the same, and it can be determined that the gate structure 200 does not have edge defects. When the breakdown voltage of the first to the nth test unit groups gradually increases, it indicates that the breakdown voltage of the first to the nth test unit groups gradually increases, and it can be determined that the gate structure 200 has edge defects.

[0066] Furthermore, after determining that the gate structure 200 has edge defects, the pass / fail status of each test cell group can be determined based on the relationship between the breakdown voltage and the failure voltage of the test cell group. Specifically, when the breakdown voltage of the test cell group is less than the failure voltage, it indicates that the edge defects of the gate structure 200 of the test cell group are relatively serious, and the test cell group can be determined to be unqualified; when the breakdown voltage of the test cell group is greater than the failure voltage, it indicates that although the gate structure 200 of the test cell group has edge defects, the edge defects are relatively minor, and the test cell group can be determined to be qualified.

[0067] In some embodiments, it is also possible to Figure 6 and Figure 8 The semiconductor test structures are all fabricated within the dicing channel, thus allowing for... Figure 6 The semiconductor test structure individually acquires the breakdown voltage of each cell under test (DUT), thereby fitting the breakdown voltages of all DUTs in each DUT group into a line. The presence or absence of edge defects in the gate structure 200 is determined based on whether the lines of each DUT group overlap, resulting in higher accuracy. Then, through... Figure 8 The semiconductor test structure in the test module obtains the breakdown voltage of each test cell group as a whole. Since the breakdown voltage of the test cell group is equal to the minimum breakdown voltage of the test cell in that test cell group, the breakdown voltage of each test cell group is used to simply determine whether the test cell group is qualified. This method has redundancy and high accuracy.

[0068] In summary, this application provides a semiconductor test structure and its fabrication method. The semiconductor test structure and its fabrication method include n test cell groups, where n is greater than or equal to 2. Each test cell group includes at least one test cell. The test cell includes an active region 100, a gate structure 200, and a source / drain epitaxial layer 300. The active region 100 includes a source region, a drain region, and a channel region located between the source and drain regions. The gate structure 200 is located on the channel region, and the source / drain epitaxial layer 300 is located within the source and drain regions. The width of the active region 100 along the first direction X is equal, and the sum of the areas of all channel regions in each test cell group is equal. From the 1st to the nth test cell group, the width of the active region 100, the channel region, and the gate structure 200 gradually increases along the second direction Y, and the width of each source and drain region along the second direction Y is equal. The first direction X is parallel to the extension direction of the gate structure 200, and the second direction Y is perpendicular to the extension direction of the gate structure 200. An unexpected effect of this application is that the sum of the channel areas of each test cell group is equal, ensuring that the breakdown voltage test area of ​​each test cell group remains consistent. Simultaneously, the widths of each source and drain region along the second direction Y are equal, ensuring that the dimensions of the source / drain epitaxial layer 300 of each test cell remain consistent. Therefore, the influence of the test area and the epitaxial process forming the source / drain epitaxial layer 300 on the breakdown voltage can be eliminated. The only factor affecting the different breakdown voltages of the test cell groups is the edge defects of the gate structure 200. Therefore, the edge defects of the gate structure 200 can be monitored based on the magnitude relationship of the breakdown voltages of each test cell group, thereby avoiding problems in the high-temperature life test of the device and shortening the development time.

[0069] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0070] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0071] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0072] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor testing structure, characterized in that, It includes n groups of test units, where n is greater than or equal to 2. Each group of test units includes at least one test unit. Each test unit includes an active region, a gate structure, and a source / drain epitaxial layer. The active region includes a source region, a drain region, and a channel region located between the source region and the drain region. The gate structure is located on the channel region, and the source / drain epitaxial layer is located within the source region and the drain region. All active regions have equal widths along the first direction, and the sum of the areas of all channel regions in each group of test cells is equal. From the 1st to the nth group of test cells, the widths of the active region, the channel region, and the gate structure gradually increase along the second direction, and the widths of each source region and the drain region along the second direction are equal. The first direction is parallel to the extension direction of the gate structure, and the second direction is perpendicular to the extension direction of the gate structure.

2. The semiconductor test structure according to claim 1, characterized in that, From the first to the nth group of test units, the number of test units gradually decreases; And / or, the test unit group is fabricated simultaneously with the device unit group in the device region, and the device unit group includes at least one device unit.

3. The semiconductor test structure according to claim 2, characterized in that, The device unit has the same structure as the unit under test. The gate structure of both the device unit and the unit under test includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer of both the device unit and the unit under test is made of metal oxide. The gate electrode layer of the device unit is made of metal. The gate electrode layer of the unit under test is made of polysilicon.

4. The semiconductor test structure according to claim 3, characterized in that, The test cell and the gate dielectric layer of the device unit are fabricated simultaneously. The test cell and the source drain epitaxial layer of the device unit are fabricated simultaneously. The gate electrode layer of the test cell and the dummy gate formed during the fabrication process of the device unit are fabricated simultaneously. The gate electrode layer of the device unit is formed at the original position of the dummy gate after the dummy gate is removed.

5. The semiconductor test structure according to claim 3, characterized in that, The area of ​​the active region in the unit group under test is equal to the area of ​​the active region in any of the device unit groups.

6. The semiconductor test structure according to claim 5, characterized in that, In the group of test cells and the group of device cells with equal areas of active regions, the number of test cells in the group of test cells is greater than the number of device cells in the group of device cells.

7. The semiconductor test structure according to any one of claims 1 to 6, characterized in that, The test cell group further includes an interconnect metal layer for connecting all the gate structures in the test cell group in series.

8. A semiconductor testing method, characterized in that, include: Provide a semiconductor test structure as described in any one of claims 1 to 7; Obtain the breakdown voltage of each of the test unit groups; as well as, The edge defects of the gate structure are monitored based on the magnitude of the breakdown voltage of the test cell group.

9. The semiconductor testing method as described in claim 8, characterized in that, When the breakdown voltage of each of the test unit groups is equal, it is determined that the gate structure does not have an edge defect. When the breakdown voltage of the first to the nth test unit groups gradually increases, it is determined that the gate structure has an edge defect.

10. The semiconductor testing method as described in claim 8, characterized in that, The breakdown voltage of each unit under test in the unit under test group is obtained, and the breakdown voltages of all units under test in the unit under test group are fitted into a line, which is used to characterize the breakdown voltage of the unit under test group. as well as, When the lines corresponding to each of the test unit groups overlap, it is determined that the gate structure does not have edge defects. When the lines corresponding to each of the test unit groups do not overlap and the lines corresponding to the 1st to nth test unit groups are arranged at intervals, it is determined that the gate structure has edge defects.

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