Scanning test device and method and chip

Abstract

The embodiment of the invention provides a scanning test device and method and a chip, and the device comprises a switching network configuration unit which comprises a configuration array and a configuration array repair logic; the configuration array is used for generating a configuration signal to configure gating of the test channel; the configuration array repairing logic is used for repairing the configuration signal based on a repairing signal when the configuration array fails; and the switching network repairing unit is used for generating a repairing signal so as to repair the configuration signal. The configuration array repairing logic is set in the switching network configuration unit, and when the configuration array fails, the configuration signal is repaired based on the repairing signal generated by the switching network repairing unit, so that the problem that the switching network configuration array cannot provide a correct configuration path for the switching network due to the existence of production defects is avoided; therefore, the test efficiency of the scanning test is improved.

Description

Technical Field

[0001] This application relates to the field of chips, specifically to a scanning test apparatus, method, and chip. Background Technology

[0002] As digital chips continue to scale up, the demand for scan channels during scan testing (SCAN) has increased dramatically. Currently, a scan test switching network can be used to enable free selection between external I / O (Input / Output) and scan test channels. Specifically, the scan test switching network can achieve free selection based on configuration signals generated by the switching network configuration array.

[0003] However, the testing efficiency of current scanning tests still needs to be improved. Summary of the Invention

[0004] In view of this, embodiments of this application provide a scanning test apparatus, method, and chip to improve the testing efficiency of scanning tests.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a scanning testing apparatus, comprising: A switching network configuration unit includes a configuration array and configuration array repair logic; the configuration array is used to generate configuration signals to configure the selection of test channels; the configuration array repair logic is used to repair the configuration signals based on repair signals when the configuration array fails. A switching network repair unit is used to generate a repair signal to repair the configuration signal.

[0007] Optionally, the switching network repair unit generates a repair signal through a test data register.

[0008] Optionally, the configuration array repair logic includes multiple XOR gates, which are used to XOR the configuration signal and the repair signal.

[0009] Optionally, the configuration array includes multiple shift register groups, one shift register group generating a set of configuration signals.

[0010] Optionally, when there are multiple switching network configuration units, the number of switching network repair units is the same as the number of switching network configuration units, and one switching network configuration unit corresponds to one switching network repair unit.

[0011] Optional, also includes: An input switching network is used to configure the gating of input test channels based on configuration signals; The output switching network is used to configure the selection of output test channels based on configuration signals.

[0012] Optional, also includes: A first input interface is connected to a scanning input channel via the input switching network; The first output interface is connected to the scan output channel via the output switching network.

[0013] Optional, also includes: A second input interface is connected to the first input interface and an external test device. The second output interface connects the first output interface and an external test device.

[0014] Secondly, embodiments of this application provide a scanning test method, applied to the scanning test apparatus described in the first aspect, comprising: Perform scan testing on the logic to be tested; If the test fails, determine whether the reason for the test failure is that the switching network configuration array is malfunctioning. If so, the switching network configuration unit is repaired based on the switching network repair unit, and the logic to be tested is scanned and tested again.

[0015] Thirdly, embodiments of this application provide a chip, including: the scanning test apparatus as described in the first aspect above.

[0016] This application provides a scanning test apparatus, method, and chip. The scanning test apparatus includes: a switching network configuration unit, which includes a configuration array and configuration array repair logic; the configuration array is used to generate configuration signals to configure the selection of test channels; the configuration array repair logic is used to repair the configuration signals based on repair signals when the configuration array fails; and a switching network repair unit is used to generate repair signals to repair the configuration signals.

[0017] As can be seen, the scanning test apparatus provided in this application embodiment sets up configuration array repair logic in the switching network configuration unit. When the configuration array fails, the configuration signal is repaired based on the repair signal generated by the switching network repair unit. This avoids the situation where the switching network configuration array cannot provide the correct configuration path for the switching network due to production defects, resulting in scanning test failure, thereby improving the testing efficiency of scanning test. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an optional structure for scanning and testing a switching network; Figure 2 This is a schematic diagram of an optional structure of the scanning testing device provided in the embodiments of this application; Figure 3 This is a schematic diagram of an optional structure of the switching network configuration unit provided in the embodiments of this application; Figure 4 This is a schematic diagram of another optional structure of the scanning testing device provided in the embodiments of this application; Figure 5 This is a schematic diagram of an optional process of the scanning test method provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] As described in the background section, with the continuous expansion of digital chip scale, the demand for scan channels during scan testing (SCAN) has also increased dramatically. Currently, scan test switching networks can be used to achieve free selection between external I / O (Input / Output) and scan test channels. Specifically, the scan test switching network can achieve free selection based on configuration signals generated by the switching network configuration array.

[0022] In one alternative implementation, refer to Figure 1An exemplary schematic diagram of an optional structure of a scan test switching network is shown. The scan test switching network includes an input switching network and an output switching network. The input switching network dynamically maps test data from the BUMP_RX[N-1:0] interface to the Scan Input Channel In based on configuration signals generated by the switching network configuration array. The output switching network dynamically maps test results generated from scanning tests on the logic under test from the Scan Output Channel to the BUMP_TX[N-1:0] interface based on configuration signals generated by the switching network configuration array.

[0023] Among them, PKG_BUMP_RX[K1-1:0] and PKG_BUMP_TX[K2-1:0] are the physical I / O interfaces of the packaged chip, which are directly connected to external test equipment.

[0024] BUMP_RX[N-1:0] and BUMP_TX[N-1:0] are the physical I / O interfaces of the unpackaged chip, which are connected to the scan channel via a switching network.

[0025] EDT (Embedded Deterministic Test) is responsible for compressing / decompressing test data, controlling test access mechanisms, and coordinating the test process.

[0026] The logic to be tested is the core functional circuit of the chip (e.g., processor, memory, etc.), and is the object that needs to be verified.

[0027] However, the inventors discovered that the configuration signals generated by the aforementioned switching network configuration array during the initialization phase lack repair capabilities. If the switching network configuration array has manufacturing defects, it cannot provide the correct configuration path for the switching network, leading to scan test failure and severely impacting test efficiency. Furthermore, since such failures originate from the test infrastructure itself rather than functional logic defects, qualified chips may be mistakenly identified as defective products during testing. This misclassification causes non-technical losses in chip production yield and affects the overall efficiency of the production line.

[0028] In view of this, embodiments of this application provide a scanning test apparatus, method, and chip, wherein the scanning test apparatus includes: a switching network configuration unit, the switching network configuration unit including a configuration array and configuration array repair logic; the configuration array is used to generate configuration signals to configure the selection of test channels; the configuration array repair logic is used to repair the configuration signals based on repair signals when the configuration array fails; and the switching network repair unit is used to generate repair signals to repair the configuration signals.

[0029] As can be seen, the scanning test apparatus provided in this application embodiment sets up configuration array repair logic in the switching network configuration unit. When the configuration array fails, the configuration signal is repaired based on the repair signal generated by the switching network repair unit. This avoids the situation where the switching network configuration array cannot provide the correct configuration path for the switching network due to production defects, resulting in scanning test failure, thereby improving the testing efficiency of scanning test.

[0030] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0031] refer to Figure 2 , Figure 2 This is a schematic diagram of an optional structure of the scanning testing apparatus provided in an embodiment of this application. For example... Figure 2 As shown, the scanning test apparatus may include: Switching network configuration unit 11, reference Figure 3 An exemplary schematic diagram of an optional structure of a switching network configuration unit 11 is shown. The switching network configuration unit 11 may include a configuration array 111 and configuration array repair logic 112. The configuration array 111 is used to generate configuration signals to configure the selection of test channels. The configuration array repair logic 112 is used to repair the configuration signals based on the repair signals when the configuration array 111 fails. In an optional implementation, the configuration array 111 may include multiple shift register groups, one shift register group generating a set of configuration signals. For example... Figure 3 As shown, multiple shift registers located in the same row constitute a shift register group. The D (Data Input) terminal of the shift register is the data input terminal, used to receive the binary data to be shifted (e.g., 0 or 1); the Q (Data Output) terminal of the shift register is the data output terminal, used to output the data value currently stored in the shift register. The CK (Clock) terminal of the shift register is the clock signal input terminal, and the state update of the shift register is synchronously controlled by the clock edge (e.g., rising edge).

[0032] Specifically, external configuration data is input to the shift register group through the first input interface BUMP_RX[N-1:0]. Each clock cycle, the data at the D input is transferred to the Q input of the current shift register and then to the D input of the next-level shift register, achieving serial shifting. Each shift register's Q input outputs a configuration signal used to configure switches or path selectors in the switching network. Multiple Q inputs within the same shift register group jointly generate a set of configuration signals. Shift registers in the same row share the same clock signal, ensuring synchronous shifting or latching of configuration data. When the clock edge arrives, the data at the D input is captured and transferred to the Q input, enabling dynamic updates of the configuration information.

[0033] The configuration array repair logic 112 may include multiple XOR gates, which are used to XOR the configuration signal and the repair signal. Each XOR gate corresponds to a shift register group, and each shift register group outputs a set of configuration signals (multiple bits) for configuring switches or path selectors in the switching network. Each repair signal corresponds to one configuration signal. By XORing each configuration signal with one repair signal, the erroneous bits in the configuration signal are dynamically corrected using the repair signal, thereby repairing the configuration signal. This avoids situations where the switching network configuration array, due to manufacturing defects, cannot provide the correct configuration path for the switching network, leading to scan test failure, thus improving the test efficiency of the scan test.

[0034] The switching network repair unit 12 is used to generate a repair signal to repair the configuration signal. In an optional implementation, the switching network repair unit 12 can generate the repair signal through a test data register (TDR).

[0035] Continue to refer to Figure 2 The scanning test apparatus may further include: Input switching network 13 is used to configure the selection of input test channels based on configuration signals. Specifically, the input switching network 13 can dynamically map test data from the first input interface BUMP_RX[N-1:0] to the scan input channel Scan Channel In based on configuration signals. It can be understood that the configuration signals generated by the configuration array, or the repaired configuration signals, determine the connection relationship between each pin of BUMP_RX and Scan Channel In.

[0036] Output switching network 14 is used to configure the selection of output test channels based on configuration signals. Specifically, the output switching network 14 can dynamically map the test results generated by scanning the logic under test from the Scan Channel Out to the first output interface BUMP_TX[N-1:0] based on the configuration signals. It can be understood that the configuration signals generated by the configuration array, or the repaired configuration signals, determine the specific BUMP_TX pins assigned to the test results of the Scan Channel Out.

[0037] In an optional implementation, the scanning test apparatus may further include: The first input interface BUMP_RX[N-1:0] is connected to the Scan Input Channel In through the input switching network 13; The first output interface BUMP_TX[N-1:0] is connected to the Scan Channel Out through the output switching network 14.

[0038] Wherein, the first input interface BUMP_RX[N-1:0] and the first output interface BUMP_TX[N-1:0] are the physical I / O interfaces of the unpackaged chip.

[0039] In an optional implementation, the scanning test apparatus may further include: The second input interface PKG_BUMP_RX[K1-1:0] connects the first input interface BUMP_RX[N-1:0] and an external test device, which provides test data to the second input interface PKG_BUMP_RX[K1-1:0].

[0040] The second output interface PKG_BUMP_TX[K2-1:0] connects the first output interface BUMP_TX[N-1:0] and an external test device. The external test device is used to receive the test results generated by scanning the logic under test transmitted by the first output interface BUMP_TX[N-1:0].

[0041] Among them, the second input interface PKG_BUMP_RX[K1-1:0] and the second output interface PKG_BUMP_TX[K2-1:0] are the physical I / O interfaces of the packaged chip.

[0042] In an optional implementation, when the number of the switching network configuration units is multiple, the number of the switching network repair units is the same as that of the switching network configuration units, and one switching network configuration unit corresponds to one switching network repair unit.

[0043] Specifically, referring to Figure 4 Another optional structural schematic diagram of the scanning test device shown exemplarily, when the number of the switching network configuration units is multiple (as shown by the first switching network configuration unit and the second switching network configuration unit in Figure 4 ), the number of the switching network repair units is the same as that of the switching network configuration units, and one switching network configuration unit corresponds to one switching network repair unit. For example, Figure 4 the first switching network configuration unit in corresponds to the first switching network repair unit, and the second switching network configuration unit corresponds to the second switching network repair unit.

[0044] It can be understood that when a new switching network is added to the scanning test device, only the corresponding switching network configuration unit and switching network repair unit need to be synchronously deployed, without changing the existing repair architecture.

[0045] Among them, Figure 4 the first switching network N*M1 in means that N is the input and M is the output. After passing through the first switching network, M1 IOs are selected from the first input interface BUMP_RX[N-1:0] as the input of the second switching network configuration unit, denoted as CFG[M1-1:]. Usually, M1 is much smaller than N (M1<<N). This dimension reduction selection mechanism can effectively avoid the signal reliability risk caused by the packaging process fluctuation and ensure the stability of the configuration signal.

[0046] Similarly, the second switching network (input) N*M2 means that N is the input and M2 is the output. Usually, M2 is much larger than N (M2>>N), so as to enhance the signal routing flexibility by increasing the output dimension. The second switching network (output) M2*N means that M2 is the input and N is the output.

[0047] It can be seen that the scanning test device provided by the embodiment of the present application sets the configuration array repair logic in the switching network configuration unit. When the configuration array fails, the configuration signal is repaired based on the repair signal generated by the switching network repair unit, thus avoiding the situation that the scanning test fails because the switching network configuration array cannot provide the correct configuration path for the switching network due to production defects, and further improving the test efficiency of the scanning test.

[0048] Next, the scanning test method provided by the embodiment of the present application will be introduced. The scanning test method is applied to the above-mentioned scanning test device.

[0049] In an optional implementation, Figure 5 An exemplary schematic diagram of an optional flow of the scanning test method provided in an embodiment of this application is shown, such as... Figure 5 As shown, the scanning test method may include: Step S100: Perform a scan test on the logic to be tested.

[0050] The logic to be tested is the core functional circuit of the chip (e.g., processor, memory, etc.), which is the object that needs to be verified.

[0051] Specifically, the external test equipment provides test data to the second input interface PKG_BUMP_RX[K1-1:0], which then transmits the test data to the first input interface BUMP_RX[N-1:0]. Next, the input switching network, based on the configuration signals of the switching network configuration unit, dynamically maps the test data from the first input interface BUMP_RX[N-1:0] to the Scan Channel In, performing a scan test on the logic under test.

[0052] Based on the configuration signals of the switching network configuration unit, the output switching network dynamically maps the test results generated by the scan test of the logic under test from the Scan Channel Out to the first output interface BUMP_TX[N-1:0]. The first output interface BUMP_TX[N-1:0] then transmits the test results to the second output interface PKG_BUMP_TX[K2-1:0]. Finally, the second output interface PKG_BUMP_TX[K2-1:0] transmits the test results to the external test equipment.

[0053] If the test fails, proceed to step S200 to determine whether the reason for the test failure is that the switching network configuration array has failed.

[0054] In particular, a failure of the switching network configuration array will cause the switching network configuration to fail, resulting in data being unable to be transmitted normally through the switching network.

[0055] If so, then step S300 is executed, the switching network configuration array in the switching network configuration unit is repaired based on the switching network repair unit, and the logic to be tested is scanned and tested again.

[0056] In an optional implementation, failed configuration signal bits can be captured, and then the network repair unit can generate a corresponding repair signal for the configuration signal. The configuration signal can then be repaired using the repair signal. Specifically, the configuration signal can be repaired by XORing the configuration signal and the repair signal.

[0057] As can be seen, the scanning test method provided in this application determines whether the failure is due to a failure of the switching network configuration array when the test fails. If so, the switching network configuration array in the switching network configuration unit is repaired based on the switching network repair unit, and the logic to be tested is scanned again. This avoids the situation where the switching network configuration array cannot provide the correct configuration path for the switching network due to production defects, thus causing the scanning test to fail, thereby improving the testing efficiency of the scanning test.

[0058] This application also provides a chip, which includes the scanning test apparatus as described above.

[0059] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0060] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A scanning testing device, characterized in that, include: A switching network configuration unit, the switching network configuration unit including a configuration array and configuration array repair logic; The configuration array is used to generate configuration signals to configure the gating of test channels; The configuration array repair logic is used to repair the configuration signal based on the repair signal when the configuration array fails. A switching network repair unit is used to generate a repair signal to repair the configuration signal.

2. The scanning testing apparatus according to claim 1, characterized in that, The switching network repair unit generates a repair signal through a test data register.

3. The scanning testing apparatus according to claim 1, characterized in that, The configuration array repair logic includes multiple XOR gates, which are used to XOR the configuration signal and the repair signal.

4. The scanning testing apparatus according to claim 1, characterized in that, The configuration array includes multiple shift register groups, and one shift register group generates a set of configuration signals.

5. The scanning testing apparatus according to claim 1, characterized in that, When there are multiple switching network configuration units, the number of switching network repair units is the same as the number of switching network configuration units, and one switching network configuration unit corresponds to one switching network repair unit.

6. The scanning testing apparatus according to claim 1, characterized in that, Also includes: An input switching network is used to configure the gating of input test channels based on configuration signals; The output switching network is used to configure the selection of output test channels based on configuration signals.

7. The scanning testing apparatus according to claim 6, characterized in that, Also includes: A first input interface is connected to a scanning input channel via the input switching network; The first output interface is connected to the scan output channel via the output switching network.

8. The scanning testing apparatus according to claim 7, characterized in that, Also includes: A second input interface is connected to the first input interface and an external test device. The second output interface connects the first output interface and an external test device.

9. A scanning test method, characterized in that, Applied to the scanning test apparatus as described in any one of claims 1-8, comprising: Perform scan testing on the logic to be tested; If the test fails, determine whether the reason for the test failure is that the switching network configuration array is malfunctioning. If so, the switching network configuration unit is repaired based on the switching network repair unit, and the logic to be tested is scanned and tested again.

10. A chip, characterized in that, include: The scanning test apparatus as described in any one of claims 1-8.

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