A reference voltage generation circuit for 12nm process

Abstract

The application provides a reference voltage generation circuit for a 12nm process, and relates to the technical field of integrated circuits, and comprises: a first reference circuit for generating a first reference voltage irrelevant to a power supply voltage by using a gate-source voltage difference of two transistors through a resistor based on a current mirror structure; a second reference circuit for generating a stable reference current by clamping based on an amplifier and generating a second reference voltage decreasing with temperature rising by using a positive temperature coefficient characteristic of a resistor; and an amplifier for receiving the first reference voltage, outputting a first differential voltage irrelevant to the power supply voltage, or receiving the second reference voltage, compensating the second reference voltage by using the positive temperature coefficient characteristic of the resistor, and outputting a second differential voltage with stable amplitude and irrelevant to temperature. In the reference voltage generation circuit, the two reference circuits with different focuses work together to provide local optimal references for different parts of a system, so that the optimization of system performance is realized as a whole.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a reference voltage generation circuit for 12nm process. Background Technology

[0002] With the rapid development of data-intensive applications such as cloud computing, Ethernet, mobile internet, and artificial intelligence, people's expectations for high-speed information transmission are increasing. As the core physical layer interface for data interconnection, the serializer / deserializer (SerDes) has been constantly pursuing higher data transmission rates. At the same time, the challenges to signal integrity are becoming increasingly greater.

[0003] In high-speed SerDes systems, the accuracy and stability of the voltage reference (Vref) directly determine the performance of critical analog circuits, serving as the "heartbeat" and "benchmark" for the reliable operation of the entire link.

[0004] On one hand, the reference voltage precisely controls the differential output swing of the SerDes transmitter (TX). The SerDes transmitter (TX) typically drives the output differential signal through a current source set by the reference voltage. Even small fluctuations in the reference voltage directly affect the output signal amplitude. An excessively small voltage swing reduces the signal-to-noise ratio at the receiver, significantly increasing the bit error rate; an excessively large swing causes unnecessary power consumption and electromagnetic interference (EMI), violating stringent system power consumption and radiation standards. Therefore, an extremely stable and precise reference is needed to define this differential swing. Using an amplifier whose output amplitude is temperature-independent ensures that the amplitude of the transmitted signal remains constant at different temperatures. This is crucial for meeting the amplitude specifications of high-speed interfaces, preventing amplitude attenuation at high temperatures leading to receiver misinterpretation, or excessive amplitude at low temperatures causing EMI problems.

[0005] On the other hand, SerDes circuits operate in a typical high-speed, high-switching-noise environment. High-frequency noise from the power supply can easily couple into the reference output, causing high-frequency ripple on the reference voltage. The receiver (RX) of a SerDes typically includes a receiver signal decision module, such as a sampler or comparator. It usually uses a high-speed clock to sample the receiver signal. If high-frequency noise from the power supply is directly coupled to the reference buffer providing Vref to the sampler, when a small-amplitude signal (on the decision edge) arrives, due to threshold jitter, it might be judged as "1" one time and "0" the next. This is equivalent to introducing vertical noise, directly reducing the receiver's sensitivity. Even if the transmitted eye diagram is open, the receiver will still generate bit errors due to the instability of its own decision threshold. This is fatal for communication systems that strive for extremely low bit error rates.

[0006] Based on the above, the performance of many key modules in SerDes is highly dependent on their internal bias voltage and bias current.

[0007] Existing technologies typically employ conventional bandgap reference voltage sources to generate a temperature-independent reference voltage of approximately 1.25V. To make the reference voltage independent of the power supply, self-biased operational amplifiers and startup circuits are usually used to construct a bias point independent of the power supply voltage. However, at 12nm processes, the core power supply voltage may be as low as 0.8V or lower, while the conventional bandgap reference voltage itself is approximately 1.25V, which exceeds the range of the power supply voltage, making it unsuitable for direct operation. Although low-voltage bandgap structures exist, they are generally more complex and more sensitive to matching and noise. Moreover, to achieve good matching and low noise, the core resistors and bipolar junction transistors (BJTs) in conventional bandgap reference voltage sources typically require large dimensions, and large-area analog circuitry significantly increases chip manufacturing costs. In addition, process variations at the 12nm node (such as linewidth and doping concentration) have a significant impact on circuit performance, and the accuracy of circuit simulation models provided by wafer foundries at extreme corners, especially in the subthreshold region and at high / low temperatures, may be uncertain. Meanwhile, in the 12nm process, the threshold voltage of the MOSFET was not scaled down proportionally, resulting in very tight voltage margin.

[0008] Therefore, under the 12nm process, how to realize a reference voltage generation circuit that is independent of temperature and power supply voltage for amplifier output amplitude has become an urgent problem to be solved. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, this invention provides a reference voltage generation circuit for 12nm process technology. The technical problem to be solved by this invention is achieved through the following technical solution:

[0010] This invention provides a reference voltage generation circuit for a 12nm process, comprising:

[0011] The first reference circuit is used to generate a first reference voltage independent of the power supply voltage by using the gate-source voltage difference of two transistors through a resistor based on a current mirror structure.

[0012] The second reference circuit is used to generate a stable reference current based on the amplifier clamping and to generate a second reference voltage that decreases with increasing temperature by utilizing the positive temperature coefficient of the resistor.

[0013] An amplifier is used to receive the first reference voltage and output a first differential voltage independent of the power supply voltage; or to receive the second reference voltage, compensate the second reference voltage using the positive temperature coefficient characteristic of the resistor, and output a second differential voltage with stable amplitude that is independent of temperature.

[0014] In one embodiment of the present invention, the first reference circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first adjustable resistor, a first capacitor, and a second capacitor;

[0015] The drain of the first transistor is used to input the start-up current signal, the gate of the first transistor is connected to the gate of the fifth transistor and the gate of the eighth transistor, and the source of the first transistor is connected to the drain and gate of the second transistor, the gate of the sixth transistor, and the gate of the ninth transistor.

[0016] The source of the second transistor is connected to one end of the first adjustable resistor, the source of the ninth transistor, the source of the thirteenth transistor, and is connected to the ground terminal;

[0017] The source of the third transistor is connected to the source of the seventh transistor, the source of the tenth transistor, and the source of the eleventh transistor and is connected to the power supply voltage terminal. The gate of the third transistor is connected to the drain of the third transistor, the source of the fourth transistor, and the gate of the eleventh transistor.

[0018] The gate of the fourth transistor is connected to the gate and drain of the seventh transistor, the drain of the eighth transistor, the drain of the tenth transistor, and the gate of the twelfth transistor; the drain of the fourth transistor is connected to the drain of the fifth transistor.

[0019] The source of the fifth transistor is connected to the drain of the sixth transistor;

[0020] The source of the sixth transistor is connected to the other end of the first adjustable resistor;

[0021] The source of the eighth transistor is connected to the drain of the ninth transistor;

[0022] The gate of the tenth transistor receives a first delayed signal;

[0023] The drain of the eleventh transistor is connected to the source of the twelfth transistor;

[0024] The drain of the twelfth transistor is connected to the drain and gate of the thirteenth transistor, one end of the first capacitor, one end of the second capacitor, the source of the fourteenth transistor, and the drain of the fifteenth transistor; the other ends of the first capacitor and the other ends of the second capacitor are both connected to the ground terminal.

[0025] The gate of the fourteenth transistor receives a positive signal, the gate of the fifteenth transistor receives a negative signal, and the drain of the fourteenth transistor is connected to the source of the fifteenth transistor and outputs the first reference voltage.

[0026] In one embodiment of the present invention, the first reference circuit further includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a first inverter, a second inverter, a third inverter, a third capacitor, and a fourth capacitor;

[0027] The source of the sixteenth transistor is connected to the source of the seventeenth transistor, the drain of the twenty-first transistor, the drain of the twenty-second transistor, the source of the twenty-third transistor, and the source of the twenty-sixth transistor, and is connected to the power supply voltage terminal. The gate of the sixteenth transistor is connected to the gate of the twentieth transistor and receives the second delay signal. The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the drain of the eighteenth transistor, and the input terminal of the first inverter.

[0028] The gate of the seventeenth transistor is connected to the output terminal of the second inverter and the gate of the nineteenth transistor;

[0029] The gate of the eighteenth transistor receives an enable signal, and the source of the eighteenth transistor is connected to the drain of the nineteenth transistor.

[0030] The source of the nineteenth transistor is connected to the drain of the twentieth transistor;

[0031] The source of the twentieth transistor is connected to the source of the twenty-fifth transistor and is also connected to ground.

[0032] The gate of the 21st transistor is connected to the output terminal of the first inverter and the gate of the 22nd transistor. The source of the 21st transistor is connected to the drain of the 24th transistor, the drain and gate of the 25th transistor, and the gate of the first transistor.

[0033] The source of the 22nd transistor is connected to the drain of the 27th transistor and the drain of the first transistor;

[0034] The drain of the 23rd transistor is connected to the source of the 24th transistor, and the gate of the 23rd transistor is connected to the gate of the 26th transistor and the gate of the 3rd transistor.

[0035] The gate of the 24th transistor is connected to the gate of the 27th transistor, the gate of the 4th transistor, one end of the 3rd capacitor, one end of the 4th capacitor, and the input of the 3rd inverter; the output of the 3rd inverter is connected to the input of the 2nd inverter; the other ends of the 3rd capacitor and the 4th capacitor are both connected to ground.

[0036] The drain of the 26th transistor is connected to the source of the 27th transistor.

[0037] In one embodiment of the present invention, it further includes: a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor;

[0038] The fourth inverter, the fifth inverter, the sixth inverter, and the seventh inverter are connected in series. An enable signal is input to the input terminal of the fourth inverter, the second delay signal is output to the output terminal of the fifth inverter, and the first delay signal is output to the output terminal of the seventh inverter.

[0039] One end of the fifth capacitor is connected to the output terminal of the fourth inverter, and the other end is connected to the ground terminal; one end of the sixth capacitor is connected to the output terminal of the fifth inverter, and the other end is connected to the ground terminal; one end of the seventh capacitor is connected to the output terminal of the sixth inverter, and the other end is connected to the ground terminal; one end of the eighth capacitor is connected to the output terminal of the seventh inverter, and the other end is connected to the ground terminal.

[0040] In one embodiment of the present invention, the second reference circuit includes: a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a second adjustable resistor, an operational amplifier, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, and a voltage generation circuit.

[0041] The non-inverting input terminal of the operational amplifier is connected to the drain and gate of the twenty-eighth transistor and one end of the second adjustable resistor. The inverting input terminal of the operational amplifier is connected to the output terminal of the voltage generation circuit and one end of the ninth capacitor. The output terminal of the operational amplifier is connected to one end of the tenth capacitor, the gate of the twenty-ninth transistor, one end of the eleventh capacitor, one end of the twelfth capacitor, the source of the thirtieth transistor, and the drain of the thirty-first transistor.

[0042] The other end of the second adjustable resistor is connected to the power supply voltage terminal; the source of the twenty-eighth transistor is connected to the drain of the twenty-ninth transistor; the other ends of the ninth capacitor, the tenth capacitor, the eleventh capacitor, the twelfth capacitor, and the source of the twenty-ninth transistor are all connected to the ground terminal.

[0043] The gate of the thirtieth transistor receives a negative signal, and the gate of the thirty-first transistor receives a positive signal; the drain of the thirtieth transistor is connected to the source of the thirty-first transistor and outputs the second reference voltage.

[0044] In one embodiment of the present invention, the voltage generating circuit includes: N resistors, N-1 transmission gates and a thirty-second transistor, where N is a positive integer greater than or equal to 2;

[0045] The N resistors are connected in series, with one end of the first resistor connected to the power supply voltage terminal and one end of the Nth resistor connected to the drain of the thirty-second transistor; the gate of the thirty-second transistor receives a positive signal, and the source of the thirty-second transistor is connected to the ground terminal.

[0046] The input of each transmission gate is connected between two adjacent resistors. The first control terminal receives the first control signal, the second control terminal receives the second control signal, and the output terminal is connected to the inverting input of the operational amplifier.

[0047] In one embodiment of the present invention, it further includes: an eighth inverter and a ninth inverter;

[0048] The input terminal of the eighth inverter receives a selection signal, the output terminal of the eighth inverter is connected to the input terminal of the ninth inverter and outputs the negative signal, and the output terminal of the ninth inverter outputs the positive signal.

[0049] In one embodiment of the present invention, the amplifier includes: a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a third adjustable resistor, and a fourth adjustable resistor;

[0050] The gate of the thirty-fourth transistor is connected to the output terminal of the first reference circuit and the output terminal of the second reference circuit. The source of the thirty-fourth transistor is connected to the ground terminal. The drain of the thirty-fourth transistor is connected to the source of the thirty-third transistor and the source of the thirty-fifth transistor.

[0051] The gate of the thirty-third transistor receives a first signal, and the drain of the thirty-third transistor is connected to one end of a fourth adjustable resistor and outputs a first voltage.

[0052] The gate of the thirty-fifth transistor receives a second signal, and the drain of the thirty-fifth transistor is connected to one end of a third adjustable resistor and outputs a second voltage; the differential voltage output by the amplifier is the difference between the first voltage and the second voltage.

[0053] The other end of the third adjustable resistor and the other end of the fourth adjustable resistor are both connected to the power supply voltage terminal.

[0054] In one embodiment of the present invention, the amplitude of the differential voltage output by the amplifier is:

[0055]

[0056] in, The first voltage, For the second voltage, The current of the thirty-fourth transistor, This is the resistance value of the third adjustable resistor. This is the resistance value of the fourth adjustable resistor. For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. The channel width of the thirty-fourth transistor. The channel length of the thirty-fourth transistor. This is the gate voltage of the thirty-fourth transistor. This is the threshold voltage of the thirty-fourth transistor.

[0057] In one embodiment of the present invention, the amplifier includes: a thirty-sixth transistor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a fifth adjustable resistor, a sixth adjustable resistor, a first resistor, and a thirteenth capacitor;

[0058] The gate of the thirty-sixth transistor is connected to the gate of the thirty-seventh transistor, the output terminal of the first reference circuit, and the output terminal of the second reference circuit; the source of the thirty-sixth transistor and the source of the thirty-seventh transistor are both connected to ground; the drain of the thirty-sixth transistor is connected to one end of the thirteenth capacitor, one end of the first resistor, and the source of the thirty-eighth transistor; the source of the thirty-seventh transistor is connected to the other end of the thirteenth capacitor, the other end of the first resistor, and the source of the thirty-ninth transistor.

[0059] The gate of the thirty-ninth transistor receives a first signal, and the drain of the thirty-ninth transistor is connected to one end of the sixth adjustable resistor and outputs a first voltage.

[0060] The gate of the thirty-eighth transistor receives a second signal, and the drain of the thirty-eighth transistor is connected to one end of the fifth adjustable resistor and outputs a second voltage.

[0061] The other end of the fifth adjustable resistor and the other end of the sixth adjustable resistor are both connected to the power supply voltage terminal.

[0062] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0063] In the reference voltage generation circuit of this invention, the first reference circuit is based on a current mirror structure. It uses the gate-source voltage difference of two transistors to provide a reference voltage to the amplifier that is independent of the power supply voltage through a resistor. The second reference circuit generates a second reference voltage that decreases with increasing temperature and compensates for the second reference voltage through the amplifier. This allows the amplifier to maintain a stable output amplitude over a wide temperature range and output a temperature-independent voltage. The first reference circuit provides a reference for critical paths that are extremely sensitive to power supply noise, while the second reference circuit provides a reference for modules that require stable bias over a wide temperature range. By having two reference circuits with different focuses work together, locally optimal references are provided for different parts of the system, thereby optimizing the overall system performance. Compared with traditional reference circuits, this method saves a lot of area and reduces costs. Attached Figure Description

[0064] Figure 1 A schematic diagram of a reference voltage generation circuit for 12nm process provided in an embodiment of the present invention;

[0065] Figure 2 This is a schematic diagram of the structure of a first reference circuit provided in an embodiment of the present invention;

[0066] Figure 3 This is a schematic diagram of an enable signal generation circuit provided in an embodiment of the present invention;

[0067] Figure 4This is a schematic diagram of the structure of a second reference circuit provided in an embodiment of the present invention;

[0068] Figure 5 A schematic diagram of a control signal generation circuit provided in an embodiment of the present invention;

[0069] Figure 6 A schematic diagram of the circuit structure of an amplifier provided in an embodiment of the present invention;

[0070] Figure 7 This is a schematic diagram of the circuit structure of another amplifier provided in an embodiment of the present invention. Detailed Implementation

[0071] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0072] Example 1

[0073] Please see Figure 1 , Figure 1 This is a schematic diagram of a reference voltage generation circuit for 12nm process provided in an embodiment of the present invention.

[0074] This embodiment of the reference voltage generation circuit for 12nm process includes a first reference circuit 1, a second reference circuit 2, and an amplifier 3. The first reference circuit 1 uses a current mirror structure to generate a first reference voltage independent of the power supply voltage by utilizing the gate-source voltage difference of two transistors through a resistor. The second reference circuit 2 generates a stable reference current based on the clamping of the amplifier and generates a second reference voltage that decreases with increasing temperature by utilizing the positive temperature coefficient of the resistor. The amplifier 3 receives the first reference voltage and outputs a first differential voltage independent of the power supply voltage; or it receives the second reference voltage, compensates for the second reference voltage using the positive temperature coefficient of the resistor, and outputs a second differential voltage with stable amplitude that is independent of temperature.

[0075] Please see Figure 2 , Figure 2 This is a schematic diagram of a first reference circuit provided in an embodiment of the present invention.

[0076] The first reference circuit 1 includes: a first transistor M12, a second transistor M13, a third transistor M14, a fourth transistor M15, a fifth transistor M16, a sixth transistor M17, a seventh transistor M18, an eighth transistor M19, a ninth transistor M20, a tenth transistor M21, an eleventh transistor M22, a twelfth transistor M23, a thirteenth transistor M24, a fourteenth transistor M25, a fifteenth transistor M26, a first adjustable resistor R0, a first capacitor C2, and a second capacitor C3.

[0077] Specifically, the drain of the first transistor M12 is used to input the start-up current signal. The gate of the first transistor M12 is connected to the gate of the fifth transistor M16 and the gate of the eighth transistor M19. The source of the first transistor M12 is connected to the drain and gate of the second transistor M13, the gate of the sixth transistor M17, and the gate of the ninth transistor M20. The source of the second transistor M13 is connected to one end of the first adjustable resistor R0, the source of the ninth transistor M20, the source of the thirteenth transistor M24, and is connected to the ground terminal GND. The source of the third transistor M14 is connected to the source of the seventh transistor M18, the source of the tenth transistor M21, and the source of the eleventh transistor M22, and is connected to the power supply voltage terminal VDD. The gate of the third transistor M14 is connected to the drain of the third transistor M14, the source of the fourth transistor M15, and the gate of the eleventh transistor M22. The gate of the fourth transistor M15 is connected to the gate and drain of the seventh transistor M18, the drain of the eighth transistor M19, the drain of the tenth transistor M21, and the twelfth transistor M20. The gate of transistor 3 is connected to the drain of the fourth transistor M15, which is connected to the drain of the fifth transistor M16; the source of the fifth transistor M16 is connected to the drain of the sixth transistor M17; the source of the sixth transistor M17 is connected to the other end of the first adjustable resistor R0; the source of the eighth transistor M19 is connected to the drain of the ninth transistor M20; the gate of the tenth transistor M21 receives the first delayed signal ENP2; the drain of the eleventh transistor M22 is connected to the source of the twelfth transistor M23; the drain of the twelfth transistor M23 is connected to the tenth transistor M20. The drain and gate of transistor M24, one end of the first capacitor C2, one end of the second capacitor C3, the source of the fourteenth transistor M25, and the drain of the fifteenth transistor M26; the other ends of the first capacitor C2 and the second capacitor C3 are both connected to the ground terminal; the gate of the fourteenth transistor M25 receives a positive signal S_P, the gate of the fifteenth transistor M26 receives a negative signal S_N, the drain of the fourteenth transistor M25 is connected to the source of the fifteenth transistor M26 and outputs the first reference voltage Vref1.

[0078] Specifically, the connection point between the gate of the second transistor M13 and the gate of the sixth transistor M17 is designated as point H, the connection point between the drain of the third transistor M14 and the source of the fourth transistor M15 is designated as point I, and the connection point between the drain of the twelfth transistor M23 and the drain of the thirteenth transistor M24 is designated as point K.

[0079] The first reference circuit 1 further includes: a sixteenth transistor M0, a seventeenth transistor M1, an eighteenth transistor M2, a nineteenth transistor M3, a twentieth transistor M4, a twenty-first transistor M5, a twenty-second transistor M6, a twenty-third transistor M7, a twenty-fourth transistor M8, a twenty-fifth transistor M9, a twenty-sixth transistor M10, a twenty-seventh transistor M11, a first inverter INV0, a ​​second inverter INV1, a third inverter INV2, a third capacitor C0, and a fourth capacitor C1.

[0080] Specifically, the source of the sixteenth transistor M0 is connected to the source of the seventeenth transistor M1, the drain of the twenty-first transistor M5, the drain of the twenty-second transistor M6, the source of the twenty-third transistor M7, and the source of the twenty-sixth transistor M10, and is connected to the power supply voltage terminal VDD. The gate of the sixteenth transistor M0 is connected to the gate of the twentieth transistor M4 and receives the second delay signal ENP0. The drain of the sixteenth transistor M0 is connected to the drain of the seventeenth transistor M1, the drain of the eighteenth transistor M2, and the input terminal of the first inverter INV0. The gate of the seventeenth transistor M1 is connected to the output terminal of the second inverter INV1 and the gate of the nineteenth transistor M3. The gate of the eighteenth transistor M2 receives the enable signal EN. The source of the eighteenth transistor M2 is connected to the drain of the nineteenth transistor M3. The source of the nineteenth transistor M3 is connected to the drain of the twentieth transistor M4. The source of the twentieth transistor M4 is connected to the source of the twenty-fifth transistor M9 and is connected to the ground terminal GND. The gate of the twenty-first transistor M5 is connected to the first inverter. The output terminal of inverter INV0, the gate of the twenty-second transistor M6, and the source of the twenty-first transistor M5 are connected to the drain of the twenty-fourth transistor M8, the drain and gate of the twenty-fifth transistor M9, and the gate of the first transistor M12; the source of the twenty-second transistor M6 is connected to the drain of the twenty-seventh transistor M11 and the drain of the first transistor M12; the drain of the twenty-third transistor M7 is connected to the source of the twenty-fourth transistor M8, and the gate of the twenty-third transistor M7 is connected to the gate of the twenty-sixth transistor M10 and the gate of the third transistor M14; the gate of the twenty-fourth transistor M8 is connected to the gate of the twenty-seventh transistor M11, the gate of the fourth transistor M15, one end of the third capacitor C0, one end of the fourth capacitor C1, and the input terminal of the third inverter INV2; the output terminal of the third inverter INV2 is connected to the input terminal of the second inverter INV1; the other end of the third capacitor C0 and the other end of the fourth capacitor C1 are both connected to ground; the drain of the twenty-sixth transistor M10 is connected to the source of the twenty-seventh transistor M11.

[0081] Specifically, the connection point between the gate of the sixteenth transistor M0 and the gate of the twentieth transistor M4 is designated as point A; the connection point between the drain of the seventeenth transistor M1 and the drain of the eighteenth transistor M2 is designated as point B; the connection point between the gate of the seventeenth transistor M1 and the gate of the nineteenth transistor M3 is designated as point C; the connection point between the gate of the twenty-first transistor M5 and the output terminal of the first inverter INV0 is designated as point D; the connection point between the drain of the twenty-fourth transistor M8 and the drain of the twenty-fifth transistor M9 is designated as point E; the connection point between the gate of the twenty-fourth transistor M8 and the gate of the twenty-seventh transistor M11 is designated as point F; and the connection point between the drain of the twenty-seventh transistor M11 and the drain of the first transistor M12 is designated as point G.

[0082] Please see Figure 3 , Figure 3 This is a schematic diagram of an enable signal generation circuit provided in an embodiment of the present invention. The enable signal generation circuit provides an enable signal EN, a second delay signal ENP0, and a first delay signal ENP2 to a first reference circuit, and includes: a fourth inverter INV3, a fifth inverter INV4, a sixth inverter INV5, a seventh inverter INV6, a fifth capacitor C8, a sixth capacitor C9, a seventh capacitor C10, and an eighth capacitor C11.

[0083] Specifically, the fourth inverter INV3, the fifth inverter INV4, the sixth inverter INV5, and the seventh inverter INV6 are connected in series. The input terminal of the fourth inverter INV3 receives the enable signal EN, the output terminal of the fifth inverter INV4 outputs the second delayed signal ENP0, and the output terminal of the seventh inverter INV6 outputs the first delayed signal ENP2. One end of the fifth capacitor C8 is connected to the output terminal of the fourth inverter INV3, and the other end is connected to the ground terminal. One end of the sixth capacitor C9 is connected to the output terminal of the fifth inverter INV4, and the other end is connected to the ground terminal. One end of the seventh capacitor C10 is connected to the output terminal of the sixth inverter INV5, and the other end is connected to the ground terminal. One end of the eighth capacitor C11 is connected to the output terminal of the seventh inverter INV6, and the other end is connected to the ground terminal.

[0084] Please see Figure 4 , Figure 4 This is a schematic diagram of a second reference circuit provided in an embodiment of the present invention. The second reference circuit 2 includes: a twenty-eighth transistor M27, a twenty-ninth transistor M28, a thirtieth transistor M29, a thirty-first transistor M30, a second adjustable resistor R10, an operational amplifier AMP, a ninth capacitor C4, a tenth capacitor C5, an eleventh capacitor C6, a twelfth capacitor C7, and a voltage generation circuit 21.

[0085] Specifically, the non-inverting input of the operational amplifier AMP is connected to the drain and gate of the twenty-eighth transistor M27, and one end of the second adjustable resistor R10. The inverting input of the operational amplifier AMP is connected to the output of the voltage generation circuit 21, and one end of the ninth capacitor C4. The output of the operational amplifier AMP is connected to one end of the tenth capacitor C5, the gate of the twenty-ninth transistor M28, one end of the eleventh capacitor C6, one end of the twelfth capacitor C7, the source of the thirtieth transistor M29, and the drain of the thirty-first transistor M30. The other end of the second adjustable resistor R10 is connected to... The power supply voltage terminal is VDD; the source of the twenty-eighth transistor M27 is connected to the drain of the twenty-ninth transistor M28; the other ends of the ninth capacitor C4, the tenth capacitor C5, the eleventh capacitor C6, the twelfth capacitor C7, and the source of the twenty-ninth transistor M28 are all connected to the ground terminal; the gate of the thirtieth transistor M29 receives a negative signal S_N, and the gate of the thirty-first transistor M30 receives a positive signal S_P; the drain of the thirtieth transistor M29 is connected to the source of the thirty-first transistor M30 and outputs the second reference voltage Vref2.

[0086] Specifically, the connection point between the output of the operational amplifier AMP and the gate of the twenty-ninth transistor M28 is designated as point M, and the connection point between the drain of the twenty-eighth transistor M27 and the non-inverting input of the operational amplifier AMP is designated as point N.

[0087] Furthermore, the voltage generation circuit 21 includes: N resistors, N-1 transmission gates, and a thirty-second transistor M31, where N is a positive integer greater than or equal to 2.

[0088] Specifically, N resistors are connected in series, with one end of the first resistor connected to the power supply voltage terminal VDD and one end of the Nth resistor connected to the drain of the thirty-second transistor M31. The gate of the thirty-second transistor M31 receives a positive signal S_P, and the source of the thirty-second transistor M31 is connected to the ground terminal. The input terminal of each transmission gate is connected between two adjacent resistors, the first control terminal receives the first control signal SW, the second control terminal receives the second control signal SWN, and the output terminal is connected to the inverting input terminal of the operational amplifier AMP.

[0089] For example, N=9, that is, the voltage generation circuit 21 includes 9 resistors R1~R9 and 8 transmission gates TGA~TGH, and the output terminals of the 8 transmission gates TGA~TGH respectively output voltage signals Vref A, Vref B, ..., Vref H.

[0090] Please see Figure 5 , Figure 5This is a schematic diagram of a control signal generation circuit provided in an embodiment of the present invention. Specifically, the control signal generation circuit includes an eighth inverter INV7 and a ninth inverter INV8. The input terminal of the eighth inverter INV7 receives a selection signal S, the output terminal of the eighth inverter INV7 is connected to the input terminal of the ninth inverter INV8 and outputs a negative signal S_N, and the output terminal of the ninth inverter INV8 outputs a positive signal S_P.

[0091] Please see Figure 6 , Figure 6 This is a schematic diagram of the circuit structure of an amplifier provided in an embodiment of the present invention. Figure 6 The amplifier 3 shown includes: the thirty-third transistor M32, the thirty-fourth transistor M33, the thirty-fifth transistor M34, the third adjustable resistor R11, and the fourth adjustable resistor R12.

[0092] Specifically, the gate of the thirty-fourth transistor M33 is connected to the output terminal of the first reference circuit 1 and the output terminal of the second reference circuit 2; the source of the thirty-fourth transistor M33 is connected to the ground terminal GND; and the drain of the thirty-fourth transistor M33 is connected to the source of the thirty-third transistor M32 and the source of the thirty-fifth transistor M34. The gate of the thirty-third transistor M32 receives the first signal VM, and the drain of the thirty-third transistor M32 is connected to one end of the fourth adjustable resistor R12 and outputs the first voltage VOP. The gate of the thirty-fifth transistor M34 receives the second signal VP, and the drain of the thirty-fifth transistor M34 is connected to one end of the third adjustable resistor R11 and outputs the second voltage VOM. The differential voltage output by the amplifier 3 is the difference between the first voltage VOP and the second voltage VOM. The other ends of the third adjustable resistor R11 and the fourth adjustable resistor R12 are both connected to the power supply voltage terminal VDD.

[0093] Please see Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of another amplifier provided in an embodiment of the present invention. Figure 7 The amplifier shown includes: the thirty-sixth transistor M35, the thirty-seventh transistor M36, the thirty-eighth transistor M37, the thirty-ninth transistor M38, the fifth adjustable resistor R13, the sixth adjustable resistor R14, the first resistor RS, and the thirteenth capacitor C12.

[0094] Specifically, the gate of the thirty-sixth transistor M35 is connected to the gate of the thirty-seventh transistor M36, the output terminal of the first reference circuit 1, and the output terminal of the second reference circuit 2; the sources of the thirty-sixth transistor M35 and the thirty-seventh transistor M36 are both connected to the ground terminal GND; the drain of the thirty-sixth transistor M35 is connected to one end of the thirteenth capacitor C12, one end of the first resistor RS, and the source of the thirty-eighth transistor M37; the source of the thirty-seventh transistor M36 is connected to the other end of the thirteenth capacitor C12, the other end of the first resistor RS, and the source of the thirty-ninth transistor M38; the gate of the thirty-ninth transistor M38 receives the first signal VM, and the drain of the thirty-ninth transistor M38 is connected to one end of the sixth adjustable resistor R14 and outputs the first voltage VOP; the gate of the thirty-eighth transistor M37 receives the second signal VP, and the drain of the thirty-eighth transistor M37 is connected to one end of the fifth adjustable resistor R13 and outputs the second voltage VOM; the other ends of the fifth adjustable resistor R13 and the sixth adjustable resistor R14 are both connected to the power supply voltage terminal VDD.

[0095] The operation process of the reference voltage generation circuit for the 12nm process in this embodiment is as follows:

[0096] When the first reference circuit 1 is working, the control signal S=0, the negative signal S_N=1, the positive signal S_P=0, the fourteenth transistor M25 and the fifteenth transistor M26 are turned on, and the amplifier 3 receives the first reference voltage Vref1 generated by the first reference circuit 1 as the reference voltage.

[0097] In the first reference circuit 1, the difference between the gate-source voltages of the second transistor M13 and the sixth transistor M17 is used to determine a unique and accurate current, i.e. ,have Therefore, it is evident that the current is independent of the power supply voltage. The eleventh transistor M22 can precisely replicate k1. ,have Furthermore, there are The thirty-fourth transistor M33 is a precise copy of the thirteenth transistor M24 at a ratio of k2. Therefore, the reference voltage of amplifier 3 remains stable and does not change with the power supply voltage. Thus, the first reference circuit 1 replicates the current through a current mirror, achieves the required gain of amplifier 3 by adjusting the first adjustable resistor R0, and accurately replicates the current proportionally, providing amplifier 3 with a reference voltage independent of the power supply voltage.

[0098] Furthermore, when the power supply voltage is applied, the current in the circuit is 0, and the circuit will remain stable in a state with a current of 0. Therefore, it is necessary to break this state, that is, to add a starting circuit. The specific working process is as follows:

[0099] When the power supply is first turned on, the enable signal EN starts the circuit. Capacitors C8~C11 are slowly charging, so the first delay signal ENP2 remains at a low level. The tenth transistor M21 is turned on, pulling the voltage at point J to a high level. After passing through two stages of inverters INV1 and INV2, the voltage at point C is at a high level. The nineteenth transistor M3 is turned on. Since the enable signal EN is high from the beginning, the voltage at point B is pulled to a low level. After passing through one stage of inverter INV0, the voltage at point D is at a high level. The twenty-first transistor M5 and the twenty-second transistor M6 are turned on, and current begins to flow into point E, thus starting the circuit.

[0100] When the circuit is working normally, the voltage at point J is pulled low. After passing through two inverters INV1 and INV2, the voltage at point C is low, and the seventeenth transistor M1 is turned on. The voltage at point B is pulled high, and after passing through one inverter INV0, the voltage at point D is low. The twenty-first transistor M5 and the twenty-second transistor M6 are turned off, the startup circuit is shut down, and the entire circuit startup process is completed.

[0101] The first reference circuit in this embodiment can optimize the power supply rejection ratio and significantly reduce the bit error rate caused by power supply noise.

[0102] When the second reference circuit 2 is working, the control signal S=1, the negative signal S_N=0, the positive signal S_P=1, the thirtieth transistor M29 and the thirty-first transistor M30 are turned on, and the amplifier 3 receives the second reference voltage Vref2 generated by the second reference circuit 2 as the reference voltage.

[0103] An external control circuit (such as a 3 / 8 decoder) selects and opens different transmission gates TGA, TGB, ..., TGH, generating different reference voltages Vref A, Vref B, ..., Vref H through resistor division, which are then sent to the inverting input of the operational amplifier AMP. Utilizing the op-amp's "virtual short," a stable voltage equal to Vref A, Vref B, ..., Vref H is also generated at point N. The ninth capacitor, C4, is used for filtering and voltage regulation, ensuring a stable and clean Vref A, Vref B, ..., Vref H.

[0104] On the branch of the twenty-eighth transistor M27, there is Since the power supply voltage and Vref A, Vref B, ..., Vref H are all stable, their difference VDD - Vref A:H also remains stable. Therefore, the generated reference current Iref1 also remains stable. When the temperature changes, because the resistance exhibits a positive temperature coefficient, that is, the resistance increases with increasing temperature, Iref1 decreases with increasing temperature. When Iref1 decreases, according to the saturation current formula:

[0105] ;

[0106] in, For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. The channel width of the twenty-ninth transistor. The channel length of the twenty-ninth transistor. This is the gate voltage of the twenty-ninth transistor. This is the threshold voltage of the twenty-ninth transistor.

[0107] Therefore, the gate voltage of the twenty-ninth transistor M28 That is, the voltage Vref 2 at point M also decreases, and vice versa.

[0108] when Figure 6 When amplifier 3 is selected as the second reference voltage Vref2, the gate voltage of the twenty-ninth transistor M28 is... As temperature increases, the voltage decreases, which is the gate voltage of the thirty-fourth transistor M33. It also decreases accordingly. The amplitude of the differential voltage output by amplifier 3 is:

[0109] ;

[0110] in, The first voltage, For the second voltage, The current of the thirty-fourth transistor, This is the resistance value of the third adjustable resistor. This is the resistance value of the fourth adjustable resistor. For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. The channel width of the thirty-fourth transistor. The channel length of the thirty-fourth transistor. This is the gate voltage of the thirty-fourth transistor. This is the threshold voltage of the thirty-fourth transistor.

[0111] From the above analysis, it can be seen that the gate voltage of the thirty-fourth transistor M33 is... While the resistance decreases with increasing temperature, due to the positive temperature coefficient of resistance, the resistances of R11 and R12 increase with increasing temperature. Therefore, the amplitude of the output voltage of amplifier 3 remains stable and does not change with temperature, thus achieving stable output amplitude over a wide temperature range. Similarly, Figure 7 The amplifier 3 shown maintains stable output amplitude over a wide temperature range.

[0112] The second reference circuit in this embodiment can optimize temperature stability and significantly reduce the bit error rate caused by excessively small or large amplitude due to temperature changes.

[0113] This embodiment uses a reference voltage generation circuit for 12nm process technology to provide a reference voltage for out-of-band (OOB), Joint Test Action Group (JTAG), and receiver detection (RX detection) circuits. These circuits do not need to generate signals completely independent of temperature and power supply voltage; they only need to produce simple responses. Taking the OOB signal as an example, its functions are: first, link reliability detection: initially, when TX and RX interact, a "handshake" is required, and a successful handshake indicates link reliability; second, response to sudden events: if one of the TX or RX sides experiences an important event and wants to quickly notify the other, this notification is sent before any "normal" data already queued for transmission. Therefore, both the receiver and transmitter only need to respond to the signal sent by the other, typically a low-to-high, sustained high (high level with the same width as the received data) response. Under these conditions, the amplifier can achieve an "optimal" reference based on specific emphasis (temperature-independent or power supply voltage-independent) to reduce area and save costs.

[0114] The reference voltage generation circuit used in this embodiment for the 12nm process can also provide a reference for the RX's continuous-time linear equalizer (CTLE) and variable-gain amplifier (VGA), which typically have certain requirements for data amplitude. Using a temperature-independent reference voltage to bias these equalizers ensures that their output amplitude remains stable throughout the operating temperature range, avoiding problems such as under-equalization (causing inter-symbol interference) or over-equalization (amplifying noise) caused by temperature variations, thereby stabilizing the opening of the receiving eye.

[0115] In the reference voltage generation circuit of this invention, the first reference circuit provides a reference voltage to the amplifier that is independent of the power supply voltage through a current mirror structure. The second reference circuit generates a second reference voltage that decreases with increasing temperature and compensates for the second reference voltage through the amplifier. This enables the amplifier to maintain a stable output amplitude over a wide temperature range and output a temperature-independent voltage. The first reference circuit provides a reference for critical paths that are extremely sensitive to power supply noise, while the second reference circuit provides a reference for modules that require stable bias over a wide temperature range. By having two reference circuits with different focuses work together, locally optimal references are provided for different parts of the system, thereby optimizing the overall system performance. Compared with traditional reference circuits, this method saves a lot of area and reduces costs.

[0116] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A reference voltage generation circuit for 12nm process, characterized in that, include: The first reference circuit is used to generate a first reference voltage independent of the power supply voltage by using the gate-source voltage difference of two transistors through a resistor based on a current mirror structure. The second reference circuit is used to generate a stable reference current based on the amplifier clamping and to generate a second reference voltage that decreases with increasing temperature by utilizing the positive temperature coefficient of the resistor. An amplifier is used to receive the first reference voltage and output a first differential voltage independent of the power supply voltage; or to receive the second reference voltage, compensate the second reference voltage using the positive temperature coefficient characteristic of the resistor, and output a second differential voltage with stable amplitude that is independent of temperature. The first reference circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a first adjustable resistor, a first capacitor, and a second capacitor. The drain of the first transistor is connected to the drain of the twenty-seventh transistor, and the gate of the first transistor is connected to the gate of the fifth transistor and the gate of the eighth transistor. The source of the transistor is connected to the drain and gate of the second transistor, the gate of the sixth transistor, and the gate of the ninth transistor; the source of the second transistor is connected to one end of the first adjustable resistor, the source of the ninth transistor, and the source of the thirteenth transistor and is connected to ground; the source of the third transistor is connected to the source of the seventh transistor, the source of the tenth transistor, the source of the eleventh transistor, the source of the twenty-third transistor, and the source of the twenty-sixth transistor and is connected to the power supply voltage terminal; the gate of the third transistor is connected to the drain of the third transistor, the source of the fourth transistor, the gate of the eleventh transistor, the gate of the twenty-third transistor, and the gate of the twenty-sixth transistor; the fourth The gate of the transistor is connected to the gate and drain of the seventh transistor, the drain of the eighth transistor, the drain of the tenth transistor, the gate of the twelfth transistor, the gate of the twenty-fourth transistor, and the gate of the twenty-seventh transistor; the drain of the fourth transistor is connected to the drain of the fifth transistor; the source of the fifth transistor is connected to the drain of the sixth transistor; the source of the sixth transistor is connected to the other end of the first adjustable resistor; the source of the eighth transistor is connected to the drain of the ninth transistor; the gate of the tenth transistor receives a first delayed signal; the drain of the eleventh transistor is connected to the source of the twelfth transistor; the drain of the twelfth transistor is connected to the drain and gate of the thirteenth transistor; and the first... One end of the first capacitor, one end of the second capacitor, the source of the fourteenth transistor, and the drain of the fifteenth transistor; the other ends of the first capacitor and the second capacitor are both connected to ground; the gate of the fourteenth transistor receives a positive signal, the gate of the fifteenth transistor receives a negative signal, the drain of the fourteenth transistor is connected to the source of the fifteenth transistor and outputs the first reference voltage; the drain of the twenty-third transistor is connected to the source of the twenty-fourth transistor; the drain of the twenty-sixth transistor is connected to the source of the twenty-seventh transistor; the drain of the twenty-fourth transistor is connected to the drain and gate of the twenty-fifth transistor; the source of the twenty-fifth transistor is connected to ground. The second reference circuit includes: a 28th transistor, a 29th transistor, a 30th transistor, a 31st transistor, a second adjustable resistor, an operational amplifier, a 9th capacitor, a 10th capacitor, an 11th capacitor, a 12th capacitor, and a voltage generation circuit. The non-inverting input of the operational amplifier is connected to the drain and gate of the 28th transistor and one end of the second adjustable resistor. The inverting input of the operational amplifier is connected to the output of the voltage generation circuit and one end of the 9th capacitor. The output of the operational amplifier is connected to one end of the 10th capacitor, the gate of the 29th transistor, one end of the 11th capacitor, one end of the 12th capacitor, the source of the 30th transistor, and the drain of the 31st transistor. The other end of the second adjustable resistor is connected to a power supply voltage terminal. The source of the 28th transistor is connected to the drain of the 29th transistor. The other ends of the 9th, 10th, 11th, and 12th capacitors, and the source of the 29th transistor are all connected to ground. The gate of the 30th transistor receives a negative signal, and the gate of the 31st transistor receives a positive signal. The drain of the 30th transistor is connected to the source of the 31st transistor and outputs the second reference voltage.

2. The reference voltage generation circuit for 12nm process according to claim 1, characterized in that, The first reference circuit further includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a first inverter, a second inverter, a third inverter, a third capacitor, and a fourth capacitor, wherein, The source of the sixteenth transistor is connected to the source of the seventeenth transistor, the drain of the twenty-first transistor, and the drain of the twenty-second transistor, and is connected to the power supply voltage terminal. The gate of the sixteenth transistor is connected to the gate of the twentieth transistor and receives the second delay signal. The drain of the sixteenth transistor is connected to the drain of the seventeenth transistor, the drain of the eighteenth transistor, and the input terminal of the first inverter. The gate of the seventeenth transistor is connected to the output terminal of the second inverter and the gate of the nineteenth transistor; The gate of the eighteenth transistor receives an enable signal, and the source of the eighteenth transistor is connected to the drain of the nineteenth transistor. The source of the nineteenth transistor is connected to the drain of the twentieth transistor; The source of the twentieth transistor is connected to the ground terminal; The gate of the 21st transistor is connected to the output terminal of the first inverter and the gate of the 22nd transistor, and the source of the 21st transistor is connected to the drain of the 24th transistor and the gate of the first transistor. The source of the 22nd transistor is connected to the drain of the 27th transistor; The gate of the 24th transistor is connected to one end of the third capacitor, one end of the fourth capacitor, and the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the second inverter; the other ends of the third capacitor and the other ends of the fourth capacitor are both connected to the ground terminal.

3. The reference voltage generation circuit for 12nm process according to claim 2, characterized in that, It also includes: a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor, among which, The fourth inverter, the fifth inverter, the sixth inverter, and the seventh inverter are connected in series. An enable signal is input to the input terminal of the fourth inverter, the second delay signal is output to the output terminal of the fifth inverter, and the first delay signal is output to the output terminal of the seventh inverter. One end of the fifth capacitor is connected to the output terminal of the fourth inverter, and the other end is connected to the ground terminal; one end of the sixth capacitor is connected to the output terminal of the fifth inverter, and the other end is connected to the ground terminal; one end of the seventh capacitor is connected to the output terminal of the sixth inverter, and the other end is connected to the ground terminal; one end of the eighth capacitor is connected to the output terminal of the seventh inverter, and the other end is connected to the ground terminal.

4. The reference voltage generation circuit for 12nm process according to claim 1, characterized in that, The voltage generation circuit includes: N resistors, N-1 transmission gates, and a thirty-second transistor, where N is a positive integer greater than or equal to 2. The N resistors are connected in series, with one end of the first resistor connected to the power supply voltage terminal and one end of the Nth resistor connected to the drain of the thirty-second transistor; the gate of the thirty-second transistor receives a positive signal, and the source of the thirty-second transistor is connected to the ground terminal. The input of each transmission gate is connected between two adjacent resistors. The first control terminal receives the first control signal, the second control terminal receives the second control signal, and the output terminal is connected to the inverting input of the operational amplifier.

5. The reference voltage generation circuit for 12nm process according to claim 1, 2, or 4, characterized in that, It also includes: the eighth inverter and the ninth inverter, wherein, The input terminal of the eighth inverter receives a selection signal, the output terminal of the eighth inverter is connected to the input terminal of the ninth inverter and outputs the negative signal, and the output terminal of the ninth inverter outputs the positive signal.

6. The reference voltage generation circuit for 12nm process according to claim 1, characterized in that, The amplifier includes: a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a third adjustable resistor, and a fourth adjustable resistor, wherein, The gate of the thirty-fourth transistor is connected to the output terminal of the first reference circuit and the output terminal of the second reference circuit. The source of the thirty-fourth transistor is connected to the ground terminal. The drain of the thirty-fourth transistor is connected to the source of the thirty-third transistor and the source of the thirty-fifth transistor. The gate of the thirty-third transistor receives a first signal, and the drain of the thirty-third transistor is connected to one end of a fourth adjustable resistor and outputs a first voltage. The gate of the thirty-fifth transistor receives a second signal, and the drain of the thirty-fifth transistor is connected to one end of a third adjustable resistor and outputs a second voltage; the differential voltage output by the amplifier is the difference between the first voltage and the second voltage. The other end of the third adjustable resistor and the other end of the fourth adjustable resistor are both connected to the power supply voltage terminal.

7. The reference voltage generation circuit for 12nm process according to claim 6, characterized in that, The amplitude of the differential voltage output by the amplifier is: in, The first voltage, For the second voltage, The current of the thirty-fourth transistor, This is the resistance value of the third adjustable resistor. This is the resistance value of the fourth adjustable resistor. For carrier mobility, The capacitance per unit area of ​​the gate oxide layer. The channel width of the thirty-fourth transistor. The channel length of the thirty-fourth transistor. This is the gate voltage of the thirty-fourth transistor. This is the threshold voltage of the thirty-fourth transistor.

8. The reference voltage generation circuit for 12nm process according to claim 1, characterized in that, The amplifier includes: a thirty-sixth transistor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a fifth adjustable resistor, a sixth adjustable resistor, a first resistor, and a thirteenth capacitor, wherein... The gate of the thirty-sixth transistor is connected to the gate of the thirty-seventh transistor, the output terminal of the first reference circuit, and the output terminal of the second reference circuit; the source of the thirty-sixth transistor and the source of the thirty-seventh transistor are both connected to ground; the drain of the thirty-sixth transistor is connected to one end of the thirteenth capacitor, one end of the first resistor, and the source of the thirty-eighth transistor; the source of the thirty-seventh transistor is connected to the other end of the thirteenth capacitor, the other end of the first resistor, and the source of the thirty-ninth transistor. The gate of the thirty-ninth transistor receives a first signal, and the drain of the thirty-ninth transistor is connected to one end of the sixth adjustable resistor and outputs a first voltage. The gate of the thirty-eighth transistor receives a second signal, and the drain of the thirty-eighth transistor is connected to one end of the fifth adjustable resistor and outputs a second voltage. The other end of the fifth adjustable resistor and the other end of the sixth adjustable resistor are both connected to the power supply voltage terminal.

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