Data transmission method and device based on solid state disk, medium and product

Abstract

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of solid state disks, in particular to a data transmission method and device based on a solid state disk, medium and product. BACKGROUND

[0002] With the popularity of data-intensive applications, solid state disks (SSD) have become mainstream storage devices due to their high read / write speed. In the traditional data transmission mode, the central processing unit (CPU) of the host deeply participates in the entire I / O (input / output) process, that is, the CPU needs to read data from the system memory and then write the read data to the controller of the solid state disk. This way, when facing the high bandwidth of the SSD, it will occupy a large amount of CPU resources, limit the computing efficiency of the upper application, and form a performance bottleneck.

[0003] In order to solve the problem of excessive CPU overhead in the data transmission process, the existing technology generally uses the direct memory access (DMA) technology. DMA allows the SSD controller to exchange data directly with the system memory without the continuous intervention of the CPU. The CPU only needs to set the data source address, target address and transmission size and other parameters before transmission, and then the DMA controller is fully responsible for data transfer and notifies the CPU of the completion of transmission through an interrupt. In this way, the CPU only needs to be set at the beginning of transmission, and then it can focus on computing tasks, thereby significantly improving system efficiency.

[0004] However, although DMA reduces the load of the CPU, it also has limitations. DMA lacks semantic awareness of data and cannot distinguish the content of different life cycles within the data block (for example, long-lived metadata and short-lived temporary data). The host system understands these differences, but cannot inform the SSD through DMA. This causes data of different life cycles to be mixed and written to the same physical block. When short-lived data is deleted, it will leave a hole in the physical block, triggering the garbage collection (GC) mechanism inside the SSD. The GC process involves additional data migration, causing the phenomenon of write amplification, which reduces the data storage efficiency of the solid state disk. SUMMARY

[0005] The present application provides a data transmission method and device based on a solid state disk, medium and product, which improves the data storage efficiency of the solid state disk.

[0006] The first aspect of the application provides a solid state disk-based data transmission method, which comprises the following steps: receiving a write instruction sent by a host, the write instruction containing a target memory starting address and a total data length; obtaining a data layout description header from a host memory by a direct memory access method according to the target memory starting address, the data layout description header being a preset data structure, the data layout description header being located at the target memory starting address and containing at least one data segment entry; parsing the data layout description header by a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and a life cycle attribute tag of a corresponding data segment from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash page as a target write address of each data segment; and based on the target write address, controlling the solid state disk to perform a DMA operation in a sequence of data segment entries in the data layout description header until the write of the total data length is completed.

[0007] By adopting the above technical solution, the write instruction containing the target memory starting address and the total data length is received, the data layout description header of the preset data structure is obtained from the host memory by the direct memory access method, the occupation of the host CPU resources in the data transmission process is avoided, and the data transmission efficiency is improved. Meanwhile, the data layout description header is parsed by the flash translation layer, each data segment entry is identified, and the length information and the life cycle attribute tag of the corresponding data segment are extracted, the fine management and optimization of different data segments are realized. In combination with the life cycle attribute tag, the corresponding physical flash page is planned as the target write address of each data segment, the access characteristics and the life cycle characteristics of different data segments are fully considered, the utilization efficiency of the flash and the data access performance are improved. Finally, the data is written in a sequence of data segment entries in the data layout description header by the DMA operation, the sequence and the integrity of the data writing are ensured, the problem of data disorder or loss is effectively avoided, and the reliability of the data transmission is significantly improved. The above technical solution introduces the data layout description header when the data is transmitted at the host end, the solid state disk can perceive the structured information and the life cycle attribute tag of the data, and the flash translation layer is combined to store and plan the physical flash page address of different life cycle data, and the data writing mode is optimized. The scheme effectively solves the problem of lack of data semantic cognition in the traditional DMA transmission, reduces the write amplification effect caused by the mixed storage of short life cycle data and long life cycle data, improves the write performance, the storage efficiency and the service life of the solid state disk, reduces the resource consumption caused by the garbage collection, and further optimizes the overall performance of the system.

[0008] Optionally, the data layout description header is parsed through the flash translation layer of the solid state disk to identify each data segment entry, specifically comprising: defining a parser corresponding to the data layout description header in the flash translation layer of the solid state disk, the parser containing data structure definition information of the data layout description header and data structure definition information of the data segment entry; decoding the binary data content of the data layout description header byte by byte using the parser to obtain a start identification bit and an end identification bit of the data layout description header; obtaining the effective data length of the data layout description header according to the start identification bit and the end identification bit; and parsing each data segment entry from the effective data of the data layout description header according to the effective data length and the data structure definition information of the data segment entry.

[0009] By adopting the above technical solution, the parser corresponding to the data layout description header is defined in the flash translation layer, and the data structure definition information of the data layout description header and the data segment entry is contained, so that the flash translation layer can accurately understand the format and content of the data layout description header, and the accuracy and efficiency of data parsing are improved. The binary data content of the data layout description header is decoded byte by byte using the parser to obtain the start and end identification bits, accurately positioning the boundary of the data layout description header, ensuring that the parsing process will not be offset or misjudged. The effective data length of the data layout description header is obtained according to the start and end identification bits, avoiding the parsing of invalid data and reducing the parsing overhead. Finally, each data segment entry is accurately parsed from the effective data of the data layout description header by combining the effective data length and the structure definition of the data segment entry, realizing efficient identification and extraction of the data segment, and providing a reliable foundation for subsequent data segment storage optimization.

[0010] Optionally, the life cycle attribute tag is used to plan a corresponding physical flash page as a target write address of each data segment, specifically including: according to the model and capacity of the solid state disk, a plurality of physical storage partitions are divided, and each physical storage partition is allocated a corresponding life cycle attribute tag; in the flash translation layer of the solid state disk, a mapping table of the life cycle attribute tag and the physical storage partition is created, and when the solid state disk is idle, the mapping relationship between the life cycle attribute tag and the physical storage partition is adjusted to update the mapping table; when a target life cycle attribute tag of a target data segment entry is parsed, a target physical storage partition corresponding to the target life cycle attribute tag is found in the mapping table, and a start address and a number of free pages of the target physical storage partition are obtained, the target data segment entry being any one of a plurality of data segment entries; according to a data segment length corresponding to the target data segment entry, a target page number required for writing the target data segment entry is calculated; if the number of free pages is greater than or equal to the target page number, a physical flash page equal to the target page number is allocated from the start address of the target physical storage partition as the target write address.

[0011] By adopting the above technical solution, according to the model and capacity of the solid state disk, a plurality of physical storage partitions are divided, and each partition is allocated a life cycle attribute tag, which realizes reasonable planning and classification of the physical storage space of the solid state disk, and provides a basis for differentiated storage management of data segments. By creating a mapping table of the life cycle attribute tag and the physical storage partition in the flash translation layer, a corresponding relationship between the life cycle characteristics of the data segment and the physical storage area is established, which facilitates quick searching of the corresponding storage area according to the life cycle attribute of the data segment. By obtaining the start address and the number of free pages of the target physical storage partition, the space usage of each physical storage partition is mastered in real time, and when allocating physical pages for data segments, the partition with sufficient free space can be selected, thereby improving the utilization rate of the storage space. At the same time, by comparing the number of free pages with the target page number, it is ensured that the allocated physical page can completely accommodate the data segment, thereby avoiding the problem of data storage overflow.

[0012] Optionally, the adjusting the mapping relationship between the life cycle attribute label and the physical storage partition when the solid state disk is idle comprises: monitoring the wear leveling degree of each physical storage partition when the solid state disk is idle; when the difference between the wear leveling degrees of a first physical storage partition and a second physical storage partition exceeds a preset threshold, obtaining a first life cycle attribute label corresponding to the first physical storage partition and a second life cycle attribute label corresponding to the second physical storage partition, the first physical storage partition and the second physical storage partition being any two physical storage partitions of the solid state disk, the wear leveling degree of the first physical storage partition being higher than that of the second physical storage partition; updating the first physical storage partition to a new first physical storage partition and updating the second physical storage partition to a new second physical storage partition; establishing a mapping relationship between the first life cycle attribute label and the new second physical storage partition, and establishing a mapping relationship between the second life cycle attribute label and the new first physical storage partition.

[0013] By using the above technical solution, when the solid state disk is idle, the wear leveling degree of each physical storage partition is monitored to real-time master the wear leveling state of each partition, and a basis is provided for dynamically adjusting the data layout. When the difference between the wear leveling degrees of two partitions exceeds a preset threshold, the life cycle attribute labels corresponding to the two partitions are obtained to prepare for the remapping of the life cycle labels. When the partitions are updated, the first and second partitions are redefined as new partitions according to the physical boundaries, so that the physical movement of data in the partitions is avoided, and the data migration overhead is reduced. By establishing the mapping relationship between the first life cycle label and the new second partition and the mapping relationship between the second life cycle label and the new first partition, the data exchange between the high-wear partition and the low-wear partition is realized, the low-wear data segment is stored in the high-wear partition, and the high-wear data segment is stored in the low-wear partition, so that the number of wear leveling times of each partition is balanced, and the overall life of the solid state disk is prolonged.

[0014] Optionally, the updating the first physical storage partition to a new first physical storage partition and the updating the second physical storage partition to a new second physical storage partition comprises: migrating all valid data in the first physical storage partition to available free pages in the second physical storage partition to obtain the new second physical storage partition; and performing overall erasing on the first physical storage partition after the data migration is completed to obtain the new first physical storage partition containing continuous free pages.

[0015] By adopting the technical scheme, in the physical storage partition updating process, all valid data of the first partition is migrated to the available free pages of the second partition, the data of the two partitions is exchanged, the low-erase data of the first partition is migrated to the second partition, the high-erase data of the second partition is indirectly migrated to the first partition, and the remapping of the life cycle attribute tag is completed. After the data migration is completed, the first partition is executed as a whole, and is converted into a new partition containing continuous free pages, on the one hand, the invalid space of the first partition is released, and on the other hand, a large number of continuous physical pages are provided for the newly written high-erase data, and the writing performance of the high-erase data is optimized. At the same time, since the physical boundary of the partition does not change, the data migration operation is transparent to the upper application, and the application program does not need to pay attention to the underlying partition adjustment, and the continuity and stability of data access are ensured.

[0016] Optionally, after the starting address and the free page number of the target physical storage partition are acquired, the method further includes: if the free page number is less than the target page number, triggering a garbage collection operation for the target physical storage partition, collecting invalid pages in the target physical storage partition, and converting the invalid pages into available free pages; after the garbage collection operation is completed, acquiring the free page number of the target physical storage partition after collection, and judging whether the free page number after collection is greater than or equal to the target page number; if yes, allocating physical flash memory pages equal to the target page number from the starting address of the target physical storage partition as the target writing address; if no, upgrading and adjusting the life cycle attribute tag of the target data segment entry to obtain a new life cycle attribute tag, and re-finding a new physical storage partition corresponding to the new life cycle attribute tag in the mapping table according to the new life cycle attribute tag.

[0017] By adopting the technical scheme, when the free page number of the target physical storage partition is insufficient to accommodate the data segment to be written, the garbage collection operation for the target partition is triggered, and the invalid pages in the partition are collected and converted into available free pages in time, the available space of the partition is dynamically expanded, and the storage space utilization rate is improved. After the garbage collection is completed, the free page number of the target partition is acquired again, and is compared with the data segment length, so that it is ensured that the free space after collection can meet the storage requirement of the data segment, and the problem of data writing failure is avoided. If the free space is still insufficient, the life cycle attribute tag of the target data segment is upgraded and adjusted to a higher level life cycle tag, and a corresponding physical storage partition is re-found according to the new tag, so that the dynamic adjustment of the data segment storage area is realized, and the reliable storage of data is ensured. The mechanism of dynamically triggering garbage collection and adjusting the life cycle of data according to the actual situation effectively adapts to the change of the data segment size and the storage space, and improves the flexibility and availability of the system.

[0018] Optionally, the controlling, based on the target write address, the solid state disk to perform DMA operation on each data segment in the order of the data segment entries in the data layout description header until the writing of the total data length is completed, specifically includes: creating a DMA task queue in a flash translation layer of the solid state disk; generating a corresponding DMA write task for each data segment entry according to the order of the data segment entries in the data layout description header, and inserting the DMA write task into the tail of the DMA task queue; reading and executing each DMA write task in turn from the head of the DMA task queue through a DMA controller of the solid state disk; for each DMA write task, reading target data of a specified length from a specified start address of a host memory through a DMA channel according to task parameters, and writing the target data to a target write address on the solid state disk; after the DMA write task is executed, deleting the DMA write task from the DMA task queue, and judging whether the DMA task queue is empty; if the DMA task queue is empty, indicating that the writing of the total data length is completed, and controlling the DMA controller to stop working; if the DMA task queue is not empty, reading and executing the next DMA write task through the DMA controller until the DMA task queue is empty.

[0019] By adopting the above technical solution, the DMA task queue is created in the flash translation layer, the data segment write operation is converted into a corresponding DMA write task, the DMA write task is inserted into the tail of the task queue according to the order of the data segment entries in the data layout description header, the serialization and asynchronization of the data write operation are realized, and the concurrency and throughput of the data write are improved. The DMA controller reads and executes each DMA write task in turn according to the first-in-first-out order of the task queue, ensuring the sequence and consistency of the data write. For each DMA write task, the target data is read from the host memory through the DMA channel according to the task parameters, and the data is written to the target physical page of the solid state disk, realizing the high-speed transmission of the data from the host to the solid state disk, and reducing the time delay of the data migration. After the task is executed, it is deleted from the task queue in time, and whether the queue is empty is judged, and the DMA controller is stopped in time, avoiding unnecessary resource waste. This data write mechanism based on the DMA task queue fully utilizes the data transmission capacity of the DMA hardware, reduces the burden of the host CPU, and realizes the automation and pipelining of the data write process, thereby significantly improving the efficiency and performance of the data write.

[0020] In a second aspect, the embodiments of the present application provide a data transmission device based on a solid state disk, which comprises one or more processors and a memory; the memory is coupled to the one or more processors, and the memory is configured to store computer program codes, the computer program codes comprising computer instructions, and the one or more processors are configured to invoke the computer instructions to enable the data transmission device based on the solid state disk to perform the method described in the first aspect and any possible implementation manner of the first aspect.

[0021] In a third aspect, the embodiments of the present application provide a computer readable storage medium comprising instructions, which, when executed on a data transmission device based on a solid state disk, enable the data transmission device based on the solid state disk to perform the method described in the first aspect and any possible implementation manner of the first aspect.

[0022] In a fourth aspect, the embodiments of the present application provide a computer program product comprising instructions, which, when executed on a data transmission device based on a solid state disk, enable the data transmission device based on the solid state disk to perform the method described in the first aspect and any possible implementation manner of the first aspect.

[0023] To sum up, the one or more technical solutions provided by the present application have at least the following technical effects or advantages: 1. By introducing a data layout description header, combining the flash translation layer of the solid state disk and the DMA technology, the data transmission process has structured and semantic perception capabilities. By analyzing the data segment entries and the life cycle attribute tags, the SSD can realize the classified storage and resource optimization allocation of data, reduce the inefficiency of indiscriminate data transfer in traditional DMA technology, and greatly improve the data transmission efficiency and overall system performance.

[0024] 2. By planning the physical storage partition based on the life cycle attribute tags and adjusting the dynamic mapping relationship, the present solution effectively avoids the frequent garbage collection (GC) operation caused by the mixed storage of short life cycle data and long life cycle data, and significantly reduces the write amplification effect. At the same time, through the erase-write balance monitoring and dynamic migration optimization of the physical storage partition, the erase-write load of the flash memory unit is further balanced, and the service life of the SSD is prolonged.

[0025] 3. The present solution ensures efficient use of physical storage space through dynamic physical page allocator, garbage collection mechanism and life cycle attribute tag upgrade adjustment. When there is insufficient storage resource, new storage resource can be dynamically allocated through emergency garbage collection or life cycle tag adjustment. In addition, the sequential operation design based on the DMA task queue ensures the orderliness and reliability of the data writing process, and improves the stability and concurrent processing capability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a flow diagram of a data transmission method based on a solid state disk according to an embodiment of the present application; Figure 2 is another flow diagram of a data transmission method based on a solid state disk according to an embodiment of the present application; Figure 3 is a structural diagram of a data transmission device based on a solid state disk according to an embodiment of the present application.

[0027] Reference signs: 301, central processing unit; 302, read-only memory; 303, random access memory; 304, bus; 305, input / output interface; 306, input part; 307, output part; 308, storage part; 309, communication part; 310, drive; 311, detachable medium. DETAILED DESCRIPTION

[0028] In order for those skilled in the art to better understand the technical solutions in the specification, the technical solutions in the specification will be clearly and completely described below in conjunction with the drawings in the embodiments of the specification. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0029] In the description of the embodiments of the present application, the words such as "for example" or "for instance" are used to represent an example, illustration or description. Any embodiment or design scheme described as "for example" or "for instance" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as "for example" or "for instance" are intended to present the relevant concept in a specific manner.

[0030] In the description of the embodiments of the present application, the term "a plurality of" means two or more. For example, a plurality of system devices means two or more system devices, and a plurality of screen terminals means two or more screen terminals. In addition, the terms "first" and "second" are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. The terms "include", "contain", "have" and their variants mean "include but are not limited to", unless otherwise specifically emphasized.

[0031] The present application provides a data transmission method based on a solid state disk, referring to Figure 1 , Figure 1is a flowchart of a data transmission method based on a solid state disk provided by an embodiment of the present application. The method is applied to a device, which is a solid state disk. The device can execute a data transmission program based on a solid state disk. The method comprises steps S101 to S105, which are as follows. Step S101: receiving a write instruction sent by a host end, the write instruction containing a target memory start address and a total data length.

[0032] In step S101, the host end refers to a computer system that initiates a data write request, such as a personal computer or a server running an operating system and an application program. The target memory start address indicates the start physical address of the data required for this write operation in the host memory. The total data length refers to the total number of bytes of data that needs to be written to the solid state disk from the start address. The write instruction is a command sent by the host end to the solid state disk controller through a bus protocol, such as NVMe or SATA. The command encapsulates the parameters required to perform the data write task.

[0033] Specifically, when an application program or an operating system of the host end needs to persistently store the data of a memory region, the device driver of the host constructs a specific write instruction. In addition to containing traditional logical block address (LBA) information, the write instruction also contains the exact start position of the data to be written in the host physical memory, i.e., the target memory start address, and the total size of the data to be written, i.e., the total data length. The controller of the solid state disk continuously monitors the command queue and receives and identifies the write instruction. The controller parses the target memory start address and the total data length from the instruction to prepare for subsequent data acquisition and processing.

[0034] Step S102: acquiring a data layout description header from the host memory through a direct memory access method according to the target memory start address, the data layout description header being a preset data structure, the data layout description header being located at the target memory start address and containing at least one data segment entry.

[0035] In step S102, the direct memory access method refers to a technique by which the solid state disk controller directly reads the host memory data without the intervention of the host central processing unit (CPU). The data layout description header refers to a data structure with a predefined format. The structure is placed at the front end of the data block to be written to describe the internal logical composition of the subsequent real data. The data segment entry is a basic component unit in the data layout description header. Each data segment entry describes the attributes of a specific data segment.

[0036] Specifically, after obtaining the target memory start address in step S101, the controller firmware of the solid state disk initializes the on-board direct memory access (DMA) controller. The firmware instructs the DMA controller to perform a small-scale data read operation, with the target address being the target memory start address and the length being the preset size of the data layout description header. The DMA controller then independently accesses the host memory through the system bus to completely capture the data layout description header at the target memory start address into the cache or static random access memory (SRAM) inside the solid state disk. This process is highly efficient because it bypasses the CPU of the host and avoids the overhead of context switching and interrupt processing.

[0037] In one possible implementation, the data layout description header is parsed by the flash translation layer of the solid state disk to identify each data segment entry, specifically including steps S1021-S1024, as follows: Step S1021: In the flash translation layer of the solid state disk, a parser corresponding to the data layout description header is defined, which contains the data structure definition information of the data layout description header and the data structure definition information of the data segment entry.

[0038] In step S1021, the parser refers to a specific program code solidified in the firmware of the flash translation layer, which is specially used to identify and interpret the binary stream of the data layout description header. The data structure definition information refers to the accurate description of the internal fields of the data layout description header and the data segment entry, including the name, data type, number of bytes occupied, and arrangement order in the overall structure of each field.

[0039] Specifically, during the design and firmware development stage of the solid state disk, an engineer will pre-define a parser in the code of the flash translation layer. The parser is embedded with complete knowledge about the data layout description header. For example, the parser knows that the data layout description header always starts with a specific 4-byte magic number and ends with another 4-byte magic number, and that the data between the start and end magic numbers is composed of a sequence of data segment entries. Meanwhile, the parser also accurately defines the structure of each data segment entry, for example, each entry is composed of a 4-byte unsigned integer for representing the data segment length and a 1-byte character for representing the lifetime attribute tag. These definition information is the fundamental basis for the correct operation of the parser.

[0040] Step S1022: The binary data content of the data layout description header is decoded byte by byte using the parser to obtain the start identification bit and the end identification bit of the data layout description header.

[0041] In step S1022, the binary data content refers to the raw data layout header data stream obtained from the host memory without any processing. The byte-by-byte decoding refers to the process in which the parser reads and analyzes the binary data content sequentially in byte units. The start identifier and the end identifier refer to the special byte sequence predefined to mark the boundary of the valid content of the data layout header.

[0042] Specifically, when the binary data content of the data layout header is loaded into the internal cache of the solid state disk, the flash translation layer invokes the parser defined in step S1021 to process the data. The parser starts scanning from the first byte of the binary data content and compares the read byte sequence with the preset start identifier. Once a match is found, the parser records the position of the start identifier. Subsequently, the parser continues to scan backward to find the preset end identifier. In this way, the parser can accurately define the start and end boundaries of the data layout header from the data stream that may contain other irrelevant data.

[0043] Step S1023: Obtain the valid data length of the data layout header according to the start identifier and the end identifier.

[0044] In step S1023, the valid data length refers to the total number of bytes of the part of the data located between the start identifier and the end identifier, which contains all the data segment entries.

[0045] Specifically, after the parser successfully locates the start identifier and the end identifier, the parser determines the valid data length by calculating the address difference of the two identifiers in the memory. For example, if the start identifier occupies 4 bytes, the valid data starts from the position after the start identifier. The parser subtracts the start address of the valid data from the start address of the end identifier to obtain an accurate byte count value, which is the valid data length. This length represents the total size of all data segment entries, providing key information for accurately separating each entry in the next step.

[0046] Step S1024: Parse each data segment entry from the valid data of the data layout header according to the valid data length and the data structure definition information of the data segment entry.

[0047] In step S1024, this step is the core link of the parsing process, aiming to decompose the continuous valid data block into independent and meaningful data segment entries.

[0048] In particular, the parser uses the valid data length obtained in step S1023 and the data structure definition information of the individual data segment entry defined in step S1021, for example, it knows that each entry occupies 5 bytes fixedly. The parser calculates how many data segment entries are contained in total by dividing the valid data length by the length of the individual data segment entry. Then, the parser starts a loop whose number of times is equal to the number of data segment entries. In each loop, the parser reads a byte block of the length of a data segment entry from the current processing position of the valid data. Then, according to the data structure definition of the data segment entry, it extracts the corresponding information from the byte block, for example, the first 4 bytes are interpreted as an integer as length information and the 5th byte is interpreted as a character as the lifetime attribute tag. After one extraction, the parser moves the processing position backward by the length of a data segment entry, ready to parse the next entry. This loop continues until all the valid data is processed, and finally all the data segment entries are parsed completely and independently.

[0049] For the convenience of understanding, the following takes a specific example to explain steps S2021-S1024: Suppose that a parser is defined in the flash translation layer of a solid state disk. The parser knows that the start identification bit of the data layout description header is 0xABCDABCD, the end identification bit is 0xDCBADBCA, and each data segment entry is composed of a 4-byte length field and a 1-byte lifetime tag field, totaling 5 bytes. Now, the solid state disk obtains a piece of binary data content from the host memory through DMA. The parser starts to work, and it scans the data byte by byte and finds 0xABCDABCD at the beginning of the data, confirming the start position. Then it continues to scan and finds 0xDCBADBCA at the 19th byte, confirming the end position. According to the two positions, the parser calculates that the valid data length between them is 10 bytes, which is located after 4 bytes of the start identification bit and before 4 bytes of the end identification bit. Then, according to the definition information that each data segment entry is 5 bytes, the parser divides the valid data length 10 bytes by 5 bytes and obtains that there are 2 data segment entries in total. The parser then starts to parse in a loop. The first time, it reads the first 5 bytes of the valid data, parses the first 4 bytes as length information, for example, 0x00001000, which is 4096, and the 5th byte as the lifetime attribute tag, for example, 0x01 representing hot data. The second time, it reads the last 5 bytes of the valid data, parses the first 4 bytes as length information, for example, 0x00004000, which is 16384, and the 5th byte as the lifetime attribute tag, for example, 0x03 representing cold data. Thus, the parser successfully extracts two complete data segment entries and the length information and lifetime attribute tags contained therein from the original binary data.

[0050] Step S103: Analyze the data layout description header through the flash translation layer of the solid state disk, identify each data segment entry, and extract the length information and life cycle attribute label of the corresponding data segment from each data segment entry.

[0051] In step S103, the flash translation layer FTL refers to the core firmware layer inside the solid state disk, which is responsible for mapping the upper logical address to the physical address of the flash memory and managing the underlying operations such as garbage collection and wear leveling. The length information refers to the number of bytes occupied by a specific data segment. The life cycle attribute label is a classification mark used to identify the data update frequency or expected retention time, which can be divided into, for example, extremely hot data, hot data, warm data, and cold data.

[0052] Specifically, when the data layout description header is successfully obtained in the internal memory of the solid state disk, the flash translation layer firmware running on the embedded processor of the solid state disk begins to execute the parsing program. The program reads the content field by field according to the pre-defined data structure of the data layout description header. For example, the firmware will first read a field to determine how many data segment entries are contained in the data layout description header, and then enter a loop. In each loop, the firmware will read all fields of a data segment entry one by one, accurately separating the length information representing the size of the data segment and the life cycle attribute label representing the characteristics of the data segment. The flash translation layer will pair each set of length information and life cycle attribute label and store it in a temporary internal data structure for subsequent write planning steps.

[0053] Step S104: Based on the life cycle attribute label, plan the corresponding physical flash page as the target write address of the data segment for each data segment.

[0054] In step S104, the physical flash page is the smallest physical unit that can perform a programming write operation in the NAND flash memory chip. The target write address refers to the specific physical page address PPA allocated for a data segment on the flash memory chip.

[0055] Specifically, the flash translation layer has internally pre-divided the physical storage space of the solid state disk into multiple logical partitions or block pools according to different life cycle attribute labels. For example, part of the high-performance SLC or low-density TLC blocks are divided into a hot data area, and other standard TLC or QLC blocks are divided into a cold data area. For each data segment entry parsed in step S103, the flash translation layer checks its life cycle attribute label. According to the label, the flash translation layer locates the corresponding physical partition and applies one or more continuous and available physical flash pages from the free block manager of the partition. The flash translation layer takes the address of the applied physical flash page as the target write address of the data segment and associates it with the length information of the data segment to form a complete write task description. This process is repeated for all data segments, and a detailed write mapping table from the data segment to the physical location is finally generated.

[0056] Reference is made to Figure 2 In a possible implementation, based on the life cycle attribute label, a corresponding physical flash page is planned for each data segment as the target write address of the data segment, specifically including steps S201-S209, which are as follows: Step S201: According to the model and capacity of the solid state disk, multiple physical storage partitions are divided, and each physical storage partition is assigned a corresponding life cycle attribute label.

[0057] In step S201, the physical storage partition refers to a continuous storage area logically divided by firmware on the physical flash medium of the solid state disk, and each partition is composed of a plurality of physical erase blocks. The life cycle attribute label refers to a classification mark used to identify the data update frequency characteristic, for example, divided into hot data label, warm data label and cold data label, corresponding to high-frequency, medium-frequency and low-frequency updated data, respectively.

[0058] Specifically, when the solid state disk is first initialized or formatted, the flash translation layer firmware will perform this step. The firmware will divide the total NAND flash physical space into a predetermined number of physical storage partitions according to the total capacity and design specifications of the solid state disk. For example, a 1TB solid state disk can be divided into three partitions: a 200GB partition, a 300GB partition, and a 500GB partition. After the division is completed, the firmware will perform initial role allocation for each partition, i.e., assign an initial life cycle attribute label to each physical storage partition. For example, the 200GB partition is marked as a hot data area, the 300GB partition is marked as a warm data area, and the 500GB partition is marked as a cold data area.

[0059] Step S202: In the flash translation layer of the solid state disk, a mapping table of the life cycle attribute label and the physical storage partition is created.

[0060] In step S202, the mapping table refers to a data structure stored in the high-speed dynamic random access memory inside the solid state disk, which records the physical starting address and range information of the specific physical storage partition currently corresponding to each life cycle attribute tag.

[0061] Specifically, after completing the division of the physical storage partition and the initial tag allocation, the flash translation layer will establish and maintain the mapping table in its working memory. This mapping table serves as a dynamic routing guide for data writing. For example, the mapping table may contain the following entries: the hot data tag points to the address information of physical storage partition A, the warm data tag points to the address information of physical storage partition B, and the cold data tag points to the address information of physical storage partition C. When writing a certain type of data is needed, the flash translation layer will query this table to determine the correct target physical location.

[0062] Step S203: Monitor the wear leveling degree of each physical storage partition when the solid state disk is idle.

[0063] In step S203, when the solid state disk is idle, it refers to the time window when the solid state disk is currently not executing read / write commands from the host or internal emergency garbage collection tasks. The wear leveling degree refers to an indicator for measuring the wear degree of a physical storage partition, which is usually quantified by calculating the average erase count of all physical blocks in the partition.

[0064] Specifically, the flash translation layer contains a background monitoring task designed to be activated during the idle period of the solid state disk. Once activated, the task will traverse each physical storage partition in the solid state disk, read and accumulate the erase count value of each physical block in the partition, and then calculate the average erase count of each partition. This average value is the wear leveling degree of the partition. The flash translation layer will update and record the wear leveling degree value of each partition in real time or periodically to provide data support for subsequent wear leveling decisions.

[0065] Step S204: When the wear leveling degree difference value of the first physical storage partition and the second physical storage partition exceeds the preset threshold, obtain the first life cycle attribute tag corresponding to the first physical storage partition and the second life cycle attribute tag corresponding to the second physical storage partition, and the first physical storage partition and the second physical storage partition are any two physical storage partitions of the solid state disk, and the wear leveling degree of the first physical storage partition is higher than that of the second physical storage partition.

[0066] In step S204, the difference value refers to the absolute value of the difference between the wear leveling values of the two physical storage partitions. The preset threshold refers to an integer value preset in the firmware, which triggers the balancing mechanism when the wear difference reaches the value. The first physical storage partition and the second physical storage partition refer to the two partitions with higher and lower wear levels when compared. The first life cycle attribute tag and the second life cycle attribute tag refer to the tags corresponding to the two partitions in the mapping table at the time of triggering the balancing mechanism.

[0067] Specifically, after obtaining the wear leveling values of all physical storage partitions, the background monitoring task compares them in pairs. Assuming that physical storage partition A and physical storage partition C are compared, it is found that the wear leveling value of partition A is 1000 and the wear leveling value of partition C is 50, and the preset threshold is 800. Since the difference value 950 exceeds the threshold 800, the balancing condition is triggered. At this time, the system determines partition A as the first physical storage partition and partition C as the second physical storage partition. Then, the system queries the mapping table and obtains that the current tag corresponding to partition A is the hot data tag, which is the first life cycle attribute tag; the current tag corresponding to partition C is the cold data tag, which is the second life cycle attribute tag.

[0068] Step S205: Migrate all valid data in the first physical storage partition to the available free pages in the second physical storage partition to obtain a new second physical storage partition.

[0069] In step S205, valid data refers to data in the physical storage partition that is still referenced by the logical address mapping and has not been marked as invalid or deleted. Available free pages refer to physical pages in the target physical storage partition that have completed the erase operation but have not yet written new data. The new second physical storage partition refers to the second physical storage partition after the data migration operation is completed.

[0070] Specifically, after triggering the balancing operation, the flash translation layer starts the data migration process. The flash translation layer first scans the first physical storage partition to identify all physical pages containing valid data. Then, the flash translation layer reads these valid data and sequentially writes them to the available free pages in the second physical storage partition. After this process is completed, the second physical storage partition will contain the original data and all valid data migrated from the first physical storage partition. The second physical storage partition in this state is referred to as the new second physical storage partition.

[0071] Step S206: Perform overall erase on the first physical storage partition after completing the data migration to obtain a new first physical storage partition containing contiguous free pages.

[0072] In step S206, the overall erasing refers to executing an erasing command on all physical blocks in a physical storage partition to restore them to a writable state. The new first physical storage partition refers to the first physical storage partition after the overall erasing operation is completed.

[0073] Specifically, after confirming that all valid data in the first physical storage partition has been safely migrated to the second physical storage partition, the flash translation layer sends a block erasing command to all physical blocks constituting the first physical storage partition. This process resets the state of all physical pages in the partition. After the operation is completed, the first physical storage partition becomes a clean area consisting entirely of contiguous free pages, ready to receive new data. The first physical storage partition in this state is referred to as the new first physical storage partition.

[0074] Step S207: Establish a mapping relationship between the first life cycle attribute tag and the new second physical storage partition, and establish a mapping relationship between the second life cycle attribute tag and the new first physical storage partition.

[0075] In step S207, the mapping relationship refers to the correspondence between the life cycle attribute tag and the physical storage partition address in the mapping table created in step S202.

[0076] Specifically, after the data migration and partition erasing are completed, the flash translation layer updates the mapping table to achieve the exchange of logical roles. The flash translation layer finds the entry of the first life cycle attribute tag, i.e., the hot data tag, and modifies the physical partition address it points to as the address of the new second physical storage partition. At the same time, the flash translation layer finds the entry of the second life cycle attribute tag, i.e., the cold data tag, and modifies the physical partition address it points to as the address of the new first physical storage partition. Through this update, the physical area that was originally heavily worn is now assigned to cold data with lower write frequency, while the physical area that was less worn starts to bear hot data with high write frequency, thus achieving wear leveling.

[0077] Step S208: When the target life cycle attribute tag of the target data segment entry is parsed, the target physical storage partition corresponding to the target life cycle attribute tag in the mapping table is found, and the start address and free page number of the target physical storage partition are obtained. The target data segment entry is any one of the plurality of data segment entries.

[0078] In step S208, the target data segment entry refers to the specific data segment that needs to be written to the solid state disk. The target life cycle attribute tag is the tag contained in the data segment entry. The target physical storage partition is the physical partition found in the current mapping table according to the tag. The start address and free page number are the state information of the target physical storage partition.

[0079] Specifically, when a write command arrives and its data segment entry is parsed, the flash translation layer extracts the target life cycle attribute tag, such as the hot data tag, in the entry. The flash translation layer immediately uses this tag as a query key to search in the mapping table. The mapping table returns the physical address information of the target physical storage partition currently associated with the hot data tag. Meanwhile, the flash translation layer reads the starting physical address of the target physical storage partition and the total number of currently remaining free pages from the partition management metadata.

[0080] Step S209: According to the data segment length corresponding to the target data segment entry, the target page number required for writing the target data segment entry is calculated.

[0081] In step S209, the data segment length is used to represent the logical size of the data segment described by the target data segment entry, usually measured in bytes; and the target page number represents the minimum integer number of physical flash memory pages required to completely store the data corresponding to the data segment length in the physical flash memory.

[0082] Specifically, when the solid state disk performs this calculation step, it first needs to obtain two key parameters: the first is the data segment length read from the target data segment entry, and the second is the size of a single physical flash memory page pre-configured in the flash management system, which is a fixed value. After obtaining these two parameters, the solid state disk takes the data segment length as the dividend and the size of the physical flash memory page as the divisor to perform a division operation. If the result of the division operation is an integer, it indicates that the data corresponding to the target data segment entry can exactly fill several complete physical flash memory pages, and at this time the solid state disk determines the integer result as the target page number. If the result of the division operation is a non-integer with a decimal part, it indicates that after filling several complete physical flash memory pages, there is still remaining data that needs to occupy part of the space of the next physical flash memory page, and at this time the solid state disk adds one to the integer part of the division operation result and determines the sum as the target page number. Such operation ensures that the calculated target page number is always sufficient to accommodate all data, avoiding the problem of insufficient data storage space allocation due to the fact that the data length cannot be divided by the page size.

[0083] Step S210: If the number of free pages is greater than or equal to the target page number, allocate physical flash memory pages equal to the target page number starting from the starting address of the target physical storage partition as the target write address.

[0084] In step S210, the target write address refers to the starting address of a continuous physical page allocated by the flash translation layer for this data segment in the physical flash memory.

[0085] In particular, the flash translation layer compares the number of free pages obtained in step S208 with the target number of pages. If the number of free pages is sufficient to accommodate the entire data segment, the flash translation layer allocates, within the target physical storage partition, a number of physical flash pages equal to the target number of pages, starting from the current available write position. The physical address of the first page of the series of allocated physical pages is determined as the target write address for the write operation. Subsequently, data is written to this address. If the number of free pages is insufficient, a garbage collection operation is first triggered in the partition to release space, and then the allocation is performed.

[0086] To facilitate understanding, a specific example is given below to explain steps S201-S210: Suppose a solid state disk is divided into physical partition A and physical partition B at initialization. The flash translation layer creates a mapping table, mapping the life cycle attribute label "hot data" to partition A and "cold data" to partition B. After running for a period of time, because a large number of high-frequency write operations are directed to "hot data", the average number of erasures of partition A reaches 600, while the average number of erasures of partition B, which mainly stores static files, is only 50. At this time, the solid state disk enters an idle state, and the background monitoring task detects that the difference value of the wear leveling degree of the two partitions is 550, which exceeds the preset threshold value 500, triggering the wear leveling mechanism. The system determines partition A as the first physical storage partition with higher wear and partition B as the second physical storage partition with lower wear. Then, the system copies and writes all the remaining valid data in partition A, for example 50 GB, to the available free pages in partition B. After the migration is completed, the system performs a full erase on partition A, making partition A a completely clean idle partition. Finally, the system updates the mapping table: the "hot data" label is directed to the address of partition B, and the "cold data" label is directed to the address of the newly erased partition A. A few days later, a host requests to write a data segment with a length of 2 GB and a "hot data" label. The flash translation layer parses the "hot data" label, queries the updated mapping table, and finds that "hot data" now corresponds to physical partition B. The system checks and finds that partition B still has a large number of free pages, much larger than 2 GB. Therefore, the system allocates 2 GB of continuous physical flash pages from the current write point of partition B, and returns the address as the target write address, and data is written to this address in the original cold data area and lightly worn physical location, effectively prolonging the overall service life of the solid state disk.

[0087] In one possible implementation, after obtaining the start address and the number of free pages of the target physical storage partition, the method further includes steps S211-S214, which are as follows: Step S211: If the number of free pages is less than the number of target pages, triggering a garbage collection operation for the target physical storage partition, collecting invalid pages in the target physical storage partition, and converting the invalid pages into available free pages.

[0088] In step S211, the garbage collection operation refers to a space consolidation mechanism automatically executed inside the solid state disk, which recycles the physical space occupied by invalid data pages by moving valid data in physical blocks and erasing old physical blocks. Invalid pages refer to physical pages that store outdated data, which are no longer pointed to by logical addresses due to being updated or deleted.

[0089] Specifically, when the flash translation layer finds that the number of free pages in the target physical storage partition is insufficient to accommodate the number of target pages in the judgment of step S209, it will immediately start a garbage collection operation for the target physical storage partition. The flash translation layer will scan all physical blocks in the partition and select one or more physical blocks containing more invalid pages as the target for collection. Then, the flash translation layer reads the remaining small amount of valid data in these target physical blocks and writes it to the free pages of other physical blocks in the partition. After confirming that all valid data has been successfully migrated, the flash translation layer will execute a full erase command on the original target physical blocks. After erasing, all pages in these physical blocks become available free pages for new data to be written, thereby increasing the available space of the target physical storage partition.

[0090] Step S212: After the garbage collection operation is completed, the number of free pages after collection of the target physical storage partition is obtained, and it is determined whether the number of free pages after collection is greater than or equal to the number of target pages.

[0091] In step S212, the number of free pages after collection refers to the total number of the latest available free pages in the target physical storage partition after the garbage collection operation of step S211 is executed.

[0092] Specifically, after the garbage collection operation is completed, the flash translation layer will immediately re-query the status information of the target physical storage partition to obtain the updated total number of free pages, which is the number of free pages after collection. Then, the flash translation layer will again perform a space judgment by comparing the number of free pages after collection with the number of target pages required by the target data segment entry to be written. The result of this comparison will determine the execution path to follow: if the space is sufficient, go to step S213; if the space is still insufficient, go to step S214.

[0093] Step S213: If yes, allocate physical flash pages equal to the number of target pages as the target write address, starting from the starting address of the target physical storage partition.

[0094] In step S213, if the result of the determination in step S212 is yes, i.e. after the garbage collection operation, the target physical storage partition has enough free pages to store the target data segment, then the flash translation layer executes the same allocation logic as in step S210. The flash translation layer starts from the current available write position of the target physical storage partition, and allocates a piece of physical flash pages in succession, the number of which is equal to the number of target pages. The start physical address of the allocated piece of physical flash pages is finally determined as the target write address of this time of write operation, and the data write operation can be performed immediately.

[0095] Step S214: If no, the life cycle attribute tag of the target data segment entry is upgraded and adjusted to obtain a new life cycle attribute tag, and a new physical storage partition corresponding to the new life cycle attribute tag is found in the mapping table according to the new life cycle attribute tag.

[0096] In step S214, the upgrade and adjustment of the life cycle attribute tag means that according to a preset strategy, the life cycle attribute tag of the data is adjusted from a level representing a higher update frequency to a level representing a lower update frequency, for example, from hot data to warm data, or from warm data to cold data. The new life cycle attribute tag refers to the new tag obtained after the upgrade and adjustment. The new physical storage partition refers to the physical storage partition associated with the new life cycle attribute tag in the mapping table.

[0097] Specifically, if the result of step S212 is no, it means that even after the garbage collection, the space of the target physical storage partition (for example, the hot data area) is still insufficient, which usually means that the partition is full of a large amount of valid data that is still used recently. At this time, the flash translation layer starts a backup strategy. The flash translation layer performs a downgrade processing on the life cycle attribute tag of the current target data segment entry to be written, for example, modifies the original “hot data” tag to a “warm data” tag, and this “warm data” tag is the new life cycle attribute tag. Then, the flash translation layer uses the new life cycle attribute tag to perform a new search in the mapping table of the life cycle attribute tag and the physical storage partition. This search locates a new physical storage partition corresponding to the “warm data” tag. Then, the whole process returns to step S209, and the system rechecks the space of the new physical storage partition and tries to allocate a write address.

[0098] In order to facilitate understanding, the following explains steps S211-S214 through a specific example: Suppose a write request arrives at the solid state disk, the request contains a target data segment entry with a length of 5GB and a lifecycle attribute tag of "hot data". The flash translation layer finds that the target physical storage partition currently used to store the hot data is partition A according to the mapping table. The system checks and finds that partition A only has 2GB of free pages, which is less than 5GB. Therefore, the system immediately triggers a garbage collection operation for partition A. However, since most of the data stored in partition A is valid hot data that is frequently accessed recently, there are few invalid pages, and the garbage collection operation can only recover 1GB of space. After the operation is completed, the system obtains the number of free pages in partition A after recovery, which is 3GB. The system judges again and finds that 3GB is still less than the required 5GB. At this time, the system determines that partition A cannot accommodate the data segment, and adjusts the lifecycle attribute tag of the data segment entry from "hot data" to "warm data". Then, the system uses the new lifecycle attribute tag "warm data" to query the mapping table again and finds that the corresponding physical storage partition is partition C. Next, the system starts the allocation process again for partition C and checks the number of free pages in partition C. If partition C has sufficient space, it allocates physical flash memory pages in partition C as the target write address for the 5GB data segment.

[0099] Step S105: Based on the target write address, control the solid state disk to perform DMA operations on each segment in the order of the data segment entries in the data layout description header until the total length of the data is written.

[0100] In step S105, the DMA operation refers to the process of the solid state disk controller using direct memory access technology again to transfer user data in the host memory to the flash memory medium.

[0101] Specifically, after the target write addresses of all data segments are planned, the solid state disk controller starts to perform the actual data write process. The controller strictly follows the original order of the data segment entries in the data layout description header. For the first data segment entry, the controller configures the DMA engine, sets the source address as the start address of the target memory plus the length of the data layout description header, sets the target address as the target write address planned for the data segment in step S104, and sets the transfer length as the length information of the data segment. After the DMA transfer is started, the first segment of data is directly written from the host memory to the specified physical flash memory page. After the transfer is completed, the DMA controller reports the completion status. The firmware then processes the second data segment entry, at which time the source address of the DMA is updated to the end address of the previous data segment in the host memory, and the target address is updated to the new physical flash memory page address planned for the second data segment. This "configure DMA - execute - complete - process the next segment" loop is continuously executed, one segment after another, until all data segments are accurately written to their respective planned physical locations, and the total amount of data written reaches the total length of the data. After the task is completed, the solid state disk sends a write completion confirmation signal to the host.

[0102] In one possible implementation, based on the target write address, the solid state disk performs DMA operations on the data segments in the order of the data segment entries in the data layout description header, until the writing of the total length of the data is completed, specifically including steps S1051-S1057, which are as follows: Step S1051: In the flash translation layer of the solid state disk, a DMA task queue is created.

[0103] In step S1051, the flash translation layer refers to the firmware layer inside the solid state disk responsible for managing flash memory chips, performing address mapping, garbage collection, wear leveling, and the like. The DMA task queue refers to a data structure created inside the flash translation layer for storing and managing direct memory access tasks to be executed. This data structure follows the first-in, first-out principle to ensure that tasks are processed in the order in which they are submitted.

[0104] Specifically, after receiving the write instruction passed down from the upper layer, the flash translation layer of the solid state disk allocates a continuous memory space in its internal working memory and initializes the space as a queue data structure. This queue is specifically designated as a DMA task queue for sequentially receiving and storing each DMA write task generated for this data write operation. The initial state of the queue is empty.

[0105] Step S1052: According to the order of the data segment entries in the data layout description header, a corresponding DMA write task is generated for each data segment entry, and the DMA write task is inserted into the tail of the DMA task queue.

[0106] In step S1052, the DMA write task refers to a data structure containing all parameters required for performing a single direct memory access operation, which usually includes the source address, the target address and the data transfer length.

[0107] Specifically, the flash translation layer will start parsing the data layout description header obtained in the previous step. The flash translation layer processes each data segment entry in the order arranged in the data layout description header. For the first data segment entry, the flash translation layer generates a DMA write task, the task parameters of which include the starting address of the data segment in the host memory, the data segment length, and the target write address determined in the previous step. For each subsequent data segment entry, the flash translation layer also generates a DMA write task, the task parameters of which include the starting address of the data segment in the host memory and the data segment length, and the target write address of the task is calculated by adding the length of the previous data segment to the target write address of the previous task. The flash translation layer inserts each DMA write task into the tail of the DMA task queue as it is generated. This process continues until all data segment entries have been processed.

[0108] Step S1053: sequentially read and execute each DMA write task from the head of the DMA task queue through the DMA controller of the solid state disk.

[0109] In step S1053, the DMA controller refers to a dedicated hardware unit inside the solid state disk, which is responsible for performing direct memory access operations and can autonomously complete data transfer between the host memory and the flash memory without occupying central processing unit resources.

[0110] Specifically, after all DMA write tasks have been filled into the DMA task queue, the flash translation layer will send a start signal to the DMA controller of the solid state disk. After receiving the signal, the DMA controller will access the head of the DMA task queue and read the first DMA write task at the head. The DMA controller parses the parameters contained in the task to prepare for the actual data transfer. This operation marks the beginning of the data write physical execution phase.

[0111] Step S1054: for each DMA write task, read the target data of the specified length from the specified starting address of the host memory through the DMA channel according to the task parameters, and write the target data to the target write address on the solid state disk.

[0112] In step S1054, the DMA channel refers to a logical path established by the DMA controller for a single independent data transfer operation. The host memory refers to the main random access memory of the computer system connected to the solid state disk.

[0113] Specifically, according to the parameters parsed from the DMA write task, the DMA controller configures a DMA channel. The DMA controller initiates a data read request to the host memory system using the host memory start address and data length specified in the task. Meanwhile, the DMA controller prepares to receive data on the internal data path of the solid state disk using the target write address specified in the task. The data stream is transmitted from the host memory to the physical flash page pointed by the target write address of the solid state disk through the DMA channel, without the intervention of the central processing unit. The DMA controller monitors the transmission process to ensure that the specified length of data is accurately written.

[0114] Step S1055: After the DMA write task is executed, the DMA write task is deleted from the DMA task queue, and it is determined whether the DMA task queue is empty.

[0115] In step S1055, when the DMA controller confirms that the data transmission specified by the current DMA write task has been successfully completed, the flash translation layer performs a dequeue operation to remove the just-executed DMA write task from the head of the DMA task queue. After the task is removed, the head pointer of the queue automatically points to the next task. Then, the flash translation layer immediately checks the current state of the DMA task queue to determine whether there are remaining tasks in the queue.

[0116] Step S1056: If the DMA task queue is empty, it indicates that the write of the total data length is completed, and the DMA controller is controlled to stop working.

[0117] In step S1056, if the result of step S1055 is yes, that is, the DMA task queue is empty, it indicates that all data segments defined in the data layout description header have been successfully written to the flash medium of the solid state disk in sequence. At this time, the flash translation layer sends a stop instruction to the DMA controller to end the work and release the occupied DMA channel. At the same time, the flash translation layer can report to the upper-layer application or operating system that the entire write operation has been successfully completed.

[0118] Step S1057: If the DMA task queue is not empty, the next DMA write task is read and executed by the DMA controller until the DMA task queue is empty.

[0119] In step S1057, if the result of the judgment in step S1055 is no, i.e. there are still DMA write tasks to be processed in the DMA task queue, the DMA controller will immediately access the updated head, read the next DMA write task. Then, the system will repeat the data transmission operation in step S1054 and the task completion processing operation in step S1055. This reading, execution, deletion, judgment cycle will continue until the DMA task queue is finally empty, thus triggering the completion logic in step S1056.

[0120] For the convenience of understanding, the following will take a specific example to explain steps S1051-S1057: Suppose the data layout description header of a write request contains two data segment entries, and the previous step has allocated a starting target write address of physical address PBA_1000 for the write request. The first data segment entry describes that 4MB data needs to be read from host memory address HMA_A; the second data segment entry describes that 8MB data needs to be read from host memory address HMA_B. First, the flash translation layer of the solid state disk creates an empty DMA task queue in its internal memory. Then, the flash translation layer parses the first data segment entry, generates a DMA write task with the task parameters including source address HMA_A, length 4MB, target address PBA_1000, and inserts the task into the queue. Then, the flash translation layer parses the second data segment entry, generates a second DMA write task with the task parameters including source address HMA_B, length 8MB, target address PBA_1000 plus an offset of 4MB, and also inserts the task into the queue. At this time, there are two tasks in the queue. The flash translation layer activates the DMA controller, the DMA controller reads the first task from the head, and transmits 4MB data at host memory HMA_A to the PBA_1000 address of the solid state disk through the DMA channel. After the transmission is completed, the task is deleted from the queue. The flash translation layer judges that the queue is not empty, so the DMA controller reads the new head task, i.e. the second task. The DMA controller then transmits 8MB data at host memory HMA_B to the address of PBA_1000 plus an offset of 4MB of the solid state disk. After the transmission is completed, the second task is also deleted. At this time, the flash translation layer judges that the queue is empty, and controls the DMA controller to stop working, and the entire data write operation of 12MB data containing two data segments is declared complete.

[0121] The following describes a solid state disk-based data transmission device in the embodiment of the application from the perspective of hardware processing. Please refer to Figure 3 , which is a structural schematic diagram of a solid state disk-based data transmission device in the embodiment of the application.

[0122] It should be noted that,Figure 3 The structure of the data transmission device based on the solid state disk shown is only an example and should not bring any limitation to the function and use range of the embodiments of the present application.

[0123] As shown in Figure 3 A data transmission device based on the solid state disk includes a central processing unit (CPU) 301 which can perform various appropriate actions and processes, such as the methods described in the above embodiments, according to programs stored in a read-only memory (ROM) 302 or loaded from a storage section 308 into a random access memory (RAM) 303. Various programs and data required for the operation of the device are also stored in the RAM 303. The CPU 301, the ROM 302, and the RAM 303 are connected to each other through a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0124] The following components are connected to the I / O interface 305: an input section 306 including an audio input device, a push button switch, and the like; an output section 307 including a liquid crystal display (LCD) and an audio output device, an indicator lamp, and the like; the storage section 308 including a hard disk, and the like; and a communication section 309 including a network interface card such as a LAN (Local Area Network) card, a modem, and the like. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as necessary. A removable media 311 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like is attached to the drive 310 as necessary so that a computer program read therefrom is installed into the storage section 308 as necessary.

[0125] In particular, the processes described above with reference to the flowcharts can be implemented as a computer software program according to the embodiments of the present application. For example, the embodiments of the present application include a computer program product including a computer program carried on a computer readable medium, the computer program containing a computer program for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication section 309 and / or installed from the removable media 311. When the computer program is executed by the central processing unit (CPU) 301, various functions defined in the present application are performed.

[0126] Note that specific examples of computer-readable storage media can include but are not limited to an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer-readable storage medium can be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0127] The flow charts and block diagrams in the attached drawings are used to illustrate the architecture, functionality, and operation of possible implementations of apparatuses, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow charts or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.

[0128] Specifically, the data transmission apparatus based on a solid state disk in the embodiment comprises a processor and a memory, and the memory stores a computer program. When the computer program is executed by the processor, the data transmission method based on a solid state disk provided in the above embodiment is implemented.

[0129] As another aspect, the present application further provides a computer-readable storage medium. The storage medium can be included in the data transmission apparatus based on a solid state disk described in the above embodiments, or can exist separately and not be assembled into the data transmission apparatus based on a solid state disk. The storage medium carries one or more computer programs. When the one or more computer programs are executed by a processor of the data transmission apparatus based on a solid state disk, the data transmission apparatus based on a solid state disk implements the data transmission method based on a solid state disk provided in the above embodiments.

Claims

1. A data transfer method based on a solid-state drive, characterized in that, The method includes: Receive a write command sent by the host, which includes the starting address of the target memory and the total length of the data; Based on the target memory start address, a data layout description header is obtained from the host memory via direct memory access. The data layout description header is a preset data structure, located at the target memory start address, and contains at least one data segment entry. The data layout description header is parsed through the flash conversion layer of the solid-state drive to identify each data segment entry, and the length information and lifecycle attribute label of the corresponding data segment are extracted from each data segment entry; Based on the lifecycle attribute tags, a corresponding physical flash page is planned for each data segment as the target write address of the data segment; Based on the target write address, the solid-state drive is controlled to perform DMA operations segment by segment according to the order of the data segment entries in the data layout description header, until the total length of data is written.

2. The method according to claim 1, characterized in that, The step of parsing the data layout description header through the flash translation layer of the solid-state drive to identify each data segment entry specifically includes: In the flash conversion layer of the solid-state drive, a parser corresponding to the data layout description header is defined. The parser contains the data structure definition information of the data layout description header and the data structure definition information of the data segment entries. The parser is used to decode the binary data content of the data layout description header byte by byte to obtain the start flag and end flag of the data layout description header; The effective data length of the data layout description header is obtained based on the start flag and the end flag. Based on the effective data length and the data structure definition information of the data segment entries, each data segment entry is parsed from the effective data of the data layout description header.

3. The method according to claim 1, characterized in that, The step of planning a corresponding physical flash page as the target write address for each data segment based on the lifecycle attribute tag specifically includes: Based on the model and capacity of the solid-state drive, multiple physical storage partitions are divided, and a corresponding lifecycle attribute tag is assigned to each physical storage partition; In the flash conversion layer of the solid-state drive, a mapping table is created between the lifecycle attribute tags and the physical storage partitions. When the solid-state drive is idle, the mapping relationship between the lifecycle attribute tags and the physical storage partitions is adjusted to update the mapping table. When the target lifecycle attribute tag of the target data segment entry is parsed, the target physical storage partition corresponding to the target lifecycle attribute tag is searched in the mapping table, and the starting address and number of free pages of the target physical storage partition are obtained. The target data segment entry is any one of the multiple data segment entries. Based on the data segment length corresponding to the target data segment entry, the number of target pages required to write the target data segment entry is calculated; If the number of free pages is greater than or equal to the number of target pages, then starting from the starting address of the target physical storage partition, a number of physical flash pages equal to the number of target pages are allocated as the target write address.

4. The method according to claim 3, characterized in that, The step of adjusting the mapping relationship between the lifecycle attribute tag and the physical storage partition when the solid-state drive is idle specifically includes: When the solid-state drive is idle, monitor the erase / write balance of each physical storage partition; When the difference in erase / write balance between the first physical storage partition and the second physical storage partition exceeds a preset threshold, the first lifecycle attribute tag corresponding to the first physical storage partition and the second lifecycle attribute tag corresponding to the second physical storage partition are obtained. The first physical storage partition and the second physical storage partition are any two physical storage partitions of the solid-state drive, and the erase / write balance of the first physical storage partition is higher than that of the second physical storage partition. Update the first physical storage partition to the new first physical storage partition, and update the second physical storage partition to the new second physical storage partition; Establish a mapping relationship between the first lifecycle attribute tag and the new second physical storage partition, and establish a mapping relationship between the second lifecycle attribute tag and the new first physical storage partition.

5. The method according to claim 4, characterized in that, The step of updating the first physical storage partition to a new first physical storage partition and updating the second physical storage partition to a new second physical storage partition specifically includes: All valid data in the first physical storage partition is migrated to the available free pages of the second physical storage partition to obtain the new second physical storage partition; The first physical storage partition after data migration is completed is completely erased to obtain a new first physical storage partition containing consecutive free pages.

6. The method according to claim 3, characterized in that, After obtaining the starting address and number of free pages of the target physical storage partition, the method further includes: If the number of free pages is less than the number of target pages, a garbage collection operation is triggered for the target physical storage partition to reclaim invalid pages in the target physical storage partition and convert the invalid pages into available free pages. After the garbage collection operation is completed, the number of free pages in the target physical storage partition after garbage collection is obtained, and it is determined whether the number of free pages after garbage collection is greater than or equal to the target number of pages. If so, then starting from the starting address of the target physical storage partition, allocate physical flash pages equal to the number of target pages as the target write address; If not, the lifecycle attribute label of the target data segment entry is upgraded and adjusted to obtain a new lifecycle attribute label, and the corresponding new physical storage partition is searched again in the mapping table according to the new lifecycle attribute label.

7. The method according to claim 1, characterized in that, Based on the target write address, controlling the solid-state drive to perform DMA operations segment by segment according to the order of data segment entries in the data layout description header until the total data length is written, specifically includes: In the flash memory translation layer of the solid-state drive, a DMA task queue is created; According to the order of the data segment entries in the data layout description header, a corresponding DMA write task is generated for each data segment entry, and the DMA write task is inserted into the tail of the DMA task queue. The DMA controller of the solid-state drive reads and executes each DMA write task sequentially, starting from the head of the DMA task queue. For each DMA write task, according to the task parameters, target data of a specified length is read from a specified starting address in the host memory through the DMA channel and written to the target write address on the solid-state drive; After the DMA write task is completed, the DMA write task is deleted from the DMA task queue, and it is determined whether the DMA task queue is empty. If the DMA task queue is empty, it indicates that the total length of data has been written and the DMA controller is stopped. If the DMA task queue is not empty, the DMA controller reads and executes the next DMA write task until the DMA task queue is empty.

8. A data transmission device based on a solid-state drive, characterized in that, The solid-state drive-based data transfer device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors call the computer instructions to cause the solid-state drive-based data transfer device to perform the method as described in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on a solid-state drive-based data transfer device, the solid-state drive-based data transfer device performs the method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the computer program product is run on a solid-state drive-based data transfer device, the solid-state drive-based data transfer device performs the method as described in any one of claims 1-7.

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