Code conversion method from Verilog-A model to C + + table model

Abstract

The invention relates to a code conversion method from a Verilog-A model to a C + + table model and a storage medium, and belongs to the technical field of electronic design automation. The method comprises the steps that a Verilog-A analysis model is read in, and model analysis and preprocessing are conducted; on the basis of preset configuration information, after discretization sampling is carried out on the analytical expression of the model, the original analytical expression is replaced with a C + + type instance for processing the table model; and converting a mathematical function and a system function built in the Verilog-A into an equivalent C / C + + standard library function or a custom function in the simulator, and finally generating a C + + table model source code capable of accessing the simulator. According to the method, derivative calculation is converted into efficient multiplexing of interpolation coefficients, so that the iteration efficiency and the simulation performance are improved; through an automatic code conversion mode, the coding efficiency is improved, and rapid iterative development is realized; and the balance between precision and speed can be adjusted according to requirements.

Description

Technical Field

[0001] This invention belongs to the field of electronic design automation technology. Specifically, this invention relates to a code conversion method and storage medium for converting a Verilog-A model to a C++ tabular model. Background Technology

[0002] A compact model of a semiconductor device is a set of formulas describing the device's electrical characteristics, including the functional relationships between the device's port voltage, current, and charge, i.e., IV and QV characteristics. Compact models are primarily used in transistor-level circuit simulation. During each iteration of solving the differential equations, the simulator calls a model evaluation subroutine to calculate the device's current, charge, conductance, capacitance, and other physical quantities under the current operating point conditions such as bias voltage and temperature, and fills the results into the right-hand side and coefficient matrix of the equations.

[0003] Traditional intensive models are based on the C programming language. Model developers not only need to construct the formulas for IV and QV characteristics (corresponding to the right-hand side), but also need to handle their first derivatives with respect to node voltages (corresponding to the coefficient matrix). This method involves a large amount of engineering work and is prone to errors. With advanced processes, transistor models introduce more model parameters, conditional branches, and internal nodes to describe more complex physical effects and adapt to different processes and geometries. This makes device models increasingly complex, making it very impractical to develop models directly based on the C programming language.

[0004] Currently, Verilog-A, the hardware description language, has become the de facto standard for intensive model development. Model developers only need to focus on the physical formulas themselves, without needing to handle symbolic derivatives, thus transferring the complexity of model implementation to simulator developers. To integrate a model into a simulator, simulator developers must first convert the Verilog-A source code into machine-compilable C / C++ code. The main difficulty lies in handling the symbolic derivative-related code. Due to the expression swell effect of symbolic derivatives, for complex models, the amount of code related to symbolic derivatives can be several times the original code. Furthermore, since symbolic derivative code is generally machine-generated, it has poor readability and is difficult to maintain and debug. During the iterative cycle of a simulator developer implementing a new model, even minor changes to the Verilog-A source code can cause significant changes in the symbolic derivative code. Once inconsistencies in accuracy occur, locating the specific problem is difficult. These factors all contribute to the low development efficiency and slow iteration when integrating new models into simulators. Summary of the Invention

[0005] To overcome the shortcomings of existing Verilog-A analytical models in circuit simulation, such as computational complexity and low development efficiency, and to avoid complex symbolic differentiation processes and quickly obtain the Jacobian matrix information corresponding to the model, the first aspect of this invention provides a code conversion method from a Verilog-A model to a C++ tabular model, including the following steps:

[0006] S10: Read in the Verilog-A analytical model and perform model analysis and preprocessing;

[0007] S20, based on the preset configuration information, after discretizing and sampling the analytical expression of the model, the original analytical expression is replaced with an instance of the C++ class for processing the table model;

[0008] S30 converts the built-in mathematical and system functions of Verilog-A into equivalent C / C++ standard library functions or user-defined functions within the simulator, ultimately generating C++ table model source code that can be accessed by the simulator.

[0009] Furthermore, step S10 specifically includes:

[0010] S11, Read the source code of the Verilog-A analytical model to obtain the device instance parameters;

[0011] S12 analyzes the internal nodes and topology of the model, identifying linear and nonlinear branches;

[0012] S13, determine whether the model contains nonlinear branches. If it contains nonlinear branches, extract the current and charge contribution statements of the nonlinear branches and separate the static current contribution and dynamic charge contribution into independent variables. If it does not contain nonlinear branches, jump to step S30.

[0013] Furthermore, the model parsing and preprocessing includes lexical analysis, syntactic analysis, and semantic analysis;

[0014] The linear branch is a branch in which the current is proportional to the voltage;

[0015] The nonlinear branch is a branch in which the current and voltage are not proportional;

[0016] The static current contribution is the current characteristic under steady-state conditions;

[0017] The dynamic charge contribution is the charge characteristic during the change process;

[0018] The preset configuration information includes preset power supply voltage range, sampling area division, and sampling step size information for each area;

[0019] The C++ class for processing the table model is defined by the target simulator.

[0020] Further, step S20 specifically includes:

[0021] S21. Based on the preset configuration information and the analytical expression of the model, the nonlinear relationship between the static current contribution, the dynamic charge contribution and the control voltage is discretized and sampled according to the intelligent sampling strategy, and the results are stored in array form to obtain the current value array and the charge value array.

[0022] S22 stores the discretized current and charge value arrays in the form of a lookup table, and replaces the original analytical expression with an instance of a C++ class that processes the table model.

[0023] Furthermore, the discretization sampling specifically includes:

[0024] For each voltage sampling point V_sample[i], perform discretization sampling:

[0025] I_table[i]=IS*(exp(V_sample[i] / (N*$vt))-1),

[0026] Q_table[i]=CJ0*VJ*2*(1-sqrt(1-V_sample[i] / VJ)),

[0027] Where V_sample[i] is the voltage at the i-th voltage sampling point, I_table[i] is the current value at the i-th voltage sampling point, Q_table[i] is the charge value at the i-th voltage sampling point, IS is the saturation current, N is the emission coefficient, CJ0 is the zero-bias junction capacitance, VJ is the junction potential, and $vt is the thermal voltage.

[0028] Furthermore, the intelligent sampling strategy includes: a balanced sampling strategy and a segmented sampling strategy.

[0029] Furthermore, the balanced sampling strategy specifically includes:

[0030] By using configuration files, different sampling strategies can be employed in different application scenarios to balance the relationship between sampling accuracy and application efficiency, including:

[0031] S211 employs a dense sampling configuration for high-precision scenarios;

[0032] S212 employs a sparse sampling configuration for high-speed scenarios.

[0033] Furthermore, the segmented sampling strategy specifically includes:

[0034] Segmented sampling is performed based on the degree of nonlinearity, dividing the region into segments, including:

[0035] S213, for areas with drastic changes, a dense sampling configuration is used;

[0036] S214. For regions with gradual changes, a sparse sampling configuration is used.

[0037] Furthermore, the C++ table model source code provides the following functionality during simulation runtime:

[0038] S31 calculates the current and charge values ​​at any voltage within the power supply voltage range by using table lookup and linear interpolation algorithms.

[0039] S32 calculates the current and charge values ​​at voltage points outside the power supply voltage range using a linear extrapolation algorithm and boundary values.

[0040] S33 simultaneously obtains approximate values ​​of the differential of current with respect to voltage and the differential of charge with respect to voltage during table lookup and interpolation.

[0041] In a second aspect, the present invention provides a processor-readable storage medium storing a computer program, wherein when the processor executes the computer program, it implements the code conversion method for converting a Verilog-A model to a C++ tabular model as described in the first aspect of the present invention.

[0042] The advantages of this invention compared to the prior art are:

[0043] This invention overcomes the shortcomings of existing Verilog-A analytical models in circuit simulation, such as computational complexity and low development efficiency. It automatically converts the analytical model code based on the behavioral hardware description language Verilog-A into compileable and executable C++ tabular model code for use in transistor-level circuit simulation systems. Unlike strictly analytical models, this invention uses tabular modeling technology, employing sampling and interpolation methods to numerically approximate the analytical model. In the initial stage, a table is established by sampling information such as current and charge from the analytical model. During simulation iterations, the analytical model is no longer invoked; instead, the table is looked up based on the current bias voltage, and interpolation and extrapolation are used to calculate the results. This avoids complex symbolic differentiation and enables rapid acquisition of the Jacobian matrix information corresponding to the model. This invention has the following advantages:

[0044] Improvements in simulation speed: Replacing complex mathematical calculations with simple table lookup and interpolation, by sacrificing a small amount of accuracy, transforms derivative calculations into efficient reuse of interpolation coefficients, resulting in more efficient model development iterations and better simulation performance.

[0045] Reduction in resource consumption: Transforming complex symbolic operations into simple numerical operations can avoid the heavy computational burden of symbolic differentiation for complex nonlinear analytical expressions, and table lookup operations are also more efficient than analytical computations.

[0046] Improved development efficiency: Automated code conversion enhances coding efficiency, enabling rapid prototype verification and iterative development. This conversion method allows even engineers unfamiliar with complex mathematical formulas to quickly perform circuit simulations using tabular models, significantly lowering the technical barrier and boosting development efficiency.

[0047] It has a wide range of applications and high flexibility: the balance between accuracy and speed can be adjusted according to the needs, which can ensure the high accuracy of small circuits and meet the high efficiency requirements of large circuits. Attached Figure Description

[0048] Figure 1 A flowchart illustrating a code conversion method from a Verilog-A model to a C++ tabular model, provided as an embodiment of the present invention.

[0049] Figure 2 The circuit schematic diagram of the diode model provided in the embodiment of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0051] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0052] Method Implementation Examples

[0053] This invention discloses a code conversion method from Verilog-A model to C++ tabular model, which can overcome the shortcomings of existing Verilog-A analytical models in circuit simulation, such as computational complexity and low development efficiency. It eliminates the heavy computational burden of symbolic differentiation for complex nonlinear analytical expressions, transforms derivative calculation into efficient reuse of interpolation coefficients, and achieves more efficient model development iteration efficiency and better simulation performance. It can be used for rapid prototype verification and iterative development.

[0054] In a first aspect, the present invention provides a method for converting a Verilog-A model to a C++ tabular model, the flowchart of which is attached. Figure 1 As shown, it specifically includes:

[0055] S10: Read in the Verilog-A analytical model and perform model analysis and preprocessing.

[0056] Specifically, including:

[0057] S11: Read the source code of the Verilog-A analytical model to obtain the device instance parameters.

[0058] The embodiments of the present invention will be described below using a simple diode model as an example. The circuit diagram of the diode model is shown below. Figure 2 As shown, the Verilog-A analytical model source code for this model is shown below.

[0059] modulediode(a,c);

[0060] inout a,c;

[0061] electrical a,c,ci;

[0062] (*desc="Saturation current",units="A"*)parameterreal IS=1e-14

[0063] (*desc="Ohmic resistance",units="Ohm"*)parameterreal RS=0.0

[0064] (*desc="Emission coefficient"*)parameterreal N=1.0

[0065] (*desc="Junction capacitance",units="F"*)parameterreal CJ0=0.0

[0066] (*desc="Junctionpotential",units="V"*)parameter real VJ=1.0;

[0067] (*desc="Minimum resistance",units="Ohm"*)parameter real MINR=1e-3

[0068] real id = 0.0, qd = 0.0;

[0069] analogbegin

[0070] if (RS>MINR) begin

[0071] I(ci,c)<+V(ci,c) / RS;

[0072] end else begin

[0073] V(ci,c)<+0.0;

[0074] end

[0075] id=IS*(exp(V(a,ci) / (N*$vt))-1);

[0076] qd=CJ0*VJ*2*(1-sqrt(1–V(a,ci) / VJ));

[0077] I(a,ci)<+id+ddt(qd);

[0078] end

[0079] endmodule

[0080] This Verilog-A code defines a diode model, which includes the following parameters:

[0081] IS: Saturation current, which represents the leakage current of a diode when it is reverse biased, and determines the diode's current-voltage characteristic curve.

[0082] RS: Ohmic resistance, representing the bulk resistance of the diode semiconductor material, which affects the voltage drop of the diode when it is operating at high current.

[0083] N: Emission coefficient, used to correct the difference between the ideal diode equation and the actual device, reflecting the non-ideal characteristics of the PN junction.

[0084] CJ0: Zero-bias junction capacitance, which represents the PN junction capacitance of the diode at zero bias voltage and affects the frequency characteristics of the diode.

[0085] VJ: Junction potential, which is the built-in potential difference of the PN junction of a diode, and determines the characteristic of the junction capacitance changing with voltage.

[0086] MINR: Minimum resistance, used to prevent singularities in numerical calculations. When RS is very small, it provides a lower limit to maintain the stability of circuit simulation.

[0087] This step involves reading the source code of the Verilog-A analytical model described above, performing model parsing and preprocessing, including:

[0088] Lexical analysis: decomposes Verilog-A code into basic units such as keywords, identifiers, and operators;

[0089] Syntax analysis: Constructing an abstract syntax tree (AST) to identify the structure of contribution statements;

[0090] Semantic analysis: Establish a symbol table and resolve variable dependencies.

[0091] Device instance parameters, such as IS = 1e-14 and RS = 10, can be obtained through model analysis and preprocessing.

[0092] S12 analyzes the internal nodes and topology of the model, identifying linear and nonlinear branches.

[0093] Based on the device instance parameters, the internal nodes and topology of the model are determined, thereby identifying linear and nonlinear branches. Linear branches are those where current and voltage are directly proportional, while nonlinear branches are those where current and voltage are not directly proportional, such as the a-ci branch of a diode. For example, as described in the aforementioned Verilog-A analytical model source code and... Figure 2 As shown:

[0094] The diode model has three nodes (a, c, ci) and one mergeable node pair (c, ci). The properties of each branch are analyzed based on its contribution statement. For branch (c, ci), the current is proportional to the corresponding branch voltage, thus it is a linear branch. However, branch (a, ci) is a branch where the current and voltage are not proportional, thus it is nonlinear.

[0095] S13, determine whether the model contains nonlinear branches. If it contains nonlinear branches, extract the current and charge contribution statements of the nonlinear branches and separate the static current contribution and dynamic charge contribution into independent variables. If it does not contain nonlinear branches, jump to step S30.

[0096] For example, as mentioned above, the Verilog-A analytical model source code and Figure 2 As shown:

[0097] Branch (a, ci) is a nonlinear branch, requiring the extraction of both static current contribution and dynamic charge contribution. The static current contribution represents the current characteristics under steady-state conditions, while the dynamic charge contribution represents the charge characteristics during the changing process.

[0098] The expression without the ddt operator describes the DC characteristics of the model, where id is the nonlinear current component of the diode characteristic curve; the expression with the ddt operator explicitly applied describes the AC characteristics. qd is the nonlinear junction capacitance charge of the diode.

[0099] S20, based on preset configuration information, discretizes and samples the analytical expression of the model, and then replaces the original analytical expression with an instance of a C++ class for processing table models.

[0100] The preset configuration information includes preset power supply voltage range, sampling area division, sampling step size for each area, and other configuration information.

[0101] The S20 steps specifically include:

[0102] S21. Based on the preset configuration information and the analytical expression of the model, the nonlinear relationship between the static current contribution, the dynamic charge contribution and the control voltage is discretized and sampled according to the intelligent sampling strategy, and the results are stored in array form to obtain the current value array and the charge value array.

[0103] For example, the power supply voltage range is set according to the parameters preset in the configuration file, such as -1.5V to +1.5V.

[0104] For each voltage sampling point V_sample[i], perform discretization sampling:

[0105] I_table[i]=IS*(exp(V_sample[i] / (N*$vt))-1),

[0106] Q_table[i]=CJ0*VJ*2*(1-sqrt(1-V_sample[i] / VJ)),

[0107] Where V_sample[i] is the voltage at the i-th voltage sampling point, I_table[i] is the current value at the i-th voltage sampling point, Q_table[i] is the charge value at the i-th voltage sampling point, and $vt is the thermal voltage.

[0108] The intelligent sampling strategy includes: a balanced sampling strategy and a segmented sampling strategy.

[0109] The balanced sampling strategy, through a configuration file, uses different sampling strategies in different application scenarios to balance the relationship between sampling accuracy and application efficiency, including:

[0110] S211, for high-precision scenarios, adopts dense sampling configuration, and the error can be controlled to the floating-point precision range;

[0111] S212 employs a sparse sampling configuration for high-speed scenarios, improving simulation speed through a moderate loss of accuracy.

[0112] For simulations of single-device circuits or small circuits, if memory is sufficient and simulation performance is not the primary concern, the grid can be set to be very fine. This allows the behavior of the table model to approximate the original analytical curve as closely as possible, and the error can theoretically be controlled within the range allowed by the floating-point precision of the computer, achieving a high-fidelity reproduction of the analytical model's behavior. For larger-scale circuits, the grid density can be appropriately relaxed to reduce the memory overhead of the table and improve the lookup speed, thereby accelerating the simulation with a suitable loss of precision.

[0113] The segmented sampling strategy involves dividing the region into segments based on the degree of nonlinearity, including:

[0114] S213, For areas with drastic changes, a dense sampling configuration is adopted (e.g., one point is sampled every 1mV);

[0115] S214. For regions with gradual changes, a sparse sampling configuration is used (e.g., one point is sampled every 10mV).

[0116] For example, based on the characteristics of the diode model, the nonlinearity of the output characteristics is very strong when forward biased and weak when reverse biased. Therefore, the sampling region can be divided with a threshold of 0.5V. If the voltage is higher than 0.5V, the sampling step is 1mV. If it is lower than 0.5V, the sampling step is 10mV. If the voltage exceeds the defined range of the power supply voltage, linear extrapolation is used.

[0117] S22 stores the discretized current and charge value arrays in the form of a lookup table, while replacing the original analytical expression with an instance of a C++ class that processes the table model.

[0118] The C++ class that handles the tabular model is defined internally by the target simulator, and its instance loads all data tables during construction. This class also contains some pre-implemented interface functions, such as memory management functions, linear interpolation functions, linear extrapolation functions, and table lookup functions. During simulation, the simulator engine calls these interface functions to complete the model calculations.

[0119] S30 converts the built-in mathematical and system functions of Verilog-A into equivalent C / C++ standard library functions or user-defined functions within the simulator, ultimately generating C++ table model source code that can be accessed by the simulator.

[0120] In this step, the built-in mathematical and system functions used in the Verilog-A source code are identified and replaced with equivalent C / C++ standard library functions or built-in functions or variables of the simulator.

[0121] For example, the Verilog-A built-in function exp can be replaced with the corresponding exponential function in the C standard math library (libm); the Verilog-A built-in variable $vt can be replaced with the simulator's built-in function, such as constants::ThermalVoltage(double T), where constants is the namespace of the simulator's internal physical constants library functions, and T is the temperature parameter.

[0122] The C++ table model source code provides the following functionality during simulation runtime:

[0123] S31 calculates the current and charge values ​​at any voltage within the power supply voltage range by using table lookup and linear interpolation algorithms.

[0124] S32 calculates the current and charge values ​​at voltage points outside the power supply voltage range using a linear extrapolation algorithm and boundary values.

[0125] S33, since the derivative form of linear interpolation and extrapolation is simple, that is, a fixed constant coefficient (the slope between sampling points), the approximate values ​​of the differential of current with respect to voltage (conductance) and the differential of charge with respect to voltage (capacitance) can be obtained simultaneously when looking up tables and interpolating.

[0126] Thus, the calculation of the model's IV, QV characteristics, and their derivatives required during simulation is transformed from complex analytical calculations into simple arithmetic operations. Through this method, the present invention, by sacrificing some accuracy, avoids the heavy computational burden of symbolic differentiation for complex nonlinear analytical expressions, transforming derivative calculation into efficient reuse of interpolation coefficients. This results in more efficient model development iterations and better simulation performance, suitable for rapid prototype verification and iterative development. It achieves the conversion from analytical calculations to arithmetic operations, maintains the synchronous calculation capability of IV / QV characteristics and their derivatives, provides configurable discretization strategies to adapt to different simulation needs, fully retains the ability to model nonlinear characteristics, and supports boundary value handling and extrapolation calculations beyond the defined domain.

[0127] Steps S22 and S30 are different steps. The main difference is that step S22 replaces the contribution statement and discretizes the nonlinear analytical expression, which is the main part of the method; step S30 replaces the built-in mathematical functions and system functions of Verilog-A. When the model does not use the built-in functions of Verilog-A, step S30 can be omitted.

[0128] In a second aspect, the present invention provides a processor-readable storage medium storing a computer program, wherein when the processor executes the computer program, it implements the code conversion method for converting a Verilog-A model to a C++ tabular model as described in the first aspect of the present invention.

[0129] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for converting Verilog-A models to C++ tabular models, characterized in that, Includes the following steps: S10: Read in the Verilog-A analytical model and perform model analysis and preprocessing; S20, based on the preset configuration information, after discretizing and sampling the analytical expression of the model, the original analytical expression is replaced with an instance of the C++ class for processing the table model; S30 converts the built-in mathematical and system functions of Verilog-A into equivalent C / C++ standard library functions or user-defined functions within the simulator, ultimately generating C++ table model source code that can be accessed by the simulator.

2. The conversion method according to claim 1, characterized in that, Step S10 specifically includes: S11, Read the source code of the Verilog-A analytical model to obtain the device instance parameters; S12 analyzes the internal nodes and topology of the model, identifying linear and nonlinear branches; S13, determine whether the model contains nonlinear branches. If it contains nonlinear branches, extract the current and charge contribution statements of the nonlinear branches and separate the static current contribution and dynamic charge contribution into independent variables. If it does not contain nonlinear branches, jump to step S30.

3. The conversion method according to claim 2, characterized in that: The model parsing and preprocessing include lexical analysis, syntactic analysis, and semantic analysis; The linear branch is a branch in which the current is proportional to the voltage; The nonlinear branch is a branch in which the current and voltage are not proportional; The static current contribution is the current characteristic under steady-state conditions; The dynamic charge contribution is the charge characteristic during the change process; The preset configuration information includes preset power supply voltage range, sampling area division, and sampling step size information for each area; The C++ class for processing the table model is defined by the target simulator.

4. The conversion method according to claim 3, characterized in that, Step S20 specifically includes: S21. Based on the preset configuration information and the analytical expression of the model, the nonlinear relationship between the static current contribution, the dynamic charge contribution and the control voltage is discretized and sampled according to the intelligent sampling strategy, and the results are stored in array form to obtain the current value array and the charge value array. S22 stores the discretized current and charge value arrays in the form of a lookup table, and replaces the original analytical expression with an instance of a C++ class that processes the table model.

5. The conversion method according to claim 4, characterized in that, The discretization sampling specifically includes: For each voltage sampling point V_sample[i], perform discretization sampling: I_table[i]=IS*(exp(V_sample[i] / (N*$vt))-1), Q_table[i]=CJ0*VJ*2*(1-sqrt(1-V_sample[i] / VJ)), Where V_sample[i] is the voltage at the i-th voltage sampling point, I_table[i] is the current value at the i-th voltage sampling point, Q_table[i] is the charge value at the i-th voltage sampling point, IS is the saturation current, N is the emission coefficient, CJ0 is the zero-bias junction capacitance, VJ is the junction potential, and $vt is the thermal voltage.

6. The conversion method according to claim 4, characterized in that, The intelligent sampling strategy includes: a balanced sampling strategy and a segmented sampling strategy.

7. The conversion method according to claim 6, characterized in that, The balanced sampling strategy specifically includes: By using configuration files, different sampling strategies can be employed in different application scenarios to balance the relationship between sampling accuracy and application efficiency, including: S211 employs a dense sampling configuration for high-precision scenarios; S212 employs a sparse sampling configuration for high-speed scenarios.

8. The conversion method according to claim 6, characterized in that, The segmented sampling strategy specifically includes: Segmented sampling is performed based on the degree of nonlinearity, dividing the region into segments, including: S213, for areas with drastic changes, a dense sampling configuration is used; S214. For regions with gradual changes, a sparse sampling configuration is used.

9. The conversion method according to claim 1, characterized in that, The C++ table model source code provides the following functionality during simulation runtime: S31 calculates the current and charge values ​​at any voltage within the power supply voltage range by using table lookup and linear interpolation algorithms. S32 calculates the current and charge values ​​at voltage points outside the power supply voltage range using a linear extrapolation algorithm and boundary values. S33 simultaneously obtains approximate values ​​of the differential of current with respect to voltage and the differential of charge with respect to voltage during table lookup and interpolation.

10. A processor-readable storage medium, characterized in that, The processor-readable storage medium stores a computer program, and when the processor executes the computer program, it implements a code conversion method from a Verilog-A model to a C++ tabular model as described in any one of claims 1 to 9.

Images