Configurable semiconductor equipment software interlocking control method and system

Abstract

The invention discloses a configurable semiconductor equipment software interlocking control method and system. The method comprises the following steps: S1, sorting equipment safety interlocking rules; s2, sorting IO point position signals of the equipment and required intermediate data variables based on interlocking rule requirements; s03, according to equipment instruction behaviors, IO point position signals and needed intermediate data variables are divided into a Trigger group and a Limit group, a corresponding Action group is generated, the Trigger group, the Limit group and the Action group are combined and matched, and interlocking entries are formed; s4, writing the interlocking entry into a software configuration file, so that the interlocking rule is separated from a software code; and S5, writing the interlocking configuration information into a software configuration file so as to perfect the interlocking content based on the interlocking entry and match the safety interlocking requirement of the specific equipment. According to the invention, the flexibility and portability of interlocking control of the semiconductor equipment are realized by adopting a configurable mode.

Description

Technical Field

[0001] This invention relates primarily to the field of semiconductor device control, and more specifically to a configurable semiconductor device software interlock control method and system. Background Technology

[0002] Interlock control in semiconductor equipment is a crucial component in ensuring the safety of both the equipment and personnel. The content of interlock control may change during equipment use or maintenance and debugging, such as ignoring a certain interlock, delaying the interlock trigger check time, or escalating the severity of an interlock trigger from a warning to an alarm. If the interlock rules are implemented internally in the software code, each change may require a software version update, causing inconvenience for equipment debugging and optimization. Furthermore, if interlocks are implemented internally in the code, the code is highly bound to the current device, making it difficult to extend the software to other devices. Summary of the Invention

[0003] To address the technical problems existing in the prior art, the present invention provides a configurable semiconductor device software interlock control method and system that achieves flexibility and portability of semiconductor device interlock control in a configurable manner.

[0004] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows: A configurable semiconductor device software interlock control method includes the following steps: S1. Review the equipment safety interlock rules, and determine the interlock rule requirements for personal safety and equipment safety. S2. Based on the interlocking rules of S1, sort out the device IO point signals and the required intermediate data variables; S03. Based on the device instruction behavior, divide the corresponding IO point signals and the required intermediate data variables sorted in S2 into Trigger group and Limit group, and generate the corresponding Action group. Use AND, OR, NOT and other logical relationships to combine and match Trigger, Limit and Action to form interlock entries. S4. Write the interlock entries formed in step S3 into the software configuration file to separate the interlock rules from the software code; S5. Write the interlock configuration information into the software configuration file to complete the interlock content based on the interlock entries in S3 and match the safety interlock requirements of specific devices.

[0005] Preferably, the device I / O point signals and the required intermediate data variables in step S2 include digital signals DI and DO, analog signals AI and AO, and intermediate data variables.

[0006] Preferably, in step S3, the Trigger is a prerequisite condition that the interlock trigger must meet. There are multiple triggers in the Trigger group. The precondition of the Trigger group is specified by the combination of AND, OR, and NOT logical relationships between the multiple triggers. Limit is the constraint condition for interlocking. It specifies whether the constraint condition of a limit group is met by using AND, OR, and NOT logical relationships between multiple Limits. Once the Trigger group is satisfied, the corresponding Limit group is automatically checked for satisfaction. If both the Trigger and Limit groups are satisfied, the corresponding Action group's action instruction is triggered.

[0007] Preferably, in step S5, the interlock configuration information includes one or more of the following: whether to ignore interlock, whether to trigger an alarm when interlock is triggered, interlock prompt details, and interlock detection time.

[0008] Preferably, in step S5, whether to ignore interlocks includes ignoring a single interlock entry, ignoring all interlock entries, ignoring a trigger in the Trigger group of a single interlock entry, ignoring a limit in the Limit group of a single interlock entry, and ignoring an action in the Action group of a single interlock entry.

[0009] Preferably, in step S5, the alarms are divided into different levels, including Warning and Alarm.

[0010] Preferably, in step S5, the interlock prompt details include: when configuring the interlock content, configuring a corresponding tip for each trigger, limit, and action, so that the software can provide a detailed reason for triggering the interlock when the interlock is triggered.

[0011] Preferably, in step S5, the interlock detection time includes: the device interlock trigger may be triggered immediately or after a fixed period of time; when configuring the interlock content, the interlock detection time is configured. If the interlock detection time is set to 0, the interlock will be triggered immediately after the condition is met; if the interlock detection time is configured to the required time, the interlock action will be triggered after the interlock condition is met for a set period of time.

[0012] Preferably, it also includes S6: before verifying the correctness of the interlock on the actual device, test whether the interlock function is normal through software simulation, and determine whether the content of the interlock file is correct in advance through software simulation test; if the corresponding function is met, test whether the interlock function is normal on the device.

[0013] The present invention also discloses a configurable semiconductor device software interlock control system, including an interconnected memory and a processor, wherein the memory stores a computer program, and the computer program executes the steps of the method described above when run by the processor.

[0014] Compared with the prior art, the advantages of the present invention are as follows: The interlock content of this invention is stored as a configuration file, which is configurable and easy to operate. The interlock content is separated from the software code, which makes it easy to modify and optimize the interlock content without updating the software version, facilitating equipment debugging and improving software adaptability and portability. The interlock rules of this invention match the logical relationship between IO signals and device instruction behavior, and directly trigger the interlock by detecting whether the PLC's IO signals and intermediate variables of the device software meet the interlock conditions.

[0015] This invention separates interlock rules from software code, adopting a configurable approach to achieve flexibility and portability in semiconductor device interlock control. It effectively solves problems such as frequent software updates, severe device binding, and low debugging efficiency caused by hard-coded interlock rules in existing technologies. By supporting dynamic configuration of interlock conditions, flexible setting of trigger levels, detailed customization of prompt information, and adjustable detection time, it significantly improves the convenience of device debugging and maintenance, while enhancing the software's adaptability and functional scalability across different devices. Attached Figure Description

[0016] Figure 1 The flowchart illustrates an embodiment of the configurable semiconductor device software interlock control method of the present invention.

[0017] Figure 2 This is a schematic diagram illustrating the equipment safety interlock rules in this invention.

[0018] Figure 3 This is a schematic diagram of the I / O signal points of the device in this invention.

[0019] Figure 4 This is a schematic diagram of the interlock configuration file content in this invention. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 As shown, the configurable semiconductor device software interlock control method provided in this embodiment of the invention includes the following steps: S1. Review the equipment safety interlock rules, and determine the interlock rule requirements for personal safety and equipment safety. S2. Based on the interlocking rules of S1, organize the device IO point signals (such as...) Figure 3 (as shown) and the required intermediate data variables, including digital signals DI and DO, analog signals AI and AO, and intermediate data variables; S3. Based on the device instruction behavior, divide the corresponding IO point signals and the required intermediate data variables sorted in S2 into Trigger group and Limit group, and generate the corresponding Actin group. Use AND, OR, NOT and other logical relationships to combine and match Trigger, Limit and Action to form interlock entries. Specifically, according to the interlock rules, the device IO signals and intermediate data variables need to be divided into Trigger group and Limit group, and matched with Action group using logical relationships such as AND, OR, NOT, etc., to obtain specific interlock entries; Trigger groups are the prerequisites that must be met for interlocking to be triggered. There are multiple triggers in a Trigger group. The prerequisites of the Trigger group can be specified by combining AND, OR, and NOT logical relationships between multiple triggers. Limit groups are the constraints that trigger interlocks. A limit group includes multiple limits, and you can specify whether the limit group constraints are met by using AND, OR, and NOT logical relationships between multiple limits. Once the Trigger group is satisfied, the corresponding Limit group is automatically checked for satisfaction. If both the Trigger and Limit groups are satisfied, the corresponding Action group's action instruction is triggered.

[0022] S4. Write the interlock entries formed in step S3 into the corresponding configuration file according to the rules that the software can parse, so that the interlock rules are separated from the software code. S5. Transfer the interlock configuration information (such as...) Figure 4 As shown, write the interlocking entries into the software configuration file to complete the interlocking content and match the safety interlocking requirements of specific devices.

[0023] The interlock configuration information includes whether to ignore interlocks, whether an alarm is triggered when an interlock is activated, details of the interlock prompt, and the interlock detection time, such as... Figure 2 As shown; Whether to ignore interlocks: Supports ignoring a single interlock entry, ignoring all interlock entries, ignoring a specific trigger in the Trigger group of a single interlock entry, ignoring a specific limit in the Limit group of a single interlock entry, and ignoring a specific action in the Action group of a single interlock entry; ignoring interlocks facilitates equipment maintenance and debugging; Whether to trigger an alarm after interlock: Equipment interlocks can be divided into different levels, such as warning and alarm; different actions can be taken after a single interlock is triggered. If the severity level of the interlock is not high after it is triggered, it can be configured as a warning; if the severity level of the interlock is high after it is triggered, it can be configured as an alarm. Interlock details: When configuring interlock content, you can configure corresponding tips for each trigger, limit, and action. This allows the software to provide a detailed reason for triggering the interlock when it is triggered. For example, which limit condition is met, causing which device action is triggered, which facilitates the analysis of device errors and device maintenance. Interlock Detection Time: Device interlocks can be triggered instantly or after a fixed period of time. When configuring interlock content, the interlock detection time can be configured. Setting the interlock detection time to 0 will trigger the interlock immediately when the condition is met; configuring the interlock detection time to the required time will trigger the interlock action after the interlock condition has been met for the set time.

[0024] S6. Before verifying the correctness of the interlock on the actual equipment, test whether the interlock function is normal through software simulation. In advance, use software simulation to determine whether the content of the interlock file is correct and whether it meets the expected function. If it meets the corresponding function, test whether the interlock function is normal on the equipment.

[0025] The interlock content of this invention is stored as a configuration file, which is configurable and easy to operate. The interlock content is separated from the software code, which makes it easy to modify and optimize the interlock content without updating the software version, facilitating equipment debugging and improving software adaptability and portability. The interlock rules of this invention match the logical relationship between IO signals and device instruction behavior, and directly trigger the interlock by detecting whether the PLC's IO signals and intermediate variables of the device software meet the interlock conditions.

[0026] This invention separates interlock rules from software code, adopting a configurable approach to achieve flexibility and portability in semiconductor device interlock control. It effectively solves problems such as frequent software updates, severe device binding, and low debugging efficiency caused by hard-coded interlock rules in existing technologies. By supporting dynamic configuration of interlock conditions, flexible setting of trigger levels, detailed customization of prompt information, and adjustable detection time, it significantly improves the convenience of device debugging and maintenance, while enhancing the software's adaptability and functional scalability across different devices.

[0027] This invention also discloses a configurable semiconductor device software interlock control system, including an interconnected memory and a processor. The memory stores a computer program that, when run by the processor, executes the steps of the method described above. The control system of this invention, corresponding to the control method described above, also possesses the advantages described above.

[0028] The present invention can implement all or part of the processes in the methods of the above embodiments, or it can be implemented by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of the above method embodiments. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable storage medium includes: any entity or device capable of carrying computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing the computer programs and / or modules stored in the memory, and by calling data stored in the memory. The memory may include high-speed random access memory, as well as non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital (SD) cards, flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0029] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A configurable semiconductor device software interlock control method, characterized in that, Including the following steps: S1. Review the equipment safety interlock rules, and determine the interlock rule requirements for personal safety and equipment safety. S2. Based on the interlocking rules of S1, sort out the device IO point signals and the required intermediate data variables; S3. Based on the device instruction behavior, divide the corresponding IO point signals and the required intermediate data variables sorted in S2 into Trigger group and Limit group, and generate the corresponding Action group. Use AND, OR, NOT and other logical relationships to combine and match Trigger, Limit and Action to form interlock entries. S4. Write the interlock entries formed in step S3 into the software configuration file to separate the interlock rules from the software code; S5. Write the interlock configuration information into the software configuration file to complete the interlock content based on the interlock entries in S3 and match the safety interlock requirements of specific devices.

2. The configurable semiconductor device software interlock control method according to claim 1, characterized in that, The device I / O point signals and the required intermediate data variables in step S2 include digital signals DI and DO, analog signals AI and AO, and intermediate data variables.

3. The configurable semiconductor device software interlock control method according to claim 1, characterized in that, In step S3, Trigger is a prerequisite condition that must be met for interlocking to be triggered. There are multiple triggers in the Trigger group. Whether the prerequisite condition of the Trigger group is met is specified by the combination of AND, OR, and NOT logical relationships between multiple triggers. Limit is the constraint condition for interlocking. It specifies whether the constraint condition of a limit group is met by using AND, OR, and NOT logical relationships between multiple Limits. Once the Trigger group is satisfied, the corresponding Limit group is automatically checked for satisfaction. If both the Trigger and Limit groups are satisfied, the corresponding Action group's action instruction is triggered.

4. The configurable semiconductor device software interlock control method according to claim 1, 2, or 3, characterized in that, In step S5, the interlock configuration information includes one or more of the following: whether to ignore interlock, whether to trigger an alarm when interlock is triggered, interlock prompt details, and interlock detection time.

5. The configurable semiconductor device software interlock control method according to claim 4, characterized in that, In step S5, whether to ignore interlocks includes ignoring a single interlock entry, ignoring all interlock entries, ignoring a trigger in the Trigger group of a single interlock entry, ignoring a limit in the Limit group of a single interlock entry, and ignoring an action in the Action group of a single interlock entry.

6. The configurable semiconductor device software interlock control method according to claim 4, characterized in that, In step S5, alarms are divided into different levels, including Warning and Alarm.

7. The configurable semiconductor device software interlock control method according to claim 4, characterized in that, In step S5, the interlock prompt details include: when configuring the interlock content, configuring corresponding tips for each trigger, limit, and action, so that the software can provide a detailed reason for triggering the interlock when it is triggered.

8. The configurable semiconductor device software interlock control method according to claim 4, characterized in that, In step S5, the interlock detection time includes: device interlock triggering can be immediate or triggered after a fixed period of time; when configuring interlock content, the interlock detection time is configured. If the interlock detection time is set to 0, it will be triggered immediately after the condition is met; if the interlock detection time is configured to the required time, the interlock action will be triggered after the interlock condition is met for a set period of time.

9. The configurable semiconductor device software interlock control method according to claim 1, 2, or 3, characterized in that, This also includes S6, which tests the interlock function through software simulation before verifying its correctness on the actual device, and determines whether the content of the interlock file is correct in advance through software simulation testing; if the corresponding function is met, then the interlock function is tested on the device to see if it is normal.

10. A configurable semiconductor device software interlock control system, comprising an interconnected memory and a processor, wherein the memory stores a computer program, characterized in that, The computer program, when run by a processor, performs the steps of the method as described in any one of claims 1-9.

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