Two-stage fusion starting method, device and equipment for embedded system and medium

Abstract

The invention discloses an embedded system two-stage fusion starting method and device, equipment and a medium. Comprising the following steps: performing basic environment configuration through an SPL layer, selecting a BL1 starting medium and verifying a BL1 mirror image, and skipping to a BL1 layer after verification is passed; a system resource and an interrupt mechanism are initialized through a BL1 layer, a multi-task operation environment is built, and a target task is created and executed concurrently based on the multi-task operation environment. By checking the mirror image, the position of the mirror image can be accurately positioned, the integrity of the mirror image is guaranteed, and starting abnormity is prevented. By initializing system resources and an interrupt mechanism, hardware support can be provided for multi-task operation and interrupt response, and the response capability of the system to hardware events is improved. By building a multi-task running environment, the single-task linear execution limitation can be broken, and support is provided for parallel processing to improve the starting efficiency. Through concurrent execution of the target task, serial waiting time can be reduced, accurate association of the task and interruption is realized, and resource waste is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded systems, and in particular to a two-level fusion startup method, device, equipment and medium for embedded systems. BACKGROUND

[0002] In the field of embedded systems, especially in lightweight chips based on ARM Cortex-M3 architecture, the design of the startup process directly affects the startup efficiency, reliability and maintainability of the system. The startup of an embedded system usually needs to go through multiple stages of booting, starting from the Bootrom at the bottom layer, gradually loading higher-level boot programs, and finally starting the operating system or application program.

[0003] In the prior art, there are three types of solutions for BL1 startup of the current Cortex-M3 platform: one is Arm Trusted Firmware (ATF), which supports multi-core and security switching, but has large code size, complex dependencies, high RAM occupancy, and is not suitable for limited resource scenarios; the second is U-Boot SPL independent startup, which supports multiple platforms, but lacks task scheduling and interrupt handling, cannot perform operations concurrently, and is difficult to extend peripheral driver and scheduling mechanism; the third is FreeRTOS directly as Bootloader, which can perform multi-task scheduling, but the startup chain is incomplete and lacks image loading and security management capabilities. SUMMARY

[0004] The present application provides a two-level fusion startup method, device, equipment and medium for embedded systems, which realizes a startup process with multi-task and interrupt linkage through a two-level fusion startup architecture, solving the technical problems of low startup efficiency, poor maintainability and delayed interrupt response of resource-constrained embedded platforms.

[0005] According to an aspect of the present application, a two-level fusion startup method for embedded systems is provided, applied to a fusion startup architecture, including a secondary program loader (SPL) layer and a first stage boot loader (BL1) layer. The method includes: performing basic environment configuration through the SPL layer, selecting a BL1 startup medium and verifying a BL1 image, and jumping to the BL1 layer after verification; initializing system resources and interrupt mechanisms through the BL1 layer, building a multi-task running environment, and creating and concurrently executing target tasks based on the multi-task running environment.

[0006] Optionally, the basic environment configuration through the SPL layer includes: obtaining configuration parameters, generating stack environment and memory allocation space through the SPL layer, wherein the configuration parameters include total memory capacity, stack space starting address and memory allocation partition ratio; obtaining parameters for clock initialization, and generating system clock configuration that meets hardware requirements.

[0007] Optionally, the selecting and checking the BL1 starting medium and the BL1 image comprises: selecting a target starting mode of the BL1, initializing a starting medium corresponding to the target starting mode; reading the BL1 image from the starting medium; and performing integrity checking on the BL1 image by using a cyclic redundancy check technology.

[0008] Optionally, the system resource and the interrupt mechanism are initialized by the BL1 layer, comprising: reading resource configuration information of a current hardware platform, generating a system resource initialization configuration adapted to the current hardware platform; obtaining a configuration rule of an interrupt controller, and resetting an interrupt vector table to a specified address recognizable by the BL1 layer based on the configuration rule.

[0009] Optionally, the target tasks comprise a peripheral driver initialization task, a storage medium detection task, an image loading task, and a secure state switching / power domain management task.

[0010] Optionally, the method further comprises: when the target tasks are executed by the BL1 layer, selecting a next stage starting mode, initializing a next stage starting medium corresponding to the next stage starting mode; loading and checking a next stage image based on the next stage starting medium, and starting the next stage image after the checking is passed.

[0011] Optionally, the method further comprises: when the target tasks are executed by the BL1 layer, selecting a next stage starting mode, initializing a next stage starting medium corresponding to the next stage starting mode; loading and checking a next stage image based on the next stage starting medium, and starting the next stage image after the checking is passed.

[0012] According to another aspect of the present application, there is provided a two-stage fusion starting device of an embedded system, applied to a fusion starting architecture, comprising: a second program loader (SPL) layer and a first stage bootloader (BL1) layer, and the device comprises:

[0013] The BL1 layer checking and starting module is configured to perform basic environment configuration by the SPL layer, select a BL1 starting medium and check a BL1 image, and jump to the BL1 layer after the checking is passed.

[0014] The multi-task execution module is configured to initialize system resources and an interrupt mechanism by the BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

[0015] According to another aspect of the present application, there is provided an electronic device, comprising:

[0016] at least one processor;

[0017] and a memory connected with the at least one processor in communication;

[0018] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the two-level fusion startup method of the embedded system according to any one of the embodiments of the application.

[0019] According to another aspect of the application, a computer readable storage medium is provided, which stores computer instructions for enabling a processor to implement the two-level fusion startup method of the embedded system according to any one of the embodiments of the application when executed by the processor.

[0020] The technical solution of the embodiments of the application can accurately locate the image position and guarantee the integrity of the image, and prevent startup abnormity. The BL1 layer initializes system resources and interrupt mechanism, which can provide hardware support for multi-task running and interrupt response, and improve the response capability of the system to hardware events. By building a multi-task running environment, the linear execution limitation of single task can be broken, and support can be provided for parallel processing to improve the startup efficiency. By concurrently executing target tasks, the serial waiting time can be reduced, and accurate association between tasks and interrupts can be realized, which not only accelerates the startup speed, but also guarantees real-time response to hardware events, and avoids resource waste.

[0021] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 is a flowchart of the two-level fusion startup method of the embedded system according to the first embodiment of the application;

[0024] Figure 2 is a flowchart of another two-level fusion startup method of the embedded system according to the second embodiment of the application;

[0025] Figure 3 is a process diagram of the two-level fusion startup of the embedded system according to the second embodiment of the application;

[0026] Figure 4 is a structural schematic diagram of a two-level fusion starting device of an embedded system according to Embodiment Three of the present application;

[0027] Figure 5 is a structural schematic diagram of an electronic device for implementing a two-level fusion starting method of an embedded system according to the present application. DETAILED DESCRIPTION

[0028] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0029] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Embodiment One

[0031] Figure 1 A flowchart of a two-level fusion starting method of an embedded system is provided for Embodiment One of the present application. The present embodiment can be applied to a resource-constrained embedded platform starting scenario. The method can be executed by a two-level fusion starting device of an embedded system, which can be realized in the form of hardware and / or software. It is applied to a fusion starting architecture, including a secondary program loader (SPL) layer and a first-stage boot loader (BL1) layer, as shown in Figure 1 The method comprises the following steps:

[0032] S110, configuring a basic environment through the SPL layer, selecting a BL1 starting medium and verifying a BL1 image, and jumping to the BL1 layer after verification.

[0033] The second program loader (SPL) refers to an earlier program level in the embedded system startup process, and belongs to a light-weight startup loading module. The SPL is responsible for completing the preliminary work such as basic environment configuration, selection and verification of a subsequent startup image. The boot loader stage 1 (BL1) refers to a startup level after the SPL level. The BL1 is used to initialize system resources, build a multi-task environment and execute a target task, and to push the system startup process to the next stage. The fusion startup architecture refers to an embedded system startup architecture in which the functions of different startup levels, such as the SPL level and the BL1 level, are fused. In the fusion startup architecture, the SPL level and the BL1 level work cooperatively, the SPL level completes the basic preparation and then jumps to the BL1 level, and the BL1 level optimizes the startup process by using a multi-task mechanism to achieve efficient startup of the embedded system. The BL1 image refers to a program image file of the BL1 level, which is stored in a corresponding startup medium. The SPL level reads and verifies the BL1 image to ensure the integrity and correctness of the BL1 image, and the SPL level jumps to execute the BL1 image only when the verification is passed, so as to start the operation of the BL1 level.

[0034] Optionally, the basic environment configuration is performed by the SPL level, including: obtaining configuration parameters by the SPL level, generating a stack environment and a memory allocation space, wherein the configuration parameters include a total memory capacity, a stack space starting address and a memory allocation partition ratio; obtaining parameters for clock initialization, and generating a system clock configuration that meets the hardware requirements.

[0035] Specifically, the SPL layer first reads preset configuration parameters, which are predefined according to the hardware resource characteristics of the Cortex-M3 platform, including total memory capacity, stack space starting address, and memory allocation partition ratio. Among them, the total memory capacity corresponds to the actual allocable memory of the Cortex-M3 chip, and the SPL layer can determine the overall boundary of the memory resource by reading the total memory capacity, avoiding subsequent operations beyond the hardware memory range. The stack space starting address needs to be set in combination with the stack growth direction of the Cortex-M3, and the area with a higher memory address is usually selected as the starting point, for example, if the total memory address range is 0x20000000-0x2000FFFF, the stack starting address can be set to 0x2000FFFF, and sufficient stack depth is reserved to ensure that stack overflow does not occur during execution of the SPL layer itself code. The memory allocation partition ratio is to divide the area for subsequent dynamic memory requirements, for example, the remaining memory is divided into a temporary data storage area and an image preloading area in a 6:4 ratio, the former is used for temporary data caching during the execution of the SPL layer, and the latter is used for temporarily storing the BL1 image to be verified. By dividing the memory allocation partition ratio, memory resource competition can be avoided, ensuring that the memory usage of different functional modules is independent of each other, and the configuration stability is improved. After obtaining the configuration parameters, the SPL layer writes the hardware initialization instructions into the memory control register of the Cortex-M3 to complete the address mapping and permission configuration of the stack space, and simultaneously calls the lightweight memory allocation function to divide the memory partition, finally generating a stack environment and memory allocation space that can be directly used by the SPL layer and subsequent pre-jump operations.

[0036] It can be known that the peripherals and kernel of the Cortex-M3 platform run in dependence on stable clock signals, and different hardware modules have different requirements for clock frequency, for example, the Flash erasing requires a 24MHz clock, and the kernel supports a maximum of 72MHz clock, therefore, the SPL layer needs to obtain clock initialization parameters first, which include clock source selection, frequency division coefficient, and phase-locked loop (PLL) configuration parameters. After the SPL layer obtains the clock initialization parameters, it completes the clock configuration by operating the clock control register of the Cortex-M3, that is, firstly, the selected clock source is enabled and waited for stabilization, then the PLL parameters are configured to realize frequency multiplication, and then the corresponding frequency division register is set according to the bus frequency division requirement, and finally the configured clock signal is distributed to the kernel and each peripheral module. By initializing the clock, it can be ensured that each hardware module obtains a clock frequency matching its working characteristics, avoiding both the performance degradation of the peripheral due to insufficient clock frequency and the malfunction caused by excessively high frequency beyond the hardware bearing range, and finally generating a stable system clock configuration meeting the hardware requirements of the entire system.

[0037] Optionally, the BL1 starting medium is selected and the BL1 image is verified, including: selecting a target starting mode of the BL1, initializing a starting medium corresponding to the target starting mode; reading the BL1 image from the starting medium; and performing integrity verification on the BL1 image by using a cyclic redundancy check technology.

[0038] It should be noted that the embedded system of the Cortex-M3 platform usually supports multiple starting media, such as an on-chip flash, a serial peripheral interface (SPI) flash, an SD card, a UART serial port, and the like, and the hardware interfaces and data transmission protocols of the starting media are different. The SPL layer needs to first determine the target starting mode of the BL1 according to the preset starting priority of the system, such as starting from the on-chip flash by default, and switching when an effective identifier of the external SPI flash is detected; or according to the hardware pin configuration, that is, according to the pin level state to select the starting mode. After the target starting mode is selected, the SPL layer needs to initialize the corresponding starting medium. Taking the external SPI flash as an example, the SPL layer will configure the SPI peripheral register of the Cortex-M3, set the clock frequency, data bit length, and transmission mode of the SPI communication, and send the initialization instruction of the SPI flash, and after confirming that the SPI flash can respond normally, the medium initialization is completed.

[0039] Among them, the BL1 image usually has a fixed storage address and a preset image size in the starting medium. The SPL layer will acquire the image data by using a corresponding reading mode according to the characteristics of the target starting medium. If the target starting medium is the on-chip flash, the Cortex-M3 supports direct access through address mapping, and the SPL layer can directly read the byte data of the specified address range by pointer operation and store it in the previously divided image preloading area. If the target starting medium is the external SPI flash, a page reading instruction needs to be sent through the SPI bus, and the starting address of the BL1 image is specified, and then the image data returned by the flash is received byte by byte through the SPI_DR register, and is also stored in the image preloading area.

[0040] Specifically, when the BL1 image is generated, a cyclic redundancy check (CRC) value of complete data of the BL1 image is calculated in advance, and the CRC value is stored at the end of the image file or a specified check address of the medium, such as the last 4 bytes of the BL1 image storage area. After the SPL layer reads the BL1 image, the preset CRC check value is extracted, and a real-time CRC check value is generated by performing CRC calculation on the BL1 image data in the image preloading area in the memory. Then, the SPL layer compares the real-time CRC value with the preset CRC value. If the two values are consistent, it indicates that the BL1 image is not lost or tampered during storage and transmission, and the check is passed, and the BL1 layer can be jumped to. If the two values are inconsistent, it is determined that the image is damaged, and the starting process is terminated. Through the integrity check, the subsequent startup crash caused by the damaged BL1 image is avoided, and the safety and reliability of the startup process are ensured.

[0041] S120, initialize system resources and interrupt mechanisms through the BL1 layer to build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

[0042] In an embodiment, the BL1 layer can build the environment based on FreeRTOS, so that the system can concurrently execute multiple tasks and improve the concurrency and response capability of the system. The target task refers to a specific task created and executed in the multi-task running environment of the BL1 layer.

[0043] Optionally, initializing system resources and interrupt mechanisms through the BL1 layer includes: reading resource configuration information of the current hardware platform to generate system resource initialization configuration adapted to the current hardware platform; and obtaining configuration rules of an interrupt controller to reset an interrupt vector table to a specified address recognizable by the BL1 layer based on the configuration rules.

[0044] Specifically, in the embedded system of Cortex-M3 platform, the resource distribution of different hardware schemes is different, for example, the number and base address of on-chip peripherals, GPIO pin function definition, power domain division, etc. may be different. The BL1 layer first obtains resource configuration information through hardware resource detection or preset configuration table reading. If it is a standardized hardware platform, the BL1 layer reads the resource configuration table stored in the ROM or a specified memory address in advance. If it is a flexible configurable platform, the BL1 layer identifies the types and quantities of mounted peripherals through detection instructions. After obtaining the resource configuration information, the BL1 layer generates system resource initialization configuration adapted to the current hardware platform for the core system resource. The system resource initialization configuration can include peripheral clock enable, peripheral basic parameter configuration and GPIO pin multiplexing configuration. Taking the UART peripheral as an example, the BL1 layer will configure its baud rate, data bits, stop bits and check bits by writing the baud rate register of the UART control register, so that the peripheral can be directly used if there is a UART data transmission requirement in the subsequent multi-task.

[0045] It should be noted that the Cortex-M3 core integrates a Nested Vectored Interrupt Controller (NVIC) for managing all interrupt requests of the system, and the interrupt vector table is the basis for the NVIC to identify the interrupt source and locate the interrupt service program address. The interrupt vector table is essentially an array storing the entry address of the interrupt service program, which is stored in the starting address of the BootROM by default. However, the BL1 layer runs in SRAM or a specific Flash area, and the interrupt vector table needs to be redirected to an address range that the BL1 layer can access and manage.

[0046] Specifically, the BL1 layer acquires configuration rules of the NVIC, the configuration rules including address alignment requirements of an interrupt vector table, configuration rules of a vector table offset register, and interrupt priority grouping rules. After acquiring the configuration rules, the BL1 layer performs an interrupt vector table reset operation: first, a BL1 interrupt vector table is created in a memory region of the BL1 layer, the table containing interrupt service program entry addresses required by the BL1 layer, and then a vector table offset register (VTOR) of the NVIC is configured, a base address of the BL1 interrupt vector table being written into the VTOR, at this time the NVIC stops reading the vector table from a default BootROM address and instead acquires the vector table from the new address. Necessary interrupt sources are enabled, for example, if task scheduling of the FreeRTOS depends on a SysTick timer interrupt, the BL1 layer configures a reload value of the SysTick timer and sets the SysTick interrupt to 1 through an interrupt enable register, ensuring that the task scheduling interrupt can be responded to. By resetting the interrupt vector table, the interrupt management authority is transferred from the SPL layer to the BL1 layer, while ensuring that multitasking of the BL1 layer can quickly respond to interrupts through the NVIC, avoiding system crashes caused by interrupt service program address errors or interrupts that cannot be handled, and providing reliable interrupt support for multitasking concurrent execution.

[0047] Optionally, the target task includes a peripheral driver initialization task, a storage medium detection task, an image loading task, and a secure state switching / power domain management task.

[0048] The peripheral device driving initialization task is a basic task executed by the BL1 layer based on the FreeRTOS multi-task environment, and aims to build a usable hardware peripheral basis for subsequent storage medium detection, image loading and other tasks. Specifically, the initialization configuration of key peripherals required for BL2 startup will be performed. For example, the control register of the peripheral device is operated, the communication parameters are set, and the GPIO pin multiplexing function associated with the peripheral device is configured. The storage medium detection task is used to identify the storage medium information where the BL2 image is located, and provides a clear loading target for the subsequent image loading task, which can ensure the accuracy of the loading target and avoid blind loading leading to startup failure. The image loading task is responsible for safely and efficiently reading the BL2 image in the storage medium to a specified area of the memory. Before execution, the medium parameters passed by the storage medium detection task and the BL2 image parameters preset by the SPL layer need to be determined. During the task loading process, the image data is read in segments according to the sector / block size of the medium through the corresponding peripheral device. At the same time, the task records the number of loaded bytes in real time, and when the loading amount reaches the preset image size, a loading completion event is triggered to notify the subsequent process to jump to BL2. The secure state switching / power domain management task is used to ensure the security and hardware stability of the startup process, and adapts to the security architecture and low power consumption requirements of the Cortex-M3 platform. In terms of secure state switching, if the system supports secure / non-secure dual states, the task will first read the preset security configuration table, mark the address space of the security peripheral as a security domain by operating the security control register of the Cortex-M3, and then execute the secure state switching instruction to switch the CPU from the non-secure state of the SPL layer to the secure state of the BL1 layer, ensuring that sensitive operations such as image loading and encryption verification are performed in a secure environment to prevent malicious code tampering. In terms of power domain management, the power domains corresponding to the peripherals that are not enabled will be turned off according to the peripheral usage requirements during the startup phase, and the system power consumption will be reduced by operating the power control register; at the same time, the voltage stability of the kernel power domain is monitored in real time, and if voltage fluctuation is detected, a power protection event is triggered immediately to suspend tasks such as image loading, and then continue after the voltage stabilizes, ensuring stable hardware operation.

[0049] Optionally, the method further comprises: registering, by the BL1 layer, a corresponding interrupt response association for each task when creating each target task, wherein the interrupt response association includes a peripheral device driving initialization task associated with a peripheral interrupt, a storage medium detection task associated with a storage interrupt, an image loading task associated with a data transmission interrupt, and a secure state switching / power domain management task associated with a power interrupt; and triggering, by the BL1 layer based on the interrupt response association, the corresponding target task to perform interrupt processing when the interrupt trigger condition is met.

[0050] It should be noted that the BL1 layer creates four target tasks of peripheral driver initialization, storage medium detection, image loading and security state switching / power domain management, and then registers the association relationship one by one according to the corresponding logic of task function and hardware interrupt source.

[0051] Specifically, the peripheral driver initialization task is associated with a peripheral interrupt, the storage medium detection task is associated with a storage interrupt, the image loading task is associated with a data transmission interrupt, and the security state / power domain management task is associated with a power interrupt. The binding can be realized by configuring the peripheral interrupt enable register and the FreeRTOS interrupt safety API. When a hardware event triggers an interrupt, the NVIC will call the corresponding interrupt service program (ISR) according to the BL1 interrupt vector table. After the ISR is verified for legality, the event is synchronized to the associated task through the FreeRTOS task notification / queue. The kernel schedules the task from the blocked state to the ready state to execute the interrupt processing, which reduces the CPU polling consumption and guarantees real-time response to the event.

[0052] The technical scheme of the embodiment of the application can accurately locate the image position and guarantee the integrity of the image, prevent abnormal startup, initialize system resources and interrupt mechanisms through the BL1 layer, provide hardware support for multi-task running and interrupt response, improve the response capability of the system to hardware events, build a multi-task running environment, break the limitation of single-task linear execution, provide support for parallel processing to improve the startup efficiency, execute target tasks in parallel, reduce the serial waiting time, realize accurate association between tasks and interrupts, accelerate the startup speed, guarantee real-time response to hardware events, and avoid resource waste.

[0053] Embodiment Two

[0054] Figure 2 A flowchart of a two-level fusion startup method of an embedded system provided by the embodiment two of the application, which adds a specific process of starting the next level image on the basis of the above-mentioned embodiment one. The specific content of steps S210-S220 is substantially the same as that of steps S110-S120 in the embodiment one, so the embodiment will not be described again. As shown in the figure, the method comprises the following steps. Figure 2

[0055] S210, configure the basic environment through the SPL layer, select the BL1 startup medium and verify the BL1 image, and jump to the BL1 layer after the verification is passed.

[0056] ​Optionally, the basic environment configuration is performed through the SPL layer, including: obtaining configuration parameters through the SPL layer, and generating a stack environment and a memory allocation space, wherein the configuration parameters include a total memory capacity, a stack space starting address, and a memory allocation partition ratio; obtaining parameters for clock initialization, and generating a system clock configuration that meets hardware requirements.

[0057] Optionally, the BL1 startup medium is selected and the BL1 image is verified, including: selecting a target startup mode of the BL1, initializing a startup medium corresponding to the target startup mode; reading the BL1 image from the startup medium; and performing integrity verification on the BL1 image by using a cyclic redundancy check technology.

[0058] S220, initializing system resources and an interrupt mechanism through the BL1 layer, building a multi-task running environment, and creating and concurrently executing target tasks based on the multi-task running environment.

[0059] Optionally, the system resources and the interrupt mechanism are initialized through the BL1 layer, including: reading resource configuration information of a current hardware platform, and generating a system resource initialization configuration that is adapted to the current hardware platform; obtaining a configuration rule of an interrupt controller, and resetting an interrupt vector table to a specified address that can be recognized by the BL1 layer based on the configuration rule.

[0060] Optionally, the target tasks include a peripheral device driver initialization task, a storage medium detection task, an image loading task, and a secure state switching / power domain management task.

[0061] Optionally, the method further includes: registering, by the BL1 layer, a corresponding interrupt response association relationship for each task when creating the target tasks, wherein the interrupt response association relationship includes that the peripheral device driver initialization task is associated with a peripheral interrupt, the storage medium detection task is associated with a storage interrupt, the image loading task is associated with a data transmission interrupt, and the secure state switching / power domain management task is associated with a power interrupt; and when an interrupt triggering condition is met, triggering, by the BL1 layer, interrupt processing of a corresponding target task based on the interrupt response association relationship.

[0062] S230, selecting, by the BL1 layer, a next-level startup mode when the target tasks are executed, and initializing a next-level startup medium corresponding to the next-level startup mode.

[0063] Specifically, in the BL1 layer, when the peripheral driver initialization, storage medium detection, image loading, and security state / power domain management target tasks are all completed, the selection operation of the next level startup mode is performed first. The selection is based on the system preset startup priority or the hardware pin state. For example, if the BL2 image identifier is detected in the external SPIFlash, the SPIFlash is selected as the next level startup mode. If no detection is made, the system switches to other media in the priority order. After determining the startup mode, the corresponding next level startup medium needs to be initialized. Taking the selected SPIFlash as an example, the BL1 layer further optimizes the medium dedicated configuration based on the SPI peripheral basic parameters configured in the previous peripheral driver initialization task, for example, adjusts the SPI clock frequency to the highest rate supported by the Flash to improve the reading efficiency, and configures the chip selection pin of the Flash to keep stable and enable.

[0064] S240, load and verify the next level image based on the next level startup medium, and start the next level image after the verification is passed.

[0065] Specifically, when loading the next level image, the BL1 layer will call the corresponding reading logic according to the medium type, for example, when loading from the SPIFlash, the sector reading instruction is sent through the SPI peripheral, the storage starting address of the BL2 image in the Flash is specified, and the image data is read into the preset loading area in segments. After loading is completed, the CRC technology consistent with the BL1 image verification is used for integrity verification, that is, the preset CRC check value stored at the end of the next level image is extracted first, and then the CRC value of the image data loaded into the memory is calculated in real time. When the two are consistent, it is indicated that the image is not damaged. After the verification is passed, the BL1 layer will execute the jump instruction to transfer the CPU execution right to the next level image, and complete the downward connection of the startup process.

[0066] Specific application scenarios: Figure 3 A two-level fusion startup process schematic diagram of an embedded system is provided for the second embodiment of the present application. Figure 3The two-stage fusion starting process of the embedded system based on the ARM Cortex-M3 architecture is shown, which is divided into Bootrom stage (SPL layer) and FreeRTOS stage (BL1 layer) two stages. After power-on, the Bootrom stage process is entered first. The first step is to configure the basic environment, configure the stack, malloc space, and allocate temporary memory resources for program execution; at the same time, the clock is initialized, the system clock is configured according to the hardware characteristics, and the stable operation of the hardware module is ensured. Then the BL1 starting mode is selected, the storage medium of the BL1 image is determined according to the preset priority of the system or the state of the hardware pin, and then the medium of the corresponding starting mode is initialized. Then the BL1 image is read from the selected starting medium, and the integrity of the image is checked by using the cyclic redundancy check technology, and the BL1 layer is jumped to the execution after the check is passed. After entering the FreeRTOS stage process, the interrupt vector table is reset first, which is redirected to the memory address that can be managed by the BL1 layer, so that the NVIC can identify the interrupt service program of the BL1 layer; at the same time, the system resources and interrupts are initialized, the peripheral resources are configured and the key interrupts are enabled. Then the starting mode of the next stage is determined, and the corresponding starting medium is initialized. Then the next stage image is read and checked from the starting medium, and the CRC technology is used to ensure the validity of the image. Then a multi-task running environment is built based on FreeRTOS, target tasks such as peripheral driver initialization tasks and storage medium detection tasks are created, and the interrupt response association relationship of each task is registered, when the interrupt is triggered, the BL1 layer triggers the corresponding task to execute the interrupt processing based on the association relationship. Finally, after the next stage image check is passed, the image is jumped to execute, and the downward connection of the starting process is completed. The above process solves the starting efficiency problem of the resource-constrained embedded platform through the two-stage architecture of the SPL layer basic preparation combined with the BL1 layer multi-task optimization, and improves the maintainability and response ability of the starting process through the multi-task and interrupt linkage mechanism.

[0067] The technical scheme of the embodiment of the application can accurately determine the storage medium direction of subsequent starting by selecting the next starting mode after the target task of the BL1 layer is executed, avoid the confusion of the starting path, and provide clear guidance for the next stage starting. By initializing the next stage starting medium corresponding to the next stage starting mode, the hardware differences of different media can be eliminated, a stable image reading link can be established, and the subsequent image loading operation can be ensured to be carried out normally. By loading the next stage image based on the next stage starting medium, the image can be reliably read from the storage medium to the specified memory area, and the program basis for the next stage starting is provided. After the next stage image is started after the check is passed, the smooth connection of the starting process can be realized, the normal execution of the next stage program is ensured, and the complete promotion of the starting chain is promoted.

[0068] Embodiment three

[0069] Figure 4A structure diagram of a two-stage fusion starting device of an embedded system is provided for Embodiment Three of the present application. The device is applied to a fusion starting architecture, a second-stage program loader (SPL) layer and a first-stage boot loader (BL1) layer, as shown in Figure 4 The device comprises:

[0070] A BL1 layer checking and starting module 310 is configured to perform basic environment configuration through the SPL layer, select a BL1 starting medium and check a BL1 image, and jump to the BL1 layer after the checking is passed.

[0071] A multi-task execution module 320 is configured to initialize system resources and an interrupt mechanism through the BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

[0072] Optionally, the BL1 layer checking and starting module 310 specifically comprises a basic environment configuration unit configured to: acquire configuration parameters through the SPL layer, generate a stack environment and a memory allocation space, wherein the configuration parameters comprise a total memory capacity, a stack space starting address and a memory allocation partition ratio; acquire parameters for clock initialization, and generate a system clock configuration meeting hardware requirements.

[0073] Optionally, the BL1 layer checking and starting module 310 specifically comprises a BL1 image checking unit configured to: select a target starting mode of the BL1, initialize a starting medium corresponding to the target starting mode; read the BL1 image from the starting medium; and perform integrity checking on the BL1 image by using a cyclic redundancy check technology.

[0074] Optionally, the multi-task execution module 320 is specifically configured to: read resource configuration information of a current hardware platform, generate a system resource initialization configuration adapted to the current hardware platform; acquire a configuration rule of an interrupt controller, and reset an interrupt vector table to a specified address recognizable by the BL1 layer based on the configuration rule.

[0075] Optionally, the device further comprises a next-stage image starting module configured to: through the BL1 layer, when the target tasks are executed, select a next-stage starting mode, initialize a next-stage starting medium corresponding to the next-stage starting mode; load and check a next-stage image based on the next-stage starting medium, and start the next-stage image after the checking is passed.

[0076] Optionally, the apparatus further comprises an interrupt processing module configured to: register, by the BL1 layer, an interrupt response association relationship for each target task when creating the target tasks, wherein the interrupt response association relationship comprises a peripheral device driver initialization task associated with a peripheral device interrupt, a storage medium detection task associated with a storage interrupt, an image loading task associated with a data transmission interrupt, and a secure state switching / power domain management task associated with a power interrupt; and trigger, by the BL1 layer, the corresponding target task to perform interrupt processing based on the interrupt response association relationship when a trigger condition of the interrupt is met.

[0077] The technical scheme of the embodiment of the application can accurately locate the image position and guarantee the integrity of the image, and prevent abnormal startup, by verifying the image. The BL1 layer can initialize system resources and an interrupt mechanism, and can provide hardware support for multi-task operation and interrupt response, and improve the response capability of the system to hardware events. The multi-task operation environment can break the limitation of linear execution of a single task, and provide support for parallel processing to improve the startup efficiency. The concurrent execution of the target tasks can reduce the serial waiting time, and realize accurate association between the tasks and the interrupts, which not only accelerates the startup speed, but also guarantees real-time response to hardware events, and avoids resource waste.

[0078] The two-level fusion startup device for an embedded system provided in the embodiment of the application can execute the two-level fusion startup method for an embedded system provided in any embodiment of the application, and has the corresponding function modules and beneficial effects of the execution method.

[0079] Embodiment Four

[0080] Figure 5 A structural schematic diagram of an electronic device 10 that can be used to implement embodiments of the application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the applications described and / or claimed in this document.

[0081] As Figure 5As shown, the electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., communicatively connected to the at least one processor 11, where the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0082] Various components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc., an output unit 17, such as various types of displays, a speaker, etc., a storage unit 18, such as a magnetic disk, an optical disk, etc., and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0083] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as an embedded system two-level fusion booting method.

[0084] In some embodiments, an embedded system two-level fusion booting method can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of an embedded system two-level fusion booting method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform an embedded system two-level fusion booting method by any other appropriate means, such as by means of firmware.

[0085] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a load programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0086] Computer programs used to implement the processes of the application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer program, when executed, can cause instructions defined in the flow charts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine or entirely on a remote machine or server.

[0087] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store computer programs for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0088] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0089] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0090] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0091] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in a different order, as long as the desired results of the technical solutions of the present disclosure are achieved, and the present disclosure is not limited herein.

[0092] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall fall within the protection scope of the present application.

Claims

1. A two-level fusion boot method for an embedded system, characterized in that, Applied to a converged boot architecture, including: a secondary program loader (SPL) layer and a first-stage boot loader (BL1) layer, the method includes: Configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After the verification is successful, jump to the BL1 layer. By initializing system resources and interrupt mechanisms through the BL1 layer, a multi-task runtime environment is built, and the target task is created and executed concurrently based on the multi-task runtime environment.

2. The method according to claim 1, characterized in that, The basic environment configuration via the SPL layer includes: The configuration parameters are obtained through the SPL layer to generate the stack environment and memory allocation space. The configuration parameters include the total memory capacity, the starting address of the stack space, and the memory allocation partition ratio. Obtain the clock initialization parameters and generate a system clock configuration that meets the hardware requirements.

3. The method according to claim 1, characterized in that, The process of selecting the BL1 boot media and verifying the BL1 image includes: Select the target boot method for BL1 and initialize the boot media corresponding to the target boot method; Read the BL1 image from the boot medium; The integrity of the BL1 image is verified using cyclic redundancy check technology.

4. The method according to claim 1, characterized in that, The system resource and interrupt mechanism initialized through the BL1 layer includes: Read the resource configuration information of the current hardware platform and generate a system resource initialization configuration adapted to the current hardware platform; Obtain the configuration rules of the interrupt controller, and reset the interrupt vector table to a specified address that can be recognized by the BL1 layer based on the configuration rules.

5. The method according to claim 4, characterized in that, The target tasks include peripheral driver initialization, storage media detection, image loading, and security state switching / power domain management.

6. The method according to claim 3, characterized in that, The method further includes: Through the BL1 layer, after the target task is completed, the next level of startup mode is selected and the next level of startup medium corresponding to the next level of startup mode is initialized. The next-level image is loaded and verified based on the next-level boot media. After the verification is successful, the next-level image is started.

7. The method according to claim 5, characterized in that, The method further includes: When creating each target task, the BL1 layer registers a corresponding interrupt response association for each task. The interrupt response association includes peripheral interrupt associated with peripheral driver initialization task, storage interrupt associated with storage medium detection task, data transmission interrupt associated with image loading task, and power interrupt associated with security state switching / power domain management task. When the interrupt triggering conditions are met, the corresponding target task is triggered to perform interrupt processing based on the interrupt response association relationship through the BL1 layer.

8. A two-level fusion startup device for an embedded system, characterized in that, Applied to a converged boot architecture, including: a secondary program loader SPL layer and a first-stage boot loader BL1 layer, the device includes: The BL1 layer verification and startup module is used to configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After the verification is successful, it jumps to the BL1 layer. The multi-task execution module is used to initialize system resources and interrupt mechanisms through the BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A computer storage medium, characterized in that, The computer storage medium stores computer instructions that are used to cause a processor to execute the method of any one of claims 1-7.

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