Memory type determination method, device and equipment
By simulating CPU access performance under NUMA architecture and determining the small-page or large-page memory type, the performance loss of remote memory access under NUMA architecture is solved, and CPU access performance is optimized.
Patent Information
- Application Number
- CN202511449475.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-11
- Publication Date
- 2026-02-27
AI Technical Summary
Under NUMA architecture, when multiple threads or processes access large pages of memory, it may lead to performance loss in remote memory access. Existing technologies have difficulty in effectively identifying and optimizing memory types to avoid this performance loss.
By identifying the target server and running program, the performance of CPU accessing local and remote memory is simulated. Performance comparison values and thresholds are used to determine whether the memory type is small-page or large-page memory, and memory allocation is optimized.
It reduces the performance degradation of remote memory access, while also mitigating the performance loss caused by a decrease in TLB hit rate, thus improving CPU access performance.
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Figure CN121579181A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of data processing, and particularly relates to a memory type determination method, device and equipment. BACKGROUND
[0002] Non-Uniform Memory Access (NUMA) is a kind of multi-node computing system architecture, in which multiple nodes constitute a whole. In this architecture, all nodes share a centralized memory pool. Each CPU is allocated its local memory and can share memory with other CPUs through the system. NUMA optimizes system performance by logically grouping CPUs and memories in servers to form different nodes. For example Figure 1 As shown in the figure, node0-3 are respectively allocated with corresponding local memories and multiple CPUs, and the CPUs in a node can access the local memory or access the memory of other nodes. When a CPU accesses the memory in its own node, the access speed is relatively fast, while accessing the memory in other nodes will result in relatively slow access speed. This is because accessing the memory in a remote node across the node boundary will introduce additional delay, affecting the memory read-write performance.
[0003] In a page-based virtual memory, the virtual storage space and the physical main memory space are both divided into a plurality of fixed-size pages, and the memory allocation for a thread is also in page units. If the page size is too small, the number of page levels is too large, and the number of page table queries is increased. The same memory requires more page table entries due to more pages, reducing the Translation Lookaside Buffer (TLB) cache hit rate. Due to these losses, the kernel implements a large page mechanism, which greatly reduces the number of TLB misses, the number of page fault interrupts, the number of page table levels, and the time to search the page table, significantly improving the performance of the application program.
[0004] However, under the NUMA architecture, when multiple threads or processes access the same large page memory, due to the system load balancing strategy, the CPU may access the memory of a remote node. The performance loss caused by such remote memory access often exceeds the performance gain due to TLB cache hit, resulting in a decrease in overall performance.
[0005] There are two cases for applying for a large page memory. One is that the application calls an API to explicitly apply, and the other case is that the kernel automatically applies the configuration of large page memory, and when the memory address accessed by the application reaches the large page address alignment, the application of the large page is also automatically triggered.
[0006] For the first case, the applicant needs to understand that there is no problem of remote process accessing this memory, otherwise there is a possibility of performance degradation, and the caller needs to decide whether to set the CPU affinity according to the business characteristics and confirm it after performance testing.
[0007] For the second case, the application usually does not know that it has applied for large page memory, such as a large data module for AI matrix operation; jvm / python and other virtual machines will also trigger the application of large page memory in order to avoid small memory application, and apply for more than 512M of virtual memory; Some underlying databases will also apply for more than 512M of virtual memory due to the need for a large amount of cache. These applications usually have multi-threaded concurrent scenarios, so it is easy to have a situation where part of the threads access remote memory.
[0008] For example, when a process performs matrix operation and applies for more than 512M of memory, the system will automatically allocate memory when a page fault exception occurs. When the memory address reaches 512M alignment, the large page memory allocation is automatically enabled. At this time, the large page memory is located on the current running node of the process, so the local memory is accessed, and there is no performance loss. However, when the process creates four threads to execute matrix operation in parallel, due to the load balancing mechanism of the system, the four threads may be scheduled to four different nodes, resulting in performance problems of remote memory access.
[0009] As shown in the following table test results, different servers have different performance degradation. For server C, there is obvious performance degradation, and when we turn off the large page memory and directly apply for small page memory, the cpu occupancy rate can be improved to 99%, and the performance is also improved by one time.
[0010] Based on the above, if small page memory is applied, performance loss may occur due to the decrease of tlb hit rate, and if large page memory is applied, accessing remote memory may occur due to the load balancing mechanism of the system, which reduces the access performance. SUMMARY
[0011] The application provides a memory type determination method, device and equipment, which allocates memory types for different running programs and improves the access performance of CPU.
[0012] In a first aspect, the application provides a memory type determination method, comprising: determining a target server and a target running program, the target server adopting a non-uniform memory access architecture, the non-uniform memory access architecture comprising a plurality of nodes, each node comprising a central processing unit (CPU) and a memory; The first access performance of the target CPU executing the target program is determined in a first simulation scenario and the second access performance in a second simulation scenario. The first simulation scenario indicates that the target CPU accesses the memory of other nodes, and the second simulation scenario indicates that the target CPU accesses the memory of the local node. The target CPU belongs to the CPUs included in the plurality of nodes. The memory type corresponding to the target running program is determined based on the first access performance and the second access performance, and the memory type includes small page memory or large page memory.
[0013] In one embodiment, determining the memory type corresponding to the target running program based on the first access performance and the second access performance includes: obtaining a performance threshold of the target server for the target running program; determining a performance comparison value based on the first access performance and the second access performance; and determining the memory type corresponding to the target running program based on the performance comparison value and the performance threshold.
[0014] In one embodiment, the performance comparison value includes the ratio of the first access performance to the second access performance, and determining the memory type corresponding to the target running program based on the performance comparison value and the performance threshold includes: determining that the memory type corresponding to the target running program is small page memory when the ratio is less than the performance threshold; and determining that the memory type corresponding to the target running program is large page memory when the ratio is greater than the performance threshold.
[0015] In one embodiment, determining the first access performance of the target CPU executing the target program in a first simulation scenario and the second access performance in a second simulation scenario includes: obtaining a preset number of first reference access performances for the target CPU performing a preset number of accesses in the first simulation scenario; obtaining a preset number of second reference access performances for the target CPU performing a preset number of accesses in the second simulation scenario; determining the first access performance based on the preset number of first reference access performances; and determining the second access performance based on the preset number of second reference access performances.
[0016] In one embodiment, determining the first access performance based on the preset first reference access performance and determining the second access performance based on the preset second reference access performance includes: determining that the average of the preset first reference access performance is the first access performance and the average of the preset second reference access performance is the second access performance.
[0017] In one embodiment, before determining the first access performance of the target running program in the first simulation scenario and the second access performance in the second simulation scenario, the method further includes: specifying the target CPU and the memory to be accessed for executing the target running program in the first simulation scenario, and the target CPU and the memory to be accessed for executing the target running program in the second simulation scenario, using the numactl command.
[0018] Secondly, this application also provides a memory type determination device, comprising: The first determining unit is used to determine the target server and the target running program. The target server adopts a non-consistent memory access architecture, which includes multiple nodes, and each node includes a central processing unit (CPU) and memory. The second determining unit is used to determine the first access performance of the target CPU executing the target program in a first simulation scenario and the second access performance in a second simulation scenario. The first simulation scenario indicates that the target CPU accesses the memory of other nodes, and the second simulation scenario indicates that the target CPU accesses the memory of the local node. The target CPU belongs to the CPUs included in the plurality of nodes. The third determining unit is used to determine the memory type corresponding to the target running program based on the first access performance and the second access performance, wherein the memory type includes small page memory or large page memory.
[0019] Thirdly, embodiments of this application provide an electronic device, including a processor and a memory storing a computer program, wherein the processor executes the program to implement the steps of the memory type determination method described in the first aspect.
[0020] Fourthly, embodiments of this application provide a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the memory type determination method described in the first aspect.
[0021] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the memory type determination method described in the first aspect.
[0022] In a sixth aspect, embodiments of this application provide a system including a processing device, the processing device being used to execute the memory type determination method described in the first aspect above.
[0023] The memory type determination method, apparatus, and device provided in this application first determine a target server and a target running program. The target server adopts a non-consistent memory access architecture, which includes multiple nodes. Each node includes a central processing unit (CPU) and memory. Then, the first access performance of the target CPU executing the target running program in a first simulation scenario and a second access performance in a second simulation scenario are determined. The first simulation scenario indicates that the target CPU accesses the memory of other nodes, and the second simulation scenario indicates that the target CPU accesses the memory of its local node. The target CPU belongs to the CPUs included in the multiple nodes. Finally, the memory type corresponding to the target running program is determined based on the first and second access performances. The memory type includes small-page memory or large-page memory. In this way, the CPU access performance in the two simulation scenarios can be obtained through intelligent learning to determine whether each running program should be allocated large-page memory or small-page memory. This minimizes the performance degradation caused by accessing remote memory and reduces the performance loss caused by the decrease in TLB hit rate, thereby improving the CPU access performance. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the NUMA architecture provided in this application.
[0026] Figure 2 This is a diagram illustrating large page memory access provided in this application.
[0027] Figure 3 This is a diagram illustrating small page memory access provided in this application.
[0028] Figure 4 This is one of the flowcharts illustrating the memory type determination method provided in this application.
[0029] Figure 5 This is the second flowchart illustrating the memory type determination method provided in this application.
[0030] Figure 6 This is a block diagram of the functional units of the memory type determination device provided in this application.
[0031] Figure 7 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0033] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0035] For example Figure 2 As shown, the NUMA-based server has 64 CPUs, divided into four nodes. Each node contains memory and 16 CPUs, with four processes (p0 to p3). Allocating large pages can improve the TLB (Translation Lookaside Buffer) hit rate. The large pages allocated from node0 are used by the four tasks (p0 to p3) (which can be processes or threads). According to load balancing principles, the four running tasks will be scheduled to run on four different CPUs. However, at this point, the CPUs in nodes 1-3 experience a significant performance degradation when accessing large pages. From a memory access perspective, allocating small pages is more performant than allocating large pages. For example... Figure 3 As shown, for operating systems based on Linux, memory is allocated only during read and write operations. Due to load balancing, memory is scheduled to remote memory, and the kernel quickly completes the memory migration to allow the task to continue accessing local memory. Therefore, the kernel also allocates local node memory, resulting in the fastest performance when accessing local memory. However, allocating small page memory also has drawbacks, such as performance loss due to decreased TLB hit rate.
[0036] Therefore, both allocating large page memory and allocating small page memory have their own advantages and disadvantages. How to determine the corresponding memory type for different running programs is an urgent problem to be solved and optimized.
[0037] To address the aforementioned issues, this application provides a method, apparatus, and device for determining memory type. The embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0038] Please see Figure 4 The method for determining memory type provided in this application includes the following steps.
[0039] S401, Identify the target server and target program.
[0040] The target server employs a non-consistent memory access architecture, comprising multiple nodes, each including a Central Processing Unit (CPU) and memory. Specifically, the target server is a Linux-based server, with each node including at least one CPU.
[0041] S402, determine the first access performance of the target CPU executing the target program in the first simulation scenario and the second access performance in the second simulation scenario.
[0042] In this scheme, the first simulated scenario indicates that the target CPU accesses the memory of other nodes, and the second simulated scenario indicates that the target CPU accesses the memory of its local node. The target CPU belongs to a group of CPUs included in the plurality of nodes. That is, this scheme uses intelligent learning to simulate two scenarios—one where the CPU executing the target program accesses local memory and the other where it accesses remote memory—to determine the CPU's access performance under these two scenarios. Specifically, this access performance can indicate the CPU's access speed.
[0043] S403, determine the memory type corresponding to the target running program based on the first access performance and the second access performance.
[0044] The memory type includes small page memory or large page memory.
[0045] As can be seen, in this embodiment, the target server and the target running program are first determined. The target server adopts a non-consistent memory access architecture, which includes multiple nodes. Each node includes at least one CPU and local memory. Then, the first access performance of the CPU executing the target running program in a first simulation scenario and the second access performance in a second simulation scenario are determined. The first simulation scenario indicates that the CPU executing the target running program accesses the memory of other nodes, and the second simulation scenario indicates that the CPU executing the target running program accesses the memory of its local node. Finally, the memory type corresponding to the target running program is determined based on the first and second access performance. The memory type includes small-page memory or large-page memory. In this way, through intelligent learning, it can determine whether each running program should be allocated large-page memory or small-page memory, thereby minimizing the performance degradation caused by accessing remote memory and reducing the performance loss caused by the decrease in TLB hit rate, thus improving the CPU's access performance.
[0046] In one possible embodiment, determining the memory type corresponding to the target running program based on the first access performance and the second access performance includes: obtaining a performance threshold of the target server for the target running program; determining a performance comparison value based on the first access performance and the second access performance; and determining the memory type corresponding to the target running program based on the performance comparison value and the performance threshold.
[0047] This involves pre-setting a performance threshold based on the target server's hardware model and the running program. Then, the system determines whether the target program should use large-page memory or small-page memory based on the relationship between this performance threshold and a performance comparison value. For example, if the performance threshold is lower than the performance comparison value, small-page memory is used; if the performance threshold is higher than the performance comparison value, large-page memory is used.
[0048] As can be seen, in this embodiment, determining whether to use large page memory or small page memory based on the comparison values of two access performance and the preset performance threshold corresponding to the running program can realize personalized allocation for different running programs when determining the memory type, thereby improving the CPU access performance.
[0049] In one possible embodiment, the performance comparison value includes the ratio of the first access performance to the second access performance, and the step of determining the memory type corresponding to the target running program based on the performance comparison value and the performance threshold includes: determining that the memory type corresponding to the target running program is small page memory when the ratio is less than the performance threshold; and determining that the memory type corresponding to the target running program is large page memory when the ratio is greater than the performance threshold.
[0050] The performance comparison value can be the ratio of the first access performance to the second access performance, or it can be the difference between the first access performance and the second access performance, etc.
[0051] As can be seen, in this embodiment, directly comparing the ratio of the first access performance to the second access performance with the performance threshold to determine whether to request small page memory or large page memory for the target running program can improve CPU access performance while reducing the amount of computation.
[0052] In one possible embodiment, determining the first access performance of the target CPU executing the target program in a first simulation scenario and the second access performance in a second simulation scenario includes: obtaining a preset number of first reference access performances of the target CPU performing a preset number of accesses in the first simulation scenario; obtaining a preset number of second reference access performances of the target CPU performing a preset number of accesses in the second simulation scenario; determining the first access performance based on the preset number of first reference access performances; and determining the second access performance based on the preset number of second reference access performances.
[0053] Specifically, when determining the first and second access performance, a program can be run targeting these performances. The CPU will test the performance a preset number of times in a first simulated scenario to obtain a preset number of first reference access performances. Similarly, the CPU will test the performance a preset number of times in a second simulated scenario to obtain a preset number of second reference access performances. In practice, when determining the first and second access performances, a first fluctuation curve and a geothermal fluctuation curve can be generated based on multiple first and second reference access performances. Then, the first and second reference access performances included in a segment of the first and second fluctuation curves where the fluctuation amplitude is less than a preset amplitude are selected as the first target reference access performance and the second target reference access performance, respectively. Finally, the average of the multiple first and second target reference access performances is determined as the first and second access performances.
[0054] As can be seen, in this embodiment, using the reference access performance obtained from multiple tests as the final access performance for determining the memory type can improve the accuracy of performance evaluation, reduce misjudgments caused by fluctuations in a single test, and reduce randomness.
[0055] In one possible embodiment, determining the first access performance based on the preset first reference access performance and determining the second access performance based on the preset second reference access performance includes: determining that the average of the preset first reference access performance is the first access performance and the average of the preset second reference access performance is the second access performance.
[0056] For example, if the preset number of times is 10, then the first access performance is the average access performance obtained from 10 tests in the first simulated scenario.
[0057] As can be seen, in this embodiment, using the average of the reference access performance obtained from multiple tests as the final access performance for determining the memory type can improve the accuracy of performance evaluation while reducing the amount of computation.
[0058] In one possible embodiment, before determining the first access performance of the target running program in the first simulation scenario and the second access performance in the second simulation scenario, the method further includes: specifying the target CPU and the memory to be accessed for executing the target running program in the first simulation scenario, and the target CPU and the memory to be accessed for executing the target running program in the second simulation scenario, using the numactl command.
[0059] `numactl` is a command-line tool in Linux used to control NUMA policies. It allows you to specify which NUMA node's CPU a process runs on and which memory it uses, thus simulating different test scenarios. Specifically, `numactl` determines the CPU executing the program and the local memory it uses, generating the first simulation scenario. It then determines the CPU executing the program and the remote memory it uses, generating the second simulation scenario.
[0060] The following is through Figure 5 This application will be described in detail.
[0061] First, determine the server model and the threshold x0 corresponding to the running program P. Then, use the numactl command to bind the running program P and memory into two scenarios: Scenario 1 (the first simulated scenario): CPU accesses remote memory; Scenario 2 (the second simulated scenario): CPU accesses local memory. Next, run program P is tested 10 times in Scenario 1, and the average performance value is taken to obtain the first access performance v1. Then, it is tested 10 times in Scenario 2, and the average performance value is taken to obtain the second access performance v2. Then, the ratio x1 of the first and second access performance is determined, i.e., v1 / v2 = x1. Finally, the ratio x1 is compared with the threshold x0. If x1 is greater than x0, the running program P requests large page memory; if x1 is less than x0, the running program P requests small page memory.
[0062] Based on the above, intelligent learning can determine whether a running program should allocate large page memory or small page memory, minimizing performance degradation caused by accessing remote memory and reducing performance loss due to decreased TLB hit rate.
[0063] The memory type determination apparatus provided in the embodiments of this application is described below. The memory type determination apparatus described below can be referred to in correspondence with the memory type determination method described above.
[0064] Please see Figure 6 The memory type determination device 600 includes: a first determination unit 601, used to determine a target server and a target running program, wherein the target server adopts a non-consistent memory access architecture, the non-consistent memory access architecture includes multiple nodes, each node including a central processing unit (CPU) and memory; a second determination unit 602, used to determine the first access performance of the target CPU executing the target running program in a first simulation scenario and the second access performance in a second simulation scenario, wherein the first simulation scenario indicates that the target CPU accesses the memory of other nodes, the second simulation scenario indicates that the target CPU accesses the memory of the local node, and the target CPU belongs to the CPUs included in the multiple nodes; and a third determination unit 603, used to determine the memory type corresponding to the target running program based on the first access performance and the second access performance, wherein the memory type includes small page memory or large page memory.
[0065] In one possible embodiment, in determining the memory type corresponding to the target running program based on the first access performance and the second access performance, the third determining unit 603 is specifically configured to: obtain the performance threshold of the target server for the target running program; determine a performance comparison value based on the first access performance and the second access performance; and determine the memory type corresponding to the target running program based on the performance comparison value and the performance threshold.
[0066] In one possible embodiment, the performance comparison value includes the ratio of the first access performance to the second access performance. Regarding determining the memory type corresponding to the target running program based on the performance comparison value and the performance threshold, the third determining unit 603 is specifically configured to: determine that the memory type corresponding to the target running program is small-page memory when the ratio is less than the performance threshold; and determine that the memory type corresponding to the target running program is large-page memory when the ratio is greater than the performance threshold.
[0067] In one possible embodiment, in determining the first access performance of the target CPU executing the target program in a first simulation scenario and the second access performance in a second simulation scenario, the second determining unit 602 is specifically configured to: obtain a preset number of first reference access performances of the target CPU performing a preset number of accesses in the first simulation scenario; obtain a preset number of second reference access performances of the target CPU performing a preset number of accesses in the second simulation scenario; determine the first access performance based on the preset number of first reference access performances; and determine the second access performance based on the preset number of second reference access performances.
[0068] In one possible embodiment, in determining the first access performance based on the preset first reference access performance and determining the second access performance based on the preset second reference access performance, the second determining unit 602 is specifically configured to: determine that the average of the preset first reference access performance is the first access performance and the average of the preset second reference access performance is the second access performance.
[0069] In one possible embodiment, the memory type determination device 600 further includes a designation unit. Before determining the first access performance of the target running program in the first simulation scenario and the second access performance in the second simulation scenario, the designation unit is specifically used to: specify the target CPU and the memory to be accessed for executing the target running program in the first simulation scenario, and the target CPU and the memory to be accessed for executing the target running program in the second simulation scenario, using the numactl command.
[0070] Please see Figure 7 , Figure 7A schematic diagram of the physical structure of an electronic device is provided. This electronic device may include: a processor 710, a communication interface 720, memory 730, and a communication bus 740. The processor 710, communication interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can invoke a computer program in memory 30 to execute a memory type determination method. This method includes: determining a target server and a target running program, wherein the target server adopts a non-uniform memory access architecture, the non-uniform memory access architecture includes multiple nodes, each node including a central processing unit (CPU) and memory; determining a first access performance of the target CPU executing the target running program in a first simulation scenario and a second access performance in a second simulation scenario, wherein the first simulation scenario indicates that the target CPU accesses the memory of other nodes, and the second simulation scenario indicates that the target CPU accesses the memory of its local node, the target CPU belonging to the CPUs included in the multiple nodes; and determining the memory type corresponding to the target running program based on the first access performance and the second access performance, the memory type including small-page memory or large-page memory.
[0071] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0072] On the other hand, this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the memory type determination method provided in the above embodiments. The method includes: determining a target server and a target running program, wherein the target server adopts a non-consistent memory access architecture, the non-consistent memory access architecture includes multiple nodes, each node including a central processing unit (CPU) and memory; determining a first access performance of the target CPU executing the target running program in a first simulation scenario and a second access performance in a second simulation scenario, wherein the first simulation scenario indicates that the target CPU accesses the memory of other nodes, the second simulation scenario indicates that the target CPU accesses the memory of the local node, and the target CPU belongs to the CPUs included in the multiple nodes; and determining the memory type corresponding to the target running program based on the first access performance and the second access performance, wherein the memory type includes small page memory or large page memory.
[0073] On the other hand, embodiments of this application also provide a processor-readable storage medium storing a computer program for causing a processor to execute the memory type determination method provided in the above embodiments. The method includes: determining a target server and a target running program, wherein the target server employs a non-uniform memory access architecture, the non-uniform memory access architecture includes multiple nodes, each node including a central processing unit (CPU) and memory; determining a first access performance of the target CPU executing the target running program in a first simulation scenario and a second access performance in a second simulation scenario, wherein the first simulation scenario indicates that the target CPU accesses memory of other nodes, and the second simulation scenario indicates that the target CPU accesses memory of a local node, and the target CPU belongs to a CPU included in the multiple nodes; and determining the memory type corresponding to the target running program based on the first access performance and the second access performance, wherein the memory type includes small-page memory or large-page memory.
[0074] The processor-readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO)), optical memory (e.g., CD, DVD, BD, HVD), and semiconductor memory (e.g., ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state drive (SSD)).
[0075] On the other hand, embodiments of this application also provide a system including a processing device, the processing device being used to execute the memory type determination method provided in the above embodiments, the method comprising: determining a target server and a target running program, the target server adopting a non-consistent memory access architecture, the non-consistent memory access architecture including multiple nodes, each node including a central processing unit (CPU) and memory; determining a first access performance of a target CPU executing the target running program in a first simulation scenario and a second access performance in a second simulation scenario, the first simulation scenario indicating that the target CPU accesses the memory of other nodes, the second simulation scenario indicating that the target CPU accesses the memory of a local node, the target CPU belonging to a CPU included in the multiple nodes; determining the memory type corresponding to the target running program based on the first access performance and the second access performance, the memory type including small page memory or large page memory.
[0076] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0077] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A method for determining memory type, characterized in that, include: The target server and the target running program are determined. The target server adopts a non-consistent memory access architecture, which includes multiple nodes, each node including a central processing unit (CPU) and memory. The first access performance of the target CPU executing the target program is determined in a first simulation scenario and the second access performance in a second simulation scenario. The first simulation scenario indicates that the target CPU accesses the memory of other nodes, and the second simulation scenario indicates that the target CPU accesses the memory of the local node. The target CPU belongs to the CPUs included in the plurality of nodes. The memory type corresponding to the target running program is determined based on the first access performance and the second access performance, and the memory type includes small page memory or large page memory.
2. The method according to claim 1, characterized in that, Determining the memory type corresponding to the target running program based on the first access performance and the second access performance includes: Obtain the performance threshold of the target server for the target running program; A performance comparison value is determined based on the first access performance and the second access performance; The memory type corresponding to the target running program is determined based on the performance comparison value and the performance threshold.
3. The method according to claim 2, characterized in that, The performance comparison value includes the ratio of the first access performance to the second access performance. Determining the memory type corresponding to the target running program based on the performance comparison value and the performance threshold includes: If the ratio is less than the performance threshold, the memory type corresponding to the target running program is determined to be small page memory; If the ratio is greater than the performance threshold, the memory type corresponding to the target running program is determined to be large page memory.
4. The method according to any one of claims 1-3, characterized in that, The step of determining the first access performance of the target CPU executing the target program in the first simulation scenario and the second access performance in the second simulation scenario includes: Obtain a preset number of first reference access performances of the target CPU in the first simulated scenario after a preset number of accesses; Obtain a preset number of second reference access performances for the target CPU performing a preset number of accesses in the second simulated scenario; The first access performance is determined based on the preset first reference access performance, and the second access performance is determined based on the preset second reference access performance.
5. The method according to claim 4, characterized in that, The step of determining the first access performance based on the preset first reference access performance and determining the second access performance based on the preset second reference access performance includes: The average of the preset first reference access performance is determined as the first access performance, and the average of the preset second reference access performance is determined as the second access performance.
6. The method according to claim 1, characterized in that, Before determining the first access performance of the target running program in the first simulation scenario and the second access performance in the second simulation scenario, the method further includes: The numactl command specifies the target CPU and the memory to be accessed for executing the target program in the first simulation scenario, and the target CPU and the memory to be accessed for executing the target program in the second simulation scenario.
7. A memory type determination device, characterized in that, include: The first determining unit is used to determine the target server and the target running program. The target server adopts a non-consistent memory access architecture, which includes multiple nodes, and each node includes a central processing unit (CPU) and memory. The second determining unit is used to determine the first access performance of the target CPU executing the target program in a first simulation scenario and the second access performance in a second simulation scenario. The first simulation scenario indicates that the target CPU accesses the memory of other nodes, and the second simulation scenario indicates that the target CPU accesses the memory of the local node. The target CPU belongs to the CPUs included in the plurality of nodes. The third determining unit is used to determine the memory type corresponding to the target running program based on the first access performance and the second access performance, wherein the memory type includes small page memory or large page memory.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the memory type determination method as described in any one of claims 1 to 6.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory type determination method as described in any one of claims 1 to 6.
10. A system, characterized in that, Includes a processing device for performing the memory type determination method as described in any one of claims 1 to 6.