System and method for quickly starting and resetting embedded system based on MCU (Microprogrammed Control Unit) and watchdog

Abstract

The invention provides an embedded system quick start reset system and method based on an MCU and a watchdog, and relates to the technical field of electronic communication. The system comprises a main processor, an external watchdog circuit, a capacitor switching circuit and an auxiliary MCU. The auxiliary MCU is in communication connection with the main processor and the external watchdog circuit. The input end of the capacitance switching circuit is connected with the control signal output end of the auxiliary MCU, and the output end of the capacitance switching circuit is connected with a CWD pin of the external watchdog circuit; the auxiliary MCU is used for controlling the capacitor switching circuit to select different capacitors to be connected to an external watchdog circuit in a system starting stage so as to dynamically adjust the reset timeout time of the external watchdog circuit, and resetting the main processor for multiple times so as to find the minimum starting time of the main processor; after the system normally operates, the capacitor switching circuit is controlled to set the reset timeout time of the external watchdog circuit to be the minimum time for ensuring that the main processor can normally feed a dog, so that the suitability and reliability of the embedded system are comprehensively improved.

Description

Technical Field

[0001] This invention relates to the field of electronic communication technology, and in particular to a fast startup and reset system and method for embedded systems based on MCU and watchdog timer. Background Technology

[0002] In complex embedded hardware systems, the external watchdog chip is a key component that ensures the system can be reset after a crash or program crash. Its core parameter is the reset time. At the same time, the system needs to feed the watchdog before it is triggered to reset from power-on to startup. This time is the processor startup time. The two must be matched to ensure the normal operation of the system.

[0003] As some scenarios demand faster system startup speeds and more efficient fault resets, the current common approach is to directly add an external watchdog timer. While this can achieve basic reset functionality, it has significant limitations.

[0004] To avoid startup failure, existing solutions often set the watchdog startup and reset times to fixed values ​​far exceeding actual needs (such as 40s-70s), resulting in slow system startup and inability to adapt to differences in different processors and PCBA components. At the same time, the lack of a dynamic adjustment mechanism for watchdog parameters makes it difficult to find the optimal startup and reset times, and also fails to consider safeguards in case of MCU malfunctions, which may lead to system startup obstruction or reset delays after malfunctions, affecting the user experience. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a fast startup and reset system and method for embedded systems based on an MCU and a watchdog timer. By dynamically adjusting the reset timeout of the external watchdog timer with the assistance of the MCU, it can accurately adapt to hardware differences to achieve the minimum startup time of the main processor, and ensure fast reset in abnormal situations during system operation, thereby comprehensively improving the adaptability and reliability of the embedded system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a fast startup and reset system for an embedded system based on an MCU and a watchdog timer, including a main processor, an external watchdog circuit, a capacitor switching circuit, and an auxiliary MCU; The auxiliary MCU is communicatively connected to the main processor and the external watchdog circuit, respectively. The input terminal of the capacitor switching circuit is connected to the control signal output terminal of the auxiliary MCU, and its output terminal is connected to the CWD pin of the external watchdog circuit. At least one capacitor is connected to its common terminal. The auxiliary MCU is used during the system startup phase to control the capacitor switching circuit to select different capacitors to connect to the external watchdog circuit, so as to dynamically adjust its reset timeout time and find its minimum startup time by resetting the main processor multiple times; after the system is running normally, the capacitor switching circuit is controlled to set the reset timeout time of the external watchdog circuit to the minimum time to ensure that the main processor can feed the watchdog normally. The reset output terminal of the external watchdog circuit is connected to the reset input terminal of the main processor.

[0007] Secondly, the present invention provides a fast startup and reset method for an embedded system based on an MCU and a watchdog timer, comprising: During the system startup phase, the auxiliary MCU controls the switching switch of the capacitor switching circuit to select different capacitor values ​​to connect to the CWD pin of the external watchdog circuit, sets different watchdog timers, and resets the main processor multiple times to monitor its startup status, records the timers corresponding to successful and failed startups, and finds the minimum startup time of the main processor through iterative adjustment. After the system is running normally, the auxiliary MCU sets the timer of the external watchdog to be the minimum time that the main processor can feed the watchdog normally, so as to realize a quick reset when the main processor is abnormal. The external watchdog circuit is configured with an initial timing period, which is used to ensure the basic startup function of the system when the auxiliary MCU fails to work.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This invention dynamically adjusts the reset timeout of the external watchdog through an auxiliary MCU and capacitor switching circuit. During the startup phase, multiple reset tests are conducted to accurately lock the minimum startup time of the main processor, avoiding startup redundancy or failure caused by fixed parameters and adapting to hardware differences. During normal operation, the timeout is set to the minimum threshold for feeding the watchdog, and combined with the direct reset link between the watchdog and the main processor, it ensures rapid reset in case of abnormalities. At the same time, the hierarchical control logic takes into account both startup efficiency and operational reliability, significantly improving the adaptability and response speed of the embedded system.

[0009] (2) This invention relies on the UART interaction capability between the MCU and the processor, combined with the CWD pin capacitor adjustment logic of the watchdog timer, to achieve automated control of the startup time. Initially, the watchdog time is configured according to the parameters recommended by the processor manufacturer to ensure startup. Subsequently, the MCU gradually approaches and locks the minimum effective startup time through a cyclical process of resetting the processor, increasing or decreasing the watchdog time (adjusting the CWD pin capacitor value), and verifying the startup result. This eliminates the need for repeated manual debugging, thereby improving efficiency and ensuring that the startup time reaches the optimal state.

[0010] (3) Due to the influence of PCBA manufacturing processes and component batches, the actual startup characteristics of different hardware vary, and fixed parameters cannot adapt to all situations. This invention uses a dynamic adjustment mechanism of the MCU to automatically test the watchdog time and startup success rate corresponding to different capacitor values ​​for each set of hardware, without relying on uniform fixed parameters. Regardless of fluctuations in component parameters or differences in PCBA assembly, it can accurately find the optimal startup time for the set of hardware, avoiding startup failure or time redundancy due to hardware differences.

[0011] (4) There are various processor models on the market, and different scenarios (such as industrial control and portable devices) have different requirements for startup time. This invention is not limited to a specific processor. Through flexible time adjustment logic (capacitor value adjustable from 100pF to 1μF, time interval selectable from 0.5s / 1s), it can adapt to the startup requirements of various processors. At the same time, by eliminating time redundancy through cyclic optimization process, it ensures that the system completes power-on startup in the shortest time while meeting the premise of successful startup, which meets the requirements of scenarios with strict requirements for startup speed (such as emergency equipment and real-time control scenarios).

[0012] (5) During the operation of the system of the present invention, the MCU adjusts the watchdog time to a value slightly greater than the minimum value of the processor's watchdog feeding time. Once the processor crashes or malfunctions, failure to feed the watchdog on time will trigger the watchdog action. Moreover, the processor and the watchdog are directly connected, eliminating intermediate signal transmission delay. After the watchdog determines the abnormality (which takes the watchdog feeding time), it quickly outputs a reset signal according to a fixed reset time (typical value of 200ms for SGM820), ensuring that the processor restarts immediately, greatly shortening the abnormal recovery time and improving the reliability of system operation.

[0013] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0014] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute a limitation thereof.

[0015] Figure 1 A schematic diagram of the main processor and external watchdog circuit in an embedded system fast boot and reset system based on an MCU and watchdog provided in this embodiment of the invention; Figure 2 A schematic diagram of an auxiliary MCU and its watchdog circuit in an embedded system fast startup and reset system based on an MCU and a watchdog timer is provided for an embodiment of the present invention. Figure 3 A schematic diagram of the first switching circuit in a fast startup and reset system for an embedded system based on an MCU and a watchdog timer, provided in an embodiment of the present invention; Figure 4 A schematic diagram of the second switching circuit in a fast startup and reset system for an embedded system based on an MCU and a watchdog timer, provided in an embodiment of the present invention; Figure 5 A flowchart of a fast startup and reset method for an embedded system based on an MCU and a watchdog timer, provided in an embodiment of the present invention; Among them, U1 is the first switching circuit; U2 is the watchdog timer for the auxiliary MCU; U3 is the second switching circuit; U4 is the main processor; U5 is the auxiliary MCU; and U6 is the external watchdog circuit. Detailed Implementation

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Explanation of technical terms 1. Watchdog: A hardware or software module that monitors the operating status of a system to prevent it from crashing or freezing.

[0018] 2. Watchdog timer: When the system is running normally, send signals (such as specific instructions or register operations) to the watchdog timer at specified intervals to indicate that "the system is normal" and prevent the watchdog timer from triggering abnormal handling.

[0019] 3. Reset the processor: When the watchdog timer detects a system malfunction, it forces a restart of the processor, which will return the system to its initial state.

[0020] Example 1 This embodiment discloses an embedded system fast startup and reset system based on MCU and watchdog timer. The system includes: a capacitor switching circuit (including a first switching circuit U1 and a second switching circuit U3), a watchdog timer U2 for the auxiliary MCU, a main processor U4, an auxiliary MCU U5, and an external watchdog circuit U6.

[0021] Among them, such as Figure 1 As shown, the main processor is an embedded CPU running a complex operating system, which has a long startup time, typically in the tens of seconds.

[0022] like Figure 2 As shown, the auxiliary MCU is a low-cost, low-power microcontroller that establishes a bidirectional communication connection with the main processor via a UART serial port to receive startup status information (such as a startup success flag) sent by the main processor.

[0023] Meanwhile, the SET pin of the auxiliary MCU is connected to the SET pin of the external watchdog circuit to control the enabling and disabling of the watchdog function.

[0024] Additionally, the RESET pin of the auxiliary MCU is connected to the RST pin of the watchdog timer U2 of the auxiliary MCU; the WDI pin of U2 is connected to the GPIO5 pin of the auxiliary MCU. When the auxiliary MCU malfunctions and cannot periodically send a feed signal to the WDI pin of U2 via GPIO5, the WDI pin of U2 will trigger its internal logic, causing the RST pin to output a reset signal, which is then transmitted to the RESET pin of the auxiliary MCU, triggering its reset. Thus, the watchdog timer U2 enables the auxiliary MCU to be reset in case of malfunction, ensuring its stable operation.

[0025] like Figure 1 As shown, the external watchdog circuit uses the SGM820 programmable watchdog timer chip. Its reset output pin ( / RST) is connected to the main processor's reset input pin, used to perform a hard reset of the main processor upon timeout. The voltage of its watchdog CWD pin (time control pin) is determined by the value of the capacitor connected to this pin. According to the chip datasheet, the relationship between its timeout time T and the capacitor C satisfies the formula: T = 78.3 * C + 51ms. This CWD pin is connected to different capacitors through a capacitor switching circuit.

[0026] The capacitor switching circuit consists of at least two analog switching chips (such as DG441DY-T1-E3) and U1 (such as... Figure 3 (as shown) and U3 (as shown) Figure 4 The system is configured as shown in the diagram. The control pins (e.g., IN0, IN1, IN2) of analog switches U1 and U3 are connected to the GPIO pins of the auxiliary MCU. The common input / output terminals of the analog switches are connected in parallel to the CWD pin of an external watchdog chip. Each independent channel of the analog switches is connected to capacitors of different capacitance values, forming a capacitor array. These capacitor values ​​are carefully selected, covering a range from 100pF to 1μF, including, for example, C1 (100pF), C2 (1nF), C3 (1nF), C4 (2.2nF), C5 (10pF), C6 (100nF), and C7 (1uF).

[0027] Compared to directly controlling the CWD pin, the design that indirectly controls the CWD pin through a capacitor switching circuit can achieve more precise capacitance value settings by increasing the number of switching switches and expanding the capacitor combinations. This adapts to the different startup / reset time requirements of different processors due to differences in components and PCBAs. At the same time, it avoids signal interference that may be introduced by directly connecting the MCU to the CWD pin, ensuring the stability and accuracy of the watchdog time adjustment.

[0028] In addition, the CWD pin is directly connected to a fixed capacitor C7 (e.g., 1nF). This fixed capacitor C7 is used to provide an initial timing period (approximately 129.3ms according to the formula above). This initial time ensures that even if the auxiliary MCU fails to control the analog switch due to program crashes or uninitialization, the watchdog circuit can still reset the main processor within a relatively safe time, ensuring that the system has the most basic self-recovery capability.

[0029] The auxiliary MCU has a pre-stored control program. As one implementation, at the initial stage of system power-on, the MCU controls the various control pins of U1 and U3 to connect different capacitors (or their parallel combinations, such as simultaneously connecting C2 and C3 to obtain a 2nF equivalent capacitance) to the CWD pin, thereby dynamically adjusting the watchdog reset timeout and executing the optimization algorithm described in the subsequent method flow.

[0030] In existing technologies, embedded systems often suffer from startup time redundancy or failure due to the difficulty in adapting fixed watchdog parameters to hardware differences, and slow response to abnormal resets. The system provided in this embodiment solves the problem of poor adaptability of fixed parameters by dynamically adjusting the timeout of the external watchdog timer with the assistance of the MCU; multiple tests during the startup phase lock the minimum startup time, overcoming the problem of low startup efficiency; and the minimum threshold setting and direct reset link during runtime solve the problem of abnormal reset delay, comprehensively improving the system's adaptability and reliability.

[0031] Example 2 like Figure 5 As shown, this embodiment discloses a fast boot and reset method for an embedded system based on an MCU and a watchdog timer, including the following steps: S1: During the system startup phase, the auxiliary MCU selects different capacitance values ​​to connect to the time control pin of the external watchdog circuit by controlling the switching switch of the capacitor switching circuit, sets different watchdog timers, and resets the main processor multiple times to monitor its startup status, records the timers corresponding to successful and failed startups, and finds the minimum startup time of the main processor through iterative adjustment. S2: After the system is running normally, the auxiliary MCU sets the timer of the external watchdog to be the minimum time that the main processor can feed the watchdog normally, so as to realize a quick reset when the main processor is abnormal. S3: The external watchdog circuit is configured with an initial timing period, which is used to ensure the basic startup function of the system when the auxiliary MCU cannot work.

[0032] Next, combined Figure 2 This embodiment will provide a detailed description of an elevation benchmark data processing method.

[0033] I. Optimization of minimum startup time during the startup phase; Upon initial power-up, the auxiliary MCU controls the capacitor switching circuit to connect the watchdog CWD pin to a combination consisting of a fixed capacitor C7 and a larger capacitor (e.g., C4 = 2.2nF). This generates a conservative timeout (e.g., 223ms) that is much longer than the startup time recommended by the main processor manufacturer (e.g., 200ms), ensuring that the system can start successfully on the first attempt.

[0034] After the main processor boots successfully, it sends a "boot successful" message to the auxiliary MCU via UART. The auxiliary MCU records the boot time T_on.

[0035] Subsequently, the auxiliary MCU triggers a system restart by controlling the main processor's reset pin or by automatically powering off and restarting. Simultaneously, the MCU, following a binary search logic, controls the capacitor switching circuit to select a smaller capacitor combination (e.g., C2+C3=2nF), reducing the watchdog timeout to 208ms.

[0036] If the main processor successfully restarts and provides feedback within the new time, MCU 2 records the new T_on and continues to execute the binary search logic time reduction operation to attempt to further shorten the time.

[0037] If the watchdog timeout resets (boot failure) before the main processor provides feedback, the MCU records the boot time T_off for this failure.

[0038] Through multiple iterations, the MCU will eventually find a critical point, namely the minimum reliable startup time T_min (between the last successful T_on and the first failed T_off). The MCU will then set the final startup time to T_min plus a safety margin (e.g., 5ms).

[0039] II. Minimum reset time setting during operation; After startup time optimization was completed, the system entered normal operating mode. The main processor began periodically executing the dog-feeding task.

[0040] The auxiliary MCU begins to gradually shorten the watchdog timer (i.e., the watchdog feeding window), decreasing it by one step each time.

[0041] The MCU monitors the status of the main processor. If the main processor fails to feed the watchdog in time within a new, shorter time interval due to the watchdog task being close to its limit, it indicates that the critical point has been reached.

[0042] The MCU sets the watchdog timer interval to a value slightly longer than this critical point, serving as the minimum reset time during operation. This setting ensures that if the main processor crashes or the program malfunctions, the watchdog can reset it in the shortest possible time, enabling rapid recovery.

[0043] As one implementation method, the recommended power-on startup time for the processor is 200ms. The watchdog time needs to be greater than the recommended startup time of 200ms. For example, the reset time is 200ms + 20ms = 220ms. The capacitor value is calculated using the formula: (220ms - 51ms) / 78.3 = 2.15nF. Therefore, the capacitor value is selected as 2.2nF. The time calculated using the formula for 2.2nF is 78.3 * 2.2nF + 51(ms) = 223.26ms. The capacitor on the CWD pin of the watchdog timer is switched to 2.2nF by controlling the MCU. That is, the MCU controls the IN5 pin to be low, and the pins 2 and 3 of the switch U3 are turned on. The CWD pin of the watchdog timer is connected to capacitor C4.

[0044] Referring to the watchdog timer formula, T3 is calculated as 78.3 * 2.2nF + 51 (ms) = 223.26ms. Therefore, the initial startup time T3 is greater than the required startup time of 223.26ms > 200ms. The system can start reliably, but to find the most suitable startup time, the MCU needs to reduce this time. The MCU calculates to reduce the 223.26ms time by 10ms. The capacitor value is calculated using the formula: (213.26ms - 51ms) / 78.3 = 2.0722nF, so the closest capacitor value is 2nF. The time for 2nF is calculated using the formula as 78.3 * 2nF + 51 (ms) = 207.6ms. The MCU controls the IN2 and IN3 pins of switch U1 to be low, and the 10 and 11 pins of switch U1 are turned on. The 14 and 15 pins of switch U1 are also turned on. When the pins are connected, capacitors C2 and C3 are connected to the CWD pin of the watchdog timer, meaning the capacitance value is C2 + C3 = 1nF + 1nF = 2nF.

[0045] If the processor restarts successfully, the MCU will reduce the startup time T3 again according to the above calculation logic, and then control the switch to find a suitable capacitor value to start the processor.

[0046] If startup fails, the calculated time of 207.6ms for 2nF is Toff. To find the most suitable startup time, the MCU needs to increase this time. The MCU calculates and increases the time of 207.6ms by 5ms. The capacitor value is calculated using the formula: (212.6ms-51ms) / 78.3=2.025nF. Therefore, the capacitor value is selected as 2.01nF. The time calculated using the formula for 2.01nF is 78.3*2.01nF+51(ms)=208.38ms. The MCU controls the IN2, IN3, and IN6 pins of switch U1 to be low, and the 10 and 11 pins of switch U1 are turned on. The 14 and 15 pins of switch U1 are turned on. Turning on the 14 and 15 pins of switch U3 connects capacitors C2, C3, and C5 to the CWD pin of U8, that is, the capacitance value is C2+C3=1nF+1nF+10pF=2.01nF.

[0047] The MCU restarts according to the above calculation logic. If the startup is successful, the time is the minimum startup time Ton. The MCU and the processor exchange information via UART, including whether the startup is normal.

[0048] This specific embodiment determines the minimum startup time of the main processor by iteratively adjusting the capacitor value during the startup phase and conducting multiple reset tests. This solves the problem of adapting fixed parameters to hardware differences and significantly shortens startup time. During runtime, the watchdog timer is set to the minimum feeding time to ensure rapid reset in case of main processor abnormalities, improving fault recovery efficiency. At the same time, the initial timer of the external watchdog is retained to ensure the basic startup capability of the system in case of auxiliary MCU failure. The three layers of logic work together to balance startup speed, abnormal response, and reliability in extreme scenarios, significantly optimizing the performance of the embedded system.

[0049] The steps involved in Embodiment 2 above correspond to those in Embodiment 1. For detailed implementation methods, please refer to the relevant description section of Embodiment 1. The above descriptions are merely preferred embodiments of the present invention and are not intended to limit the invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A fast boot and reset system for an embedded system based on an MCU and a watchdog timer, characterized in that, Includes the main processor, external watchdog circuit, capacitor switching circuit, and auxiliary MCU; The auxiliary MCU is communicatively connected to the main processor and the external watchdog circuit, respectively. The input terminal of the capacitor switching circuit is connected to the control signal output terminal of the auxiliary MCU, and its output terminal is connected to the CWD pin of the external watchdog circuit. At least one capacitor is connected to its common terminal. The auxiliary MCU is used during the system startup phase to control the capacitor switching circuit to select different capacitors to connect to the external watchdog circuit, so as to dynamically adjust its reset timeout time and find its minimum startup time by resetting the main processor multiple times; after the system is running normally, the capacitor switching circuit is controlled to set the reset timeout time of the external watchdog circuit to the minimum time to ensure that the main processor can feed the watchdog normally. The reset output terminal of the external watchdog circuit is connected to the reset input terminal of the main processor.

2. The embedded system fast boot and reset system based on MCU and watchdog timer as described in claim 1, characterized in that, The auxiliary MCU is connected to the main processor via UART serial communication.

3. The embedded system fast boot and reset system based on MCU and watchdog timer as described in claim 1, characterized in that, The capacitor switching circuit includes one or more analog switch chips, and the control pins of the analog switch chips are connected to the control signal output terminal of the auxiliary MCU.

4. The embedded system fast boot and reset system based on MCU and watchdog timer as described in claim 3, characterized in that, The capacitors connected to the capacitor switching circuit form a capacitor array. The auxiliary MCU controls the on / off combination of the analog switch chip to connect a single capacitor or multiple capacitors connected in parallel to the CWD pin of the external watchdog circuit.

5. The embedded system fast boot and reset system based on MCU and watchdog as described in claim 1, characterized in that, The external watchdog circuit is a programmable watchdog timer, and its reset timeout is determined linearly or quasi-linearly by the capacitor value connected to the CWD pin.

6. The embedded system fast boot and reset system based on MCU and watchdog as described in claim 1, characterized in that, The CWD pin of the external watchdog circuit is also connected to a fixed capacitor to provide initial timing.

7. A fast startup and reset method for an embedded system based on an MCU and a watchdog timer, wherein the fast startup and reset system is based on any one of claims 1-6, characterized in that, During the system startup phase, the auxiliary MCU controls the switching switch of the capacitor switching circuit to select different capacitor values ​​to connect to the time control pin of the external watchdog circuit, sets different watchdog timer intervals, and resets the main processor multiple times to monitor its startup status, records the timer intervals corresponding to successful and failed startups, and finds the minimum startup time of the main processor through iterative adjustment. After the system is running normally, the auxiliary MCU sets the timer of the external watchdog to be the minimum time that the main processor can feed the watchdog normally, so as to realize a quick reset when the main processor is abnormal. The external watchdog circuit is configured with an initial timing period, which is used to ensure the basic startup function of the system when the auxiliary MCU fails to work.

8. The fast startup and reset method for an embedded system based on an MCU and a watchdog timer as described in claim 7, characterized in that, The step of finding the minimum startup time of the main processor through iterative adjustment specifically includes: The auxiliary MCU starts from an initial watchdog timer that will not trigger a reset, gradually decreases the time, and triggers a system restart. Record the time of the last successful startup and the time of the first failed startup; Set the minimum startup time to a safe value between the two times.

9. A fast boot and reset method for an embedded system based on an MCU and a watchdog timer as described in claim 8, characterized in that, The auxiliary MCU controls the capacitor switching circuit according to the binary search logic, selecting different capacitor combinations to gradually reduce the watchdog timer duration.

10. A fast startup and reset method for an embedded system based on an MCU and a watchdog timer as described in claim 7, characterized in that, The method for determining the minimum time during which the main processor can feed the watchdog normally is as follows: when the system is running normally, the auxiliary MCU gradually shortens the watchdog timer until the main processor is reset due to untimely watchdog feeding, and then the watchdog timer is set to a time greater than this critical value.

Images