A server signal false pull-up prevention system and server

Abstract

The application provides a server signal false pull-up prevention system and a server, and relates to the technical field of computers.The server signal false pull-up prevention system comprises a power management module, a first controller, a logic judgment module and a pull-up module;an output end of the power management module is electrically connected with the first controller;the first output end of the first controller is connected with the first signal input end of the logic judgment module, and the second output end of the first controller is connected with the second signal input end of the logic judgment module;the output end of the logic judgment module is electrically connected with one end of the pull-up module;the other end of the pull-up module is electrically connected with the output end of the power management module;the pull-up module is used for turning on the circuit when a high level is input, pulling down the enable pin of the target voltage regulator and completing false pull-up operation.When the first controller initialization is not completed, the logic judgment module pulls down the enable pin of the target voltage regulator, eliminates false start or state misjudgment caused by the unready controller and strictly guarantees the timing specification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and particularly relates to a server signal false pull-up prevention system and a server. BACKGROUND

[0002] With the development of server technology, the performance of the server is higher and higher, and the reliability requirement is higher and higher. In order to ensure the normal operation of the server, each power supply design needs to not only meet the stability requirement, but also ensure that each power supply as a pull-up signal does not appear false pull-up. It can meet the stable operation under various special working conditions.

[0003] At present, the enable pin EN pin of the voltage regulator (VR) is directly provided by the controller. When the initialization of the controller is not completed, if the EN pin is falsely pulled up by the pull-up signal, the controller will not take any monitoring action at this time, and the system will not cause false judgment. After the initialization of the controller is completed, the EN pin is falsely pulled up by the pull-up signal. At this time, the controller will monitor, and when the voltage of the EN pin falsely pulled up exceeds the threshold value at which the VR can work, the system will mistakenly think that the EN pin has been high. At this time, the VR will normally output. Since each power supply of the server has strict timing requirements, if the EN pin is falsely pulled to high level before the initialization of the controller is completed, the VR will not work in accordance with the timing requirements of the server. SUMMARY

[0004] The present application provides a server signal false pull-up prevention system and a server to at least solve the problem that the VR does not work in accordance with the timing requirements of the server caused by the EN pin being falsely pulled to high level before the initialization of the controller is completed in the related art.

[0005] In a first aspect, the present application provides a server signal false pull-up prevention system, comprising: a power management module, a first controller, a logic judgment module and a pull-up module;

[0006] The output end of the power management module is electrically connected with the first controller, and the power management module is configured to convert standard electricity into controller initialization electricity.

[0007] The first output end of the first controller is connected with the first signal input end of the logic judgment module, and the second output end of the first controller is connected with the second signal input end of the logic judgment module. The first controller is configured to receive the controller initialization electricity output by the power management module, and output a low level and an enable signal when it is detected that the initialization of the first controller is not completed.

[0008] An output end of the logic judgment module is electrically connected with one end of the pull-up module, the logic judgment module is used for comparing a low level with a threshold level to obtain a first condition determination result, and comparing the enable signal with a fixed signal to obtain a second condition determination result, and outputs a high level when the first condition determination result or the second condition determination result is not satisfied;

[0009] The other end of the pull-up module is electrically connected with the output end of the power management module, and the pull-up module is used for turning on the circuit and pulling the enable pin of the target voltage regulator low when a high level is input, and completing the false pull-up operation.

[0010] In a second aspect, the application provides a server, comprising a server body and the server false signal pull-up prevention system provided in the first aspect.

[0011] The application provides a server false signal pull-up prevention system and a server, comprising a power management module, a first controller, a logic judgment module and a pull-up module; wherein an output end of the power management module is electrically connected with the first controller, the power management module is used for converting a standard electric into controller initialization electricity; a first output end of the first controller is connected with a first signal input end of the logic judgment module, a second output end of the first controller is connected with a second signal input end of the logic judgment module, the first controller is used for receiving the controller initialization electricity output by the power management module, and outputting a low level and an enable signal when detecting that the first controller initialization is not completed; an output end of the logic judgment module is electrically connected with one end of the pull-up module, the logic judgment module is used for comparing the low level with a threshold level to obtain a first condition determination result, and comparing the enable signal with a fixed signal to obtain a second condition determination result, and outputting a high level when detecting that the first condition determination result or the second condition determination result is not satisfied; the other end of the pull-up module is electrically connected with the output end of the power management module, and the pull-up module is used for turning on the circuit and pulling the enable pin of the target voltage regulator low when a high level is input, and completing the false pull-up operation. Through the above structural design, the following technical effects are achieved: when the first controller initialization is not completed, the first output end of the first controller outputs a low level signal to the logic judgment module, the low level is less than the threshold level, the first condition determination result is not satisfied, the logic judgment module outputs a high level, the pull-up module receives the high level and turns on the circuit, pulls the enable pin of the target voltage regulator low, and completes the false pull-up operation. Through the logic judgment module, when detecting that the first controller initialization is not completed, the enable pin of the target voltage regulator is pulled low, the false start or state misjudgment caused by the first controller not being ready is eliminated, the opening of the related components strictly follows the power sequence specification of the server, so that the power-on impact or short-circuit current caused by the power sequence disorder is avoided, and the potential hidden danger of device damage is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0013] Figure 1 Structure diagram of a server anti-signal false pull-up system provided by an embodiment of the present application Figure One ;

[0014] Figure 2 Structure diagram of a server anti-signal false pull-up system provided by an embodiment of the present application Figure Two . DETAILED DESCRIPTION

[0015] The exemplary embodiments will be described in detail herein with reference to the drawings. When the description below refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims, and not all inclusive, as exemplified by the following.

[0016] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", etc. The skilled in the art can understand that "first", "second", etc. do not limit the quantity and execution order, and "first", "second", etc. do not necessarily mean different. It should be noted that the words "exemplary" or "for example" in the embodiments of the present application are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are intended to present the relevant concept in a specific manner. In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more.

[0017] It should be noted that the server anti-signal false pull-up system and the server provided by the embodiments of the present application are only examples, and the server anti-signal false pull-up system and the server can include more or less content.

[0018] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards, and provide corresponding operation portal for user to choose authorization or refusal.

[0019] First, some terms involved in the embodiments of the present application are explained.

[0020] STBY power and core power: The current server power supply is divided into STBY power and core power. The STBY power refers to the power supply of the mainboard when the power supply unit (PSU) is in place. The core power refers to the power of the controller on the controlled board, that is, the controller must be initialized before starting.

[0021] VR: EN pin is its enable pin, and PG pin is its Power Good Pin. When the EN pin receives a high-level signal, the VR starts to work and outputs a voltage; when the output voltage of the VR is stable and normal, the PG pin sends out a high-level signal.

[0022] In order to clearly understand the technical solutions of the present application, the solutions of related technologies are introduced in detail.

[0023] Currently, the enable pin EN pin of the VR is directly provided by the controller. Before the initialization of the controller is completed, if the EN pin is mistakenly pulled up by the signal, the controller will not take any monitoring action at this time, and will not cause false judgment to the system. After the initialization of the controller is completed, the situation that the EN pin is mistakenly pulled up by the signal still exists, at this time the controller will monitor, when the voltage of the EN pin mistakenly pulled up exceeds the threshold value that the VR can work, the system will mistakenly think that the EN pin has been high level, at this time the VR will normally output. Because each power supply of the server has strict timing requirements, if the EN pin is mistakenly pulled to high level before the initialization of the controller is completed, it will cause the VR to work not in accordance with the timing requirements of the server.

[0024] In summary, how to design a kind of server signal anti-mistakenly-pulled-up system and server, which can solve the problem that the EN pin is mistakenly pulled to high level before the initialization of the controller is completed, causing the VR to work not in accordance with the timing requirements of the server, is an urgent problem to be solved by the present application.

[0025] Therefore, in view of the above technical problems existing in the related art, the embodiments of the present application provide a kind of server signal anti-mistakenly-pulled-up system and server, to effectively guarantee the strict timing requirements of the server.

[0026] The application scenario of the server anti-signal false pull-up system and the server provided by the embodiment of the present application is introduced as follows. The following application scenario is only an example, and the purpose is to help those skilled in the art to understand the technical content of the present application, but it does not mean that the embodiment of the present application cannot be used for other devices, systems, environments or scenarios.

[0027] Data center server cluster: through the server anti-signal false pull-up system and the server provided by the embodiment of the present application, the power supply timing problem is strictly guaranteed, and it is ensured that only after the CPU, memory and other core hardware complete self-checking and initialization and reach a stable working state, the subsequent power supply and peripheral components are sequentially awakened, thereby providing a safer and more reliable startup environment.

[0028] Figure 1 Structure of the server anti-signal false pull-up system provided by the embodiment of the present application Figure One As shown in Figure 1 , the server anti-signal false pull-up system provided by the embodiment of the present application comprises a power management module, a first controller, a logic judgment module and a pull-up module.

[0029] Among them, the output end of the power management module is electrically connected with the first controller, and the power management module is used for converting standard electricity into controller initialization electricity.

[0030] In the embodiment, the power management module comprises a PSU, an electronic fuse module and a power management integrated circuit (PMIC) module.

[0031] After the server is plugged in, the PSU outputs 12V DC voltage, i.e. standard electricity, which is marked as P12V_PSU, and after passing through the electronic fuse module, it becomes P12V_STBY, i.e. standby 12V, and is sent to the PMIC module. The input of the PMIC module is the standby voltage output by the electronic fuse module, and the output is a plurality of low-voltage standby voltages, i.e. controller initialization electricity.

[0032] The first output end of the first controller is connected with the first signal input end of the logic judgment module, and the second output end of the first controller is connected with the second signal input end of the logic judgment module, and the first controller is used for receiving the controller initialization electricity output by the power management module, and outputting a low level and an enable signal when it is detected that the first controller initialization is not completed.

[0033] In the embodiment, the signal outputted by the first output end of the first controller includes but is not limited to the CPLD_Done signal or the MCU_Ready signal, and the signal outputted by the second output end of the first controller includes but is not limited to the CPLD_ENn signal or the MCU_Enable signal. The first controller receives the controller initialization power outputted by the power management module, and when the first controller initialization is not completed, the signal outputted by the first output end of the first controller is a low-level signal, and the signal outputted by the second output end of the first controller is an enable signal.

[0034] The first controller sends the En signal of each Core, that is, the enable signal outputted by the second output end of the first controller, and the signal is determined by 0 or 1 to determine whether the EN is provided or not.

[0035] The output end of the logic judgment module is electrically connected with one end of the pull-up module. The logic judgment module is used for comparing the low level with the threshold level to obtain a first condition determination result, and comparing the enable signal with a fixed signal to obtain a second condition determination result. When it is detected that the first condition determination result or the second condition determination result is not satisfied, a high level is outputted.

[0036] In the embodiment, the logic judgment module can be a digital comparator or other components capable of achieving the same function, which is not specifically limited here.

[0037] The threshold level is a fixed reference threshold value set in the logic judgment module in advance. If the input signal of the first signal input end of the logic judgment module is less than the threshold level, the first condition determination result is not satisfied. Specifically, in the embodiment, the low level is less than the threshold level, the first condition determination result is not satisfied, and no matter whether the second condition determination result is satisfied or not, the logic judgment module outputs a high level at this time.

[0038] The other end of the pull-up module is electrically connected with the output end of the power management module. The pull-up module is used for turning on the circuit when the input high level is inputted, and pulling down the enable pin of the target voltage regulator to complete the false pull-up operation.

[0039] In the embodiment, if the logic judgment module outputs a high level, the high level signal is inputted into the pull-up module, Q1 is turned on through the pull-up module, the enable pin EN pin of the target VR is pulled down, and the target device is not started. The NMOS is controlled by the first basic voltage and the output of the logic judgment module at this time.

[0040] Optionally, the first controller can be a Complex Programmable Logic Device (CPLD) or a Microcontroller Unit (MCU). When the first controller is a CPLD, the signal output by the first output end of the first controller is a CPLD_Done signal, and is electrically connected to the first signal input end of the logic judgment module; the signal output by the second output end of the first controller is a CPLD_ENn signal, and is electrically connected to the second signal input end of the logic judgment module. When the first controller is an MCU, the signal output by the first output end of the first controller is an MCU_Ready signal, and is electrically connected to the first signal input end of the logic judgment module; the signal output by the second output end of the first controller is an MCU_Enable signal, and is electrically connected to the second signal input end of the logic judgment module. The first controller is not specifically limited here.

[0041] When the first controller initialization is not completed, the first output end of the first controller outputs a low-level signal to the logic judgment module, the low level is less than the threshold level, the first condition judgment result is not satisfied, the logic judgment module outputs a high level, the pull-up module receives the high level and turns on the circuit, pulls down the enable pin of the target voltage regulator, and completes the false pull-up operation. By detecting that the first controller initialization is not completed through the logic judgment module, the enable pin of the target voltage regulator is pulled down, the false start or state misjudgment caused by the unready first controller is eliminated, and it is ensured that the opening of the related components strictly follows the power sequence specification of the server, so as to avoid the power-on impact or short-circuit current caused by the power sequence disorder, and to avoid the potential risk of device damage.

[0042] The application provides a server signal false pull-up prevention system, comprising a power management module, a first controller, a logic judgment module and a pull-up module; wherein the output end of the power management module is electrically connected with the first controller, and the power management module is used for converting standard electricity into controller initialization electricity; the first output end of the first controller is connected with the first signal input end of the logic judgment module, the second output end of the first controller is connected with the second signal input end of the logic judgment module, and the first controller is used for receiving the controller initialization electricity output by the power management module, and outputting a low level and an enable signal when detecting that the first controller initialization is not completed; the output end of the logic judgment module is electrically connected with one end of the pull-up module, the logic judgment module is used for comparing the low level with a threshold level to obtain a first condition judgment result, and comparing the enable signal with a fixed signal to obtain a second condition judgment result, and outputting a high level when detecting that the first condition judgment result or the second condition judgment result is not satisfied; the other end of the pull-up module is electrically connected with the output end of the power management module, and the pull-up module is used for turning on the circuit when inputting the high level, and pulling down the enable pin of the target voltage regulator to complete the false pull-up operation. Through the above structural design, the following technical effects are realized: when the first controller initialization is not completed, the first output end of the first controller outputs a low level signal to the logic judgment module, the low level is less than the threshold level, the first condition judgment result is not satisfied, the logic judgment module outputs a high level, the pull-up module receives the high level and turns on the circuit, and the enable pin of the target voltage regulator is pulled down to complete the false pull-up operation. Through the logic judgment module, when detecting that the first controller initialization is not completed, the enable pin of the target voltage regulator is pulled down, the false start or state misjudgment caused by the first controller not being ready is eliminated, the opening of the related components strictly follows the power sequence specification of the server, so that the power-on impact or short-circuit current caused by the power sequence disorder is avoided, and the potential hidden danger of device damage is avoided.

[0043] On the basis of the above embodiment, the application provides a server signal false pull-up prevention system. In the embodiment, the controller initialization electricity output by the output end of the power management module in the server signal false pull-up prevention system comprises a first basic voltage, a second basic voltage and a third basic voltage; wherein the first basic voltage is greater than the second basic voltage, the second basic voltage is greater than the third basic voltage, and the other end of the pull-up module is electrically connected with the output end of the power management module for receiving the first basic voltage; the first basic voltage, the second basic voltage and the third basic voltage are all input into the first controller for completing the initialization of the first controller.

[0044] In this embodiment, the first base voltage is P3V3_STBY, the second base voltage is P1V8_STBY, and the third base voltage is P1V2_STBY. The PMIC module converts P12V_STBY into P3V3_STBY, P1V8_STBY, and P1V2_STBY, and the first controller is powered by P3V3_STBY, P1V8_STBY, and P1V2_STBY to start initialization. Optionally, the PMIC module can output other standby voltages in addition to the three standby voltages P3V3_STBY, P1V8_STBY, and P1V2_STBY. The PMIC module can realize multi-path power conversion, has small board area, and can meet the design requirements of limited board cards.

[0045] The first base voltage, the second base voltage, and the third base voltage are output by the power management module, and the first controller is initialized by using these voltages, which realizes an efficient, stable, and integrated power management scheme. By providing multiple accurate voltage levels, not only is the energy utilization rate optimized and heat generation reduced, but the reliable startup and operation sequence of each component of the system are also ensured, thereby improving the response speed and reliability of the system, simplifying the hardware design, and supporting flexible power consumption control strategies.

[0046] The output end of the logic judgment module is electrically connected to one end of the pull-up module, and the other end of the pull-up module is connected to the first base voltage. Optionally, the other end of the pull-up module can be connected to the first base voltage or other appropriate STBY, such as P5V_STBY, which is not specifically limited here. The electronic fuse module, the power management integrated circuit module, the first controller, the logic judgment module, and the pull-up module are connected by electrical signals. The logic judgment module detects the working state of the first controller, i.e., monitors the initialization completion state of the first controller.

[0047] On the basis of the above embodiment, the application provides a server anti-signal false pull-up system. In this embodiment, the pull-up module in the server anti-signal false pull-up system includes a switch resistor, a negative charge type metal oxide semiconductor field effect transistor, and a pull-up resistor.

[0048] The switch resistor is connected to the first base voltage and the gate level of the negative charge type metal oxide semiconductor field effect transistor, the source level of the negative charge type metal oxide semiconductor field effect transistor is grounded, the drain of the negative charge type metal oxide semiconductor field effect transistor is connected to the enable pin of the target voltage regulator and the pull-up resistor, and the pull-up resistor is connected to the first base voltage.

[0049] In this embodiment, as Figure 1As shown, the switch resistor is R1, the negative charge type metal oxide semiconductor field effect transistor is an N-channel Depletion-mode Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS), the NMOS transistor is Q1, and the pull-up resistor is R2. The G pole of Q1 is connected with R1, the S pole of Q1 is grounded, and the D pole of Q1 is connected with the EN pin of the target voltage regulator and the pull-up resistor R2 respectively.

[0050] The pull-up module is composed of the switch resistor, the negative charge type metal oxide semiconductor field effect transistor, and the pull-up resistor, so that the voltage regulator can be pulled to a low level when the first controller is not initialized, i.e., not in a normal working state, thereby eliminating the false start or state misjudgment caused by the unready first controller and strictly ensuring the strict timing problem of the server.

[0051] On the basis of the above embodiment, the embodiment of the application provides a server signal false pull-up prevention system. In the embodiment, the first controller in the server signal false pull-up prevention system is further configured to receive the controller initialization power output by the power management module and output a high level and an enable signal when it is detected that the first controller initialization is completed.

[0052] In the embodiment, the first controller is further configured to receive the controller initialization power output by the power management module, and when the first controller initialization is completed, the signal output by the first output end of the first controller is a high level signal, and the signal output by the second output end of the first controller is an enable signal.

[0053] The logic judgment module is further configured to compare the high level with a threshold level to obtain a first condition determination result, compare the enable signal with a fixed signal to obtain a second condition determination result, and output a low level when it is detected that the first condition determination result is satisfied and the second condition determination result is satisfied.

[0054] In the embodiment, the fixed signal is a digital 1, and the threshold level is a fixed reference threshold value pre-set in the logic judgment module. If the input signal of the first signal input end of the logic judgment module is greater than or equal to the threshold level, the first condition determination result is satisfied. Specifically, in the embodiment, the high level is greater than the threshold level, and the first condition determination result is satisfied. If the enable signal = 1, the second condition determination result is satisfied, otherwise, the second condition determination result is not satisfied. The enable signal is controlled to be a high level or a low level by internal logic.

[0055] When the first condition determination result and the second condition determination result are both satisfied, the output end of the logic judgment module outputs a low level signal.

[0056] The pull-up module is further configured to cut off the circuit when the input is low and pull up the enable pin of the target voltage regulator, thereby completing the pull-up operation.

[0057] In this embodiment, when it is detected that both the first condition determination result and the second condition determination result are satisfied, the logic judgment module outputs a low-level signal at the output end, inputs the low-level signal to the pull-up module, cuts off Q1 through the pull-up module, and pulls up the EN pin of the target VR, thereby starting the target device.

[0058] This method realizes strict timing control and fault safety protection. Only when both the first condition determination result and the second condition determination result are satisfied, the system is allowed to power on the target voltage regulator, which not only ensures that each functional module is started in turn according to the predetermined order and avoids system instability caused by power competition or logic confusion, but also serves as an interlocking mechanism to effectively prevent false start when necessary conditions are not met, thereby avoiding potential inrush current, power conflict or signal latch error, and significantly improving the robustness and reliability of the hardware.

[0059] The following is the control logic of the server signal false pull-up prevention system:

[0060] First, the electronic fuse module converts P12V_PSU into P12V_STBY and sends P12V_STBY to the PMIC module. P12V_STBY is converted into P3V3_STBY, P1V8_STBY and P1V2_STBY by the PMIC module, which provides power for the first controller and is used for pull-up. The initialization state signal of the first controller is obtained, which is used to indicate whether the first controller has completed initialization.

[0061] Secondly, according to the initialization state signal, the level signal output by the first output end of the first controller is determined. Specifically, if the first controller is initialized, the level signal output by the first output end of the first controller is high; if the first controller is not initialized, the level signal output by the first output end of the first controller is low.

[0062] Then, the level signal output by the first output end of the first controller, the enable signal output by the second output end of the first controller and the threshold level are input into the logic judgment module to obtain the level signal output by the logic judgment module. The level signal output by the first output end is compared with the threshold level to obtain a first condition determination result, the enable signal output by the second output end of the first controller is compared with a fixed signal to obtain a second condition determination result, and the level signal output by the logic judgment module is obtained according to the comparison result of the first condition and the comparison result of the second condition. Specifically, when the level signal output by the first output end is greater than or equal to the threshold level, the first condition determination result is satisfied, otherwise, the first condition determination result is not satisfied; when the enable signal output by the second output end of the first controller is equal to the fixed signal, the second condition determination result is satisfied, otherwise, the second condition determination result is not satisfied. The first condition determination result and the second condition determination result are the control logic of AND, and only when the first condition determination result and the second condition determination result are both satisfied, the logic judgment module outputs a low level signal, otherwise, the logic judgment module outputs a high level signal.

[0063] Finally, the level signal output by the logic judgment module is input into the pull-up module to dynamically adjust the input signal pull-up state of the enable pin of the target voltage regulator according to the level signal output by the logic judgment module. Specifically, if the level signal output by the logic judgment module is a high level signal, the high level signal is input into the pull-up module, and the negative charge type metal oxide semiconductor field effect transistor is turned on through the pull-up module, so that the enable pin of the target voltage regulator is pulled low and the target device is not started; if the level signal output by the logic judgment module is a low level signal, the low level signal is input into the pull-up module, and the negative charge type metal oxide semiconductor field effect transistor is turned off through the pull-up module, so that the enable pin of the target voltage regulator is pulled high and the target device is started.

[0064] When starting, since the STBY voltage is earlier than the CPLD, the CPLD is earlier than the core, when the input of the core voltage VR is the STBY voltage, if the EN signal is pulled up by the STBY voltage, the VR will have an output in advance, causing timing and CPLD logic confusion, resulting in abnormal server startup. The server signal anti-pull-up system and the server provided by the embodiment of the application can strictly guarantee the timing problem.

[0065] When the EN signal of the electronic fuse module for supplying power to components such as hard disks and fans is repeatedly pulled up by mistake, the electronic fuse module is repeatedly turned on, and the large current caused by the un-timely jump of the back-end load causes the back-end components to burn out. The server signal anti-pull-up system and the server provided by the embodiment of the application can effectively solve the problem of mistaken pull-up.

[0066] Due to the EN signal being pulled up, when the mainboard fails, accurate positioning cannot be performed. The server signal false pull-up prevention system and server provided in the embodiment of the application can effectively solve the false pull-up problem.

[0067] In the related art, the pull-up signal is inhibited by increasing the pull-down capacitor of the EN signal. In the design process, if the capacitor is too large, the power-on will be too slow, causing the controller to recognize a timeout and resulting in a problem of not powering on. At the same time, as the capacitor ages, the capacitance value becomes smaller, the inhibition effect decreases, and the inhibition failure may also occur. The server signal false pull-up prevention system and server provided in the embodiment of the application can effectively solve the inhibition failure problem.

[0068] For the later-stage VR, the EN pin of the VR is pulled high, and at this time, the input has not been reached, which is easy to pull the EN pin and cause device damage. The server signal false pull-up prevention system and server provided in the embodiment of the application can strictly guarantee the timing problem and avoid device damage caused by the destruction of the timing problem.

[0069] Figure 2 The structure of the server signal false pull-up prevention system provided in the embodiment of the application Figure Two . As Figure 2 shown, the pull-up module in the server signal false pull-up prevention system provided in the embodiment of the application further includes: an AND gate part with a first input end grounded and connected to an enable pin of a target voltage regulator, a second controller with an input end connected to an output end of the AND gate part, and a second input end of the AND gate part connected to a second output end of the first controller.

[0070] In the embodiment, the second controller M1 can be an MCU, and the pull-up module further includes an AND gate part A1 and the second controller M1. The first input end of the AND gate part A1 is an interface 1, the second input end of the AND gate part A1 is an interface 2, and the output end of the AND gate part is an interface 3.

[0071] The first input end of A1 is grounded and connected to the VR EN pin, the second input end of A1 is connected to the second output end of the first controller, and the output end of A1 is connected to the second controller M1.

[0072] The second output end of the first controller is connected to the enable pin of the target voltage regulator.

[0073] In the embodiment, the second output end of the first controller is connected to the VR EN pin, which is used to turn on or off the VR module. When the VR module is turned on, it is used to output the working voltage of the target component to start the target component.

[0074] The second controller is configured to detect a target enable signal output by the target voltage regulator when the target voltage regulator is in normal operation, and send a reset signal to the AND gate part according to a detection result in a preset time period.

[0075] In this embodiment, the target enable signal output by the target voltage regulator when the target voltage regulator is in normal operation is a level signal sent by a PG pin, that is, a PG signal, and the second controller M1 is configured to detect the PG signal and send a reset signal to A1 according to a detection result in a preset time period. Optionally, the preset time period is 20 minutes. The preset time period is not limited here.

[0076] The AND gate part is configured to receive the reset signal and output the reset signal to a second output end of the first controller, and the reset signal is configured to control the target voltage regulator to reset and restart.

[0077] In this embodiment, A1 is configured to receive the reset signal and output the reset signal to the second output end of the first controller, and the second output end of the first controller receives the reset signal and controls the target voltage regulator to reset and restart according to the reset signal.

[0078] The second controller and the AND gate part are used to detect and reset the PG signal output by the VR module, which can realize real-time monitoring of the PG signal through the second controller to ensure that no transient abnormality is lost, and can reset and restart the VR module through the combination of the second controller and the AND gate part. This scheme combines the determinacy of the hardware circuit and the programmability of the controller, and has extremely high response speed and flexible fault handling strategy, which can not only capture and respond to transient power supply abnormalities in the first time to prevent system collapse, but also execute targeted reset actions through intelligent judgment, and report accurate fault information when autonomous recovery is invalid, thereby fundamentally improving the reliability and maintainability of the system.

[0079] On the basis of the above embodiment, the application provides a server anti-signal false pull-up system. In the server anti-signal false pull-up system provided by the embodiment, the second controller is specifically configured to:

[0080] detect a falling edge of a target enable signal output by the target voltage regulator when the target voltage regulator is in normal operation, and determine that a latch fault occurs when the target enable signal has a first target number of falling edges in a preset time period and continuously outputs a low level.

[0081] In this embodiment, the first target number is 1 or 2. When the enable pin EN pin of the target VR is set high, the VR module is in normal operation and outputs a PG signal.

[0082] If one falling edge of the PG signal is detected and the output is low within a preset time period, it is determined that there is a latch fault, and it is considered that the VR module is a Latch module. Similarly, if two falling edges of the PG signal are detected and the output is low within a preset time period, it is determined that there is a latch fault, and it is considered that the VR module is a Latch module.

[0083] After determining that there is a latch fault, the second controller M1 sends a reset signal to A1, A1 receives the reset signal and outputs the reset signal to the second output end of the first controller, and the second output end of the first controller receives the reset signal and controls the VR module to reset and restart according to the reset signal.

[0084] When it is detected that the number of times of resetting and restarting of the target voltage regulator reaches a preset target number of times, the target enable signal is low, and the target voltage regulator latch power supply abnormality is output.

[0085] In this embodiment, the preset target number of times is three. Specifically, if the PG signal returns to normal after the first time of resetting and restarting of the VR module, it indicates that the VR module also returns to normal. If the PG signal is still low after the first time of resetting and restarting of the VR module, the second controller M1 sends a reset signal to A1 again, and the VR module is reset and restarted for the second time.

[0086] If the PG signal returns to normal after the second time of resetting and restarting of the VR module, it indicates that the VR module also returns to normal. If the PG signal is still low after the second time of resetting and restarting of the VR module, the second controller M1 sends a reset signal to A1 again, and the VR module is reset and restarted for the third time.

[0087] If the PG signal returns to normal after the third time of resetting and restarting of the VR module, it indicates that the VR module also returns to normal. If the PG signal is still low after the third time of resetting and restarting of the VR module, the target voltage regulator latch power supply abnormality is output, it is considered that the VR module has a power supply abnormality, an alarm signal is generated, and feedback is given to the baseboard management controller (BMC) for fault processing.

[0088] When it is detected that there is a first target number of falling edges of the PG signal and the output is low, it is determined that there is a latch fault, and the VR module is reset and restarted. This method can accurately distinguish between transient interference and real permanent latch fault, effectively avoids misjudgment and system misoperation caused by signal glitches or temporary jitter, ensures the accuracy of fault identification, and thus triggers the subsequent reset or alarm process only when it is necessary, greatly improving the stability of system operation and the reliability of decision-making.

[0089] On the basis of the above-mentioned embodiments, the application provides a server signal false pull-up prevention system. In the server signal false pull-up prevention system, the second controller is further configured to:

[0090] When it is detected that the target enable signal has a second target number of falling edges within a preset time period and continuously outputs a low level, a target voltage regulator latch power supply abnormality is output.

[0091] In the embodiment, the second target number is 3 or more. If it is detected that the PG signal has 3 or more falling edges within a preset time period and continuously outputs a low level, a target voltage regulator latch power supply abnormality is output, the VR module is considered to be a retry module, the VR module is considered to have a power supply abnormality, and feedback is given to the BMC for fault processing.

[0092] Through accurate identification of specific fault modes, the essential difference between intermittent faults and permanent hardware faults can be effectively identified and located. Not only can transient interference that may be misjudged by single falling edge detection be avoided, but more importantly, the module that is truly abnormal can be accurately marked and reported, thereby realizing rapid diagnosis and accurate isolation of system power supply problems and greatly improving system reliability and maintenance efficiency.

[0093] On the basis of the above-mentioned embodiments, the application provides a server signal false pull-up prevention system. In the server signal false pull-up prevention system, the pull-up module further comprises a capacitor, one end of the capacitor is connected with the second controller, the other end of the capacitor is grounded, and the capacitor is configured to filter high-frequency noise in the target enable signal and input the denoised target enable signal to the second controller.

[0094] In the embodiment, one end of the capacitor C1 is connected with the second controller M1, and the other end of the capacitor is grounded. The capacitor C1 can suppress the instantaneous fluctuation of the PG signal, for example, the glitch when the PG signal jumps, so that the PG signal received by the second controller M1 is more stable and accurate, and the second controller M1 avoids misjudging the state of the PG signal, for example, misidentifying noise as a falling edge of the PG signal.

[0095] On the basis of the above-mentioned embodiments, the application provides a server signal false pull-up prevention system. In the server signal false pull-up prevention system, the logic judgment module is any one of a digital comparator, an AND gate circuit, and a logic processor.

[0096] In the embodiment, the logic judgment module can be any one of a digital comparator, an AND gate circuit, and a logic processor.

[0097] This architecture has great flexibility and scalability, allowing free selection of implementation solutions according to performance requirements, cost constraints and functional complexity of different scenarios, thereby accurately optimizing resource allocation and performance under the premise of guaranteeing core judgment functions.

[0098] The embodiment provides a server, comprising a server body and the server anti-signal false pull-up system provided in the above embodiment.

[0099] In the embodiment, the server is composed of the server body and the server anti-signal false pull-up system provided in the above embodiment.

[0100] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. Each technical feature of the above embodiments can be combined arbitrarily, and in order to make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0101] Other embodiments of this application will be readily apparent to those skilled in the art upon considering the description herein, the drawings and the annexed claims. The present application is intended to cover any adaptations or variations of the application followed in the general principles of the application and including such further modifications as can occur to those skilled in the art in the application of the application. The application is not to be limited to the precise details of practice set forth above for describing the precise embodiments of the application.

[0102] It should be understood that the application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A server anti-signal false pull-up system, characterized in that, The application relates to a power management module, a first controller, a logic judgment module and a pull-up module. The output end of the power management module is electrically connected with the first controller, and the power management module is used for converting standard electricity into controller initialization electricity. The first output end of the first controller is connected with the first signal input end of the logic judgment module, the second output end of the first controller is connected with the second signal input end of the logic judgment module, and the first controller is used for receiving the controller initialization electricity output by the power management module and outputting a low level and an enable signal when it is detected that the first controller initialization is not completed. The output end of the logic judgment module is electrically connected with one end of the pull-up module, the logic judgment module is used for comparing the low level with a threshold level to obtain a first condition judgment result and comparing the enable signal with a fixed signal to obtain a second condition judgment result, and a high level is output when it is detected that the first condition judgment result or the second condition judgment result is not satisfied. The other end of the pull-up module is electrically connected with the output end of the power management module, and the pull-up module is used for turning on a circuit and pulling down an enable pin of a target voltage regulator when a high level is input, so that the false pull-up operation is completed. The controller initialization electricity output by the output end of the power management module comprises a first basic voltage, a second basic voltage and a third basic voltage, the first basic voltage is greater than the second basic voltage, the second basic voltage is greater than the third basic voltage, the other end of the pull-up module is electrically connected with the output end of the power management module and is used for receiving the first basic voltage, and the first basic voltage, the second basic voltage and the third basic voltage are all input into the first controller and are used for completing the initialization of the first controller.

2. The system of claim 1, wherein, The pull-up module comprises a switch resistor, a negative charge type metal oxide semiconductor field effect transistor and a pull-up resistor.

3. The system of claim 2, wherein, The switch resistor is connected with the first basic voltage and the gate level of the negative charge type metal oxide semiconductor field effect transistor respectively, the source level of the negative charge type metal oxide semiconductor field effect transistor is grounded, the drain of the negative charge type metal oxide semiconductor field effect transistor is connected with the enable pin of the target voltage regulator and the pull-up resistor respectively, and the pull-up resistor is connected with the first basic voltage. The first controller is also used for receiving the controller initialization electricity output by the power management module and outputting a high level and an enable signal when it is detected that the first controller initialization is completed.

4. The system of claim 1, wherein, The logic judgment module is also used for comparing the high level with the threshold level to obtain a first condition judgment result, comparing the enable signal with the fixed signal to obtain a second condition judgment result, and outputting a low level when it is detected that the first condition judgment result is satisfied and the second condition judgment result is satisfied. The pull-up module is also used for turning off a circuit and pulling up the enable pin of the target voltage regulator when a low level is input, so that the pull-up operation is completed. ​ ​ 5. The system of claim 3, wherein, The pull-up module further comprises an AND gate part having a first input terminal grounded and connected with an enable pin of the target voltage regulator, and a second controller having an input terminal connected with an output terminal of the AND gate part, and a second input terminal of the AND gate part connected with a second output terminal of the first controller; the second output terminal of the first controller is connected with the enable pin of the target voltage regulator; the second controller is configured to detect a target enable signal output by the target voltage regulator when the target voltage regulator is working normally, and send a reset signal to the AND gate part according to a detection result in a preset time period; the AND gate part is configured to receive the reset signal and output the reset signal to the second output terminal of the first controller, and the reset signal is used to control the target voltage regulator to reset and restart.

6. The system of claim 5, wherein, The second controller is specifically configured to: detect a falling edge of the target enable signal output by the target voltage regulator when the target voltage regulator is working normally, and determine that a latch fault occurs when a first target number of falling edges of the target enable signal are detected in a preset time period and the target enable signal continuously outputs a low level; output a target voltage regulator latch power supply abnormality when the target enable signal is a low level after a number of times of resetting and restarting of the target voltage regulator reaches a preset target number.

7. The system of claim 6, wherein, The second controller is further configured to: output a target voltage regulator latch power supply abnormality when a second target number of falling edges of the target enable signal are detected in a preset time period and the target enable signal continuously outputs a low level.

8. The system of claim 6, wherein, The pull-up module further comprises a capacitor, one end of the capacitor is connected with the second controller, and the other end of the capacitor is grounded, and the capacitor is used to filter high-frequency noise in the target enable signal and input the target enable signal after noise elimination to the second controller.

9. The system of any one of claims 1 to 8, wherein, The logic judgment module is any one of a digital comparator, an AND gate circuit and a logic processor.

10. A server, characterized by The server body and the server false signal pull-up prevention system according to any one of claims 1 to 9 are included.

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