Method and device for accessing asymmetric capacity memory, chip and electronic equipment

Abstract

The invention provides a method and device for accessing an asymmetric capacity memory, a chip and electronic equipment. The method comprises the following steps: receiving a memory access request from main equipment; performing memory access judgment based on the memory access request and a preset address line of a memory; if the address of the memory access request is within the asymmetric memory capacity range, converting the memory access request based on a set conversion rule to obtain a converted memory access request; and accessing the memory according to the converted memory access request so as to execute a corresponding access operation. According to the method and the device, more content capacity can be supported, various memory particle resources are fully utilized, the cost of the memory particles is saved, and the problems of low DRAM particle resource utilization rate and high system cost caused by strict limitation of DDR memory on DRAM particle capacity and bit width in the prior art are solved.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of memory, and relates to asymmetric DDR capacity technology, in particular to a method and device for accessing asymmetric capacity memory, a chip and an electronic device. BACKGROUND

[0002] In modern electronic devices, double data rate (DDR) memory as a key storage component, its capacity and performance directly affect the system running efficiency. The traditional DDR memory design usually adopts a standardized way to build each memory rank: that is, a number of DRAM particles with the same capacity and consistent bit width (such as x8, x16, etc.) are combined in parallel. For example, a 32-bit wide DDR rank is usually composed of two 16-bit wide DRAM particles, each with a capacity of 512MB, thereby realizing a total capacity of 1024MB. Such design relies on symmetrical particle configuration, and through uniform capacity and bit width, it meets the standardized needs of memory controller for data bandwidth and address mapping. This symmetrical particle layout is widely adopted in JEDEC standards, and its advantages are high hardware compatibility, simplified memory controller design, and easy to realize uniform bandwidth allocation.

[0003] However, with the popularity of advanced extensible interface (AXI) bus protocol in system on chip (SoC) architecture, the traditional symmetrical DRAM particle design exposes significant architectural contradictions. AXI (Advanced eXtensible Interface, AXI) is a bus protocol, which is a kind of on-chip bus oriented to high performance, high bandwidth and low latency. AXI bus as the mainstream interconnection protocol in the field of high-performance computing, its core features include: address / control and data channels are separated, supporting independent pipeline operation; separate read / write data channels (Read / Write Data Separation) in burst transfer mode; support Outstanding transmission (multiple address concurrent access) and out-of-order data return (Out-of-Order Completion). SUMMARY

[0004] The present disclosure provides a method and device for accessing asymmetric capacity memory, a chip and an electronic device, which solves the problem of strict limitation of DDR memory on DRAM particle capacity and bit width in the prior art, resulting in low utilization of DRAM particle resources and high system cost.

[0005] In a first aspect, the present disclosure provides a method for accessing a non-symmetrical capacity memory. The method comprises: receiving a memory access request from a host device; performing a memory access judgment based on the memory access request and a preset address line of the memory; if an address of the memory access request is within a non-symmetrical memory capacity range, performing a conversion on the memory access request based on a set conversion rule to obtain a converted memory access request; and accessing the memory according to the converted memory access request to perform a corresponding access operation.

[0006] In an implementation form of the first aspect, the memory access judgment based on the memory access request and the preset address line of the memory comprises: if the address of the memory access request is greater than or equal to the preset address line, determining that the address of the memory access request is within the non-symmetrical memory capacity range; and if the address of the memory access request is less than the preset address line, determining that the address of the memory access request is within a symmetrical memory capacity range.

[0007] In an implementation form of the first aspect, the method further comprises: if the address of the memory access request is within the symmetrical memory capacity range, directly accessing the memory according to the memory access request without conversion according to the set conversion rule.

[0008] In an implementation form of the first aspect, the memory access request comprises a write access and a read access, the write access comprises a write command and write data, and the read access comprises a read command and read data.

[0009] In an implementation form of the first aspect, when the memory access request is the write access, the conversion on the memory access request based on the set conversion rule to obtain the converted memory access request comprises: converting the write command in the memory access request based on the set conversion rule to obtain a converted write command; converting the write data in the memory access request based on the set conversion rule to obtain converted write data; and taking the converted write command and the converted write data as the converted memory access request.

[0010] In an implementation form of the first aspect, the write command comprises a write address, a write data length and a write data bit width, and the converting the write command in the memory access request based on the set conversion rule to obtain a converted write command comprises: converting the write address in the memory access request based on the set conversion rule to obtain a converted write address; converting the write data length in the memory access request based on the set conversion rule to obtain a converted write data length; converting the write data bit width in the memory access request based on the set conversion rule to obtain a converted write data bit width; and taking the converted write address, the converted write data length and the converted write data bit width as the converted write command.

[0011] In an implementation form of the first aspect, the converting the write address in the memory access request based on the set conversion rule to obtain a converted write address comprises: obtaining a converted write address of a converted memory access request by: converted write address of the converted memory access request = ((write address of the memory access request - preset address line) << 1) + preset address line.

[0012] In an implementation form of the first aspect, when the memory access request is a read access, the converting the memory access request based on the set conversion rule to obtain a converted memory access request comprises: converting a read command in the memory access request based on the set conversion rule to obtain a converted read command; and taking the converted read command as the converted memory access request.

[0013] In an implementation form of the first aspect, the write command comprises a write address, a write data length and a write data bit width, and the converting the write command in the memory access request based on the set conversion rule to obtain a converted write command comprises: converting the write address in the memory access request based on the set conversion rule to obtain a converted write address; converting the write data length in the memory access request based on the set conversion rule to obtain a converted write data length; converting the write data bit width in the memory access request based on the set conversion rule to obtain a converted write data bit width; and taking the converted write address, the converted write data length and the converted write data bit width as the converted write command.

[0014] In an implementation form of the first aspect, the converting the read address in the memory access request based on the set conversion rule to obtain a converted read address comprises: obtaining the converted read address of the memory access request by: converted read address of the memory access request = ((read address of the memory access request - preset address line) << 1) + preset address line.

[0015] In an implementation form of the first aspect, the accessing the memory according to the converted memory access request to perform a corresponding access operation comprises: when the memory access request is a write access, accessing the memory according to the converted write access to perform a corresponding write access operation; or when the memory access request is a read access, accessing the memory according to the converted read access to perform a corresponding read access operation.

[0016] In an implementation form of the first aspect, the accessing the memory according to the converted read access to perform a corresponding read access operation comprises: accessing the memory according to the converted read access to obtain corresponding read data in the memory; and converting the read data based on the set conversion rule to obtain converted read data.

[0017] In a second aspect, the disclosure provides a device for accessing an asymmetric capacity memory. The device comprises: a receiving module configured to receive a memory access request from a host device; a judging module configured to perform a memory access judgment based on the memory access request and a preset address line of the memory; a converting module configured to, if an address of the memory access request is within an asymmetric memory capacity range, convert the memory access request based on a set conversion rule to obtain a converted memory access request; and an access control module configured to access the memory according to the converted memory access request to perform a corresponding access operation.

[0018] In an implementation form of the second aspect, the converting module is further configured to, if an address of the memory access request is within a symmetric memory capacity range, directly access the memory according to the memory access request without conversion according to the set conversion rule to perform a corresponding access operation.

[0019] In an implementation form of the second aspect, the conversion module comprises: a write access conversion unit, configured to: convert a write command in the memory access request based on the set conversion rule to obtain a converted write command; convert write data in the memory access request based on the set conversion rule to obtain converted write data; take the converted write command and the converted write data as the converted memory access request; and access the memory according to the converted memory access request to perform a corresponding write access operation; and a read access conversion unit, configured to: convert a read command in the memory access request based on the set conversion rule to obtain a converted read command; take the converted read command as the converted memory access request; and access the memory according to the converted memory access request to perform a corresponding read access operation.

[0020] In a third aspect, the present disclosure provides a chip. The chip comprises: one or more master devices; a memory having an asymmetric capacity; an apparatus according to the above-mentioned apparatus, electrically coupled to the one or more master devices via an AXI bus; and a DDR controller electrically coupled between the apparatus and the memory and configured to convert an AXI bus interface protocol into a DFI interface protocol.

[0021] In a fourth aspect, the present disclosure provides an electronic device. The electronic device comprises: a memory configured to store executable programs or data; and at least one processor electrically coupled to the memory and configured to execute the programs or data to perform the method according to the above-mentioned method.

[0022] According to the embodiments of the present disclosure, the conversion module Axisplit can support memories with non-power-of-two DDR capacities (for example, 384 / 768 / 1536 / 3072 MB, etc.), fully utilize various DDR particle resources, and save the cost of memory particles. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A structural schematic diagram of an AXI bus protocol conversion apparatus according to an embodiment of the present disclosure is shown.

[0024] Figure 2 A structural schematic diagram of a DRAM particle according to an embodiment of the present disclosure is shown.

[0025] Figure 3 A structural schematic diagram of an Axisplit module according to an embodiment of the present disclosure is shown.

[0026] Figure 4 A flowchart of a method for accessing a memory with an asymmetric capacity according to an embodiment of the present disclosure is shown.

[0027] Figure 5 A flowchart showing the Axisplit conversion module operating in mode 0 according to an embodiment of the present disclosure.

[0028] Figure 6 A flowchart showing the Axisplit conversion module operating in mode 1 according to an embodiment of the present disclosure.

[0029] Figure 7 A flowchart showing the Axisplit conversion module operating in mode 2 according to an embodiment of the present disclosure.

[0030] Figure 8 A flowchart showing the Axisplit conversion module operating in mode 3 according to an embodiment of the present disclosure.

[0031] Figure 9 A structural diagram of a device for accessing asymmetric capacity memory according to an embodiment of the present disclosure.

[0032] Figure 10 A structural diagram of a chip according to an embodiment of the present disclosure.

[0033] Figure 11 A structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The present disclosure will be described with specific reference to particular embodiments thereof, but it is to be understood that no limitation of the scope of the disclosure is intended thereby. Other advantages and benefits will also become apparent. The disclosure is intended to encompass all such alterations and modifications of the specific embodiments. The embodiments described herein are examples of one or more aspects of the present disclosure. Other embodiments are possible, and apparent to one skilled in the art, from this disclosure. Each of the embodiments described herein for a method, system, and apparatus can be used as or combined to produce a method, system, and apparatus in its various embodiments. A combination of embodiments illustrated in different embodiments herein can be combined.

[0035] It is to be understood that the drawings are designed solely for purposes of illustration. In reality, the components shown in the drawings can differ in shape, size and proportions from how they are depicted in the drawings and / or from what is described herein. Further, the preferred embodiments of the present disclosure can be carried out in a manner that differs from the illustrative embodiments without departing from the spirit and scope of the disclosure.

[0036] The embodiments of the present disclosure provide a scheme for accessing asymmetric capacity memory, which solves the problem of strict limitation of DDR memory on DRAM particle capacity and bit width in the prior art, resulting in low utilization of DRAM particle resources and high system cost.

[0037] The AXI bus protocol conversion device provided by the embodiments of the present disclosure can convert a standard AXI bus protocol into an AXI bus in a specific data format and output to a DDR controller, which can be compatible with the DDR controller. The DDR controller converts the input AXI data format into an interface behavior that can access an asymmetric capacity DRAM particle. For example, a DDR with a total capacity of 768 MB is composed of two 16-bit DRAM particles, one with a capacity of 512 MB and the other with a capacity of 256 MB, and the two particles are combined to form a DDR with a total bit width of 32 bits and a total capacity of 768 MB. The AXI bus protocol conversion device provided by the embodiments of the present disclosure can support more DDR capacities (not limited to the capacities of 256 / 512 / 1024 / 2048 / 4096 / 8192 MB listed above, but also support 384 / 768 / 1536 / 3072 MB, etc.), and can fully utilize various DDR particle resources and save the cost of memory particles. Axisplit has the characteristics of small area, low power consumption, easy porting, strong compatibility, support for 32-bit / 16-bit DDR bus bit width, support for various asymmetric capacities, and basically no influence on system performance.

[0038] In some embodiments, Axisplit can support non-power-of-two DDR memory capacities, support a DDR with a total bit width of 32 bits composed of two 16-bit DRAM particles with different capacities, and also support a DDR with a total bit width of 16 bits composed of two 8-bit DRAM particles with different capacities. When the input address of Axisplit is within the split address (such as DRAM particle regions 0 and 1), the entire DDR bit width is valid, and when the input address of Axisplit is greater than the split address, only half of the data bit width is valid and the other half is masked, thereby ensuring that all valid data are stored in the DRAM storage medium. This scheme can maximize the rational use of DRAM particles, especially for disassembly material recycling, saving memory costs.

[0039] Figure 1 The structure schematic diagram of the AXI bus protocol conversion device described in the embodiments of the present disclosure is shown. As Figure 1As shown, Axisplit acts as a bridge for internal CPU, DMA, and other Master devices to access DRAM. Its input AXI bus is connected to the system's Interconnect module, and its output is connected to the DDR Controller. The Axisplit module transforms the AXI address input from the Interconnect according to rules, and simultaneously transforms the data input from the AXI according to the format required by the DDR Controller. When the Master device accesses a DRAM memory address less than or equal to 512MB, both the high 16 bits and low 16 bits of the DRAM chip are valid and written to regions 0 and 1. When the Master device accesses a DRAM memory address exceeding 512MB, the high 16 bits are invalid (e.g., ...). Figure 1 The invalid region shown is 3), while all valid data is written to the lower 16 bits of the higher address space (e.g., Invalid region 3). Figure 1 (Region 2 of the DRAM shown).

[0040] Figure 2 The diagram shown is a structural schematic of a DRAM chip according to an embodiment of this disclosure. Figure 2 As shown, regions 0 / 1 / 2 are memory storage spaces composed of DRAM chips, while region 3 is empty and non-existent. Region 3 is shown in this disclosure to illustrate the difference between the asymmetric capacity chip structure and the symmetric capacity chip structure. Region 0+2 belongs to a 512MB chip, and region 1 is a 256MB chip. This division does not require a DDR controller; the user decides which chips to use. For example, two chips, 256MB and 128MB, can be used to form a 32-bit DRAM storage space, or a 1GB + 512MB configuration, etc. The overall chip address order is as described above. Figure 2 As shown, the address starts from 0x0000_0000 and increases upwards, with the last word address corresponding to region 2.

[0041] like Figure 2 As shown in the example diagram, a total of two 16-bit DRAM chips form a 32-bit DRAM storage space. The capacities of these two 16-bit chips are different, which is what this disclosure aims to express. Regions 0 and 2 form one chip with a total capacity of 512MB. The other chip is region 1, with only 256MB. Region 3 does not exist. Traditional memory storage space capacity is symmetrical, with... Figure 2For example, it is required that both 16-bit memory particles are 512 MB. The present disclosure uses an Axisplit protocol conversion module to convert the standard AXI protocol into the specific input timing of the DDR controller, thereby enabling support for another architecture in which only one particle is 256 MB. For a CPU or other master device that needs to access the DDR particle memory, the read and write addresses issued to the DDR storage space are continuous. When the accessed address is below the split address line, the data is written to regions 0 and 1, and when the address exceeds the split address line, the data is only written to region 2, and not to region 3, because region 3 is an illegal non-existent storage space. The split address line is the boundary between regions 0 and 2 in the figure, that is, the 0x2000_0000 address (512 MB address).

[0042] The high 16 bits and the low 16 bits of the DRAM particle are both valid, where valid means that the two 16-bit DRAM particles can be used to store data. The two 16-bit DRAM particles can be spliced into a 32-bit DRAM particle, but one quarter of the storage space of the 32-bit DRAM particle does not exist and cannot be used to store data. After splicing, the address for accessing the DRAM is continuous from the perspective of the device accessing the DRAM, and the particles are also continuous in the address.

[0043] Regarding the high 16 bits of the data, the input interface of the DRAM particle has a DM[1:0] signal (data mask) that masks the high 16-bit data to become invalid data, and the truly valid data is all mapped to region 2 after processing by the Axisplit.

[0044] Regarding the high address space of the low 16 bits, the storage space exceeding the split address line (0x2000_0000 address) is region 2 in Figure 2 The storage space exceeding the split address is all asymmetric storage space.

[0045] Figure 3 A structure diagram of the Axisplit module according to the embodiment of the present disclosure is shown. As shown in Figure 3 , the Axisplit is internally composed of two modules, an axi_write_split module (write access conversion module) and an axi_read_split module (read access conversion module).

[0046] The role of the axi_write_split module is to transform the input AXI write command and data, so that the output AXI behavior can be recognized by the DDR Controller, and the write operation of the asymmetric DRAM is correctly accessed.

[0047] The axi_read_split module contains a read command FIFO with a depth of 32, which is used to buffer read commands. The role of the axi_read_split module is to transform the input AXI read command, so that the output AXI read command can be recognized by the DDR Controller, and the read operation of the asymmetric DRAM is correctly accessed. At the same time, the read data returned by the DDR Controller can be correctly spliced, and finally returned to the Master device through the Interconnect.

[0048] The Interconnect module is used to connect and manage multiple AXI Master and Slave devices to realize flexible system topology; the Axisplit module is used to convert the input AXI protocol to an AXI protocol that can access asymmetric capacity DRAM particles; the DDR Controller module is used to connect the AXI Master (such as CPU, GPU, etc.) and the control module of the DDR memory, which is responsible for converting the AXI protocol into the access protocol of the DDR memory, and managing the scheduling, efficiency and stability of data transmission. The DDRPHY module represents the DDR Physical Layer Interface in AXI, which is a key module connecting the DDR Controller and the DDR memory particles, responsible for converting high-level protocols (such as DFI) into low-level electrical signals of DDR memory, and ensuring the reliability and efficiency of data transmission.

[0049] The input and output of the Axisplit module in the embodiments of the present disclosure are AXI buses, independent of the DDR Controller and the DDR PHY. The Axisplit module is simple in design and easy to integrate, and supports asymmetric DDR grain capacity at a small area cost. Meanwhile, the Axisplit module supports a DDR memory system with a total bit width of 32 bits, which can be composed of two 16-bit DRAM grains with different capacities (different rows and the same column). The software can be configured to select whether the 16-bit grain with a smaller capacity is in the high 16 bits or the low 16 bits. The Axisplit module also supports a DDR memory system with a total bit width of 16 bits, which can be composed of two 8-bit DRAM grains with different capacities (different rows and the same column). The software can be configured to select whether the 8-bit grain with a smaller capacity is in the high 8 bits or the low 8 bits. The Axisplit module in the present disclosure can support different types of DDR grains, such as DDR2, DDR3, DDR4, and LPDDR2 / 3 / 4. The present disclosure is not limited in this regard.

[0050] The embodiments of the present disclosure provide a method for accessing asymmetric capacity memory, which can be applied to AXI conversion of the Axisplit module. In the method, the standard AXI bus protocol is converted into AXI bus output in a specific data format to the DDR Controller, which can be compatible with the DDR Controller. The DDR Controller converts the input AXI data format into an interface behavior capable of accessing the asymmetric capacity DRAM grain.

[0051] The technical solutions in the embodiments of the present disclosure will be described in detail below with reference to the drawings in the embodiments of the present disclosure.

[0052] Figure 4 A flowchart of the method for accessing asymmetric capacity memory according to the embodiments of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the method for accessing asymmetric capacity memory according to the embodiments of the present disclosure includes the following steps S1-S4. Figure 4

[0053] In step S1, a memory access request from a host device is received. In some embodiments, the memory access request is an AXI protocol. In some embodiments, the memory access request includes write access and read access, the write access includes a write command and write data, and the read access includes a read command and read data.

[0054] In some embodiments, the host device includes but is not limited to a CPU, a DMA, a GPU, and a DPU. The host device is not limited to one, and there can be multiple host devices. The memory access request is not limited to one, and there can be multiple memory access requests, each of which performs AXI conversion without affecting each other. ​

[0055] Step S2, judging the memory access request based on the preset address line of the memory. In some embodiments, the preset address line of the memory is a split address line of the memory configured by a register. The split address line can divide the memory into two parts, one part is a symmetric storage particle and the other part is an asymmetric storage particle. The split address line is divided by a user according to actual needs.

[0056] In an embodiment of the present disclosure, the step of judging the memory access request based on the preset address line of the memory includes steps S21-S22.

[0057] Step S21, if the address of the memory access request is greater than or equal to the preset address line, it is determined that the address of the memory access request is in the asymmetric memory capacity range.

[0058] In some embodiments, if the address of the memory access request is in the asymmetric memory capacity range, the memory access request is converted according to the set conversion rule to access the memory.

[0059] Step S22, if the address of the memory access request is less than the preset address line, it is determined that the address of the memory access request is in the symmetric memory capacity range.

[0060] In an embodiment of the present disclosure, if the address of the memory access request is in the symmetric memory capacity range, the memory is directly accessed according to the memory access request without conversion according to the set conversion rule.

[0061] In some embodiments, when the storage address of the memory is less than the preset address line, the storage space is symmetric, indicating that the storage space can be directly accessed. When the address of the memory access request is less than the preset address line, it is determined that the address of the memory access request is in the symmetric memory capacity range. The memory access request can directly access the memory without conversion according to the set conversion rule. When the storage address of the memory is greater than or equal to the preset address line, the storage space is asymmetric, indicating that the storage space cannot be directly accessed. When the address of the memory access request is greater than or equal to the preset address line, it is determined that the address of the memory access request is in the asymmetric memory capacity range. The memory access request cannot directly access the memory and needs to be converted into an access request that can directly access the memory, that is, the memory access request is converted according to the set conversion rule to access the memory.

[0062] Step S3, if the address of the memory access request is in the asymmetric memory capacity range, converting the memory access request based on a set conversion rule to obtain a converted memory access request. In some embodiments, the converted memory access request is an AXI protocol that can access the memory.

[0063] In an embodiment of the present disclosure, when the memory access request is a write access, converting the memory access request based on a set conversion rule to obtain a converted memory access request includes the following steps S31A-S33A.

[0064] Step S31A, converting a write command in the memory access request based on the set conversion rule to obtain a converted write command.

[0065] Step S32A, converting write data in the memory access request based on the set conversion rule to obtain converted write data.

[0066] Step S33A, taking the converted write command and the converted write data as the converted memory access request.

[0067] In an embodiment of the present disclosure, the write command includes a write address, a write data length, and a write data bit width, and converting a write command in the memory access request based on the set conversion rule to obtain a converted write command includes the following steps S311A-S314A.

[0068] Step S311A, converting a write address in the memory access request based on the set conversion rule to obtain a converted write address.

[0069] Step S312A, converting a write data length in the memory access request based on the set conversion rule to obtain a converted write data length.

[0070] Step S313A, converting a write data bit width in the memory access request based on the set conversion rule to obtain a converted write data bit width.

[0071] Step S314A, taking the converted write address, the converted write data length, and the converted write data bit width as the converted write command.

[0072] In an embodiment of the present disclosure, converting a write address in the memory access request based on the set conversion rule to obtain a converted write address includes obtaining the write address of the converted memory access request by the following formula:

[0073] The converted memory access request write address = ((the memory access request write address - the preset address line) << 1) + the preset address line.

[0074] In an embodiment of the present disclosure, when the memory access request is a read access, converting the memory access request based on the set conversion rule to obtain a converted memory access request includes the following steps S31B-S32B.

[0075] Step S31B, converting the read command in the memory access request based on the set conversion rule to obtain a converted read command.

[0076] Step S32B, taking the converted read command as the converted memory access request.

[0077] In an embodiment of the present disclosure, the read command includes a read address, a read data length, and a read data bit width, and converting the read command in the memory access request based on the set conversion rule to obtain a converted read command includes the following steps S311B-S314B.

[0078] Step S311B, converting the read address in the memory access request based on the set conversion rule to obtain a converted read address.

[0079] Step S312B, converting the read data length in the memory access request based on the set conversion rule to obtain a converted read data length.

[0080] Step S313B, converting the read data bit width in the memory access request based on the set conversion rule to obtain a converted read data bit width.

[0081] Step S314B, taking the converted read address, the converted read data length, and the converted read data bit width as the converted read command.

[0082] In an embodiment of the present disclosure, converting the read address in the memory access request based on the set conversion rule to obtain a converted read address includes obtaining the converted memory access request read address by the following formula:

[0083] The converted memory access request read address = ((the memory access request read address - the preset address line) << 1) + the preset address line.

[0084] Then, in step S4, the memory is accessed according to the converted memory access request to perform a corresponding access operation.

[0085] In an embodiment of the present disclosure, accessing the memory according to the converted memory access request to perform a corresponding access operation includes the following steps S41-S42.

[0086] In step S41, when the memory access request is a write access, the memory is accessed according to the converted write access to perform a corresponding write access operation.

[0087] In step S42, when the memory access request is a read access, the memory is accessed according to the converted read access to perform a corresponding read access operation.

[0088] It should be noted that in the embodiments of the present disclosure, steps S41 and S42 are two independent steps, and do not affect each other, and can be performed simultaneously.

[0089] In an embodiment of the present disclosure, accessing the memory according to the converted read access to perform a corresponding read access operation includes the following steps S421-S422.

[0090] In step S421, the memory is accessed according to the converted read access to obtain read data in the memory.

[0091] In step S422, the read data is converted according to the set conversion rule to obtain converted read data, and the converted read data is taken as an access result of the memory.

[0092] In an embodiment of the present disclosure, the method can further include step S5: if the memory access request can access the memory, accessing the memory according to the memory access request to perform a corresponding access operation.

[0093] According to the embodiments of the present disclosure, the scheme for accessing asymmetric capacity memory solves the problem in the prior art that DDR memory has strict restrictions on DRAM particle capacity and bit width, resulting in low utilization of DRAM particle resources and high system cost. In addition, the AXI bus protocol conversion module Axisplit provided by the embodiments of the present disclosure can support more memory with DDR capacity (for example, non-power-of-two DDR capacity), can fully utilize various DDR particle resources, and save memory particle cost. In addition, the Axisplit conversion module has the characteristics of small area, low power consumption, easy porting, strong compatibility, support for 32bit / 16bit DDR bus bit width, support for various asymmetric capacities, and basically no influence on system performance.

[0094] Specifically, in some embodiments, the memory in the present disclosure is an off-chip DRAM memory particle, and the present disclosure is a specific AXI interface timing converted from the AXI protocol to the input of the DDR controller, so that the controller can support the storage structure of the asymmetric DDR particle. That is, the present disclosure is AXI protocol to AXI protocol. At the same time, the read access and the write access in the present disclosure are completely independent access processes and do not affect each other, and can be performed at the same time.

[0095] In the following embodiments, the signal with the suffix _m is recorded as the signal of the Master port of the Axisplit, which is connected with the system interconnection bus Interconnect. The signal with the suffix _s is recorded as the signal of the Slave port of the Axisplit, which is connected with the DDR Controller.

[0096] In some embodiments, when the input read or write command is valid and the DDR controller interfaced with the Axisplit can receive the read or write command converted by the Axisplit, it is judged whether the input read or write address exceeds the spaddr address, and the signal bypass_split is used to indicate whether the access is within the spaddr preset address split line range of the DRAM.

[0097] bypass_split=1: indicates that the read or write access address is within the spaddr range, and all AXI interface signals are directly transmitted to the DDR controller.

[0098] bypass_split=0: indicates that the read or write access address exceeds the spaddr range, and part of the AXI interface signals input to the Axisplit module need to be transformed.

[0099] The transformation of the main signals of the AXI output interface is as follows:

[0100] For the read or write address signal, when the read or write address (awaddr_m / araddr_m) input to the Axisplit does not exceed the split address line, the relationship between the output address (awaddr_s / araddr_s) and the input address satisfies the following formula (1).

[0101] Formula (1)

[0102] When the read or write address (awaddr_m / araddr_m) input to the Axisplit exceeds the split address line, the relationship between the output address (awaddr_s / araddr_s) and the input address satisfies the following formula (2).

[0103] Formula (2)

[0104] spaddr is the split address of the register configuration, awaddr_m represents the write address of the input Axisplit, araddr_m represents the read address of the input Axisplit, awaddr_s represents the write address of the Axisplit output, and araddr_s represents the read address of the Axisplit output.

[0105] For the input awsize_m / arsize_m, the conversion process is as follows: the output awsize_s=3'b100, arsize_s=3'b100, that is, regardless of the input awsize_m and arsize_m, the output is processed according to the bit width of 128 bits. awsize_m represents the width of each data transmission in the write operation of the input Axisplit, that is, the write data bit width, arsize_m represents the width of each data transmission in the read operation of the input Axisplit, that is, the read data bit width. awsize_s represents the width of each data transmission in the write operation of the Axisplit output, that is, the converted write data bit width, and arsize_s represents the width of each data transmission in the read operation of the Axisplit output, that is, the converted read data bit width.

[0106] For the output AXI transmission length awlen_s / arlen_s signal, the conversion is as follows:

[0107] When bypass_split=1: awlen_s / arlen_s is equal to the input transmission length awlen_m / arlen_m.

[0108] When bypass_split=0: at this time, the access address exceeds the spaddr address, and awlen_s / arlen_s is related to the AXI input awsize_m / arsize_m and awlen_m / arlen_m.

[0109] ①awlen_m / arlen_m=0, then awlen_s / arlen_s=0, that is, the converted read transmission length only needs 1 beat.

[0110] ②If awlen_m / arlen_m is greater than 0 and awsize_m / arsize_m=0, then the value of awlen_s / arlen_s can be calculated in the following way (take the write awlen_s as an example for description, the read arlen_s is similar to awlen_s, and will not be described in detail here):

[0111] for(i=0;i<awlen_m;i=i+1) begin

[0112] if(((start_addr+i&4’hf)==4’h7) || ((start_addr+i&4’hf)==4’hf))

[0113] awlen_s=awlen_s+1;

[0114] end

[0115] wherein start_addr is the burst start address after transmitting the lower 4 bits of the input address aligned to size.

[0116] ③If awlen_m / arlen_m is greater than 0 and awsize_m / arsize_m=1, the value of awlen_s / arlen_s can be calculated in the following way (take write awlen_s as an example, the read arlen_s is similar to write awlen_s, which will not be described in detail here) :

[0117] for(i=0;i<awlen_m;i=i+1) begin

[0118] if(((start_addr+(i<<1)&4’hf)==4’h6) || ((start_addr+(i<<1)&4’hf)==4’he))

[0119] awlen_s=awlen_s+1;

[0120] end

[0121] ④If awlen_m / arlen_m is greater than 0 and awsize_m / arsize_m=2, the value of awlen_s / arlen_s can be calculated in the following way (take write awlen_s as an example, the read arlen_s is similar to write awlen_s, which will not be described in detail here) :

[0122] for(i=0;i<awlen_m;i=i+1) begin

[0123] if(((start_addr+(i<<2)&4’hf)==4’h4) || ((start_addr+(i<<2)&4’hf)==4’hc))

[0124] awlen_s=awlen_s+1;

[0125] end

[0126] ⑤If awsize_m is equal to 3, awlen_s / arlen_s = awlen_m / arlen_m.

[0127] ⑥If awsize_m is equal to 4, the value of awlen_s / arlen_s can be calculated in the following way (take the write awlen_s as an example, the read arlen_s is similar to the write awlen_s, and is not described in detail here) :

[0128] awlen_s = ((awlen_m « 1) + 4'h1) - {3'b0, awaddr_m[3]}.

[0129] awlen_m represents the length of each data transmission in the write operation input to Axisplit, i.e., the write data length; arlen_m represents the length of each data transmission in the read operation input to Axisplit, i.e., the read data length; awlen_s represents the length of each data transmission in the write operation output from Axisplit, i.e., the converted write data length; arlen_s represents the length of each data transmission in the read operation output from Axisplit, i.e., the converted write / read data length.

[0130] For write data wdata conversion, the input data is wdata_m, and the output converted data is wdata_s.

[0131] When bypass_split = 1: wdata_s = wdata_m.

[0132] When bypass_split = 0: it indicates that the address of the write DDR has exceeded the spaddr address, at which time wdata_s is converted as follows:

[0133] First step: accumulate and merge the input data first to obtain intermediate data wdata_tmp, the process is as follows.

[0134] If awsize_m is less than 4 (i.e., the input AXI transmission size is less than 128 bits), in the case of valid input data (wvalid_m = 1, wready_m = 1), wdata_tmp[127:0] = (wdata_m[127:0] | wdata_m_reg[127:0]), where wdata_m_reg[127:0] is the data cached for one beat of wdata_tmp[127:0]. When the data cached by wdata_m_reg[63:0] or wdata_m_reg[127:64] is full, it needs to be cleared to 0 in the next clock cycle in order to store the next converted data.

[0135] If awsize_m is equal to 4, wdata_tmp[127:0] = wdata_m[127:0] when input data is valid (wvalid_m = 1, wready_m = 1).

[0136] When input data is invalid, i.e. wvalid_m & wready_m = 0, wdata_tmp[127:0] needs to be kept, wdata_tmp[127:0] = wdata_m_reg[127:0].

[0137] Second step: split wdata_tmp[127:0] into two parts, high 64 bits and low 64 bits, and send the 64-bit low or high data to wdata_next[63:0] in turn.

[0138] Third step: recombine wdata_next[63:0] according to the data bit width mode (there are four working modes in total, which are working modes 0 / 1 / 2 / 3, please refer to Figures 5-8 These working modes), to get the final output data wdata_s[127:0]. The data recombination process is as follows:

[0139] if (split_mode[1] == 1'b0)

[0140] for (i = 0; i < 4; i = i + 1) begin

[0141] if (split_mode[0] == 1'b0)

[0142] wdata_s[32*i+ : 16] = wdata_next[16*i+ : 16]; / / mode 0

[0143] else

[0144] wdata_s[32*i+31- : 16] = wdata_next[16*i+ : 16]; / / mode 1

[0145] end

[0146] else begin

[0147] for (i = 0; i < 8; i = i + 1) begin

[0148] if (split_mode[0] == 1'b0)

[0149] wdata_s[16*i+15-:8]=wdata_next[8*i+:8]; / / mode 3

[0150] else

[0151] wdata_s[16*i+15-:8]=wdata_next[8*i+:8]; / / mode 3

[0152] end

[0153] wdata_m represents the write operation data input to Axisplit, i.e. the write data; wdata_s represents the write operation data output from Axisplit, i.e. the converted write data.

[0154] The conversion of the write wstrb is exactly the same as the conversion of the write data, except that the signal bit width is different. The input is wstrb_m, and the converted data output is wstrb_s. This will not be described again here.

[0155] wstrb represents the write byte enable signal, wstrb_m represents the write byte enable signal input to Axisplit, and wstrb_s represents the write byte enable signal output from Axisplit.

[0156] In an embodiment, the conversion of read data rdata_s to rdata_m.

[0157] When the DDR Controller reads data back from the DRAM, it is transmitted to the Axisplit module through AXI data rdata_s. Axisplit needs to convert rdata_s to obtain rdata_m, and finally returns it to the Master device through the bus interconnection unit Interconnect.

[0158] rdata_s represents the read data input to Axisplit; rdata_m represents the read operation data output from Axisplit, i.e. the converted read data.

[0159] The axi_read_split read access conversion module is responsible for converting rdata_s to rdata_m, and the conversion process is just the opposite of the write data conversion process of the axi_write_split write access conversion module.

[0160] According to the configured data bit width mode, the data corresponding to the bit position of rdata_s[127:0] is taken out and placed in an intermediate signal rdata_next.

[0161] if(split_mode[1]==1’b0)

[0162] for(i=0;i<4;i=i+1) begin

[0163] if(split_mode[0]==1'b0)

[0164] rdata_next[16*i+:16]=rdata_s[32*i+:16]; / / mode 0

[0165] else

[0166] rdata_next[16*i+:16]=rdata_s[32*i+31-:16]; / / mode 1

[0167] end

[0168] else begin

[0169] for(i=0;i<8;i=i+1) begin

[0170] if(split_mode[0]==1'b0)

[0171] rdata_next[8*i+:8]=rdata_s[16*i+:8]; / / mode 2

[0172] else

[0173] rdata_next[8*i+:8]=rdata_s[16*i+15-:8]; / / mode 3

[0174] end

[0175] end

[0176] Put the 64-bit rdata_next data in order to the low 64 bits and high 64 bits of rdata_m, whether to put high 64 bits first or low 64 bits first depends on whether the lowest 4 bits of the address of the read command starts to exceed 8, if it exceeds 8, then put rdata_next to rdata_m[127:64] first, then put rdata_next to rdata_m[63:0] when the next data is valid, so as to splice a complete 128-bit rdata_m data.

[0177] In some embodiments, considering a more general case, the DRAM adopts M capacity, X bit width particles and N capacity, X bit width particles (M>N). Here, M is greater than N, which must be 2 times N. The bit width of the two particles is equal. When the CPU or other master device accesses the DRAM, the address range is 0~M, the data bit width is 2X, at this time the DRAM particle capacity is symmetrical, the high X bit and the low X bit are both valid data, which can be written or read out from the DRAM. When the address range of the DRAM is M~M+N-1, the valid data bit width becomes X bit, which is reduced by half, and the data is all written to the particle with larger capacity. M represents the storage capacity of a storage particle, X represents the bit width of a storage particle, and N represents the storage capacity of another storage particle.

[0178] The Axisplit conversion module provided by the present disclosure supports the following four working modes.

[0179] Figure 5 The flowchart of the Axisplit conversion module working in mode 0 is shown in the embodiment of the present disclosure, and the data format corresponding relationship of the 32-bit DRAM data bit width in working mode 0 is shown in Table 1A to Table 1C. As shown in Table 1A to Table 1C, Figure 5 for mode 0, the data bit width of the DDR storage system is 32 bits, the DDR controller and the DDR PHY work in 32-bit mode, and the 2 16-bit DRAM particles form a 32-bit DRAM storage system, wherein the particle capacity of the low 16 bits is twice the capacity of the high 16 bits. As shown in the following mode 0 storage structure, here taking a total capacity of 768MB as an example for illustration, other capacities are also supported, and this is not limited. Figure 5

[0180] For a traditional symmetrical DRAM capacity storage system, the regions 0 / 1 / 2 / 3 are all valid storage spaces, and if the DDR PHY writes 32-bit valid data to the DRAM particle, the written data will be simultaneously stored in the 32-bit storage unit composed of regions 0 / 1 or the 32-bit storage unit composed of regions 2 / 3. When the DDR PHY reads 32-bit data from the DRAM particle, the data of the 32-bit storage unit composed of regions 0 / 1 or the 32-bit storage unit composed of regions 2 / 3 will be returned to the DDR PHY at the same time. Figure 5 For the asymmetric DRAM capacity storage system in the present disclosure, an Axisplit working register needs to be configured before working: split address register (upper 32 bits) and split data register (lower 32 bits). The split address register is used to store the split address, and the split data register is used to store the split data.

[0181] Figure 5 ​​The split address line). When the AXI read or write address input by Axisplit is less than the split address line, both region 0 and 1 can write or read data; when the AXI read or write address input by Axisplit is greater than the split address line, the data originally written or read in region 3 is mapped to region 2 by Axisplit, ensuring that no data is lost.

[0182] The data format correspondence between the above Figure 5 , ② (DDR Controller AXI input interface), ③ (DFI interface) and ④ (DRAM interface) is shown in Tables 1A to 1C.

[0183] Table 1A shows the AXI input data format of the DDR Controller in Figure 5 Table 1B shows the DFI interface output data format of the DDR Controller in Figure 5 Table 1C shows the DRAM interface input data format in Figure 5

[0184]

[0185] Table 1A

[0186]

[0187] Table 1B

[0188]

[0189] Table 1C

[0190] As can be seen from the above Tables 1A to 1C, when the address accessed by the CPU or other master device to the DRAM exceeds the split address line of the Axisplit module, the DRAM bit width changes from 32 bits to only the low 16 bits (byte 0 and 1 of the ④ DRAM interface), and the high 16 bits are all masked as invalid data. To ensure that all valid data is written to the low 16-bit DRAM grain, the AXI behavior of the DDR Controller needs to be changed, that is, the Axisplit module is used to change the standard AXI bus protocol, so that the output data is all placed in A0 / B0 / E0 / F0 / I0 / J0 / M0 / N0 of beat 0 of the DDR Controller and A1 / B1 / E1 / F1 / I1 / J1 / M1 / N1 of beat 1 of the DDR Controller, and the other positions are all invalid data. In this way, the mapping to the DRAM interface can ensure that all valid data is in the low 16-bit DRAM grain. ​

[0191] Figure 6 Figure 2A to Figure 2C show the data format corresponding relationship between the DDR Controller and the DRAM interface in the mode 1 of the Axisplit conversion module. Figure 6 As shown in Figure 2A to Figure 2C, for mode 1, the data bit width of the DDR storage system is 32 bits, the DDR Controller and the DDR PHY work in 32-bit mode, and two 16-bit DRAM particles form a 32-bit DRAM storage system, wherein the capacity of the high 16-bit particle is twice that of the low 16-bit particle. As shown below Figure 6 The storage structure of mode 1 is shown in the following table. Here, the total capacity is taken as an example of 768 MB, and other capacities are also supported, and this is not limited thereto.

[0192] In the above Figure 6 , the data format corresponding relationship between ②, ③ and ④ (DRAM interface) is shown in the following table 2A to table 2C.

[0193] Table 2A shows the AXI input data format of the DDR Controller in Figure 6 Table 2B shows the DFI interface output data format of the DDR Controller in Figure 6 Table 2C shows the DRAM interface input data format in Figure 6 .

[0194]

[0195] Table 2A

[0196]

[0197] Table 2B

[0198]

[0199] Table 2C

[0200] As can be seen from Table 2A to Table 2C above, when the address accessed by the CPU or the like main device to the DRAM exceeds the split address of the Axisplit module, the DRAM bit width changes from 32 bits to only the high 16 bits (④DRAM interface byte2 and 3), and the low 16 bits are all masked as invalid data. To ensure that all valid data is written into the DRAM grain of the high 16 bits, the AXI behavior of the DDR Controller needs to be transformed, that is, the Axisplit module is used to transform the standard AXI bus protocol, so that the data output is all placed in C0 / D0 / G0 / H0 / K0 / L0 / O0 / P0 of beat 0 of the DDR Controller and C1 / D1 / G1 / H1 / K1 / L1 / O1 / P1 of beat 1 of the DDR Controller, and the other positions are invalid data. In this way, the mapping to the DRAM interface can ensure that all valid data is in the DRAM grain of the high 16 bits.

[0201] Figure 7 The flowchart of the Axisplit conversion module working in mode 2 according to the embodiments of the present disclosure is shown, and Table 3A to Table 3C show the data format corresponding relationship of the 32-bit DRAM data bit width in working mode 2 according to the embodiments of the present disclosure. As shown in Table 3A to Table 3C, Figure 7 , the data bit width of the DDR storage system is 16 bits, and the DDR Controller and the DDR PHY work in 16-bit mode, 2 8-bit DRAM grains form a 16-bit DRAM storage system, and the capacity of the low 8-bit grain is twice that of the high 8-bit grain. As shown below Figure 7 , the storage structure in mode 2, here taking a total capacity of 768MB as an example for description, and other capacities are also supported.

[0202] In the above Figure 7 , the data format corresponding relationship between ②, ③ and ④ (DRAM interface) is shown in Table 3A to Table 3C.

[0203] Table 3A shows the AXI input data format of the DDR Controller in Figure 7 . Table 3B shows the DFI interface output data format of the DDR Controller in Figure 7 . Table 3C shows the DRAM interface input data format in Figure 7 .

[0204]

[0205] Table 3A

[0206]

[0207] Table 3B

[0208]

[0209] Table 3C

[0210] As shown in the above Tables 3A to 3C, when the address accessed by the CPU or the like to the DRAM exceeds the split address of the Axisplit module, the DRAM bit width is changed from 16 bits to only the low 8 bits (byte0 of the DRAM interface), and the high 8 bits are all masked as invalid data. To ensure that all valid data is written into the DRAM grain of the low 8 bits, the AXI behavior of the DDR Controller needs to be changed, that is, the Axisplit module is used to transform the standard AXI bus protocol, so that the output data is all placed in A0 / C0 / E0 / G0 / I0 / K0 / M0 / O0 of beat 0 of the DDR Controller and A1 / C1 / E1 / G1 / I1 / K1 / M1 / O1 of beat 1 of the DDR Controller, and the other positions are all invalid data. In this way, the mapping to the DRAM interface can ensure that all valid data is in the DRAM grain of the low 8 bits.

[0211] Figure 8 The flowchart shown in Figure 4A to 4C shows the working mode of the Axisplit module according to the embodiment of the present disclosure. As shown in Figure 4A to 4C, the data bit width of the DDR storage system is 16 bits, and the DDR Controller and the DDR PHY work in 16-bit mode, 2 8-bit DRAM grains form a 16-bit DRAM storage system, and the grain capacity of the high 8 bits is twice that of the low 8 bits. Figure 8 Figure 8 As shown in the mode 3 storage structure, a total capacity of 768 MB is taken as an example for illustration, and other capacities are also supported.

[0212] In the above Figure 8 , the data format corresponding relationship between ②, ③ and ④ (DRAM interface) is shown in Tables 4A to 4C.

[0213] Table 4A shows the AXI input data format of the DDR Controller in Figure 8 Table 4B shows the DFI interface output data format of the DDR Controller in Figure 8 Table 4C shows the DRAM interface input data format in Figure 8 .

[0214] ​

[0215] Table 4A

[0216]

[0217] Table 4B

[0218]

[0219] Table 4C

[0220] As can be seen from the above Table 4A to Table 4C, when the address accessed by the CPU and the like main device to the DRAM exceeds the split address of the Axisplit module, the DRAM bit width is changed from 16 bits to only the high 8 bits (④ byte 1 of the DRAM interface), and the low 8 bits are all masked as invalid data. To ensure that all valid data is written into the DRAM particles of the high 8 bits, the AXI behavior of the DDR Controller needs to be transformed, that is, the Axisplit module is used to transform the standard AXI bus protocol, so that the output data is all placed in B0 / D0 / F0 / H0 / J0 / L0 / N0 / P0 of beat 0 and B1 / D1 / F1 / H1 / J1 / L1 / N1 / P1 of beat 1 of the DDR Controller, and the other positions are all invalid data. In this way, the mapping to the DRAM interface can ensure that all valid data is in the DRAM particles of the high 8 bits.

[0221] The input and output of the Axisplit conversion module in the embodiment of the present disclosure are all AXI buses, independent of the DDR Controller and the DDR PHY, simple in design and easy to integrate, and capable of supporting asymmetric DDR particle capacity at a small area cost; the Axisplit conversion module can support more content capacity, and reasonably use the DRAM particles to the greatest extent, especially for disassembling materials for recycling, saving memory cost, and solving the problem of low DRAM particle resource utilization and high system cost caused by the strict limitation of the DRAM particle capacity and bit width of the DDR memory in the prior art.

[0222] The protection scope of the method in the embodiment of the present disclosure is not limited to the execution order of the steps listed in the embodiment, and any scheme realized by adding, replacing or replacing steps of the prior art according to the principle of the present disclosure is included in the protection scope of the present disclosure.

[0223] The embodiment of the present disclosure also provides a device for accessing asymmetric capacity memory, which can implement the method of the present disclosure, but the implementation device of the method of the present disclosure includes but is not limited to the structure of the device listed in the embodiment, and any structure deformation and replacement of the prior art according to the principle of the present disclosure is included in the protection scope of the present disclosure.

[0224] As shown in Figure 9 the embodiment, an apparatus for accessing asymmetric memory capacity is provided. The apparatus 200 comprises a receiving module 210, a judging module 220, a converting module 230 and an access control module 240.

[0225] The receiving module 210 is configured to receive a memory access request from a host device.

[0226] The judging module 220 is configured to make a memory access judgment based on the memory access request and a preset address line of the memory.

[0227] The converting module 230 is configured to, if an address of the memory access request is within an asymmetric memory capacity range, convert the memory access request based on a set conversion rule to obtain a converted memory access request.

[0228] The access control module 240 is configured to access the memory according to the converted memory access request to perform a corresponding access operation.

[0229] In an embodiment of the disclosure, the converting module 230 is further configured to, if an address of the memory access request is within a symmetric memory capacity range, directly access the memory according to the memory access request without conversion according to the set conversion rule to perform a corresponding access operation.

[0230] As shown in Figure 9 the embodiment, the converting module 230 comprises a write access conversion unit 231 and a read access conversion unit 232.

[0231] The write access conversion unit 231 is configured to: convert a write command in the memory access request based on the set conversion rule to obtain a converted write command; convert write data in the memory access request based on the set conversion rule to obtain converted write data; take the converted write command and the converted write data as the converted memory access request; and access the memory according to the converted memory access request to perform a corresponding write access operation.

[0232] The read access conversion unit 232 is configured to: convert a read command in the memory access request based on the set conversion rule to obtain a converted read command; take the converted read command as the converted memory access request; and access the memory according to the converted memory access request to perform a corresponding read access operation.

[0233] It should be noted that the functions or operations of the receiving module 210, the determining module 220, the conversion module 230, the access control module 240, and the write access conversion module 231 and the read access conversion module 232 in the conversion module 230 described in the embodiments of the present disclosure correspond one-to-one to the steps in the method for accessing the asymmetric capacity memory described above, and thus will not be described again here.

[0234] In several embodiments provided by the present disclosure, it should be understood that the disclosed system, device, or method can be implemented by other means. For example, the device embodiments described above are only illustrative, and for example, the division of the modules / units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed modules / units can be indirect coupling or communication connection through some interfaces, devices or modules / units, which can be electrical, mechanical or other forms.

[0235] The modules / units described as separate components can or can not be physically separated, and the components shown as modules / units can or can not be physical modules, i.e., can be located in one place or can be distributed on a plurality of network units. Part or all of the modules / units can be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, the functional modules / units in each embodiment of the present disclosure can be integrated in one processing module, or each module / unit can be physically present separately, or two or more modules / units can be integrated in one module / unit.

[0236] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0237] As Figure 10As shown, this disclosure provides a chip. The chip 300 includes one or more host devices 310, a memory 320 with asymmetric capacity, a means 200 for accessing the asymmetric capacity memory as described above, and a DDR controller 340. The means 200 is electrically coupled to the one or more host devices 310 via an AXI bus 330. Furthermore, the DDR controller 340 is electrically coupled between the means 200 and the memory 320 and is configured to convert the AXI bus interface protocol to the DFI interface protocol.

[0238] like Figure 11 As shown, this disclosure provides an electronic device. The electronic device 400 includes a memory 410 and at least one processor 420. The memory 410 is configured to store an executable program or data. The processor 420 is electrically coupled to the memory 410 and configured to execute the program or data to perform a method for accessing asymmetric capacity memory as described above.

[0239] This disclosure also provides a computer-readable and writable storage medium. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0240] The embodiments of the present disclosure can also provide a computer program product including one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions described in the embodiments of the present disclosure are generated in whole or in part. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer or data center to another website, computer or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner.

[0241] When the computer program product is executed by a computer, the computer executes the method described in the foregoing method embodiments. The computer program product can be a software installation package, and when the foregoing method needs to be used, the computer program product can be downloaded and executed on the computer.

[0242] To sum up, according to the method and device for accessing asymmetric capacity memory, the chip and the electronic equipment provided by the present disclosure, by receiving a memory access request from a host device, the memory access request is an AXI protocol; based on the memory access request and the preset address line of the memory, the memory access judgment is performed; if the address of the memory access request is within the asymmetric memory capacity range, the memory access request is converted based on the set conversion rule to obtain the converted memory access request; the converted memory access request is an AXI protocol that can access the memory; the memory is accessed according to the converted memory access request to perform the corresponding access operation.

[0243] The present disclosure can support more content capacity, fully utilize various memory particle resources, save the cost of memory particles, and solve the problem that the DDR memory in the prior art has strict restrictions on the DRAM particle capacity and bit width, resulting in low utilization rate of DRAM particle resources and high system cost.

[0244] The present disclosure converts the memory access request by setting a conversion rule, and the read access and the write access are completely independent and do not affect each other, and the read access and the write access can be performed at the same time, which is high in working efficiency.

[0245] The description of the flow or structure corresponding to each of the above figures has its own emphasis, and the parts not described in detail in a certain flow or structure can be referred to the related description of other flows or structures.

[0246] The above embodiments are only illustrative of the principles of the present disclosure and its effects, and are not intended to limit the present disclosure. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present disclosure shall be covered by the claims of the present disclosure.

Claims

1. A method for accessing asymmetric capacity memory, characterized in that, include: Receive memory access requests from the master device; Memory access is determined based on the memory access request and the preset address lines of the memory. If the address of the memory access request is within the range of asymmetric memory capacity, the memory access request is converted based on the set conversion rules to obtain the converted memory access request; as well as Access the memory according to the converted memory access request to perform the corresponding access operation.

2. The method according to claim 1, characterized in that, Memory access determination based on the memory access request and the preset address lines of the memory includes: If the address of the memory access request is greater than or equal to the preset address line, then the address of the memory access request is determined to be within the asymmetric memory capacity range; and If the address of the memory access request is less than the preset address line, then the address of the memory access request is determined to be within the symmetrical memory capacity range.

3. The method according to claim 2, characterized in that, Also includes: If the address of the memory access request is within the symmetric memory capacity range, the memory can be accessed directly according to the memory access request without conversion according to the set conversion rules.

4. The method according to claim 1, characterized in that, The memory access request includes write access and read access. The write access includes write commands and write data, and the read access includes read commands and read data.

5. The method according to claim 4, characterized in that, When the memory access request is a write access, the memory access request is transformed based on the set transformation rules to obtain the transformed memory access request, including: Based on the defined conversion rules, the write command in the memory access request is converted to obtain the converted write command; Based on the defined conversion rules, the write data in the memory access request is converted to obtain the converted write data; and The converted write command and the converted write data are used as the converted memory access request.

6. The method according to claim 5, characterized in that, The write command includes a write address, write data length, and write data bit width. Based on the defined conversion rules, the write command in the memory access request is converted to obtain the converted write command, which includes: Based on the defined conversion rules, the write address in the memory access request is converted to obtain the converted write address; Based on the defined conversion rules, the length of the write data in the memory access request is converted to obtain the converted write data length. Based on the defined conversion rules, the write data bit width in the memory access request is converted to obtain the converted write data bit width; and The converted write address, the converted write data length, and the converted write data bit width are used as the converted write command.

7. The method according to claim 6, characterized in that, Based on the established conversion rules, the write address in the memory access request is converted to obtain the converted write address, including obtaining the converted write address of the memory access request using the following formula: The write address of the converted memory access request = ((write address of the memory access request - preset address line) << 1) + the preset address line.

8. The method according to claim 4, characterized in that, When the memory access request is a read access, the memory access request is converted based on the set conversion rule to obtain the converted memory access request, including: Based on the defined conversion rules, the read command in the memory access request is converted to obtain the converted read command; and The converted read command is used as a converted memory access request.

9. The method according to claim 8, characterized in that, The read command includes a read address, read data length, and read data bit width. Based on the defined conversion rules, the read command in the memory access request is converted to obtain the converted read command, which includes: Based on the defined conversion rules, the read address in the memory access request is converted to obtain the converted read address; Based on the defined conversion rules, the length of the read data in the memory access request is converted to obtain the converted read data length; Based on the defined conversion rules, the read data bit width in the memory access request is converted to obtain the converted read data bit width; and The converted read address, the converted read data length, and the converted read data bit width are used as the converted read command.

10. The method according to claim 9, characterized in that, Based on the established conversion rules, the read address in the memory access request is converted to obtain the converted read address, including obtaining the converted read address of the memory access request using the following formula: The converted memory access request read address = ((the memory access request read address - the preset address line) << 1) + the preset address line.

11. The method according to claim 4, characterized in that, Accessing the memory according to the converted memory access request to perform the corresponding access operation includes: When the memory access request is a write access, the memory is accessed according to the converted write access request to execute the corresponding write access operation; or When the memory access request is a read access, the memory is accessed according to the converted read access request to perform the corresponding read access operation.

12. The method according to claim 11, characterized in that, Accessing the memory according to the converted read access, and performing the corresponding read access operation includes: Access the memory according to the converted read access to obtain the corresponding read data in the memory; and The read data is converted according to the set conversion rules to obtain the converted read data.

13. An apparatus for accessing asymmetric capacity memory, characterized in that, include: The receiving module is configured to receive memory access requests from the master device; The judgment module is configured to perform memory access judgment based on the memory access request and the preset address lines of the memory; The conversion module is configured to convert the memory access request based on a set conversion rule if the address of the memory access request is within the range of asymmetric memory capacity, so as to obtain the converted memory access request. as well as The access control module is configured to access the memory according to the converted memory access request in order to perform the corresponding access operation.

14. The apparatus according to claim 13, characterized in that, The conversion module is further configured to: If the address of the memory access request is within the symmetric memory capacity range, the memory is accessed directly according to the memory access request without conversion according to the set conversion rules, so as to perform the corresponding access operation.

15. The apparatus according to claim 13, characterized in that, The conversion module includes: A write access translation unit is configured to: translate a write command in a memory access request based on a set translation rule to obtain a translated write command; translate write data in the memory access request based on the set translation rule to obtain translated write data; use the translated write command and the translated write data as the translated memory access request; access the memory according to the translated memory access request to perform a corresponding write access operation; and The read access conversion unit is configured to: convert the read command in the memory access request based on the set conversion rule to obtain the converted read command; use the converted read command as the converted memory access request; and access the memory according to the converted memory access request to perform the corresponding read access operation.

16. A chip, characterized in that, include: One or more master devices; Memory with asymmetric capacity; The device according to any one of claims 13 to 15 is electrically coupled to the one or more host devices via an AXI bus; as well as A DDR controller is electrically coupled between the device and the memory and is configured to convert the AXI bus interface protocol to the DFI interface protocol.

17. An electronic device, characterized in that, include: Memory, configured to store executable programs or data; as well as At least one processor is electrically coupled to the memory and configured to execute the program or data to perform the method according to any one of claims 1 to 12.

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