PCIe link width expansion system and method

Abstract

The invention discloses a PCIe link width expansion system and method. The system comprises: a physical layer link establishment module, which performs physical layer link negotiation with a target PCIe device according to a second link rate and a second link width and feeds back a link negotiation result; the PCIe controller performs link negotiation of a physical layer with the self-establishing link module at a first link rate and a first link width after receiving a link negotiation result; initiating data link layer initialization to the target PCIe equipment after the link negotiation is completed; the signal conversion module is used for converting a link rate and a link width of initialization information sent by the PCIe controller into a second link rate and a second link width and outputting the second link rate and the second link width to the target PCIe equipment in a data link layer initialization stage of the PCIe controller and the target PCIe equipment; and converting the link rate and the link width of the initialization information fed back by the target PCIe device into a first link rate and a first link width, and feeding back the first link rate and the first link width to the PCIe controller. According to the invention, the link width expansion of the PCIe is realized, and the communication performance of the PCIe is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a PCIe link width extension system and method. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial bus that enables full-duplex communication by simultaneously transmitting and receiving data via bidirectional connections. It is widely used for interconnecting servers or PC hosts with peripherals and for high-speed data transfer between chips. With its high bandwidth and excellent scalability, PCIe has become the mainstream high-speed interconnect interface standard.

[0003] In traditional PCIe device interconnection scenarios, when upstream and downstream PCIe devices differ in link speed or link width, they adhere to the backward compatibility mechanism of the PCIe protocol when establishing a communication link. This involves negotiating a minimum link speed and minimum link width that both devices support to ensure normal data transmission. For example, when a PCIe device with a Gen3×16 link specification interconnects with a Gen4×8 link specification, the maximum link specification that can be achieved after establishing a communication link is Gen3×8. While this method ensures that the upstream and downstream PCIe devices can establish a link for communication, it reduces the effective bandwidth of the PCIe devices, making it difficult to fully utilize the performance of PCIe devices with high link widths. Summary of the Invention

[0004] In view of the above problems, this application provides a PCIe link width extension system and method to solve the above technical problems.

[0005] In a first aspect, this application provides a PCIe link width extension system, used to extend the actual link width negotiated between the PCIe controller and the target PCIe device to the second link width when a PCIe controller that supports a maximum first link rate and a first link width establishes a communication link with a target PCIe device that supports a maximum second link rate and a second link width, wherein the PCIe controller and the target PCIe device have matching transmission bandwidths, and the PCIe link width extension system includes a PCIe controller, a physical layer link establishment module, a self-established link module, and a signal conversion module; The physical layer link establishment module is used to perform physical layer link negotiation with the target PCIe device according to the second link rate and the second link width, and to feed back the link negotiation result to the PCIe controller. The PCIe controller is configured to, upon receiving the link negotiation result, perform physical layer link negotiation with the self-built link module at the first link rate and the first link width; and to initiate data link layer initialization to the target PCIe device after completing link negotiation with the self-built link module. The signal conversion module is used to convert the link rate and link width of the initialization information sent by the PCIe controller into the second link rate and the second link width and output them to the target PCIe device during the data link layer initialization process; and to convert the link rate and link width of the initialization information fed back by the target PCIe device into the first link rate and the first link width and feed them back to the PCIe controller to complete the data link layer initialization.

[0006] Secondly, this application also provides a PCIe link width extension method, applied to the PCIe link width extension system as described in the first aspect, the PCIe link width extension method comprising: The physical layer link establishment module performs the following: negotiates a physical layer link with the target PCIe device according to the second link rate and the second link width, and feeds back the link negotiation result to the PCIe controller. The PCIe controller performs the following actions: upon receiving the link negotiation result, it negotiates the physical layer link with the self-built link module at the first link rate and the first link width, and after completing the link negotiation, it initiates data link layer initialization to the target PCIe device. The signal conversion module performs the following actions during the data link layer initialization process: converting the link rate and link width of the initialization information sent by the PCIe controller into the second link rate and the second link width and outputting them to the target PCIe device; and converting the link rate and link width of the initialization information fed back by the target PCIe device into the first link rate and the first link width and feeding them back to the PCIe controller, thereby completing the data link layer initialization.

[0007] This application provides a PCIe link width extension system and method. The PCIe link width extension system uses a physical layer link establishment module to negotiate a physical layer link with the target PCIe device at a second link rate and a second link width, and feeds the result back to the PCIe controller. This allows the PCIe controller to obtain the link rate and link width supported by the target PCIe device. Subsequently, the PCIe controller and the self-established link module complete link negotiation at the first link rate and the first link width, ensuring that the PCIe controller enters normal operation at its supported first link rate and first link width. Finally, a signal conversion module performs bidirectional conversion of the link rate and link width of the initialization information during the data link layer initialization process between the PCIe controller and the target PCIe device. This ensures bandwidth adaptation between the PCIe controller and the target PCIe device at different link rates and link widths, thereby extending the link width of the PCIe controller from the first link width to a second link width consistent with the target PCIe device. The PCIe link width extension system provided in this application enables both parties establishing a link to communicate with the highest possible link width while adhering to the PCIe protocol. This avoids the link width degradation problem caused by backward compatibility when establishing a link with traditional PCIe devices, thus achieving the extension of PCIe link width and improving the communication performance of PCIe devices.

[0008] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This paper illustrates an application diagram of the PCIe link width extension system provided in an embodiment of this application.

[0011] Figure 2 A schematic diagram of a PCIe link width extension system provided in an embodiment of this application is shown.

[0012] Figure 3 Another schematic diagram of the PCIe link width extension system provided in this application embodiment is shown.

[0013] Figure 4 This illustration shows another schematic diagram of the PCIe link width extension system provided in an embodiment of this application.

[0014] Figure 5 This illustration shows another schematic diagram of the PCIe link width extension system provided in an embodiment of this application.

[0015] Figure 6 A flowchart of the PCIe link width extension method provided in an embodiment of this application is shown. Detailed Implementation

[0016] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0017] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0018] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0019] This application provides a PCIe link width extension system, used to extend the actual link width negotiated between the PCIe controller and the target PCIe device from the first link width to the second link width when a PCIe controller with a maximum support for a first link rate and a first link width establishes a communication link with a target PCIe device with a maximum support for a second link rate and a second link width. The PCIe controller's transmission bandwidth is matched to that of the target PCIe device. For example, Figure 1 This paper illustrates an application diagram of the PCIe link width extension system provided in an embodiment of this application, such as... Figure 1As shown, the PCIe controller 10 is located within a PCIe device 100 and operates in GEN4×8 mode. The target PCIe device 200 also has another PCIe controller 20, which is different from the PCIe controller 10 and operates in GEN3×16 mode. The PCIe link width extension system provided in this embodiment can extend the ×8 link width of the PCIe controller 10 to ×16, thereby enabling the PCIe controller 100 and the target PCIe device 200 to transmit data with a ×16 link width.

[0020] Optionally, in the PCIe link width extension system provided in this application embodiment, the transmission bandwidth of the PCIe controller and the target PCIe device must match. That is, the PCIe controller and the target PCIe device can only achieve a matching transmission bandwidth when the first link rate is greater than the second link rate and the first link width is less than the second link width. Optionally, only when the PCIe controller and the target PCIe device maintain the same total bandwidth can the signal conversion module perform stable data conversion between different link rates and link widths. Only then can this application embodiment effectively extend the link width of the PCIe controller with a low link width to the same high link width as the target PCIe device.

[0021] In some embodiments of the PCIe link width extension system provided in this application, when the link width of the target PCIe device is less than or equal to the link width of the PCIe controller, this application embodiment can also achieve backward compatibility with the target PCIe link width through conventional functions conforming to the PCIe protocol.

[0022] It is understood that in the embodiments of this application, "establishing a communication link between the PCIe controller and the target PCIe device" means that a data communication link conforming to the PCIe protocol is established between the PCIe controller and the PCIe controller contained within the target PCIe device. The PCIe controller is also located within the PCIe device during application. "Matching transmission bandwidth" means that even when there are differences in link speed and link width, the PCIe controller and the target PCIe device, whose individual speed or width parameters are not the same, can still achieve the same total transmission capacity through a combination of speed and width. For example, GEN4×8 and GEN3×16 have the same total bandwidth of 128 GT / s even with different link speeds and link widths.

[0023] It's understandable that "GENi×j" is a general representation of PCIe link configuration. "GENi" indicates the PCIe generation of the link; different generations correspond to different link rates. For example, GEN3 corresponds to a PCIe link rate of 8GT / s per channel, while GEN4 corresponds to a PCIe link rate of 16GT / s per channel. "×j" indicates the link width, i.e., the number of channels for parallel transmission. For example, GEN4×8 indicates that the link operates at a fourth-generation link rate of 16GT / s with a width of 8 channels; GEN3×16 indicates that the link operates at a third-generation link rate of 8GT / s with a width of 16 channels.

[0024] To facilitate the explanation of the PCIe link width extension system provided in the embodiments of this application, "GENi" will be used to represent the single-channel link rate of PCIe, and "×j" will be used to represent the link width of PCIe.

[0025] Figure 2 A schematic diagram of a PCIe link width extension system provided in an embodiment of this application is shown, as follows: Figure 2 As shown, the system includes a PCIe controller, a physical layer link establishment module, a self-established link module, and a signal conversion module.

[0026] The physical layer link establishment module is used to negotiate physical layer links with the target PCIe device according to the second link rate and the second link width, and to feed back the link negotiation results to the PCIe controller. Optionally, the physical layer link establishment module is configured to have the maximum link rate and link width supported by the target PCIe device, so as to negotiate physical layer links with the target PCIe device, determine the link rate and link width supported by the target PCIe device, and provide the negotiation results to the PCIe controller, so that the PCIe controller can obtain the link rate and link width information supported by the target PCIe device.

[0027] Upon receiving a link negotiation result, the PCIe controller selects a link rate and width matching the result to negotiate the physical layer link with the self-established link module. Specifically, it negotiates the link with the self-established link module using a first link rate and a first link width. Optionally, when the link width of the target PCIe device is greater than the link width of the PCIe controller (e.g., the target PCIe device is GEN3×16 while the PCIe controller is GEN4×8), the PCIe controller will choose to maintain GEN4×8 for physical layer link negotiation with the self-established link module. In this case, the first link rate and first link width are GEN4×8. Conversely, when the link width of the target PCIe device is less than or equal to the link width of the PCIe controller (e.g., the target device only supports GEN3×8), the PCIe controller will be backward compatible with GEN3×8 based on the negotiation result to ensure the link can be established normally and maintain stable communication. In this case, the first link rate and first link width are GEN3×8. However, it should be clarified that the design purpose of this application's embodiments is to enable a PCIe controller with a lower link width to establish a communication link with a target PCIe device with a higher link width, thereby achieving link width expansion. When the link width of the target PCIe device is less than or equal to the link width of the PCIe controller, the backward compatibility capability of the PCIe controller is only implemented as a regular function conforming to the PCIe protocol and is not the design purpose of this application's embodiments. This application's embodiments achieve physical layer link negotiation between the PCIe controller and the self-built link module, eliminating the need for the PCIe controller and the target PCIe device to contact each other during the physical layer link negotiation phase. This avoids the problem of establishing a communication link in a backward-compatible manner due to differences in link speed and link width between the two parties.

[0028] The PCIe controller is also used to initiate data link layer initialization to the target PCIe device after completing physical layer link negotiation with the self-established link module. Optionally, the PCIe controller enables itself to operate at its highest supported link rate and highest link width by establishing a link with the self-established link module. After completing this link establishment, the PCIe controller will establish the data link layer operating environment with the target PCIe device in accordance with the requirements of the PCIe protocol.

[0029] The signal conversion module is used during the data link layer initialization process between the PCIe controller and the target PCIe device. It converts the link rate and link width of the initialization information sent by the PCIe controller into a second link rate and second link width, outputting them to the target PCIe device. It also converts the link rate and link width of the initialization information fed back by the target PCIe device into a first link rate and first link width, feeding them back to the PCIe controller, thus completing the data link layer initialization between the PCIe controller and the target PCIe device. Optionally, the PCIe controller includes a Physical Layer, a Data Link Layer, and a Transaction Layer, where the establishment of the communication link is jointly completed by the Physical Layer and the Data Link Layer. The Physical Layer link negotiation is used to determine the link rate and link width between the two parties establishing the link. After the Physical Layer completes the link establishment, the Data Link Layer further performs its initialization. By bidirectionally converting the parameters of the initialization information, the signal conversion module enables the PCIe controller and the target PCIe device to complete the data link layer initialization under their respective supported link parameters, thereby ensuring that both parties establish communication with a consistent link width upon completing the data link layer initialization, thus achieving link width expansion.

[0030] In some embodiments, such as Figure 2 As shown in the PCIe link width extension system of this application embodiment, the signal conversion module is configured to connect to the target PCIe device through the physical layer link establishment module. At this time, the physical layer link establishment module can be configured to act only as a physical channel for signal transmission after completing physical layer link negotiation with the target PCIe device. It is responsible for directly forwarding the data output by the signal conversion module to the target PCIe device, and at the same time, transmitting the signal returned by the target PCIe device back to the signal conversion module, thus forming a data transmission path between the PCIe controller and the target PCIe device. The physical layer link establishment result negotiated between the physical layer link establishment module and the target PCIe device can also be configured to be transmitted to the PCIe controller through the signal conversion module.

[0031] It is understood that, in the embodiments of this application, the connection method between the physical layer connection module, the signal conversion module, and the target PCIe device is not unique. For example, Figure 3 This paper illustrates another schematic diagram of the PCIe link width extension system provided in an embodiment of this application, as shown below. Figure 3 As shown, the signal conversion module can also be designed to directly establish a transmission path with the target PCIe device, while the physical layer link establishment module is independently connected to the target PCIe device and the PCIe controller respectively.

[0032] The PCIe link width extension system provided in this application embodiment negotiates physical layer links with the target PCIe device at a second link rate and a second link width through a physical layer link establishment module, and feeds the result back to the PCIe controller. This allows the PCIe controller to obtain the link rate and link width supported by the target PCIe device. Subsequently, the PCIe controller and the self-established link module complete physical layer link negotiation at the first link rate and the first link width. This ensures that the PCIe controller enters a normal working state at its own supported first link rate and first link width, and avoids direct physical layer link negotiation with the target PCIe device. Finally, the signal conversion module performs bidirectional conversion of the link rate and link width of the initialization information during the data link layer initialization process between the PCIe controller and the target PCIe device. This ensures bandwidth adaptation between the PCIe controller and the target PCIe device at different link rates and link widths, thereby extending the link width of the PCIe controller from the first link width to a second link width consistent with the target PCIe device. The PCIe link width extension system provided in this application enables both parties establishing a link to communicate with the highest possible link width while adhering to the PCIe protocol. This avoids the link width degradation problem caused by backward compatibility when establishing a link with traditional PCIe devices, thus achieving the extension of PCIe link width and improving the communication performance of PCIe devices.

[0033] In some embodiments, the PCIe link width extension system provided in this application includes a signal conversion module comprising an asynchronous FIFO (Asynchronous First-In-First-Out) data buffer circuit. This circuit receives initialization information sent by the PCIe controller and concatenates every two data packets of the initialization information sent by the PCIe controller into one data packet, thereby converting the link rate and link width of the initialization information sent by the PCIe controller into a second link rate and a second link width. It also receives initialization information fed back by the target PCIe device and splits every data packet of the initialization information fed back by the target PCIe device into two data packets, thereby converting the link width and link rate of the initialization information fed back by the target PCIe device into a first link rate and a first link width. Optionally, the signal conversion module uses an asynchronous FIFO buffer mechanism to adjust the data timing during the concatenation and splitting of the initialization information. By inserting buffers and reassembling data between clock domains, high-speed, narrow-width data can be stably converted into low-speed, wide-width data, and vice versa. This ensures the effective transmission of initialization information under different link rates and link widths, avoids bidirectional conversion under the premise of data loss or out-of-order delivery, and enables PCIe controllers with low link widths to maintain a consistent transmission bandwidth when initializing and communicating with target PCIe devices with high link widths, thereby expanding the link width and improving the overall communication performance of the system.

[0034] In some embodiments, when the link width of the target PCIe device is less than or equal to the link width of the PCIe controller, the asynchronous first-in-first-out queue data buffer circuit can also be configured to convert the rate and width of the initialization information, thereby ensuring that both parties can still successfully complete the data conversion and bandwidth matching during the initialization phase, ensuring system compatibility.

[0035] It is understood that the specific implementation method of the asynchronous first-in-first-out (FIFO) queue data buffer circuit for data splitting and data concatenation in this application embodiment is not limited, and the implementation method is not unique. For example, in one implementation method, a clock control mechanism can be used to adjust the data write and read rates, so that multi-phase narrow-width data written on one side is output in the form of a single-phase width on the other side, or vice versa, the single-phase width data is split into multi-phase narrow-width data. Another example is that in another implementation method, data can be managed through programmable logic control, such as setting the control logic to perform combination and splitting operations during the data write or read phase, thereby realizing the conversion between different link widths and link rates. The above implementation methods are all conventional means in the art, and this application does not limit them.

[0036] In some embodiments, in the PCIe link width extension system provided in this application, the physical layer link establishment module is a logical functional unit configured to simulate the PCIe physical layer operating at the second link rate and the second link width, to perform physical layer link negotiation with the target PCIe device, and to feed back the link negotiation result to the PCIe controller. Optionally, the physical layer link establishment module, as a logical functional unit, can be implemented through logic circuits, programmable logic resources, or independent IP (Intellectual Property) cores to simulate the PCIe physical layer interaction process at the second link rate and the second link width.

[0037] It is understood that the implementation method of the logical functional unit of the physical layer link establishment module in this application embodiment is not limited. Since the operating mechanism of the PCIe physical layer is disclosed in the PCIe protocol standard, those skilled in the art can build logic circuits, programmable logic devices, or IP cores based on this disclosure to implement corresponding physical layer interaction functions, thereby constituting a physical layer link establishment module. Furthermore, the physical architecture of the physical layer link establishment module can be completely or partially the same as the PCIe physical layer to enable physical layer link negotiation with the PCIe physical layer. Moreover, the design purpose of this application is not the implementation method of the physical layer link establishment module, but its application method in link width expansion scenarios. In addition, the process of physical layer link negotiation with PCIe is also disclosed in the PCIe protocol; therefore, this application embodiment will not describe the physical layer link negotiation process between the physical layer link establishment module and the PCIe device in detail. For example, a typical physical layer link negotiation process includes: both devices detecting whether a valid link connection exists; after confirming the link exists, entering the polling phase, both parties exchange training sequences to synchronize link numbers, exchange supported link rates and bandwidth, and other capability information; subsequently entering the configuration phase, the final working link rate is determined based on the capability negotiation in the polling phase; finally, entering the activation phase, the link switches to the data transmission state, and the physical layer link establishment process is completed. All of the above processes comply with the PCIe protocol specification.

[0038] In some embodiments of the PCIe link width extension system provided in this application, the self-established link module is also a logical functional unit. The self-established link module is configured to simulate the PCIe physical layer operating at a first link rate and a first link width to perform link negotiation with the PCIe controller at the physical layer. Optionally, the self-established link module can be implemented through logic circuits, programmable logic resources, or independent IP cores to provide a link establishment environment that matches the capabilities of the PCIe controller itself. In this link establishment environment, the PCIe controller can complete the entire link establishment process according to the first link rate and the first link width, ensuring that it enters a working state that conforms to the link width and link rate it supports.

[0039] As one implementation, the self-built link module includes a self-built link adapter, which is used to build a physical layer link building environment for the PCIe controller that is adapted to its own link parameters.

[0040] It is understood that the implementation method of the logical functional unit of the self-built chain module is not limited in the embodiments of this application. Since the operating mechanism of the PCIe physical layer has been disclosed in the PCIe protocol standard, those skilled in the art can build logic circuits, programmable logic devices, or IP cores based on the disclosed content to implement the corresponding physical layer interaction functions, thereby constituting the self-built chain module. Even the physical architecture of the self-built chain module can be completely or partially the same as the PCIe physical layer to enable physical layer link negotiation with the PCIe physical layer. Furthermore, the design purpose of this application is not the implementation method of the self-built chain module, but its application method in the scenario of link width expansion. In addition, as mentioned above, the process of physical layer link negotiation with PCIe is also disclosed in the PCIe protocol; therefore, the embodiments of this application will not describe the physical layer link negotiation process between the self-built chain module and the PCIe controller in detail.

[0041] In some embodiments, such as Figure 1 and Figure 2 As shown, the PCIe link width extension system provided in this application embodiment further includes: The selection module enables communication between the PCIe controller and the self-established link module during link negotiation. It also enables communication between the PCIe controller and the target PCIe device via the signal conversion module during the data link layer initialization process. Optionally, the selection module dynamically switches the communication path at different link establishment stages. During link negotiation, the selection module directs the PCIe controller's interaction path to the self-established link module; during the data link layer initialization phase, it switches the path to allow the PCIe controller to establish interaction with the signal conversion module, ensuring both parties complete data link layer initialization.

[0042] It is understood that the implementation of the selection module in this application is not limited, and its implementation can be varied. For example, the selection module can be implemented by hardware circuits such as multiple multiplexer combination circuits or programmable interconnect logic, used to correctly guide the output of the PCIe controller to the self-link module or signal conversion module at different stages, while guiding the self-link module or target PCIe device back to the PCIe controller via the feedback signal of the signal conversion module; it can also be dynamically switched by logic resources configured in a programmable logic device (such as an FPGA), thereby adjusting the bidirectional communication path between the PCIe controller and each module at different link establishment stages; or it can be implemented by other equivalent methods known to those skilled in the art. Any method that can realize the switching of input / output paths and feedback paths between the PCIe controller and the self-link module and signal conversion module at different stages should be considered to fall within the protection scope of this application.

[0043] In some embodiments of the PCIe link width extension system provided in this application, the selection module is further configured to enable the PCIe controller to communicate with the target PCIe device through the signal conversion module after the PCIe controller and the target PCIe device complete the data link layer initialization. Optionally, after the PCIe controller and the target PCIe device establish a link with high link width, the selection module is configured to switch the communication path to the signal conversion module, enabling the PCIe controller to perform subsequent data transmission with the target PCIe device through the signal conversion module with high link width.

[0044] In some embodiments, Figure 4 and Figure 5 Two more schematic diagrams of the PCIe link width extension system provided in the embodiments of this application are shown, such as... Figure 4 and Figure 5 As shown, in the PCIe link width extension system provided in this application embodiment, the physical layer link establishment module, the self-link establishment module, and the signal conversion module are disposed between the PCIe controller and the high-speed transmission interface of the PCIe controller, so as to communicate with the target PCIe device through the high-speed transmission interface of the PCIe controller. Optionally, in this application embodiment, the PCIe controller, the physical layer link establishment module, the self-link establishment module, the signal conversion module, and the high-speed transmission interface of the PCIe controller are integrated to prepare a PCIe device with link width extension capability, thereby expanding the link width of the PCIe controller inside the PCIe device, and then enabling communication and link establishment with other PCIe devices with high link width through the high-speed transmission interface of the PCIe controller. The high-speed transmission interface of the PCIe controller is the physical channel for data interaction with external devices, and is usually implemented by a serializer / deserializer (SerDes) or a high-speed transceiver (HSST).

[0045] In some embodiments, such as Figure 4 As shown in the PCIe link width extension system provided in this application embodiment, the physical layer link establishment module is located between the signal conversion module and the high-speed transmission interface of the PCIe controller. The physical layer link establishment module is also used to switch to a communication transmission mode after completing physical layer link negotiation with the target PCIe device. This data transmission mode allows the physical layer link establishment module to act as a signal transmission path, enabling the signal conversion module to communicate with the target PCIe device through the high-speed transmission interface of the physical layer link establishment module and the PCIe controller. The signal conversion module is also used to transmit the link negotiation result fed back by the physical layer link establishment module to the PCIe controller.

[0046] In some embodiments, such as Figure 5 As shown, the physical layer link establishment module is also configured to communicate directly with the PCIe controller without having to communicate with the PCIe controller through a selection module.

[0047] In some embodiments, in the PCIe link width extension system provided by this application, the maximum supported link width of the target PCIe device is greater than the maximum supported link width of the PCIe controller. Optionally, the design purpose of this application is to enable the PCIe controller with a low link width to extend the link width when communicating with the target PCIe device with a higher link width, so as to improve the communication performance of the two. Therefore, the target PCIe device is preferably a PCIe device whose maximum supported link width is greater than the maximum supported link width of the PCIe controller.

[0048] In some embodiments, in the PCIe link width extension system provided in this application, the target PCIe device includes the PCIe link width extension system. Optionally, the target PCIe device may also be a PCIe device that includes the PCIe link width extension system, thereby enabling two PCIe devices with low link widths to establish a communication link with a higher link width, thereby improving the communication performance of both parties.

[0049] In some embodiments, in the PCIe link width extension system provided in this application, the target PCIe device can also be a PCIe device with a link width less than or equal to that of the PCIe controller. In this application, the PCIe controller can also establish a communication link with the target PCIe device according to the link width and link rate supported by both parties when interconnecting with the PCIe protocol itself, based on the backward compatibility of the PCIe protocol itself, thereby ensuring the normal establishment of the link and data transmission, and ensuring the basic compatibility and interoperability of the system.

[0050] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0051] For example, for various devices and products applied to or integrated into chips, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into chip modules, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0052] This application also provides a PCIe link width extension method, applied to the PCIe link width extension system described in the above embodiments. This method extends the link width of the PCIe controller to the second link width when establishing a communication link with a target PCIe device of a first link speed and first link width. For example, the application scenarios of this PCIe link width extension method are as follows: Figure 1 As shown, the PCIe controller 100 operates in GEN4×8 mode, and the target PCIe device 200 operates in GEN3×16 mode. The PCIe link width extension system provided in this embodiment can extend the ×8 link width of the PCIe controller 100 to ×16, so that the PCIe controller 100 and the target PCIe device 200 can complete data transmission with a ×16 link width.

[0053] Figure 6 A flowchart of the PCIe link width extension method provided in an embodiment of this application is shown, as follows: Figure 4 As shown, the method includes: The physical layer link establishment module performs the following steps: negotiates a physical layer link with the target PCIe device at the second link rate and the second link width, and feeds back the link negotiation result to the PCIe controller.

[0054] Optionally, the physical layer link establishment module is configured to have the maximum link rate and link width supported by the target PCIe device, so as to negotiate the physical layer link with the target PCIe device, determine the link rate and link width supported by the target PCIe device, and provide the negotiation result to the PCIe controller, so that the PCIe controller can obtain the link rate and link width information supported by the target PCIe device.

[0055] The PCIe controller performs the following steps: after receiving the link negotiation result, it negotiates the physical layer link with the self-built link module at the first link rate and the first link width, and after completing the link negotiation, it initiates the data link layer initialization to the target PCIe device.

[0056] Optionally, when the link width of the target PCIe device is greater than the link width of the PCIe controller, such as when the target PCIe device is GEN3×16 and the PCIe controller is GEN4×8, the PCIe controller chooses to maintain GEN4×8 for link negotiation with the self-established link module. In this case, the first link rate and the first link width are GEN4×8. Conversely, when the link width of the target PCIe device is less than or equal to the link width of the PCIe controller, such as when the target device only supports GEN3×8, the PCIe controller will be backward compatible with GEN3×8 based on the negotiation result to ensure that the link can be established normally and maintain stable communication. In this case, the first link rate and the first link width are GEN3×8. After the PCIe controller completes the link establishment with the self-established link module, the PCIe controller establishes a data link layer operating environment with the target PCIe device according to the requirements of the PCIe protocol. It should be noted that the design purpose of this embodiment is to enable a PCIe controller with a lower link width to establish a communication link with a target PCIe device with a higher link width, thereby achieving link width expansion. When the link width of the target PCIe device is less than or equal to the link width of the PCIe controller, the backward compatibility capability of the PCIe controller is only used as a routine function to comply with the PCIe protocol and is not the design purpose of the embodiments in this application.

[0057] The signal conversion module performs the following steps: during the data link layer initialization process, the link rate and link width of the initialization information sent by the PCIe controller are converted into a second link rate and a second link width and output to the target PCIe device; and the link rate and link width of the initialization information fed back by the target PCIe device are converted into a first link rate and a first link width and fed back to the PCIe controller, so as to complete the data link layer initialization between the PCIe controller and the target PCIe device.

[0058] Optionally, the signal conversion module performs bidirectional conversion of the parameters of the initialization information, enabling the PCIe controller and the target PCIe device to complete the data link layer initialization under their respective supported link parameters. This ensures that both parties establish communication with a consistent link width when completing the data link layer initialization, thereby achieving the expansion of the link width.

[0059] In the PCIe link width extension method provided in this application embodiment, the transmission bandwidth of the PCIe controller and the target PCIe device must be matched. That is, the PCIe controller and the target PCIe device can only achieve bandwidth matching when the first link rate is greater than the second link rate and the first link width is less than the second link width. Optionally, only when the PCIe controller and the target PCIe device maintain a consistent total bandwidth can the signal conversion module perform stable data conversion between different link rates and link widths. Only then can this application embodiment effectively extend the link width of the PCIe controller with a low link width to the same high link width as the target PCIe device.

[0060] In some embodiments, in the PCIe link width extension method provided in this application, when the link width of the target PCIe device is less than or equal to the link width of the PCIe controller, this application embodiment can also achieve backward compatibility with the target PCIe link width through conventional functions conforming to the PCIe protocol.

[0061] The PCIe link width extension method provided in this application involves a physical layer link establishment module negotiating a physical layer link with the target PCIe device at a second link rate and a second link width, and feeding the result back to the PCIe controller. Subsequently, the PCIe controller and the self-established link module complete physical layer link negotiation at the first link rate and a first link width, ensuring that the PCIe controller enters normal operation at its supported first link rate and first link width. Finally, a signal conversion module performs bidirectional conversion of the link rate and link width of the initialization information during the data link layer initialization process between the PCIe controller and the target PCIe device, ensuring bandwidth adaptation between the PCIe controller and the target PCIe device at different link rates and link widths. Ultimately, this extends the link width of the PCIe controller from the first link width to a second link width consistent with the target PCIe device. The PCIe link width extension method provided in this application, while adhering to the PCIe protocol, enables both parties to communicate at the highest link width, avoiding the link width degradation problem caused by backward compatibility during traditional PCIe device link establishment, thus achieving PCIe link width extension and improving PCIe device communication performance.

[0062] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A PCIe link width expansion system, comprising: The PCIe controller and the target PCIe device are matched in transmission bandwidth, and the PCIe link width expansion system comprises a PCIe controller, a physical layer link establishment module, a self-link establishment module and a signal conversion module. The physical layer link establishment module is configured to perform link negotiation of a physical layer with the target PCIe device at the second link rate and the second link width, and feed back a link negotiation result to the PCIe controller. The PCIe controller is configured to perform link negotiation of a physical layer with the self-link establishment module at the first link rate and the first link width after receiving the link negotiation result. The signal conversion module is configured to convert a link rate and a link width of initialization information sent by the PCIe controller to the second link rate and the second link width and output to the target PCIe device during the data link layer initialization process. The signal conversion module is configured to convert a link rate and a link width of initialization information sent by the PCIe controller to the second link rate and the second link width and output to the target PCIe device during the data link layer initialization process. The signal conversion module comprises:

2. The PCIe link width expansion system of claim 1, wherein, An asynchronous first-in-first-out queue data buffer circuit is configured to receive initialization information sent by the PCIe controller, splice every two data of the initialization information sent by the PCIe controller into one data, so as to convert a link rate and a link width of the initialization information sent by the PCIe controller to the second link rate and the second link width. The signal conversion module is configured to convert a link rate and a link width of initialization information sent by the PCIe controller to the second link rate and the second link width and output to the target PCIe device during the data link layer initialization process. The physical layer link establishment module is a logical functional unit configured to simulate a PCIe physical layer running at the second link rate and the second link width to perform link negotiation of a physical layer with the target PCIe device and feed back a link negotiation result to the PCIe controller.

3. The PCIe link width expansion system of claim 1, wherein, The self-link establishment module is a logical functional unit configured to simulate a PCIe physical layer running at the first link rate and the first link width to complete link negotiation of a physical layer with the PCIe controller.

4. The PCIe link width expansion system of claim 1, wherein, Further comprising:

5. The PCIe link width expansion system of claim 1, wherein, ​ The selection module is configured to enable the PCIe controller to communicate with the self-built chain module when the PCIe controller and the self-built chain module perform link negotiation at a physical layer. The selection module is further configured to enable the PCIe controller to communicate with the target PCIe device through the signal conversion module after the PCIe controller and the target PCIe device complete data link layer initialization.

6. The PCIe link width expansion system of claim 5, wherein, The selection module is further configured to enable the PCIe controller to communicate with the target PCIe device through the signal conversion module after the PCIe controller and the target PCIe device complete data link layer initialization.

7. The PCIe link width expansion system of claim 1, wherein, The physical layer chain building module, the self-built chain module and the signal conversion module are arranged between the PCIe controller and a high-speed transmission interface of the PCIe controller, so that the PCIe controller communicates with the target PCIe device through the high-speed transmission interface of the PCIe controller.

8. The PCIe link width expansion system of claim 7, wherein, The physical layer chain building module is arranged between the signal conversion module and the high-speed transmission interface of the PCIe controller, and is further configured to switch to a data transmission mode after completing link negotiation at the physical layer with the target PCIe device, so that the physical layer chain building module serves as a signal transmission path, and the signal conversion module communicates with the target PCIe device through the physical layer chain building module and the high-speed transmission interface of the PCIe controller. The signal conversion module is further configured to transmit a link negotiation result fed back by the physical layer chain building module to the PCIe controller.

9. The PCIe link width expansion system of claim 1, wherein, The target PCIe device supports a maximum link width greater than a maximum link width supported by the PCIe controller, or the target PCIe device comprises the PCIe link width expansion system.

10. A PCIe link width expansion method, comprising: The PCIe link width expansion method comprises: performing, by the physical layer chain building module, link negotiation at a physical layer with the target PCIe device at a second link rate and a second link width, and feeding back a link negotiation result to the PCIe controller; performing, by the PCIe controller, link negotiation at a physical layer with the self-built chain module at a first link rate and a first link width after receiving the link negotiation result, and initiating data link layer initialization to the target PCIe device after completing the link negotiation; performing, by the signal conversion module, conversion of a link rate and a link width of initialization information sent by the PCIe controller to the second link rate and the second link width during the data link layer initialization process, and outputting the initialization information to the target PCIe device; and conversion of a link rate and a link width of initialization information fed back by the target PCIe device to the first link rate and the first link width, and feeding back the initialization information to the PCIe controller, so as to complete the data link layer initialization.

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