Method and device for converting AXI protocol into CHI protocol

Abstract

The invention relates to a method and device for converting an AXI protocol into a CHI protocol, and the method comprises the steps: receiving an AXI request which comprises an AXI read-write request; splitting the received AXI read-write request into a plurality of target AXI read-write requests conforming to the size of a single data volume of a CHI interface protocol based on the total data volume required to be accessed by the AXI read-write request; caching the split target AXI read-write request and related write-in data; converting the cached target AXI read-write request into a read-write request of a request type corresponding to a CHI interface protocol; converting the write-in data into write-in data of a data packet type corresponding to the CHI interface protocol; and receiving the converted read-write request and write data, and carrying out request processing according to the specification of the CHI protocol. Therefore, through splitting and conversion of the AXI request, a plurality of target AXI read-write requests can be operated at the same time, and the parallelism degree of data access is improved; data resources of different interface protocols can be managed conveniently, and the conversion efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a method and device for converting AXI protocol into CHI protocol. BACKGROUND

[0002] At present, with the wide application of CHI protocol in multi-core systems, more and more chips are mixed with Coherent Hub Interface Protocol (CHI) and Advanced eXtensible Interface Protocol (AXI), and the conversion of AXI protocol into CHI protocol is indispensable.

[0003] However, in the related art, the request channel of AXI is converted into the request channel of CHI, and the response channel of AXI is converted into the response channel of CHI, and there is an unequal data amount problem between the two protocols, which causes the blocking of the request address receiving of the AXI request channel and reduces the access bandwidth of the entire system. SUMMARY

[0004] The present disclosure provides a method and device for converting AXI protocol into CHI protocol.

[0005] According to a first aspect of the embodiments of the present disclosure, a method for converting AXI protocol into CHI protocol is provided, and the method comprises the following steps: receiving an AXI request, wherein the AXI request comprises an AXI read-write request; based on the total data amount required to be accessed by the AXI read-write request, splitting the received AXI read-write request into a plurality of target AXI read-write requests conforming to the single data amount size of the CHI interface protocol; buffering the split target AXI read-write request and the write-in data involved in the target AXI write request; converting the buffered target AXI read-write request into a read-write request of a corresponding request type of the CHI interface protocol; converting the write-in data involved in the AXI write request into write data of a corresponding data packet type of the CHI interface protocol; receiving the converted read-write request and write data, and performing request processing according to the specification of the CHI protocol.

[0006] In one embodiment of the present disclosure, in response to the target AXI request being an AXI read request, the method comprises: receiving an AXI read request, wherein the AXI read request address has no correlation with the addresses in the first cache queue, and the first cache queue is a cache queue for managing AXI read requests; based on the total data amount required to be accessed by the AXI read request, splitting the received AXI read request into a plurality of target AXI read requests conforming to the single data amount size of the CHI interface protocol, and deploying the target AXI read requests in the first cache queue respectively; saving each of the target AXI read requests in the first cache queue in a preset target AXI read request cache module; converting the target AXI read request into a CHI read request of a corresponding request type of the CHI interface protocol according to the cache attribute of the target AXI read request in the target AXI read request cache module, and deploying the CHI read request in a second cache queue for managing CHI read requests; and receiving each CHI read request periodically sent by the second cache queue through a preset functional module for processing the CHI interface protocol, and performing read request processing according to the specification of the CHI protocol.

[0007] In one embodiment of the present disclosure, the read request processing according to the specification of the CHI protocol comprises: receiving read response data returned by the CHI read request through the preset functional module for processing the CHI interface protocol, and forwarding the read response data to the corresponding target cache queue in the second cache queue; wherein the read response data includes a data block read and a read request identifier; after the corresponding target cache queue in the second cache queue obtains the read response data, the target cache queue first completes the CHI interface handshake protocol, then writes the data block and the read request identifier into a preset target AXI read request storage module, and notifies the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, and can be used for the next target AXI read request; after the first cache queue receives that all the split target AXI read requests have been completed, the first cache queue reads each data block from the storage module based on the read request identifier and returns the data block to the functional module for processing the AXI interface protocol; the functional module for processing the AXI interface protocol performs handshake processing at the AXI protocol end, and completes the current AXI read request process.

[0008] In one embodiment of the present disclosure, in response to the target AXI request being an AXI write request, the method comprises: receiving an AXI write request, wherein the AXI write request address has no correlation with the address in a third cache queue, and the third cache queue is a cache queue for managing AXI write requests; based on the total data amount of the AXI write request, splitting the received AXI write request into a plurality of target AXI write requests conforming to the single data amount size of the CHI interface protocol, and respectively deploying the target AXI write requests in the third cache queue; saving each target AXI write request in the third cache queue in a preset target AXI write request cache module; converting the target AXI write request into a CHI write request of a corresponding request type of the CHI interface protocol according to the cache attribute of the target AXI write request in the target AXI write request cache module, and deploying the CHI write request in a fourth cache queue for managing CHI write requests; receiving each CHI write request periodically sent by the fourth cache queue through a preset function module for processing the CHI interface protocol, and after obtaining a write data response signal returned by the CHI write request, notifying the third cache queue to return an AXI write request completion response, while the fourth cache queue continues to process the write request according to the specification of the CHI protocol.

[0009] In one embodiment of the present disclosure, the write request processing according to the specification of the CHI protocol comprises: after receiving a write data transmittable response signal returned by the CHI write request through the preset request processing module, the write data transmittable response signal is forwarded to the corresponding target cache queue in the fourth cache queue; wherein the write data transmittable response signal is used to indicate the address of the write data involved in the target AXI write request to the lower module in the CHI protocol, and simultaneously notify the third cache queue; the write data involved in the target AXI write request is saved in the preset storage module of the target AXI write request; after the corresponding target cache queue in the fourth cache queue obtains the write data transmittable response signal, a read request is initiated to the storage module of the target AXI write request, the write data of the corresponding address is packaged into a write data packet and sent to the functional module processing the CHI interface protocol; the functional module processing the CHI interface protocol sends the write data packet, the corresponding target cache queue in the fourth cache queue completes the CHI protocol process of the current CHI write request, and then releases the fourth cache queue resource; the cache module of the target AXI write request corresponding to the write request identifier and the storage module of the target AXI write request are also released at the same time, and can be used for the next target AXI write request; at the same time, when the third cache queue receives the completion identifier of all the split target AXI write requests, a completion signal is sent to the functional module processing the AXI interface protocol, without waiting for the processing process of the fourth cache queue about the CHI interface protocol; based on the completion signal, the internal other cache resources are released and reset to the initial state of processing a new AXI write request, and the AXI write request process is completed; wherein the internal other cache resources include the cache of the third cache queue itself, the residual resources of the fourth cache queue, the local cache of the functional module processing the AXI interface protocol / CHI interface protocol, and the residual data of the storage module of the target AXI write request.

[0010] According to the second aspect of the embodiments of the present disclosure, an AXI protocol to CHI protocol conversion device is also provided, which comprises: a receiving module configured to receive an AXI request, the AXI request comprising an AXI read-write request; a splitting module configured to split the received AXI read-write request into a target AXI read-write request conforming to a data access type supported by the CHI interface protocol; a cache module configured to cache the split target AXI read-write request and write data involved in the target AXI write request; a conversion module configured to convert the target AXI read-write request into a read-write request of a corresponding request type of the CHI interface protocol, and convert the write data involved in the AXI write request into a write data of a corresponding data packet type of the CHI interface protocol; and a request processing module configured to receive the converted read-write request and write data, and process the request according to the specification of the CHI protocol.

[0011] According to a third aspect of the embodiments of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to implement the steps of the method for converting AXI protocol to CHI protocol as described above.

[0012] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer readable storage medium is provided, when instructions in the storage medium are executed by a processor, the processor is enabled to perform the method for converting AXI protocol to CHI protocol as described above.

[0013] The technical solutions provided by the embodiments of the present disclosure bring at least the following beneficial effects: Based on the total data amount required to be accessed by the AXI read / write request, the received AXI read / write request is split into a plurality of target AXI read / write requests conforming to the single data amount size of the CHI interface protocol; the target AXI read / write request after splitting and the involved write data are cached; the cached target AXI read / write request is converted into a read / write request of the corresponding request type of the CHI interface protocol; the write data is converted into write data of the corresponding data packet type of the CHI interface protocol; the converted read / write request and write data are received, and the request processing is performed according to the specification of the CHI protocol. Thus, through the splitting and conversion of the AXI request, a plurality of target AXI read / write requests can be operated at the same time, the parallelism of data access is improved; the data resources of different interface protocols are facilitated to be managed, and the conversion efficiency is improved.

[0014] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings incorporated in the specification hereof and forming a part thereof illustrate embodiments consistent with the present disclosure and together with the description are used to explain the principles of the present disclosure, and are not intended to limit the present disclosure.

[0016] Figure 1 Flow chart of the method for converting AXI protocol to CHI protocol of an embodiment of the present disclosure; Figure 2 Flow chart of the method for converting AXI protocol to CHI protocol of another embodiment of the present disclosure; Figure 3 Flow chart of the method for converting AXI protocol to CHI protocol of another embodiment of the present disclosure; Figure 4 Principle schematic diagram of the method for converting AXI protocol to CHI protocol of an embodiment of the present disclosure; Figure 5 Structural schematic diagram of the device for converting AXI protocol to CHI protocol of an embodiment of the present disclosure; Figure 6 A structural block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0017] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings.

[0018] It should be noted that the terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0019] Figure 1 A flowchart of a method of converting an AXI protocol to a CHI protocol according to an embodiment of the present disclosure. It should be noted that the method of converting an AXI protocol to a CHI protocol according to the present embodiment can be applied to a device for converting an AXI protocol to a CHI protocol, which can be configured in an electronic device to enable the electronic device to perform the function of converting an AXI protocol to a CHI protocol.

[0020] The electronic device can be any device with computing capability, such as a terminal device, a server, etc. In the following embodiments, the execution subject is taken as a terminal device for illustration.

[0021] As shown in FIG. 1, the method comprises the following steps: Figure 1 Step 101, receiving an AXI request, the AXI request comprising an AXI read-write request.

[0022] In the embodiments of the present disclosure, the AXI request can be received by a functional module for processing the AXI interface protocol, wherein the functional module for processing the AXI interface protocol is responsible for parsing each channel signal (such as a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel) in the AXI protocol and performing corresponding processing according to the protocol specification. For example, parsing the read-write request, managing data transmission, generating a response signal, etc.

[0023] Step 102, based on the total data amount required to be accessed by the AXI read-write request, splitting the received AXI read-write request into a plurality of target AXI read-write requests conforming to the single data amount size of the CHI interface protocol.​

[0024] In the embodiments of the present disclosure, the AXI read-write request can be split based on the total data amount required to be accessed by the AXI read-write request, so that the device using the AXI protocol can communicate with the device using the CHI protocol. For example, according to the CHI protocol specification, the information is reorganized into a request in the format supported by the CHI protocol. Through the splitting of the AXI read-write request, it can be identified whether there is an address associated with the AXI read-write request and does not need to be associated with the cache queue of the CHI read-write request. In the process of AXI to CHI, the AXI protocol interface is independently transmitted and received, and the CHI protocol interface is also independently transmitted and received.

[0025] In the embodiments of the present disclosure, the AXI read-write request can be split based on the total data amount required to be accessed by the AXI read-write request, so that the device using the AXI protocol can communicate with the device using the CHI protocol. For example, according to the CHI protocol specification, the information is reorganized into a request in the format supported by the CHI protocol. Through the splitting of the AXI read-write request, it can be identified whether there is an address associated with the AXI read-write request and does not need to be associated with the cache queue of the CHI read-write request. In the process of AXI to CHI, the AXI protocol interface is independently transmitted and received, and the CHI protocol interface is also independently transmitted and received.

[0026] Step 103, cache the target AXI read-write request after splitting and the write data involved in the target AXI write request.

[0027] In the embodiments of the present disclosure, the AXI read-write request can be split based on the total data amount required to be accessed by the AXI read-write request, so that the device using the AXI protocol can communicate with the device using the CHI protocol. For example, according to the CHI protocol specification, the information is reorganized into a request in the format supported by the CHI protocol. Through the splitting of the AXI read-write request, it can be identified whether there is an address associated with the AXI read-write request and does not need to be associated with the cache queue of the CHI read-write request. In the process of AXI to CHI, the AXI protocol interface is independently transmitted and received, and the CHI protocol interface is also independently transmitted and received.

[0028] Step 104, converting the cached target AXI read-write request into a read-write request of a corresponding request type of the CHI interface protocol; and converting the write data involved in the AXI write request into write data of a corresponding data packet type of the CHI interface protocol.

[0029] In the embodiments of the present disclosure, the AXI read-write request can be split based on the total data amount required to be accessed by the AXI read-write request, so that the device using the AXI protocol can communicate with the device using the CHI protocol. For example, according to the CHI protocol specification, the information is reorganized into a request in the format supported by the CHI protocol. Through the splitting of the AXI read-write request, it can be identified whether there is an address associated with the AXI read-write request and does not need to be associated with the cache queue of the CHI read-write request. In the process of AXI to CHI, the AXI protocol interface is independently transmitted and received, and the CHI protocol interface is also independently transmitted and received.

[0030] Step 105, receiving the converted read-write request and write data, and processing the request according to the specification of the CHI protocol.

[0031] In this embodiment of the disclosure, the functional module for processing the CHI interface protocol can receive the converted read / write requests and write data, parse the various channel signals in the CHI protocol (such as request channel, listening channel, response channel, data channel, etc.), and perform corresponding processing according to the CHI protocol specifications. For example, it can handle cache consistency requests, coordinate data access between multiple nodes, and maintain cache state.

[0032] It should be noted that, in this embodiment of the disclosure, as an example, the AXI interface has a burst length (LEN) bit width of 8 bits, a data size (SIZE) bit width of 3 bits, a data bit width of 256 bits, and supports burst types of fixed address burst, incremental address burst (INCR), and wraparound address burst (WRAP). The CHI interface does not have a LEN field, the DATA bit width is 256 bits, the SIZE bit width is 3 bits, the cache size is 512 bits, and the amount of data that can be accessed at one time is 512 bits. The method for converting the AXI protocol to the CHI protocol according to this embodiment of the disclosure splits the received AXI read / write request into multiple target AXI read / write requests with a single data volume size conforming to the CHI interface protocol, based on the total data volume required by the AXI read / write request. The split target AXI read / write requests and the related write data are cached. The cached target AXI read / write requests are converted into read / write requests of the corresponding request type of the CHI interface protocol. The write data is converted into write data of the corresponding data packet type of the CHI interface protocol. The converted read / write requests and write data are received and processed according to the CHI protocol specifications. Therefore, by splitting and converting AXI requests, multiple target AXI read / write requests can be operated simultaneously, improving the parallelism of data access; facilitating the management of data resources of different interface protocols; and improving conversion efficiency.

[0033] Figure 2 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to another embodiment of this disclosure. It should be noted that the AXI protocol to CHI protocol method of this embodiment can be applied to an AXI protocol to CHI protocol device, which can be configured in an electronic device to enable the electronic device to perform the AXI protocol to CHI protocol function.

[0034] The electronic device can be any device with computing capabilities, such as a terminal device or a server. The following embodiments use a terminal device as an example for illustration.

[0035] like Figure 2 As shown, the method includes the following steps: Step 201, receiving an AXI read request, wherein the AXI read request address has no correlation with the address in the first cache queue, and the first cache queue is a cache queue for managing the AXI read request.

[0036] In the embodiments of the present disclosure, as an example, the AXI read request is received by a functional module (AXI_HANDLE) for processing the AXI interface protocol, the AXI read request address is determined, it is judged whether the AXI read request address has correlation with the address previously entered into the first cache queue (AXI_QUEUE), if there is correlation, then wait, if there is no correlation, then apply to enter the AXI_QUEUE to continue subsequent processing, wherein the first cache queue (AXI_QUEUE) can include 16 items such as AXI_QUEUE0,..., AXI_QUEU15.

[0037] Step 202, based on the total data amount required to be accessed by the AXI read request, the AXI read request received is split into multiple target AXI read requests conforming to the single data amount size of the CHI interface protocol, and is respectively deployed in the first cache queue.

[0038] In the embodiments of the present disclosure, the AXI_QUEUE splits the target AXI read request received. In an example, the target AXI read request enters a first cache queue, enters the AXI_QUEUE0, and according to the read burst length (ARLEN), the read transmission granularity (ARSIZE), and the read burst type (ARBURST), the total data amount required to be accessed by the AXI read request is calculated. In an example, the AXI read request is: ARADDR='h1000, ARLEN='h5, ARCACHE[3:2]='h3, ARBURST=INCR; ARLEN='h5 indicates that 6 pieces of data are required to be returned by the AXI read request, ARSIZE='h5 indicates that the data length of single access is 256 bits of data, and ARBURST=INCR indicates that the burst type of this time is the incremental address burst mode; at this time, the total data amount is calculated as 6*256 bits. The AXI_QUEUE0 splits the AXI read request into the data access amount conforming to the CHI interface single time; then, the AXI read request is split into three target AXI read requests, the first one is: ARADDR='h1000, ARLEN='h1, ARSIZE='h5, ARCACHE[3:2]='h3, NEW_RID0='h1; the second one is: ARADDR='h1040, ARLEN='h1, ARSIZE='h5, ARCACHE[3:2]='h3, NEW_RID1='h2; the third one is: ARADDR='h1080, ARLEN='h1, ARSIZE='h5, ARCACHE[3:2]='h3, NEW_RID2='h3; and the values of other fields use the values of the original AXI read request before splitting. The RDONE_FLAG_CNT can also be added in the AXI_QUEUE, which is used to identify the number of split target AXI read requests. In an example, the number of split requests set by the RDONE_FLAG_CNT is 3, and the RDONE_FLAG_CNT is reduced by 1 each time a target AXI read request completion signal is received, and when the RDONE_FLAG_CNT is reduced to 0, it indicates that the split target AXI read request has been executed and completed.

[0039] In step 203, each target AXI read request in the first cache queue is saved in a preset target AXI read request cache module.

[0040] In the embodiments of the present disclosure, the split target AXI read request is saved in a preset cache module (AR_CMD_BUFFER) to cope with scenarios such as burst transmission, rate difference, or cross-clock domain transmission.

[0041] Step 204, according to the cache attribute of the target AXI read request in the cache module of the target AXI read request, the conversion of the CHI request is performed, the target AXI read request is converted into a CHI read request of the corresponding request type of the CHI interface protocol, and is arranged in a second cache queue for managing the CHI read request.

[0042] In the embodiment of the present disclosure, the second cache queue (CHI_QUEUE) can include 32 entries, for example, CHI_QUEUE0, CHI_QUEUE1, CHI_QUEUE2, CHI_QUEUE3, CHI_QUEUE4, CHI_QUEUE5, CHI_QUEUE6, CHI_QUEUE7, CHI_QUEUE8, CHI_QUEUE9, CHI_QUEUE10, CHI_QUEUE11, CHI_QUEUE12, CHI_QUEUE13, CHI_QUEUE14, CHI_QUEUE15, CHI_QUEUE16, CHI_QUEUE17, CHI_QUEUE18, CHI_QUEUE19, CHI_QUEUE20, CHI_QUEUE21, CHI_QUEUE22, CHI_QUEUE23, CHI_QUEUE24, CHI_QUEUE25, CHI_QUEUE26, CHI_QUEUE27, CHI_QUEUE28, CHI_QUEUE29, CHI_QUEUE30, and CHI_QUEUE31.

[0043] In the embodiment of the present disclosure, the target AXI read request in the AR_CMD_BUFFER enters the second cache queue (CHI_QUEUE) for processing, and three target AXI read requests enter different CHI_QUEUE queues in sequence. They are CHI_QUEUE0, CHI_QUEUE1, and CHI_QUEUE2. According to the cache attribute (ARCACHE, for example, cache state and transaction type) information in the target AXI read request, the CHI command is converted. If ARCACHE[3:2] is equal to 2'h0, the operation type (OPCODE) field of the request in the request packet (REQ_FLIT) of the CHI read request of the CHI protocol uses a non-snooping read request (READNOSNP), and the SIZE field is 256 bits. If ARCACHE[3:2] is not equal to 2'h0, the OPCODE field in the REQ_FLIT request packet of the CHI protocol uses a one-time read request (READONCE), and the SIZE field is 256 bits. Therefore, the key field values in the converted REQ_FLIT packet are as follows: the first REQ_FLIT packet: ADDR='h1000, OPCODE=READONCE, SIZE='h6; the second REQ_FLIT packet: ADDR='h1040, OPCODE=READONCE, SIZE='h6; and the third REQ_FLIT packet: ADDR='h1080, OPCODE=READONCE, SIZE='h6.

[0044] Step 205, each CHI read request periodically sent by the second cache queue is received by a preset functional module for processing the CHI interface protocol, and the read request processing is performed according to the specification of the CHI protocol.

[0045] In the embodiment of the present disclosure, the converted CHI read request is sent to the functional module (CHI_HANDLE) for processing the CHI interface protocol. One REQ_FLIT request packet can be sent in each period, and there is no need to wait for the completion of the processing of the previous CHI read request.

[0046] Step 206, the read response data returned by the CHI read request is received by the preset function module processing CHI interface protocol and is forwarded to the corresponding target cache queue in the second cache queue; wherein, the read response data contains the read data block and the read request identifier.

[0047] In the embodiment of the present disclosure, the CHI_HANDLE will receive the read response data (DATA_FLIT package) returned by the read request, and forward the received DATA_FLIT package to the corresponding CHI_QUEUE. In the example, the first returned DATA_FLIT package corresponds to CHI_QUEUE5, and the CHI_HANDLE sends the DATA_FLIT package to CHI_QUEUE1, and CHI_QUEUE1 continues to wait for the second DATA_FLIT package. The CHI_HANDLE receives the second DATA_FLIT package which also corresponds to CHI_QUEUE5, and the CHI_HANDLE sends the DATA_FLIT to CHI_QUEUE1. After CHI_QUEUE1 receives the required two DATA_FLIT packages, a completion confirmation response package (SRSP_FLIT) is generated, and the SRSP_FLIT is sent to the CHI_HANDLE and forwarded to the corresponding target cache queue in the second cache queue.

[0048] Wherein, the read response data can also contain an error check code for verifying the correctness of the read response data.

[0049] Step 207, after the corresponding target cache queue in the second cache queue obtains the read response data, the CHI interface handshake protocol is first completed, then the data block and the read request identifier are written into the preset target AXI read request storage module, and the first cache queue is notified that the current CHI read request has been completed. At the same time, the second cache queue is released, and the corresponding target AXI read request cache module of the read request identifier is also released at the same time, which can be used for the next target AXI read request.

[0050] In the embodiment of the present disclosure, after being forwarded to the corresponding target cache queue in the second cache queue, the CHI_HANDLE notifies the outside that the CHI read request process is completed, at the same time, the CHI_QUEUE1 writes the data block and the corresponding read request identifier (NEW_RID1) into the target AXI read request storage module (R_DATA_BUFFER), and then notifies the first cache queue that the current CHI read request has been completed. Finally, the completion status is updated to the AXI_QUEUE0, and the RDONE_FLAG_CNT of the AXI_QUEUE0 is reduced by 1. The CHI_QUEUE1 releases the queue, and the AR_CMD_BUFFER corresponding to the NEW_RID is also released at the same time, which can be used for the next request.

[0051] Step 208, after the first cache queue receives that all the split target AXI read requests have been completed, the data blocks are read from the storage module based on the read request identifier and returned to the functional module for processing the AXI interface protocol.

[0052] In the embodiments of the present disclosure, similarly, CHI_QUEUE0 and CHI_QUEUE2 perform the same steps of steps 206 and 207, and the CHI_QUEUE0 and CHI_QUEUE2 queues are released, and the AR_CMD_BUFFER corresponding to the NEW_WID is also released at the same time. The final result of the RDONE_FLAG_CNT of the AXI_QUEUE0 is 0, which indicates that the AXI_QUEUE1 has completed all the split target AXI read requests, and the data blocks required by all the target AXI read requests have been saved in the R_DATA_BUFFER. The execution of the CHI_QUEUE0, CHI_QUEUE1 and CHI_QUEUE2 is not limited by the order.

[0053] Step 209, the handshake process of the AXI protocol end based on the functional module for processing the AXI interface protocol is performed, and the AXI read request process is completed.

[0054] In the embodiments of the present disclosure, when the RDONE_FLAG_CNT in the AXI_QUEUE0 is 0, the AXI_QUEUE0 starts subsequent processing, the AXI_QUEUE0 reads data from the R_DATA_BUFFER according to the currently saved NEW_RID value, and obtains data in the order of NEW_RID0, NEW_RID1 and NEW_RID2, and the corresponding R_DATA_BUFFER is released. The AXI_QUEUE0 further sends the data to the AXI_HANDLE in sequence for AXI protocol communication, and provides corresponding read data valid signals (RVALID), read data signals (RDATA) and the like, when 6 target AXI read requests have been completed AXI protocol handshake, the AXI_QUEUE0 is released, and the entire AXI read request processing flow is completed.

[0055] In the method for converting the AXI protocol to the CHI protocol, an AXI read request is received, wherein the AXI read request address has no correlation with the address in the first cache queue, and the first cache queue is a cache queue for managing the AXI read request; based on the total data amount of the AXI read request, the received AXI read request is split into a plurality of target AXI read requests conforming to the single data amount size of the CHI interface protocol, and the target AXI read requests are respectively arranged in the first cache queue; the target AXI read requests in the first cache queue are stored in a preset target AXI read request cache module; the target AXI read requests in the target AXI read request cache module are converted into CHI read requests of a corresponding request type of the CHI interface protocol according to the cache attribute of the target AXI read requests, and the target AXI read requests are arranged in a second cache queue for managing the CHI read requests; each CHI read request periodically sent by the second cache queue is received through a preset functional module for processing the CHI interface protocol, and the read request processing is performed according to the specification of the CHI protocol; the read response data returned by the CHI read request is received through the preset functional module for processing the CHI interface protocol, and the read response data is forwarded to the corresponding target cache queue in the second cache queue; wherein the read response data includes a read data block and a read request identifier; after obtaining the read response data, the corresponding target cache queue in the second cache queue first completes the CHI interface handshake protocol, then writes the data block and the read request identifier into a preset target AXI read request storage module, and notifies the first cache queue that the current CHI read request is completed; at the same time, the second cache queue is released, and the target AXI read request cache module corresponding to the read request identifier is also released at the same time, and can be used for the next target AXI read request; after receiving that all the split target AXI read requests are completed, each data block is read from the storage module based on the read request identifier and returned to the functional module for processing the AXI interface protocol; the handshake processing of the AXI protocol end is performed based on the functional module for processing the AXI interface protocol, and the current AXI read request process is completed. In this way, by splitting the AXI read request, converting the protocol and managing the cache queue, the problems of data amount mismatch between the AXI and the CHI protocol, complex cache management and handshake protocol difference are solved.

[0056] Figure 3 The flowchart of the method for converting the AXI protocol to the CHI protocol of one embodiment of the present disclosure. It should be noted that the method for converting the AXI protocol to the CHI protocol of the present embodiment can be applied to a device for converting the AXI protocol to the CHI protocol, and the device can be configured in an electronic device, so that the electronic device can perform the function of converting the AXI protocol to the CHI protocol.

[0057] The electronic device can be any device with computing capability, such as a terminal device or a server. In the following embodiments, the terminal device is taken as an example for illustration.

[0058] As shown in Figure 3 The method comprises the following steps: Step 301, receiving an AXI write request, wherein the AXI write request address has no correlation with the address in the third cache queue, and the third cache queue is a cache queue for managing the AXI write request.

[0059] In the embodiments of the present disclosure, as an example, the AXI write request can be received by a functional module processing the AXI interface protocol, it is judged whether the AXI write request has correlation with the address previously entering the third cache queue (AXI_QUEUE), if there is correlation, it is waited, if there is no correlation, it is applied to enter the AXI_QUEUE to continue subsequent processing, at the same time, the write data corresponding to the write AXI write request is started to be received.

[0060] Step 302, based on the total data amount of the AXI write request, the received AXI write request is split into multiple target AXI write requests conforming to the single data amount size of the CHI interface protocol, and is respectively deployed in the third cache queue.

[0061] The third cache queue can be implemented by the first cache queue (AXI_QUEUE) described above, and can include 16 items, for example, AXI_QUEUE0,..., AXI_QUEU15.

[0062] In the embodiments of the present disclosure, the AXI protocol data conversion module receives the AXI write request and the completion, and then performs subsequent analysis. The AXI write request enters the AXI_QUEUE1, and the total data amount required to be accessed by the AXI write request is calculated according to the read burst length (AWLEN), the read transmission granularity (AWSIZE) and the read burst type (AWBURST). In the example, the AXI write request is: AWADDR='h2000, AWLEN='h5, AWCACHE[3:2]='h3, AWBURST=INCR; AWLEN='h5 indicates that 6 pieces of data are required to be returned by the AXI write request, ARSIZE='h5 indicates that the data length of single access is 256 bits of data, and ARBURST=INCR indicates that the burst type of this time is an incremental address burst mode. The valid bits (WSTRB) of the 6 pieces of data are: WSTRB0=32 'hffffffff, WSTRB1=32 'hffffffff, WSTRB2=32 'hffffffff, WSTRB3=32 'hffffffff, WSTRB4=32 'hffffffff, and WSTRB5=32 'haaaaaaaa. At this time, the total operation data amount of the AXI write request calculated is 6*256 bits. The AXI_QUEUE1 splits the AXI write request into single data access amount conforming to the CHI interface, and inserts a write data valid signal (WSTRB_ALL_EN) identifier into the split target AXI write request. For example, the AXI write request is split into three AXI write requests: The first one is: AWADDR='h2000, AWLEN='h1, AWSIZE='h5, AWCACHE[3:2]='h3, WSTRB_ALL_EN0=&(WSTRB0&WSTRB1), NEW_WID0='h100, NEW_DATA0={DATA1, DATA0}, NEW_WSTRB0={WSTRB1, WSTRB0}; The second one is: AWADDR='h2040, AWLEN='h1, AWSIZE='h5, AWCACHE[3:2]='h3, WSTRB_ALL_EN1=&(WSTRB2&WSTRB3), NEW_WID1='h101, NEW_DATA1={DATA3, DATA2}, NEW_WSTRB1={WSTRB3, WSTRB2}; The third: AWADDR='h2080, AWLEN='h1, AWSIZE='h5, AWCACHE[3:2]='h3; WSTRB_ALL_EN2=&(WSTRB4&WSTRB5), NEW_WID2='h102, NEW_DATA2={DATA5, DATA4}, NEW_WSTRB2={WSTRB5, WSTRB4}.

[0063] The values of other fields use the values of the original AXI write request before splitting. The WDONE_FLAG_CNT is added in the AXI_QUEUE to identify the number of split target AXI write requests. In the example, the number of split requests set by WDONE_FLAG_CNT is 3, and the WDONE_FLAG_CNT is reduced by 1 for each received write request completion signal, and when it is reduced to 0, it indicates that the split target AXI write request has been executed and completed.

[0064] In step 303, the target AXI write requests in the third cache queue are saved in the preset target AXI write request cache module.

[0065] In the embodiments of the present disclosure, the split target AXI write requests are saved into the target AXI write request cache module (AW_CMD_BUFFER). This is to cope with scenarios such as burst transmission, rate difference, or cross-clock domain transmission.

[0066] In step 304, the target AXI write requests are converted into CHI write requests of the corresponding request type of the CHI interface protocol according to the cache attributes of the target AXI write requests in the target AXI write request cache module, and are deployed in the fourth cache queue for managing the CHI write requests.

[0067] The fourth cache queue can be implemented by the second cache queue (CHI_QUEUE) described above, and can include 32 items, for example, CHI_QUEUE0,..., CHI_QUEUE32.

[0068] In the embodiments of the present disclosure, the target AXI write request application in the AW_CMD_BUFFER enters the CHI_QUEUE for processing, and three write requests enter different CHI_QUEUE queues in sequence. The three write requests are CHI_QUEUE3, CHI_QUEUE4 and CHI_QUEUE5, and the conversion of the CHI command is performed according to the cache attribute (AWCACHE) in the target AXI write request and the information of WSTRB_ALL_EN. If AWCACHE[3:2] is equal to 2 'h0 and WSTRB_ALL_EN is 0, the OPCODE field in the REQ_FLIT of the CHI write request of the CHI protocol uses the non-monitoring partial write request (WRITENOSNPPTL); if AWCACHE[3:2] is equal to 2 'h0 and WSTRB_ALL_EN is 1, the OPCODE field in the REQ_FLIT of the CHI protocol uses the non-monitoring full write request (WRITENOSNPFULL); if AWCACHE[3:2] is not equal to 2 'h0 and WSTRB_ALL_EN is 0, the OPCODE field in the REQ_FLIT of the CHI protocol uses the write unique partial cache line request (WRITEUNIQUEPTL); if AWCACHE[3:2] is not equal to 2 'h0 and WSTRB_ALL_EN is 1, the OPCODE field in the REQ_FLIT of the CHI protocol uses the write unique full cache line request (WRITEUNIQUEFULL); in the example, the key field values in the converted REQ_FLIT packet are as follows: the first REQ_FLIT packet: ADDR='h2000, OPCODE=WRITEUNIQUEFULL, SIZE='h6; the second REQ_FLIT packet: ADDR='h2040, OPCODE=WRITEUNIQUEFULL, SIZE='h6; and the third REQ_FLIT packet: ADDR='h2080, OPCODE=WRITEUNIQUEPTL, SIZE='h6.

[0069] In step 305, each CHI write request sent by the fourth cache queue in a cycle is received by the preset function module for processing the CHI interface protocol, and after obtaining the write data sending response signal, the AXI request queue is notified to return the AXI write request completion response, and the fourth cache queue continues to process the write request according to the specification of the CHI protocol.

[0070] In the embodiments of the present disclosure, the converted CHI write request is sent to the CHI_HANDLE module, and one REQ_FLIT request packet can be sent in each cycle without waiting for the completion of the processing of the previous CHI write request.

[0071] Step 306, after receiving the write data transmittable response signal returned by the CHI write request through the preset request processing module, the corresponding target cache queue in the fourth cache queue is forwarded; wherein, the write data transmittable response signal is used to indicate the address of the write data involved in the target AXI write request to the lower module in the CHI protocol, and at the same time, the third cache queue is notified; the write data involved in the target AXI write request is saved in the preset storage module of the target AXI write request.

[0072] Wherein, when the split target AXI write request is saved to the cache module (AW_CMD_BUFFER) of the target AXI write request, at the same time, the write data is stored in the storage module (W_DATA_BUFFER) of the target AXI write request. In addition, the corresponding write data valid bit and write request identifier are also stored in W_DATA_BUFFER, which is used to verify and identify the write data.

[0073] In the embodiment of the present disclosure, at this time, the write data is also in W_DATA_BUFFER, and CHI_HANDLE will receive the write data transmittable response signal (CRSP_FLIT) corresponding to the target AXI write request, and the function of CRSP_FLIT in the CHI protocol is to indicate the address of the write data involved in the target AXI write request to the lower module, and at the same time, the third cache queue is notified. CHI_HANDLE forwards the received CRSP_FLIT to the corresponding CHI_QUEUE. In the example, it is assumed that the first returned CRSP_FLIT corresponds to CHI_QUEUE5, then CHI_QUEUE5 carries out subsequent processing.

[0074] Step 307, after the corresponding target cache queue in the fourth cache queue obtains the write data transmittable response signal, a read request is initiated to the storage module of the target AXI write request, and the write data of the corresponding address is sent to the functional module processing the CHI interface protocol as a write data packet.

[0075] In the embodiment of the present disclosure, after the CHI_QUEUE5 receives the CRSP_FLIT, the CHI_QUEUE5 initiates a data request to the W_DATA_BUFFER using the write request identifier (NEW_WID2), reads the write data out into the CHI_QUEUE5, and generates two write data (DATA_FLIT) packets. The DATA field in the first DATA_FLIT has a value of DATA4, and the BE field has a value of WSTRB4. The DATA field in the second DATA_FLIT has a value of DATA5, and the BE field has a value of WSTRB5. Then, the two DATA_FLIT packets are sent to the CHI_HANDLE module in sequence, the CHI_HANDLE sends the write data packets, and the CHI write request processing flow is completed. At the same time, after the third cache queue receives the write data sendable response signal, the WDONE_FLAG_CNT is decremented by 1.

[0076] In step 308, the function module processing the CHI interface protocol sends the write data packet, the corresponding target cache queue in the fourth cache queue completes the CHI protocol flow of the current CHI write request, and then releases the fourth cache queue resource. The target AXI write request cache module corresponding to the write request identifier and the target AXI write request storage module are also released at the same time, and can be used for the next target AXI write request.

[0077] In the embodiment of the present disclosure, after the CHI_QUEUE5 processing is completed, the CHI_QUEUE5 releases the queue, and the AW_CMD_BUFFER and the W_DATA_BUFFER corresponding to the NEW_WID are also released at the same time, and can be used for the next request.

[0078] In step 309, when the third cache queue receives the completion identifier of all the split target AXI write requests, a completion signal is sent to the function module processing the AXI interface protocol, and there is no need to wait for the processing flow of the CHI interface protocol in the fourth cache queue.

[0079] In the embodiments of the present disclosure, similarly, after the steps 306, 307, and 308 are performed, the CHI_QUEUE3 and the CHI_QUEUE4 are released, and the AW_CMD_BUFFER and the W_DATA_BUFFER corresponding to the NEW_WID are also released. Meanwhile, the final result of the WDONE_FLAG_CNT of the AXI_QUEUE1 is 0, which indicates that the AXI_QUEUE1 has completed all the split target AXI write requests. When the WDONE_FLAG_CNT is 0, it is the write completion flag of the AXI write request. At this time, a completion signal can be sent to the functional module for processing the AXI interface protocol, and there is no need to wait for the subsequent processing flow of the CHI_QUEUE about the CHI interface protocol to be completed. The execution of the CHI_QUEUE3, the CHI_QUEUE4, and the CHI_QUEUE5 is not limited by the order, and the execution of the AXI_QUEUE1 is not limited by the CHI_QUEUE after the WDONE_FLAG_CNT is 0.

[0080] In the step 310, based on the completion signal, internal other cache resources are released, and a reset to an initial state for processing a new AXI write request is performed, and the AXI write request flow is completed.

[0081] In the embodiments of the present disclosure, the AXI_QUEUE1 provides a completion signal (BVALID) return to the AXI_HANDLE module, indicating that the write target AXI write request is valid. After the AXI_HANDLE module completes the AXI protocol communication (performs the handshake processing of the AXI protocol end), the AXI_QUEUE1 is released, and the entire AXI write request processing flow is completed, and can be used for subsequent new AXI write requests. The internal other cache resources include a third cache queue self cache, a residual resource of a fourth cache queue, a local cache of a functional module for processing the AXI interface protocol / CHI interface protocol, and residual data of a storage module of a target AXI write request.

[0082] In the method for converting the AXI protocol to the CHI protocol, an AXI write request is received, wherein the AXI write request address has no correlation with the address in the third cache queue, and the third cache queue is a cache queue for managing the AXI write request; based on the total data amount of the AXI write request, the received AXI write request is split into a plurality of target AXI write requests conforming to the single data amount size of the CHI interface protocol, and the target AXI write requests are respectively deployed in the third cache queue; each target AXI write request in the third cache queue is saved in a preset target AXI write request cache module; the target AXI write request is converted into a CHI write request of a corresponding request type of the CHI interface protocol according to the cache attribute of the target AXI write request in the target AXI write request cache module, and the CHI write request is deployed in a fourth cache queue for managing the CHI write request; each CHI write request periodically sent by the fourth cache queue is received through a preset functional module for processing the CHI interface protocol, and the write request processing is performed according to the specification of the CHI protocol; after receiving the write data transmittable response signal returned by the CHI write request through a preset request processing module, the write data transmittable response signal is forwarded to the corresponding target cache queue in the fourth cache queue; the write data transmittable response signal is used to indicate that the write-in data involved in the target AXI write request is written to the address of the lower module, and the third cache queue is simultaneously notified; the write-in data involved in the target AXI write request is saved in a preset target AXI write request storage module; after obtaining the write data transmittable response signal, the corresponding target cache queue in the fourth cache queue initiates a read request to the target AXI write request storage module, and the write-in data of the corresponding address is packed into a write data packet and sent to the functional module for processing the CHI interface protocol; the functional module for processing the CHI interface protocol sends the write data packet, the corresponding target cache queue in the fourth cache queue completes the CHI protocol process of the current CHI write request, and then releases the fourth cache queue resource; the target AXI write request cache module and the target AXI write request storage module corresponding to the write request identifier are also simultaneously released, and can be used for the next target AXI write request; meanwhile, when the third cache queue receives the completion identifier of all the split target AXI write requests, a completion signal is sent to the functional module for processing the AXI interface protocol, and the processing process of the CHI interface protocol in the fourth cache queue is not needed to wait; based on the completion signal, the internal other cache resources are released, and the initial state for processing a new AXI write request is reset, and the current AXI write request process is completed. Therefore, in combination with the cross-protocol cache management mechanism of the AXI and CHI protocols, the efficient data interaction between the AXI and CHI protocols is realized through the multi-level cache queue and the protocol conversion module, the write request on the AXI interface can obtain the write completion response in advance, and the overall efficiency of the write channel is improved.

[0083] In summary, in order to clearly describe the principle of the method for converting the AXI protocol to the CHI protocol,Figure 4 This is a schematic diagram illustrating the principle of a method for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure, as shown below. Figure 4 As shown. The AXI protocol function processing module receives and processes AXI requests. The AXI protocol data conversion module splits the received AXI requests into target AXI read / write requests conforming to the data access types supported by the CHI interface protocol (e.g., multiple target AXI read / write requests conforming to the single data volume size of the CHI interface protocol). The AXI request command buffer and data buffer module caches the parsed target AXI read / write requests and the related write data. The AXI command to CHI command module converts the target AXI read / write requests into read / write requests of the corresponding request type in the CHI interface protocol; and converts the write data involved in the AXI write request into write data of the corresponding data packet type in the CHI interface protocol. The CHI protocol function processing module receives the converted read / write requests and write data, and processes the requests according to the CHI protocol specifications.

[0084] like Figure 4 As shown, the AXI protocol data conversion module, in this example, uses 16 first or third buffer queues (AXI_QUEUE0, ..., AXI_QUEUE15) for illustration; the AXI request command buffer and data buffer module includes a buffer module for target AXI read requests (AR_CMD_BUFFER), a storage module for target AXI read requests (R_DATA_BUFFER), a buffer module for target AXI write requests (AW_CMD_BUFFER), and a storage module for target AXI write requests (W_DATA_BUFFER); the AXI command to CHI command module, in this example, uses 32 second or fourth buffer queues (CHI_QUEUE0, ..., CHI_QUEUE31) for illustration.

[0085] Figure 5 This is a schematic diagram of the structure of an AXI protocol to CHI protocol device according to an embodiment of the present disclosure.

[0086] like Figure 5 As shown, this is an apparatus for converting the AXI protocol to the CHI protocol, comprising: a receiving module 501, a splitting module 502, a caching module 503, a conversion module 504, and a request processing module 505. The receiving module 501 is used to receive AXI requests, including AXI read / write requests. The splitting module 502 is used to split the received AXI read and write requests into multiple target AXI read and write requests that conform to the single data volume size of the CHI interface protocol, based on the total amount of data that the AXI read and write requests need to access. The cache module 503 is configured to cache the split target AXI read-write request and write data involved in the target AXI write request. The conversion module 504 is configured to convert the cached target AXI read-write request into a read-write request of a corresponding request type of the CHI interface protocol, and convert the write data involved in the AXI write request into write data of a corresponding data packet type of the CHI interface protocol. The request processing module 505 is configured to receive the converted read-write request and write data, and perform request processing according to the specification of the CHI protocol.

[0087] In one embodiment of the present disclosure, in response to the target AXI request being an AXI read request, the apparatus comprises: a receiving module 501 configured to receive the AXI read request, wherein the AXI read request address has no correlation with an address in a first cache queue, and the first cache queue is a cache queue for managing AXI read requests; a splitting module 502 configured to split the received AXI read request based on a total data amount to be accessed by the AXI read request, to split the AXI read request into a plurality of target AXI read requests conforming to a single data amount size of the CHI interface protocol, and to respectively deploy the target AXI read requests in the first cache queue; a cache module 503 configured to save each target AXI read request in the first cache queue in a preset target AXI read request cache module; a conversion module 504 configured to perform CHI request conversion according to a cache attribute of the target AXI read request in the target AXI read request cache module, to convert the target AXI read request into a CHI read request of a corresponding request type of the CHI interface protocol, and to deploy the CHI read request in a second cache queue for managing CHI read requests; and a request processing module 505 configured to receive each CHI read request periodically sent by the second cache queue through a preset functional module for processing the CHI interface protocol, and to perform read request processing according to the specification of the CHI protocol.

[0088] In one embodiment of the present disclosure, the read request processing according to the specification of the CHI protocol includes: a first forwarding module configured to receive read response data returned by a CHI read request through a preset functional module for processing the CHI interface protocol, and forward the read response data to a corresponding target cache queue in a second cache queue; wherein the read response data includes a read data block and a read request identifier; a writing module configured to, after the corresponding target cache queue in the second cache queue obtains the read response data, first complete a CHI interface handshake protocol, and then write the data block and the read request identifier into a preset target AXI read request storage module, and notify a first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and a target AXI read request cache module corresponding to the read request identifier is also released at the same time, and can be used for a next target AXI read request; a first reading module configured to, after the first cache queue receives that all split target AXI read requests have been completed, read each data block from the storage module based on the read request identifier and return the data block to a functional module for processing the AXI interface protocol; and a first processing module configured to perform handshake processing at an AXI protocol end based on the functional module for processing the AXI interface protocol, and complete the current AXI read request process.

[0089] In one embodiment of the present disclosure, in response to the target AXI request being an AXI write request, the device includes: a receiving module 501 configured to receive an AXI write request, wherein the AXI write request address has no correlation with an address in a third cache queue, and the third cache queue is a cache queue for managing AXI write requests; a splitting module 502 configured to split the received AXI write request based on a total data amount of the AXI write request, and split the AXI write request into a plurality of target AXI write requests conforming to a single data amount size of a CHI interface protocol, and deploy the target AXI write requests in the third cache queue respectively; a cache module 503 configured to save each target AXI write request in the third cache queue in a preset target AXI write request cache module; a conversion module 504 configured to convert a CHI request according to a cache attribute in the target AXI write request in the target AXI write request cache module, convert the target AXI write request into a CHI write request of a corresponding request type of the CHI interface protocol, and deploy the CHI write request in a fourth cache queue for managing CHI write requests; and a request processing module 505 configured to receive each CHI write request periodically sent by the fourth cache queue through a preset functional module for processing the CHI interface protocol, notify an AXI request queue to return an AXI write request completion response after obtaining a write data sendable response signal, and at the same time, the fourth cache queue continues to process the write request according to the specification of the CHI protocol.

[0090] In one embodiment of the present disclosure, the device further comprises: a second forwarding module, configured to, after receiving a write data transmittable response signal returned by the preset request processing module to the CHI write request, forward to a corresponding target cache queue in the fourth cache queue; wherein the write data transmittable response signal is used to indicate, in the CHI protocol, an address of write data involved in the target AXI write request to be written to a lower module, and simultaneously notify the third cache queue; the write data involved in the target AXI write request is saved in a preset target AXI write request storage module; a second reading module, configured to, after the corresponding target cache queue in the fourth cache queue obtains the write data transmittable response signal, initiate a read request to the target AXI write request storage module, and send the write data of the corresponding address to a functional module processing the CHI interface protocol in a write data packet; a first sending module, configured to, after the functional module processing the CHI interface protocol sends the write data packet, the corresponding target cache queue in the fourth cache queue completes the CHI protocol process of the current CHI write request, and then releases the fourth cache queue resource, the target AXI write request cache module and the target AXI write request storage module corresponding to the write request identifier are also released at the same time, and can be used for the next target AXI write request; at the same time, when the third cache queue receives completion identifiers of all the split target AXI write requests, a completion signal is sent to the functional module processing the AXI interface protocol, without waiting for the processing process of the CHI interface protocol in the fourth cache queue; a second processing module, configured to, based on the completion signal, release internal other cache resources and reset to an initial state of processing a new AXI write request, to complete the AXI write request process; wherein the internal other cache resources include a third cache queue itself cache, a residual resource of the fourth cache queue, a local cache of the functional module processing the AXI interface protocol / CHI interface protocol, and residual data of the target AXI write request storage module.

[0091] The device for converting the AXI protocol to the CHI protocol in the embodiment of the present disclosure splits the received AXI read / write request into a plurality of target AXI read / write requests conforming to the single data size of the CHI interface protocol based on the total data amount required to be accessed by the AXI read / write request; caches the split target AXI read / write request and the write data involved; converts the cached target AXI read / write request into a read / write request of a corresponding request type of the CHI interface protocol; converts the write data into a write data of a corresponding data packet type of the CHI interface protocol; receives the converted read / write request and write data, and processes the request according to the specification of the CHI protocol. In this way, through the splitting and conversion of the AXI request, a plurality of target AXI read / write requests can be operated at the same time, the parallelism of data access is improved, the data resources of different interface protocols are facilitated to be managed, and the conversion efficiency is improved.

[0092] According to a third aspect of the present disclosure, an electronic device is also provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor is configured to: implement the method of converting the AXI protocol to the CHI protocol as described above.

[0093] To implement the above embodiments, this disclosure also proposes a storage medium.

[0094] When the instructions in the storage medium are executed by the processor, the processor is able to execute the AXI protocol to CHI protocol method as described above.

[0095] To implement the above embodiments, this disclosure also provides a computer program product.

[0096] When the computer program product is executed by the processor of the electronic device, it enables the electronic device to perform the above-described method.

[0097] Figure 6 This is a structural block diagram of an electronic device according to an exemplary embodiment. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0098] like Figure 6 As shown, the electronic device 600 includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from memory 606 into a random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device 600. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0099] The following components are connected to I / O interface 605: memory 606 including hard disk; and communication section 607 including network interface card such as local area network (LAN) card, modem, etc., communication section 607 performs communication processing via network such as Internet; driver 608 is also connected to I / O interface 605 as needed.

[0100] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program carried on a computer-readable medium, the computer program containing program code for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication section 607. When the computer program is executed by the processor 601, the above-described functions defined in the methods of the present disclosure are executed.

[0101] In an exemplary embodiment, a storage medium including instructions, such as a memory including instructions, is also provided, which can be executed by the processor 601 of the electronic device 600 to complete the above-described methods. Optionally, the storage medium can be a non-transitory computer-readable storage medium, for example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0102] In the present disclosure, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, the computer readable signal medium can include a data signal that propagates in a baseband or as part of a carrier wave, in which the computer readable program code is carried. Such a propagated data signal can take a variety of forms, including but not limited to electro-magnetic, optical, or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport program for use by or in connection with an instruction execution system, apparatus, or device. Program code contained on a computer readable medium can be transmitted by any suitable medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0103] Furthermore, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Thus, use of the articles in this application and the following claims is not limiting.

[0104] Also, although the disclosure has been described with respect to only one or more implementations thereof, those skilled in the art will readily appreciate that other alternatives can be used. It is contemplated that the disclosure can be carried out in other specific ways than those expressly disclosed herein. Any and all such changes, modifications, variations, and improvements that have been or can be made to the disclosure are intended to be included within the scope of the disclosure. Specifically with respect to the various functions performed by the components (e.g., elements, resources, etc.) described above, unless otherwise specified, the terms used are intended to encompass any component which performs the specified function (functionally equivalent), even if not structurally equivalent. Additionally, although a particular feature of the disclosure can have been disclosed with respect to only one of several implementations, other implementations can include the particular feature. It is, therefore, contemplated that features described with respect to one implementation can be incorporated in other implementations as appropriate, and vice versa. Still further, the order in which operations are described is not necessarily the order in which the operations are performed. Also, the terms "include," "have," "possess," "contain," and "comprise" and their conjugates, as used herein, are used inclusively and in the negative thereof, "does not include," "does not have," "does not possess," "does not contain," and "does not comprise," are each intended to be understood in the manner as set forth in the State Street Bank v. Signature Financial Group, Inc., 149 F.3d 1368, 1373 (Fed. Cir. 1998) decision.

[0105] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features of the disclosure disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

[0106] It is understood that the present disclosure is not limited to the precise construction disclosed and as illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A method for converting AXI protocol to CHI protocol, characterized in that, The method includes: Receive AXI requests, including AXI read and write requests; Based on the total amount of data that the AXI read / write request needs to access, the received AXI read / write request is split into multiple target AXI read / write requests that conform to the single data volume size of the CHI interface protocol. The split target AXI read / write requests and the write data involved in the target AXI write requests are cached. Convert the cached target AXI read / write request into a read / write request of the corresponding request type in the CHI interface protocol; convert the write data involved in the AXI write request into write data of the corresponding data packet type in the CHI interface protocol; It receives the converted read / write requests and write data, and processes the requests according to the CHI protocol specifications.

2. The method according to claim 1, characterized in that, In response to the target AXI request being an AXI read request, the method includes: Receive an AXI read request, wherein the address of the AXI read request is not related to the address in the first cache queue, and the first cache queue is a cache queue that manages AXI read requests; Based on the total amount of data that the AXI read request needs to access, the received AXI read request is split into multiple target AXI read requests that conform to the single data volume size of the CHI interface protocol, and deployed in the first cache queue respectively. Each target AXI read request in the first cache queue is stored in a preset target AXI read request cache module; Based on the cache attributes of the target AXI read request in the cache module of the target AXI read request, the CHI request is converted into a CHI read request of the corresponding request type of the CHI interface protocol and deployed in the second cache queue that manages CHI read requests. The system receives each CHI read request periodically sent by the second cache queue through a pre-defined functional module that processes the CHI interface protocol, and processes the read requests in accordance with the specifications of the CHI protocol.

3. The method according to claim 2, characterized in that, The process of handling read requests according to the CHI protocol specifications includes: The pre-defined functional module for processing the CHI interface protocol receives the read response data returned by the CHI read request and forwards it to the corresponding target cache queue in the second cache queue; the read response data includes the data block to be read and the read request identifier; After the target cache queue in the second cache queue obtains the read response data, it first completes the CHI interface handshake protocol, then writes the data block and read request identifier into the preset storage module of the target AXI read request, and notifies the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, which can be used by the next target AXI request. Once the first cache queue has received all the split target AXI read requests and completed them, it reads each data block from the storage module based on the read request identifier and returns it to the functional module that processes the AXI interface protocol. Based on the functional module for processing the AXI interface protocol, the handshake process on the AXI protocol side is performed to complete the AXI read request process.

4. The method according to claim 2, characterized in that, In response to the target AXI request being an AXI write request, the method includes: Receive an AXI write request, wherein the address of the AXI write request is not related to the address in the third cache queue, and the third cache queue is a cache queue that manages AXI write requests; Based on the total data volume of the AXI write requests, the received AXI write requests are split into multiple target AXI write requests that conform to the single data volume size of the CHI interface protocol, and deployed in the third cache queue respectively. Each target AXI write request in the third cache queue is stored in a preset target AXI write request cache module; Based on the cache attributes of the target AXI write request in the cache module of the target AXI write request, the CHI request is converted into a CHI write request of the corresponding request type of the CHI interface protocol and deployed in the fourth cache queue that manages CHI write requests. The pre-defined CHI interface protocol processing module receives each CHI write request periodically sent by the fourth cache queue. After receiving the write data response signal returned by the CHI write request, it notifies the third cache queue to return the AXI write request completion response. At the same time, the fourth cache queue continues to process the write request according to the CHI protocol specification.

5. The method according to claim 4, characterized in that, The write request processing according to the CHI protocol specifications includes: After receiving the write data response signal returned by the CHI write request through the preset request processing module, the module forwards it to the corresponding target cache queue in the fourth cache queue. The write data response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and at the same time notifies the third cache queue. The write data involved in the target AXI write request is stored in the preset target AXI write request storage module. After the target cache queue in the fourth cache queue receives the write data and sends a response signal, it initiates a read request to the storage module of the target AXI write request, and packages the write data of the corresponding address into a write data packet and sends it to the functional module that processes the CHI interface protocol. The functional module that processes the CHI interface protocol sends out the write data packet. The target cache queue in the fourth cache queue completes the CHI protocol process for the current CHI write request and then releases the resources of the fourth cache queue. The cache module and storage module of the target AXI write request corresponding to the write request identifier are also released at the same time and can be used by the next target AXI write request. Meanwhile, when the third cache queue receives the completion flags of all split target AXI write requests, it sends a completion signal to the functional module that handles the AXI interface protocol, without waiting for the processing flow of the CHI interface protocol in the fourth cache queue. Based on the completion signal, other internal cache resources are released and the system is reset to the initial state for processing new AXI write requests, thus completing the AXI write request process. The other internal cache resources include the cache of the third cache queue itself, the residual resources of the fourth cache queue, the local cache of the functional module that processes the AXI interface protocol / CHI interface protocol, and the residual data of the storage module of the target AXI write request.

6. An apparatus for converting AXI protocol to CHI protocol, characterized in that, The device includes: The receiving module is used to receive AXI requests, including AXI read and write requests. The splitting module is used to split the received AXI read and write requests into multiple target AXI read and write requests that conform to the single data volume size of the CHI interface protocol, based on the total amount of data that the AXI read and write requests need to access. The caching module is used to cache the split target AXI read / write requests and the write data involved in the target AXI write requests; The conversion module is used to convert the cached target AXI read / write request into a read / write request of the corresponding request type of the CHI interface protocol; and to convert the write data involved in the AXI write request into write data of the corresponding data packet type of the CHI interface protocol. The request processing module is used to receive the converted read / write requests and write data, and process the requests in accordance with the CHI protocol specifications.

7. The apparatus according to claim 6, characterized in that, In response to the target AXI request being an AXI read request, the apparatus includes: The receiving module is used to receive AXI read requests, wherein the address of the AXI read request is not related to the address in the first cache queue, and the first cache queue is a cache queue that manages AXI read requests; The splitting module is used to split the received AXI read request into multiple target AXI read requests that conform to the single data volume size of the CHI interface protocol, based on the total amount of data that the AXI read request needs to access, and deploy them in the first cache queue respectively. A caching module is used to store each of the target AXI read requests in the first cache queue in a preset target AXI read request caching module; The conversion module is used to convert the CHI request according to the cache attribute of the target AXI read request in the cache module of the target AXI read request, convert the target AXI read request into a CHI read request of the corresponding request type of the CHI interface protocol, and deploy it in the second cache queue that manages CHI read requests. The request processing module is used to receive each CHI read request sent periodically by the second cache queue through a preset CHI interface protocol processing function module, and process the read requests in accordance with the CHI protocol specifications.

8. The apparatus according to claim 7, characterized in that, The process of handling read requests according to the CHI protocol specifications includes: The first forwarding module is used to receive the read response data returned by the CHI read request through the preset functional module for processing the CHI interface protocol, and forward it to the corresponding target cache queue in the second cache queue; wherein, the read response data includes the read data block and the read request identifier; The write module is used to complete the CHI interface handshake protocol after the target cache queue corresponding to the second cache queue obtains the read response data, and then write the data block and read request identifier into the preset storage module of the target AXI read request, and notify the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, so that it can be used by the next target AXI read request. The first reading module is used to read each data block from the storage module based on the read request identifier and return it to the functional module that processes the AXI interface protocol after the first cache queue has received all the split target AXI read requests. The first processing module is used to perform handshake processing on the AXI protocol side based on the functional module for processing the AXI interface protocol, and complete the current AXI read request process.

9. The apparatus according to claim 7, characterized in that, In response to the target AXI request being an AXI write request, the apparatus includes: The receiving module is used to receive AXI write requests, wherein the address of the AXI write request is not related to the address in the third cache queue, and the third cache queue is a cache queue that manages AXI write requests. The splitting module is used to split the received AXI write requests based on the total data volume of the AXI write requests, splitting them into multiple target AXI write requests that conform to the single data volume size of the CHI interface protocol, and deploying them in the third cache queue respectively; A caching module is used to store each of the target AXI write requests in the third caching queue in a preset target AXI write request caching module; The conversion module is used to convert the CHI request according to the cache attributes of the target AXI write request in the cache module of the target AXI write request, convert the target AXI write request into a CHI write request of the corresponding request type of the CHI interface protocol, and deploy it in the fourth cache queue that manages CHI write requests. The request processing module is used to receive each CHI write request periodically sent by the fourth cache queue through a preset CHI interface protocol processing function module. After obtaining the write data return response signal of the CHI write request, it notifies the third cache queue to return the AXI write request completion response. At the same time, the fourth cache queue continues to process the write request according to the CHI protocol specification.

10. The apparatus according to claim 9, characterized in that, The write request processing according to the CHI protocol specifications includes: The second forwarding module is used to receive the write data sendable response signal returned by the CHI write request through the preset request processing module, and then forward it to the corresponding target cache queue in the fourth cache queue. The write data sendable response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and at the same time notifies the third cache queue. The write data involved in the target AXI write request is stored in the preset target AXI write request storage module. The second reading module is used to initiate a read request to the storage module of the target AXI write request after the target cache queue in the fourth cache queue obtains the write data and can send a response signal, and to send the write data of the corresponding address into a write data packet to the functional module that processes the CHI interface protocol. The first sending module, which is a functional module for processing the CHI interface protocol, sends out the write data packet. The target cache queue in the fourth cache queue completes the CHI protocol process for the current CHI write request and then releases the resources of the fourth cache queue. The cache module and storage module of the target AXI write request corresponding to the write request identifier are also released at the same time and can be used by the next target AXI write request. Meanwhile, when the third cache queue receives the completion flags of all split target AXI write requests, it sends a completion signal to the functional module that handles the AXI interface protocol, without waiting for the processing flow of the CHI interface protocol in the fourth cache queue. The second processing module is used to release other internal cache resources and reset to the initial state for processing new AXI write requests based on the completion signal, thereby completing the current AXI write request process. The other internal cache resources include the cache of the third cache queue itself, the residual resources of the fourth cache queue, the local cache of the functional module for processing the AXI interface protocol / CHI interface protocol, and the residual data of the storage module of the target AXI write request.

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