Chip performance evaluation method and device, electronic equipment and storage medium

Abstract

The invention provides a chip performance evaluation method and device, electronic equipment and a storage medium, and belongs to the technical field of chips. The method comprises the following steps: acquiring time sequence data of a plurality of performance indexes in a chip simulation running process; based on the time series data of the plurality of performance indexes, determining a two-dimensional feature tensor, rows and columns of the two-dimensional feature tensor respectively corresponding to different performance indexes and different time windows, and elements in the two-dimensional feature tensor representing the number of valid data of the corresponding performance indexes under the corresponding time windows; and inputting the two-dimensional feature tensor into a performance evaluation model to obtain a performance evaluation result of the chip. Therefore, the cross-module performance coupling problem can be revealed, and the accuracy of chip performance evaluation is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip performance evaluation method, apparatus, electronic device, and storage medium. Background Technology

[0002] Pre-silicon chip performance evaluation is a crucial step in ensuring chip iteration and upgrades. At this stage, no physical chip has been formed yet. Hardware simulation technology is used to simulate the chip's operating environment and replicate the instruction execution and data transmission processes in application scenarios to complete the collection and analysis of performance parameters.

[0003] Currently, the industry commonly uses single metrics for chip performance evaluation, such as computing speed and throughput. However, chips are complex systems with multiple modules working collaboratively. A single metric cannot cover key collaborative scenarios such as data interaction and resource scheduling between modules, and it is difficult to capture hidden performance bottlenecks caused by cross-module coupling. This leads to evaluation results deviating from actual operating conditions, affecting the judgment of the chip's overall performance and reducing the accuracy of chip performance evaluation. Summary of the Invention

[0004] This application provides a chip performance evaluation method, apparatus, electronic device, and storage medium, which can reveal cross-module performance coupling problems and improve the accuracy of chip performance evaluation. The technical solution is as follows: On the one hand, a chip performance evaluation method is provided, the method comprising: Acquire timing data of multiple performance indicators during chip simulation; Based on the time-series data of the multiple performance indicators, a two-dimensional feature tensor is determined. The rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively. The elements in the two-dimensional feature tensor represent the number of valid data entries for the corresponding performance indicator under the corresponding time window. The two-dimensional feature tensor is input into the performance evaluation model to obtain the performance evaluation results of the chip.

[0005] On the other hand, a chip performance evaluation apparatus is provided, the apparatus comprising: The data acquisition module is used to acquire timing data of multiple performance indicators during chip simulation. The tensor determination module is used to determine a two-dimensional feature tensor based on the time-series data of the multiple performance indicators. The rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively. The elements in the two-dimensional feature tensor represent the number of valid data entries for the corresponding performance indicator under the corresponding time window. The performance evaluation module is used to input the two-dimensional feature tensor into the performance evaluation model to obtain the performance evaluation result of the chip.

[0006] In some embodiments, the data acquisition module is used to acquire monitoring data during the chip simulation process sent by a hardware emulator, the hardware emulator being used for accelerated chip simulation; and to filter out the timing data of the plurality of performance indicators from the monitoring data.

[0007] In some embodiments, the tensor determination module includes: The first determining unit is used to count the time series data of the multiple performance indicators in segments according to time windows to obtain a one-dimensional time series of each performance indicator. The elements in the one-dimensional time series represent the number of valid data entries of the performance indicator under the corresponding time window. The second determining unit is used to align the one-dimensional time series of the multiple performance indicators to obtain the two-dimensional feature tensor.

[0008] In some embodiments, the first determining unit is configured to divide the time span corresponding to the time series data of each performance indicator based on a preset time window value and the timestamp in the time series data to obtain multiple time windows; and determine the number of valid data entries of the time series data of the performance indicator in each time window to obtain a one-dimensional time series of the performance indicator.

[0009] In some embodiments, the second determining unit is configured to determine a reference length based on a one-dimensional time series of the plurality of performance indicators, wherein the reference length is the minimum sequence length among the plurality of one-dimensional time series; and to truncate the one-dimensional time series of the plurality of performance indicators to the reference length to generate the two-dimensional feature tensor.

[0010] In some embodiments, the apparatus further includes: The feature map determination module is used to determine the feature map of each performance indicator based on the time-series data of the multiple performance indicators. The feature map is used to describe the relationship between the indicator value of each performance indicator and time. The report generation module is used to generate a performance analysis report for the chip based on the feature maps of the multiple performance indicators and the performance evaluation results.

[0011] In some embodiments, the apparatus further includes: The model training module is used to obtain a defined training sample set, which includes multiple two-dimensional feature tensors and a label for each two-dimensional feature tensor, wherein the label is the true value for chip performance evaluation; and to train the model based on the training sample set to obtain the performance evaluation model.

[0012] On the other hand, an electronic device is provided, comprising a processor and a memory, the memory being used to store at least one computer program, the at least one computer program being loaded and executed by the processor to implement the chip performance evaluation method in the embodiments of this application.

[0013] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored in the computer-readable storage medium, and the at least one computer program is loaded and executed by a processor to implement the chip performance evaluation method in the embodiments of this application.

[0014] On the other hand, a computer program product is provided, including a computer program that is executed by a processor to implement the chip performance evaluation method in the embodiments of this application.

[0015] This application provides a chip performance evaluation method. By comprehensively collecting time-series data of multi-dimensional performance indicators during chip simulation, and integrating and aligning the data in the time domain, it accurately captures the dynamic changes of each indicator under different time windows. Combined with a performance evaluation model, it performs comprehensive analysis of the collaborative data of multiple indicators, covering key collaborative scenarios such as instruction execution, data interaction, and resource scheduling of multiple chip modules. This comprehensively reflects the collaborative state of each module, overcomes the limitations of single indicator analysis, avoids missing hidden performance bottlenecks in cross-module coupling, and can reveal cross-module performance coupling problems. The performance evaluation results can more realistically reflect the actual operating state of the chip, reduce evaluation bias, and improve the accuracy and reliability of chip performance evaluation in the pre-silicon stage, thus providing accurate and effective data support for chip iterative upgrades. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the implementation environment of a chip performance evaluation method provided in an embodiment of this application; Figure 2 This is a flowchart of a chip performance evaluation method provided according to an embodiment of this application; Figure 3 This is a flowchart of another chip performance evaluation method provided according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating a training sample set construction process according to an embodiment of this application; Figure 5This is a schematic diagram of a model training process provided according to an embodiment of this application; Figure 6 This is a schematic diagram of a performance evaluation model architecture provided according to an embodiment of this application; Figure 7 This is a schematic diagram of a model processing procedure provided according to an embodiment of this application; Figure 8 This is a schematic diagram of a chip performance analysis process provided according to an embodiment of this application; Figure 9 This is a schematic diagram of an overall process provided according to an embodiment of this application; Figure 10 This is a block diagram of a chip performance evaluation device according to an embodiment of this application; Figure 11 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with essentially the same function. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on the quantity or execution order.

[0020] In this application, the term "at least one" means one or more, and "multiple" means two or more.

[0021] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the monitoring data and time-series data of various performance indicators involved in this application were obtained with full authorization.

[0022] Figure 1 This is a schematic diagram illustrating the implementation environment of a chip performance evaluation method provided in an embodiment of this application. See also... Figure 1 The implementation environment includes a hardware emulator 101 and an electronic device 102. The hardware emulator 101 and the electronic device 102 can be connected directly or indirectly via wired or wireless communication, which is not limited herein.

[0023] The hardware emulator 101 is a dedicated hardware device for accelerating chip simulation, addressing the problem of excessively long processing times associated with traditional software simulation. More specifically, a hardware emulator is a hardware device specifically designed to accelerate and optimize hardware simulation, a widely used method in computer hardware design that verifies and debugs designs by simulating circuit behavior.

[0024] Electronic device 102 is a device with data processing and analysis capabilities, used to acquire data from the hardware emulator 101 during chip simulation for data analysis. Exemplarily, electronic device 102 can be a server, terminal, etc. In some embodiments, electronic device 102 is implemented as a server, which can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. In other embodiments, electronic device 102 is implemented as a terminal, including but not limited to desktop computers, laptops, tablets, and other types of terminals, but not limited to these; it may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names.

[0025] It should be noted that the above implementation environment is only an example, and the method provided in this application embodiment can also be implemented in other environments, which is not limited in this application embodiment.

[0026] Figure 2 This is a flowchart of a chip performance evaluation method according to an embodiment of this application. The method is executed by an electronic device. See also... Figure 2 The method includes the following steps: 201. Electronic devices acquire timing data of multiple performance indicators during chip simulation.

[0027] In this embodiment, chip simulation refers to simulating the operation of a chip using tools, allowing for early verification of its functionality and performance without the need for actual chip manufacturing. Chip simulation can be implemented using a hardware emulator or a combination of a hardware emulator and software tools; this embodiment does not impose any limitations on this. Performance metrics are key parameters for measuring the chip's operating status, such as bandwidth, operating frequency, and data throughput. Timing data refers to performance metric data recorded in chronological order; each row of data (equivalent to each data point) in the timing data contains a corresponding timestamp and performance metric data. For example, performance metric data refers to bus data generated by concatenating the signal bits corresponding to the performance metrics.

[0028] 202. Electronic devices determine a two-dimensional feature tensor based on time-series data of multiple performance indicators. The rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively. The elements in the two-dimensional feature tensor represent the number of valid data entries for the corresponding performance indicator under the corresponding time window.

[0029] In this embodiment, the two-dimensional feature tensor is a two-dimensional data structure where rows correspond to different performance metrics and columns correspond to different time windows. A time window is a segment that divides the time span of continuous time-series data into a predetermined time length, used to extract metric features within that time period, such as the number of valid data rows mentioned above. The number of valid data rows indicates the actual amount of usable data (number of rows) after excluding outliers and missing values.

[0030] 203. Electronic devices input two-dimensional feature tensors into performance evaluation models to obtain chip performance evaluation results.

[0031] In this embodiment, the performance evaluation model is an algorithm model built based on machine learning or deep learning, trained with a large amount of sample data. Its core function is to read the data patterns in the two-dimensional feature tensor and output a quantitative evaluation result of the chip performance. For example, the performance evaluation result is a numerical value in the range of 0-1, where a higher value indicates better chip performance and a lower value indicates weaker chip performance. When the value is close to 1, it indicates that the effective data performance of each performance indicator in the simulation runs meets expectations, and the overall performance reaches a relatively good level. When the value is close to 0, it indicates that the chip may have a performance bottleneck, such as insufficient effective data for key indicators within a certain time window, or the operating state does not meet design requirements, requiring targeted optimization. Furthermore, the intermediate range can correspond to gradient performance levels, such as being divided into different performance levels like qualified and good according to actual needs, to quickly determine whether the chip meets the application scenario requirements.

[0032] This application provides a chip performance evaluation method. By comprehensively collecting time-series data of multi-dimensional performance indicators during chip simulation, and integrating and aligning them in the time domain, the method accurately captures the dynamic changes of each indicator under different time windows. Combined with a performance evaluation model, the method performs comprehensive analysis of the collaborative data of multiple indicators, covering key collaborative scenarios such as instruction execution, data interaction, and resource scheduling of multiple chip modules. This comprehensively reflects the collaborative state of each module, overcomes the limitations of single indicator analysis, avoids missing hidden performance bottlenecks in cross-module coupling, and can reveal cross-module performance coupling problems. The performance evaluation results can more realistically reflect the actual operating state of the chip, reduce evaluation bias, and improve the accuracy and reliability of chip performance evaluation in the pre-silicon stage, thereby providing accurate and effective data support for chip iterative upgrades.

[0033] Figure 3This is a flowchart of another chip performance evaluation method provided according to an embodiment of this application. This method is performed by an electronic device. See [link to flowchart]. Figure 3 The method includes the following steps: 301. Electronic devices acquire monitoring data during chip simulation operation sent by a hardware emulator, which is used for accelerated chip simulation.

[0034] In this embodiment, monitoring data refers to various data continuously generated by the hardware emulator during chip simulation operation, and the monitoring data is presented in a multi-source time-series format. For example, monitoring data can be transmitted to the electronic device in real time during simulation operation, or it can be transmitted to the electronic device in batches after the simulation ends; this embodiment does not impose any limitations on this. Furthermore, this application uses obtaining monitoring data from the hardware emulator as an example for illustration; the electronic device can also obtain this type of data from other paths, such as from a preset log storage server, a third-party data acquisition device, or receive chip simulation monitoring data forwarded from the cloud. As long as valid data reflecting the chip simulation operation status can be obtained, the specific acquisition path does not constitute a limitation on this application.

[0035] 302. Electronic equipment filters time-series data of multiple performance indicators from monitoring data.

[0036] In this embodiment, after acquiring multi-source timing monitoring data from the hardware emulator, valuable feature data for model prediction, i.e., timing data of multiple performance indicators, are filtered out. For example, the monitoring data includes, but is not limited to, AXI interface data, SDP channel data, T0 RIP signal data, T1 RIP signal data, DDR bandwidth data, etc. Through filtering, timing data of these performance indicators can be obtained based on the monitoring data. This data is non-uniform and noisy. The non-uniformity originates from the difference in data generation frequency at different stages of chip simulation, while the noise originates from signal interference during hardware simulation or errors in the transmission link.

[0037] In some embodiments, multiple performance indicators include at least one of data transmission indicators, computation execution indicators, and hardware status indicators. Data transmission indicators indicate the data transmission capabilities of each interface and network of the chip; computation execution indicators indicate program execution and cache utilization efficiency; and hardware status indicators indicate the operating speed of key components. Accordingly, transmission data of each interface and network (such as data request volume and bandwidth usage), operating parameters of the chip's core modules (such as instruction execution status and cache interaction information), and status signals of key hardware (such as clock frequency and signal level changes) are filtered from the monitoring data. These data reflect the dynamic operating status of the chip during simulation in real time and are the core basis for subsequent performance evaluation models to extract features and analyze bottlenecks.

[0038] For example, data transmission metrics include at least one of the following: DDR bandwidth, DF network bandwidth, SMN network bandwidth, and SDP request count. DDR (Double Data Rate) bandwidth is reflected by changes in the DQS (Data Strobe Signal) to ensure accurate assessment of data transmission rate. DF (TCDX FTI) interface network bandwidth is calculated by statistically analyzing the data transmission efficiency of the FTI (Fabric Test Interface) channel within the interface. SMN (System Management Network) network bandwidth is calculated by statistically analyzing the data transmission efficiency of each channel within the network. SDP (System Data Path) includes CORE, UMC (Unified Memory Controller), and IOMS (Input / Output Management Subsystem), etc. The request count requires statistical analysis of data requests and transmission volume per unit time for each channel, calculating the number of valid requests, the number of clock cycles during data transmission, and the traffic of channels such as req / rdrsp / wr / wrrsp / prb according to the protocol, and then calculating the interface data bandwidth to reflect IP data acquisition. It should be noted that the calculation principles for the bandwidth of interfaces such as DF, SMN, and SDP are the same to ensure the consistency and accuracy of network bandwidth assessment. Execution metrics include at least one of the following: number of instructions completed, L2 cache hit rate, and L3 cache hit rate. The number of instructions completed is measured by the number of retrieved instructions per unit time, reflecting program execution efficiency. The L2 (Level 2 Cache) and L3 (Level 3 Cache) cache hit rates are obtained by statistically analyzing cache hit counts and are used to evaluate the effective utilization of the cache. Hardware status metrics include the frequency values ​​of key IPs. By monitoring key frequencies such as Core clock (Core clock), FCK (Functional clock), Memory clock (Memory clock), and NBIO LCLK (North Bridge Input / Output Local Clock), and calculating the actual values ​​of each frequency proportionally, accurate data is provided for performance evaluation. It should be noted that the above performance metrics are for illustrative purposes only and do not constitute a limitation; more or fewer performance metrics may be included.

[0039] In some embodiments, the timing data of various performance indicators undergoes data preprocessing, such as noise removal and missing value imputation, to ensure data continuity and reliability. For example, the timing data is in txt format: the first column is the timestamp; the second column is the channel bus data, generated by concatenating multiple signal bits in a fixed order. Two types of invalid information exist in the timing data and need to be processed and removed: first, initial values ​​(first row of data), which are default values ​​during channel initialization and cannot represent address or data changes, thus constituting noise data; second, incomplete data, where the length of each row of bus data is checked to ensure it conforms to the preset format. If data truncation occurs, it is determined to be incomplete data and deleted.

[0040] The following describes data preprocessing using AXI's ar read channel signal (denoted as data A) and aw write channel signal (denoted as data B) as examples, as shown in (1) and (2) below.

[0041] (1) The data format of data A is: ar={ARADDR,ARBUST,ARCACHE,ARID,ARLEN,ARLOCK,ARQOS,ARREGION,ARSIZE,ARUSER}.

[0042] Data A is as follows: Time(ps) ar(ar channe bus) 5530879500 000000000000000000fffff00000000000000c000002800 (Line 1) 34908789500 00000000000000000000000000000000000000002840 (Line 2) 34999881500 00000000000000000000000000000000000002002840 (Line 3) 34543291500 00000532e978000000000007003758000000002002840 (Line 4) 36783521500 0000000000000000003e91a0012000000000002002840 (Line 5) ……………… 46783371500 000012e080000000003e91a0012000000000002002840 (Line 100) 48903371500 0000340000000003e91a001 (Line 101) The new data A1 obtained after preprocessing data A is as follows: 34908789500 00000000000000000000000000000000000000002840 (Line 2) 34999881500 00000000000000000000000000000000000002002840 (Line 3) 34543291500 00000532e978000000000007003758000000002002840 (Line 4) 36783521500 0000000000000000003e91a0012000000000002002840 (Line 5) ……………… 46783371500 000012e080000000003e91a0012000000000002002840 (Line 100) Data A1 contains records from row 2 to row 100 of data A, excluding the initial value in the first row and incomplete data in the last row. Each row contains a complete timestamp and AR bus data. Here, the last row of data A represents a case where the data is incomplete.

[0043] (2) The data format of data B is: aw={AWADDR,AWBUST,AWCACHE,AWID,AWLEN,AWLOCK,AWQOS,AWREGION,AWSIZE,AWUSER}.

[0044] Data B is as follows: Time(ps) aw(aw channe bus) 5530879500 000000000000000000fffff00000000000000c000002800 (Line 1) 24908789500 00000000000000000000000000000000000000002840 (Line 2) 34999881500 00000000000000000000000000000000000002002840 (Line 3) 35543291500 00000532e978000000000007003758000000002002840 (Line 4) 36783521500 0000000000000000003e91a0012000000000002002840 (Line 5) ……………… 40783371500 000012e080000000003e91a0012000000000002002840 (Line 120) 50783371500 000012e080000000003e91a0012000000000002002840 (Line 121) The new data B1 obtained after preprocessing data B is as follows: 24908789500 00000000000000000000000000000000000000002840 (Line 2) 34999881500 00000000000000000000000000000000000002002840 (Line 3) 35543291500 00000532e978000000000007003758000000002002840 (Line 4) 36783521500 0000000000000000003e91a0012000000000002002840 (Line 5) ……………… 40783371500 000012e080000000003e91a0012000000000002002840 (Line 120) 50783371500 000012e080000000003e91a0012000000000002002840 (Line 121) Data B1 contains records from row 2 to row 121 of data B. The initial value of the first row has been removed, and the data of the remaining rows is complete and has been retained.

[0045] Steps 301 and 302 described above are an exemplary method for obtaining timing data of multiple performance indicators during the simulation of an electronic device chip. This is illustrated using the example of acquiring monitoring data and filtering timing data through a hardware emulator, but it does not constitute a limitation. In other embodiments, the hardware emulator sends the monitoring data to an intermediate device, which then filters the timing data and sends it to the current electronic device; these methods will not be elaborated upon here. All of these methods ensure that the electronic device quickly obtains high-quality performance indicator timing data, laying a reliable data foundation for subsequent feature extraction and performance evaluation.

[0046] 303. Electronic devices count the time-series data of multiple performance indicators in segments according to time windows to obtain a one-dimensional time series for each performance indicator. The elements in the one-dimensional time series represent the number of valid data entries for the corresponding performance indicator under the time window.

[0047] In this embodiment, a time window refers to a segment that divides the time span corresponding to continuous time series data into segments of a preset time length, used to extract indicator features within the time period, such as the number of valid data entries. After the time series data has undergone data preprocessing, the number of data rows in each time window is the number of valid data entries in that time window. A one-dimensional time series refers to a sequence in which the number of valid data entries for a single performance indicator in different time windows is arranged sequentially.

[0048] In some embodiments, the time-series data of multiple performance indicators are segmented and counted according to time windows to obtain a one-dimensional time series for each performance indicator. This includes: dividing the time span corresponding to the time-series data of each performance indicator into multiple time windows based on a preset time window value and timestamps in the time-series data; and determining the number of valid data entries in each time window to obtain the one-dimensional time series of that performance indicator. The preset time window value is the preset time length, and the timestamps in the time-series data refer to the timestamps included in each row of data. The following explanation uses a preset time window value of 1ms as an example.

[0049] The one-dimensional time series obtained after time segmentation of data A1 is T1=[0 0 0 …3 101 20 … 1]. Specifically, after time segmentation of data A1, in the 0th time window (0-1ms), no data timestamps of data A1 fall within this range, and the statistical result is recorded as 0; in the 1st time window, there are still no matching data, recorded as 0; in the 2nd time window, there are still no matching data, recorded as 0; in the 33rd time window (33-34ms), 3 data timestamps of data A1 fall within this range, recorded as 3; in the 34th time window, 101 data timestamps fall within this range, recorded as 101; in the 35th time window, 20 data matches, recorded as 20; and in the 46th time window, 1 data matches, recorded as 1.

[0050] The one-dimensional time series obtained after time segmentation of data B1 is T2=[0 0 0 … 2 0 0 … 1]. Specifically, after time segmentation of data B1, in the 0th time window (0-1ms), no timestamps of any data in data B1 fall within this range, and the statistical result is recorded as 0; in the 1st time window, there are still no matching data, recorded as 0; in the 2nd time window, there are still no matching data, recorded as 0; in the 34th time window (34-35ms), there are 2 timestamps of data B1 that fall within this range, recorded as 2; in the 35th time window, there are no matching data, recorded as 0; in the 36th time window, there are no matching data, recorded as 0; in the 50th time window, there is 1 matching data, recorded as 1.

[0051] This transforms scattered, randomly distributed data by timestamps into a sequence statistically analyzed at fixed time intervals, thereby accurately capturing the effective data distribution of performance indicators within each time period, providing a foundation for subsequent observation of performance fluctuations or analysis using machine learning.

[0052] 304. Electronic devices are aligned with one-dimensional time series of multiple performance indicators to obtain a two-dimensional feature tensor.

[0053] In this embodiment, the rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively, and each row of data in the two-dimensional feature tensor is a one-dimensional time series after alignment processing. The two-dimensional feature tensor has the characteristics of alignment and matrix representation.

[0054] In some embodiments, aligning one-dimensional time series of multiple performance indicators to obtain a two-dimensional feature tensor includes: determining a baseline length based on the one-dimensional time series of multiple performance indicators; truncating the one-dimensional time series of multiple performance indicators to the baseline length to generate a two-dimensional feature tensor. The baseline length is the minimum sequence length among the multiple one-dimensional time series, which is also the minimum number of time windows among the multiple one-dimensional time series. After obtaining multiple one-dimensional time series of equal length using the baseline length, the one-dimensional time series are converted into one-dimensional tensors; based on global timestamps, the one-dimensional tensors of each performance indicator are unified to the same time grid to generate a two-dimensional feature tensor. This method solves the problem of inconsistent lengths of multiple indicator time series, ensures the regularity of the two-dimensional feature tensor structure, eliminates the interference of length differences on subsequent model inputs, enables the model to stably process feature data of uniform dimension, and improves the consistency of evaluation results.

[0055] Truncation, in this context, refers to a process for a one-dimensional time series of multiple performance indicators. Using a baseline length as a standard, it retains the first N time windows (N equals the baseline length) of data in each series, discarding data from subsequent time windows exceeding N. Specifically, if the length of a one-dimensional time series of a performance indicator is M (containing M time windows), and the baseline length is N (N≤M), the truncation operation only retains the statistical values ​​(such as the number of valid data points) of the first N time windows in the series, deleting all data from the (N+1)th to the Mth time windows. This ensures that the series retains only information from the N time windows, guaranteeing that the same column in the subsequent two-dimensional feature tensor represents the same time window.

[0056] For example, the one-dimensional time series of multiple performance indicators are T1, T2, ..., Tn. Taking the minimum sequence length as the baseline length L, and the number of one-dimensional time series as D, we obtain a corresponding L×D two-dimensional feature tensor. Specifically, the baseline feature is Lmin = min [len(T1), len(T2), len(T3), ..., len(Tn)], and the two-dimensional feature vector is as follows: Tensor ([ [0 0 0 …3 101 20 … 1], [0 0 0 … 200 … 0] , [0 1 0 … 200 … 0] , … [0 0 0 … 200 … 0] ]) Steps 303 and 304 above are an exemplary method for determining a two-dimensional feature tensor based on time-series data of multiple performance indicators for electronic devices, but they do not constitute a limitation. By transforming multi-indicator time-series data into structured features and unifying the data format, not only is the distribution pattern of each indicator in the time dimension preserved, but also the effective fusion of multi-indicator data is achieved, facilitating efficient reading and analysis of data patterns by the model.

[0057] 305. Electronic devices input two-dimensional feature tensors into performance evaluation models to obtain chip performance evaluation results.

[0058] In this embodiment of the application, the principle by which the electronic device determines the performance evaluation result is the same as step 203 described above, and will not be repeated here.

[0059] In some embodiments, the training steps of the performance evaluation model include: obtaining a determined training sample set, which includes multiple two-dimensional feature tensors and a label for each two-dimensional feature tensor, wherein the label is the true value of the chip's performance evaluation; and training the model based on the training sample set to obtain the performance evaluation model.

[0060] It should be noted that the training steps of the performance evaluation model can be performed on the current electronic device or on other electronic devices, and this application embodiment does not impose any restrictions on this. The determination method of the two-dimensional feature tensor in the training sample set is the same as that of the two-dimensional feature tensor during model inference, that is, the two-dimensional feature tensor in the training sample set can also be determined based on the above steps 301 to 304, which will not be repeated here. The multiple two-dimensional feature tensors in the training sample set come from multiple CASE (test cases), that is, from different chip verification scenarios or combinations, or in other words, the multiple two-dimensional feature tensors in the training sample set come from different tags or different projects. Combining the verification results of the test cases, labels are added to each feature tensor used as a sample through manual annotation or automatic annotation, serving as the target for model learning. For example, the labels and two-dimensional feature tensors correspond one-to-one, and the labels are numerical values ​​in the range of 0-1. In this way, through supervised learning, the model learns the mapping relationship between features and performance, enabling the trained model to accurately output evaluation results based on input features, ensuring that the model has reliable performance evaluation capabilities and meeting the actual needs of chip simulation scenarios.

[0061] For a clearer description of the process of constructing the training sample set, see [link to documentation]. Figure 4 As shown, Figure 4 This is a schematic diagram illustrating a training sample set construction process according to an embodiment of this application. First, the selected data is filtered and denoised to obtain multi-source time series data, i.e., time series data of multiple performance indicators, as described in steps 301 and 302 above. Then, the multi-source time series data is time-segmented to obtain multi-source one-dimensional time series, i.e., one-dimensional time series of multiple performance indicators, which can form a multi-source one-dimensional time series array, as described in step 303 above. Afterward, the multi-source one-dimensional time series is structurally transformed to obtain two-dimensional feature tensors, as described in step 304 above. Finally, labels are bound to each two-dimensional feature tensor to obtain training samples, forming a training sample set.

[0062] For a clearer description of the entire training process, see [link to documentation]. Figure 5 As shown, Figure 5 This is a schematic diagram illustrating a model training process according to an embodiment of this application. First, monitoring data is acquired and processed through time segmentation to obtain a one-dimensional time series. This data is then combined to generate a two-dimensional feature tensor, and numerical labels are added to obtain a training sample set. The training sample set is split into a training set and a test set. The machine learning model is trained using the training set and tested using the test set. This machine learning model is the performance evaluation model, used for performance evaluation, and the performance evaluation results are output.

[0063] For a clearer description of the performance evaluation model, see [link / reference]. Figure 6 As shown, Figure 6This is a schematic diagram of a performance evaluation model architecture provided according to an embodiment of this application. The input of the model is a two-dimensional feature tensor, and the output performance evaluation value is a value in the range of 0-1. For example, a Bidirectional Long Short Short-Term Memory (BiLSTM) network is used to construct the performance evaluation model. BiLSTM is a special type of recurrent neural network that, through its bidirectional LSTM structure, can simultaneously consider forward and backward dependencies in time series data, improving the model's prediction accuracy. Accordingly, after the data is input into the model, it passes through a bidirectional LSTM layer to obtain the forward and backward hidden states. After concatenation, the output is taken at the end of the sequence, and then passed through a fully connected layer and a sigmoid activation layer before the model output.

[0064] The training process of the performance evaluation model is described in detail below. Throughout the training process, through feature selection, data preprocessing, reasonable loss function and optimizer, as well as efficient training iteration, the model has achieved good performance on the test set, verifying the model's strong predictive and generalization abilities. The training process of the model is described in several different aspects below (1)-(4).

[0065] (1) Model parameters: The core parameters of the performance evaluation model include input feature dimension (input_size), hidden layer dimension (hidden_size), number of network layers (num_layers), learning rate (learning_rate) and training epochs (num_epochs).

[0066] The input feature dimension (input feature dimension parameter) is determined by the feature dimension of the two-dimensional feature tensor, which is equal to the number of performance metrics and determines the input layer structure of the model. The hidden layer dimension (hidden state dimension parameter) is set to 128 to control the feature extraction capability of the LSTM. The number of network layers (network depth parameter) is set to 2 to configure a two-layer LSTM stacked structure, where the primary layer captures local features and the advanced layer extracts global abstract features. The learning rate (gradient update step size parameter) is configured to 0.001, using the default learning rate of the Adam optimizer to ensure stable convergence during training and avoid oscillations. The number of training epochs (training cycle parameter) is set to 20, which, together with the early stopping mechanism, prevents overfitting and ensures sufficient convergence, thereby guaranteeing the convergence of model training and the accuracy of evaluation.

[0067] (2) Model structure: The performance evaluation model includes a bidirectional LSTM processing layer and a fully connected output layer.

[0068] The bidirectional LSTM layer employs a multi-layer stacked structure (the number of layers is configurable), processing the input two-dimensional feature tensor in parallel via both forward and backward channels. This means it extracts features simultaneously from both the start and end points of the data, and from the end point to the start point. The feature extraction capability is controlled by the hidden state dimension parameter, outputting a concatenated bidirectional feature vector. The input data format of this bidirectional LSTM layer follows the order of batch size, sequence length, and feature dimension. The initialization module automatically generates all-zero initial hidden states and cell states, whose dimensions are adaptively adjusted according to the number of network layers and batch size. For example, both the initial hidden states and cell states are set to zero vectors, and the vector dimension matches the number of network layers, hidden layer dimensions, and the number of bidirectional paths, i.e., the dimension is network layer number × 2 × hidden layer dimension. The sequence feature extraction module specifically captures the terminal features of the input sequence, utilizing the contextual information from bidirectional processing to achieve sequence-level prediction. For instance, after processing by the bidirectional LSTM layer, the output is a feature vector containing all time windows. The feature vector corresponding to the last time window is selected as the key temporal feature representation. This feature vector integrates the hidden layer output information from both directions, with a dimension of hidden layer dimension × 2. The fully connected output layer maps the feature dimension of the bidirectional LSTM output to a single predicted value; the activation module uses the Sigmoid function to normalize the output value to the [0,1] interval. If the key temporal feature vector is input into the fully connected output layer, the feature dimension is mapped to 1 dimension through linear transformation, and then processed by the Sigmoid activation function to map the output result to the 0-1 interval, and finally the chip performance evaluation result is obtained.

[0069] By simultaneously capturing the historical and future contextual features of a sequence through a bidirectional processing mechanism, enhancing feature abstraction capabilities through a multi-layer stacked structure, focusing on the overall representation of the sequence through end-point feature extraction, and adapting the Sigmoid output to probabilistic prediction scenarios, this model can be efficiently applied to sequence data processing tasks such as time series prediction. Compared to unidirectional LSTM models, it has better context awareness and prediction accuracy, and can better achieve chip performance evaluation.

[0070] (3) Loss function and optimizer: Configure the loss function and optimizer to achieve iterative optimization of parameters.

[0071] The loss function uses mean squared error loss (MSELoss) to quantify the deviation between the model's predictions and the actual labels. It measures the degree of difference by calculating the average of the squared differences between the predicted and true values, providing direction for adjusting model parameters. The optimizer uses the Adam optimization algorithm, which dynamically adjusts the model's parameters based on the deviation calculated from the loss function to minimize the loss function.

[0072] Accordingly, the electronic device also includes an error calculation module and a parameter optimization module. In the error calculation module, the mean squared error loss function is used as the performance evaluation standard for the training process, mathematically expressed as: MSE = 1 / N * Σ(y_pred - y_true)². By calculating the arithmetic mean of the squared Euclidean distance between the predicted and true values, a continuously differentiable scalar evaluation metric is provided to quantify the model's output accuracy. In the parameter optimization module, a gradient optimizer based on adaptive moment estimation (Adam) is configured. This optimizer possesses the following technical features: a dynamic learning rate adjustment mechanism, adaptively adjusting the learning step size based on the first and second moments of the parameter gradient; a built-in momentum buffer, preserving historical gradient information to achieve smooth parameter updates; a weight decay function, implicitly implementing L2 regularization to prevent overfitting; an operation object, binding to the set of all trainable parameters of the model (including the LSTM layer weight matrix and the fully connected layer bias vector); and learning rate control, precisely controlling the parameter update magnitude through an externally configurable parameter (learning_rate=0.001).

[0073] The error calculation module and the parameter optimization module form a closed-loop training system. Accordingly, during the forward propagation phase, the bidirectional LSTM device generates predicted values; the error calculation module generates a loss scalar in real time and calculates the gradient field; the parameter optimization module iteratively updates the network weights along the reverse direction of the gradient; the two modules work together to achieve the automatic optimization process of model parameters; together ensuring a balance between model convergence speed and prediction accuracy.

[0074] (4) Iterative training: Divide the training data into batches, and input each batch into the model. Calculate the loss and update the model parameters based on the gradient information. Repeat the above process until the preset number of iterations is reached or the loss converges. This will not be elaborated further here.

[0075] Having provided a detailed introduction to the performance evaluation model above, the following section further explains the data flow within the model to better understand its processing steps. See also... Figure 7 As shown, Figure 7 This is a schematic diagram of a model processing procedure provided according to an embodiment of this application.

[0076] The system consists of several layers. The input layer receives a two-dimensional feature tensor. It processes the original data to generate a two-dimensional feature tensor, which serves as the input. The BiLSTM layer performs temporal feature extraction, capturing long-range dependencies in the sequence data; bidirectional context modeling, with the forward LSTM processing the sequence from start to finish and the backward LSTM processing it from finish to start; and feature fusion, concatenating the bidirectional hidden states into the final output. The BiLSTM layer processes the two-dimensional tensor from the input layer and outputs a three-dimensional tensor (containing temporal features). The fully connected layer performs feature compression, mapping the high-dimensional features output from the BiLSTM layer to a low-dimensional space; nonlinear transformation, introducing nonlinearity through activation functions (such as ReLU); and information aggregation, integrating feature information from all temporal locations. The fully connected layer takes the three-dimensional output of the BiLSTM layer as input, flattens it into a two-dimensional matrix, and outputs a one-dimensional vector. The output layer performs scalar prediction, generating performance evaluation values ​​within the 0-1 range; and value range constraints, using the Sigmoid function to ensure the output is within the (0,1) interval. The output layer maps the one-dimensional vector of the fully connected layer to (0,1) through a linear transformation, and outputs the performance evaluation value.

[0077] After training the performance evaluation model, its performance is tested. The test set is not used in the model optimization during training; instead, unseen data (the test set) is used to evaluate the model's performance. Correspondingly, the training set is used to train the model, yielding the chip's performance evaluation value (output_tensor, 0-1) and the loss value (Validationloss). A performance evaluation value closer to 1 indicates better chip performance. The loss value reflects the model's prediction error on unseen data; a smaller loss value indicates that the model fits the validation set well, and the prediction results are close to the true labels, demonstrating strong generalization ability.

[0078] Through the above process, machine learning technology was used to fit the relationship between various performance indicators and simulation performance, and a performance evaluation model was established. This model can output performance evaluation results and predict simulation results. At the same time, the performance target values ​​of chip performance, cache and DF were incorporated into the fitting process, making the chip performance evaluation more comprehensive and accurate.

[0079] 306. Electronic devices determine the feature map of each performance indicator based on time-series data of multiple performance indicators. The feature map is used to describe the relationship between the indicator value and time of each performance indicator.

[0080] In this embodiment, to facilitate the analysis of various indicators, the time-series data of each performance indicator are visualized to obtain a feature map for each performance indicator. A feature map is a chart showing the changes in performance indicator values ​​over time, reflecting the dynamic trend of the indicator. By combining the feature map and the evaluation results, not only is the dynamic change of the indicator over time visually displayed through the feature map, but quantitative evaluation results are also provided, making chip performance analysis more comprehensive and easier to understand. This facilitates designers in quickly identifying performance bottlenecks and provides both visual and quantitative evidence for chip optimization.

[0081] For clarity, please refer to Figure 8 to illustrate the process of analyzing chip performance described above. Figure 8 This is a schematic diagram illustrating a chip performance analysis process according to an embodiment of this application. During hardware emulator simulation, factors affecting chip performance can be mainly divided into two categories: one is the running speed of the simulation environment, which relates to the real-time performance and efficiency of the simulation; the other is the performance of the design itself, which reflects the design's performance capability in actual operation. For the first category of factors, the hardware simulation rate is accurately determined by monitoring the comparison between the actual running time and the simulation time. For the second category of factors, given the diversity of influencing factors, the method proposed in this application is used to identify and locate potential bottlenecks in chip performance. The method proposed in this application is summarized below with reference to the accompanying drawings.

[0082] In a hardware emulator, key data is monitored, including but not limited to the number of instructions completed, the number of SDP data requests, the number of AXI data requests, and DDR access bandwidth. As shown in the diagram, in the hardware emulator (HDL), RIP (CORE) corresponds to the number of instructions completed. RIP (Relative Instruction Point) is the address location component in the processor instruction execution flow; monitoring its operation allows us to count the total number of instructions completed per unit of time. SDP (CORE / UMC / IOMS) corresponds to the number of SDP data requests. SDP (Data Path) is responsible for data interaction between CORE, UMC (Unified Memory Controller), and IOMS (Input / Output Module System); monitoring the frequency of data requests from this module helps us understand its operation. AXI (MP0 / MP1 / RSMU / otherIP) corresponds to the number of AXI data requests. AXI is a high-speed bus protocol used by MP (Processing Module) and RSMU (Runtime System Management Module). Communication between IP cores such as the Power Management Unit (PMU) and the AXI bus is monitored to count the number of data requests. The DDR monitor corresponds to DDR access bandwidth and specifically monitors DDR memory access. By counting the amount of read and write data per unit time, the DDR access bandwidth can be calculated. Monitoring these modules allows for performance monitoring from multiple dimensions, including instruction execution, data path, bus communication, and memory access, and yields monitoring data. Furthermore, by comparing actual runtime with simulation time (Simtime & Realtime), the hardware simulation rate can be accurately determined; this will not be elaborated further.

[0083] Monitoring data is transferred from the hardware emulator to the workstation via DPI-C (Direct Programming Interface for C). The workstation can be considered an intermediary device between the hardware emulator and the current electronic device. As shown in the diagram, the monitoring data from the hardware emulator is transferred to the workstation (HVL), where it is processed by a C / C++ model to obtain timing data for various performance indicators. This process does not consume additional simulation time, ensuring efficient simulation. After obtaining the timing data for each performance indicator, performance evaluation results can be obtained not only through machine learning models (performance evaluation models) but also through analysis tools to obtain visualization results, thus achieving output. This not only intuitively displays the changing trends of key performance indicator values ​​during each chip operation but also provides quantitative evaluation results, offering data support for chip performance analysis.

[0084] For a clearer description of the entire process, please refer to [link / reference]. Figure 9 As shown, Figure 9 This is a schematic diagram of an overall process provided according to an embodiment of this application.

[0085] As shown in the figure, simulation acceleration is achieved through a hardware emulator. A multi-protocol detection module analyzes the monitoring data during chip simulation, including but not limited to AXI control flow analysis, SDP data flow analysis, DDR bandwidth detection, and instruction throughput analysis, to obtain timing data for various performance indicators (see steps 301 to 302 above). Then, on one hand, timing features are extracted from the timing data of these performance indicators to obtain two-dimensional feature tensors, which are then used to evaluate the chip's performance through a performance evaluation model (see steps 303 to 305 above). On the other hand, the timing data of these performance indicators is visualized (see step 306 above).

[0086] 307. Electronic devices generate chip performance analysis reports based on feature maps and performance evaluation results of multiple performance indicators.

[0087] In this embodiment, the electronic device can integrate the feature maps and performance evaluation results of various performance indicators into a performance analysis report and output it. To adapt to different usage needs, the electronic device supports diverse report output methods, including editable document formats, table formats that facilitate secondary data analysis, and web page formats that support online preview. Furthermore, the performance analysis report can be delivered through local storage, network transmission (to a designated terminal or server), or printout. This embodiment does not limit the format or output method of the performance analysis report.

[0088] It should be noted that steps 306 and 307 above are optional. In some embodiments, the electronic device outputs the performance evaluation results obtained by the performance evaluation model without visualizing the time-series data of each performance indicator or generating a report. In other embodiments, the electronic device outputs the performance evaluation results obtained by the performance evaluation model and visualizes the time-series data of each performance indicator without generating a report.

[0089] This application provides a chip performance evaluation method. By comprehensively collecting time-series data of multi-dimensional performance indicators during chip simulation, and integrating and aligning them in the time domain, the method accurately captures the dynamic changes of each indicator under different time windows. Combined with a performance evaluation model, the method performs comprehensive analysis of the collaborative data of multiple indicators, covering key collaborative scenarios such as instruction execution, data interaction, and resource scheduling of multiple chip modules. This comprehensively reflects the collaborative state of each module, overcomes the limitations of single indicator analysis, avoids missing hidden performance bottlenecks in cross-module coupling, and can reveal cross-module performance coupling problems. The performance evaluation results can more realistically reflect the actual operating state of the chip, reduce evaluation bias, and improve the accuracy and reliability of chip performance evaluation in the pre-silicon stage, thereby providing accurate and effective data support for chip iterative upgrades.

[0090] More specifically, this paper presents a chip performance analysis and evaluation method based on a hardware emulator. This method solves the problems of accurately locating performance issues and inconvenient analysis in traditional chip performance verification processes, improving verification efficiency, reducing verification cycle, and enabling early detection of potential performance bottlenecks. By shifting the performance localization method from traditional hardware waveform capture to the host computer side, combined with a host computer visualization interface, it is possible to quickly locate and analyze performance changes in the current chip design. This primarily involves monitoring information such as the number of instructions completed by the chip system, the chip's internal bus bandwidth, DDR bandwidth, and operating frequency. Through performance evaluation models and analysis tools, machine learning techniques are used to evaluate changes in key performance indicators. This effectively analyzes the current chip performance, compares it with previous projects, determines whether performance improvements meet expectations, and intuitively reveals chip performance bottlenecks. This improves the efficiency and accuracy of chip evaluation, thereby enhancing chip design quality, shortening development cycles, and reducing development costs.

[0091] Specifically, by real-time monitoring of the transaction type and clock cycle of the AXI control channel, dynamic parsing and statistics of the protocol layer load of the SDP data channel, analysis of latency bandwidth through DDRmonitor, and statistical analysis of instruction completion count through redirection performance counter, and inputting the monitoring data into the performance evaluation model for timing correlation analysis, it provides the ability to collaboratively analyze control flow (AXI), data flow (SDP), and instruction flow. At the same time, it provides a performance evaluation model with effective timing feature modeling capabilities. Based on the performance index analysis data, problems existing in the verification process can be quickly located, and multi-source performance bottlenecks can be quickly identified in the pre-silicon verification stage.

[0092] This chip performance analysis method based on a hardware emulator provides a novel and efficient hardware performance monitoring and optimization solution by combining multi-dimensional monitoring, data collaborative analysis, and a time-series analysis-based machine learning model. It not only enables independent performance evaluation of each module but also reveals cross-module performance coupling issues, thus providing crucial support for hardware optimization and debugging. The multi-dimensional monitoring system covers AXI, SDP, DDR latency bandwidth, and instruction throughput; data collaborative analysis establishes a time-domain correlation matrix between AXI control flow, SDP data flow, and instruction flow, enabling dynamic detection of cross-module performance coupling issues (such as instruction stalling due to DDR latency); and the time-series analysis-based machine language learning model achieves the evaluation of chip system performance parameters.

[0093] As shown in Table 1 below, the method proposed in this application can reveal chip performance bottlenecks in various scenarios and improve the efficiency and accuracy of chip evaluation. For example, the DDR bandwidth analysis scenario is used to determine whether DDR is a bottleneck in simulation speed; the cache bottleneck location scenario is used to determine the simulation performance loss caused by unreasonable cache design; the instruction pipeline analysis scenario is used to locate problems affecting instruction execution efficiency in pipeline design; and the cross-module coupling analysis scenario is used to investigate coupling bottlenecks when multiple modules work together.

[0094] Table 1. Effects in various scenarios

[0095] Figure 10 This is a block diagram of a chip performance evaluation apparatus according to an embodiment of this application. The apparatus is used to perform the steps of the chip performance evaluation method described above, see below. Figure 10 The chip performance evaluation device includes: a data acquisition module 1001, a tensor determination module 1002, and a performance evaluation module 1003.

[0096] The data acquisition module 1001 is used to acquire timing data of multiple performance indicators during chip simulation. Tensor determination module 1002 is used to determine a two-dimensional feature tensor based on time series data with multiple performance indicators. The rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively. The elements in the two-dimensional feature tensor represent the number of valid data entries for the corresponding performance indicator under the corresponding time window. The performance evaluation module 1003 is used to input the two-dimensional feature tensor into the performance evaluation model to obtain the chip's performance evaluation results.

[0097] In some embodiments, the data acquisition module 1001 is used to acquire monitoring data during the chip simulation process sent by the hardware emulator, the hardware emulator being used for accelerated chip simulation; and to filter out time-series data of multiple performance indicators from the monitoring data.

[0098] In some embodiments, the tensor determination module 1002 includes: The first determining unit is used to count the time series data of multiple performance indicators by segmenting them according to time windows, so as to obtain a one-dimensional time series of each performance indicator. The elements in the one-dimensional time series represent the number of valid data entries of the performance indicator under the corresponding time window. The second determining unit is used to align the one-dimensional time series of multiple performance indicators to obtain a two-dimensional feature tensor.

[0099] In some embodiments, the first determining unit is used to divide the time span corresponding to the time series data of each performance indicator based on a preset time window value and timestamps in the time series data to obtain multiple time windows; and to determine the number of valid data entries in each time window of the time series data of the performance indicator to obtain a one-dimensional time series of the performance indicator.

[0100] In some embodiments, the second determining unit is used to determine a baseline length based on a one-dimensional time series of multiple performance indicators, wherein the baseline length is the minimum sequence length among the multiple one-dimensional time series; and to truncate the one-dimensional time series of multiple performance indicators to the baseline length to generate a two-dimensional feature tensor.

[0101] In some embodiments, the apparatus further includes: The feature map determination module is used to determine the feature map of each performance indicator based on time-series data of multiple performance indicators. The feature map is used to describe the relationship between the indicator value and time of each performance indicator. The report generation module is used to generate a chip performance analysis report based on feature maps and performance evaluation results of multiple performance indicators.

[0102] In some embodiments, the apparatus further includes: The model training module is used to obtain a defined training sample set, which includes multiple two-dimensional feature tensors and a label for each two-dimensional feature tensor. The label is the true value of the chip's performance evaluation. The model is trained based on the training sample set to obtain the performance evaluation model.

[0103] This application provides a chip performance evaluation device that comprehensively collects time-series data of multi-dimensional performance indicators during chip simulation, integrates and aligns the data in the time domain, accurately captures the dynamic changes of each indicator under different time windows, and performs comprehensive analysis of multi-indicator collaborative data in conjunction with a performance evaluation model. This covers key collaborative scenarios such as instruction execution, data interaction, and resource scheduling of multiple chip modules, comprehensively reflecting the collaborative state of each module. It overcomes the limitations of single-indicator analysis, avoids missing hidden performance bottlenecks in cross-module coupling, and can reveal cross-module performance coupling problems. The performance evaluation results can more realistically reflect the actual operating state of the chip, reduce evaluation bias, and improve the accuracy and reliability of chip performance evaluation in the pre-silicon stage, thus providing accurate and effective data support for chip iterative upgrades.

[0104] It should be noted that the chip performance evaluation device provided in the above embodiments is only illustrated by the division of the above functional modules when running the application. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the electronic device can be divided into different functional modules to complete all or part of the functions described above. In addition, the chip performance evaluation device and the chip performance evaluation method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0105] This application also provides an electronic device. Figure 11 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. This electronic device can be implemented as a server or a terminal. See also... Figure 11 The electronic device 1100 may vary considerably due to different configurations or performance, and may include one or more Central Processing Units (CPUs) 1101 and one or more memories 1102.

[0106] Processor 1101 may include one or more processing cores, such as a 4-core processor or an 11-core processor. Processor 1101 may be implemented using at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). Processor 1101 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state.

[0107] The memory 1102 may include one or more computer-readable storage media, which may be non-transitory. The memory 1102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0108] For electronic device 1100, the memory 1102 stores at least one computer program, which is loaded and executed by processor 1101 to implement the chip performance evaluation method provided in the above-described method embodiments. Of course, electronic device 1100 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input / output. Electronic device 1100 may also include other components for implementing device functions, which will not be elaborated here.

[0109] Those skilled in the art will understand that Figure 11 The structure shown does not constitute a limitation on the electronic device 1100, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0110] This application also provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to implement the chip performance evaluation method described in the above embodiments. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc. This application also provides a computer program product, including a computer program that is executed by a processor to implement the chip performance evaluation method in this application.

[0111] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0112] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip performance evaluation method, characterized in that, The method includes: Acquire timing data of multiple performance indicators during chip simulation; Based on the time-series data of the multiple performance indicators, a two-dimensional feature tensor is determined. The rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively. The elements in the two-dimensional feature tensor represent the number of valid data entries for the corresponding performance indicator under the corresponding time window. The two-dimensional feature tensor is input into the performance evaluation model to obtain the performance evaluation results of the chip.

2. The method according to claim 1, characterized in that, The acquisition of timing data for multiple performance indicators during chip simulation includes: The monitoring data during the chip simulation process sent by the hardware emulator is acquired. The hardware emulator is used for accelerated chip simulation. Time-series data of the multiple performance indicators are selected from the monitoring data.

3. The method according to claim 1, characterized in that, The determination of the two-dimensional feature tensor based on the time-series data of the multiple performance metrics includes: The time series data of the multiple performance indicators are segmented and counted according to time windows to obtain a one-dimensional time series for each performance indicator. The elements in the one-dimensional time series represent the number of valid data entries of the performance indicator under the corresponding time window. Align the one-dimensional time series of the multiple performance metrics to obtain the two-dimensional feature tensor.

4. The method according to claim 3, characterized in that, The time-series data of the multiple performance indicators are segmented and counted according to time windows to obtain a one-dimensional time series for each performance indicator, including: Based on the preset time window value and the timestamps in the time series data, the time span corresponding to the time series data of each performance indicator is divided to obtain multiple time windows; The number of valid data entries in each time window of the time series data of the performance indicator is determined to obtain the one-dimensional time series of the performance indicator.

5. The method according to claim 3, characterized in that, The process of aligning the one-dimensional time series of the multiple performance metrics to obtain the two-dimensional feature tensor includes: Based on the one-dimensional time series of the multiple performance indicators, a baseline length is determined, wherein the baseline length is the minimum sequence length among the multiple one-dimensional time series. The one-dimensional time series of the multiple performance indicators are truncated to the baseline length to generate the two-dimensional feature tensor.

6. The method according to claim 1, characterized in that, The method further includes: Based on the time-series data of the multiple performance indicators, a feature map is determined for each performance indicator, and the feature map is used to describe the relationship between the indicator value and time for each performance indicator. Based on the feature maps of the multiple performance indicators and the performance evaluation results, a performance analysis report for the chip is generated.

7. The method according to claim 1, characterized in that, The training steps for the performance evaluation model include: Obtain a defined training sample set, which includes multiple two-dimensional feature tensors and a label for each two-dimensional feature tensor, wherein the label is the true value for chip performance evaluation. The performance evaluation model is obtained by training the model based on the training sample set.

8. A chip performance evaluation device, characterized in that, The device includes: The data acquisition module is used to acquire timing data of multiple performance indicators during chip simulation. The tensor determination module is used to determine a two-dimensional feature tensor based on the time-series data of the multiple performance indicators. The rows and columns of the two-dimensional feature tensor correspond to different performance indicators and different time windows, respectively. The elements in the two-dimensional feature tensor represent the number of valid data entries for the corresponding performance indicator under the corresponding time window. The performance evaluation module is used to input the two-dimensional feature tensor into the performance evaluation model to obtain the performance evaluation result of the chip.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory being used to store at least one computer program, the at least one computer program being loaded by the processor and executed as the chip performance evaluation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store at least one computer program for performing the chip performance evaluation method according to any one of claims 1 to 7.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the chip performance evaluation method as described in any one of claims 1 to 7.

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