Automatic wiring method and device and computer equipment

Abstract

The invention relates to an automatic wiring method and device and computer equipment. The method comprises the following steps: determining node information and routing rules of a plurality of network nodes according to circuit principle design; constructing a line width and line distance constraint and a network node parameter constraint corresponding to a network node type according to the node information of the network node and a routing rule; determining a priority parameter of each network node according to the node information of the network nodes; and based on the line width and line distance constraint, the network node parameter constraint corresponding to the network node type and the priority parameter of each network node, completing automatic wiring of the network nodes through a path optimization algorithm, and obtaining a wiring result designed for the circuit principle. According to the method, automatic wiring is carried out by combining the line width and line distance constraint, the network node parameter constraint and the priority parameter of each network node, so that the accuracy of automatic wiring is improved, and the actual circuit can be further ensured to be normally used after wiring is completed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, and in particular to an automatic wiring method and device and computer equipment. BACKGROUND

[0002] PCB automatic wiring is an important function in modern electronic design automation tools, which automatically completes the wire connection on the circuit board through software algorithm, thereby reducing manual intervention, improving design efficiency and accuracy. In the process of PCB automatic wiring, basic information such as circuit board size, number of layers, component layout, etc. is determined, and detailed design rules are set. The network table is extracted from the schematic diagram, and the data required for electrical connection between pins is determined. According to the specific requirements, appropriate wiring strategy and algorithm are selected. Run the automatic wiring program to complete the wiring task according to the predetermined rules and strategies. Common wiring strategies and algorithms include artificial potential field method, grid method and template model method, etc.

[0003] The PCB automatic wiring method in the related art has poor wiring accuracy, so that the actual circuit after wiring completion cannot be normally used. SUMMARY

[0004] Therefore, it is necessary to provide an automatic wiring method, device and computer equipment in view of the above technical problems.

[0005] In a first aspect, the present application provides an automatic wiring method, comprising: determining node information of a plurality of network nodes and wiring rules according to a circuit schematic design; constructing line width and distance constraints and network node parameter constraints corresponding to network node types according to the node information of the network nodes and the wiring rules; determining a priority parameter of each network node according to the node information of the network nodes; and completing automatic wiring of the network nodes by a path optimization algorithm based on the line width and distance constraints, the network node parameter constraints corresponding to the network node types, and the priority parameter of each network node, to obtain a wiring result for the circuit schematic design.

[0006] In one embodiment, the constructing line width and distance constraints and network node parameter constraints corresponding to network node types according to the node information and wiring rules comprises: the network nodes include power supply network nodes and signal transmission network nodes; line width and distance constraints are constructed according to line width rules and line distance rules in the wiring rules; if the type of the network node is a power supply network node, first parameter constraints corresponding to the power supply network node are constructed according to the node information and the wiring rules; and if the type of the network node is a signal transmission network node, second parameter constraints corresponding to the signal transmission network node are constructed according to the node information and the wiring rules.

[0007] In one of the embodiments, the constructing the first parameter constraint corresponding to the power supply network node according to the node information and the routing rule includes: the first parameter constraint includes a current capacity constraint, a loop area constraint and a noise constraint; the current capacity constraint is constructed according to the copper foil thickness of the routing layer in the node information and the material coefficient of the copper foil and the current rule in the routing rule; the loop area constraint is constructed according to the Manhattan length in the node information; and the noise constraint is constructed according to the specification allowable noise in the node information.

[0008] In one of the embodiments, the constructing the second parameter constraint corresponding to the signal transmission network node according to the node information and the routing rule includes: the second parameter constraint includes an impedance deviation constraint, a loss constraint and a routing layer constraint; the impedance deviation constraint is constructed according to the target impedance value in the node information; the loss constraint is constructed according to the specification loss value in the node information; and the routing layer constraint is constructed according to the routing layer rule in the routing rule.

[0009] In one of the embodiments, the determining the priority parameter of each network node according to the node information of the network node includes: determining a plurality of key indicators of each network node according to the node information of the network node; obtaining an indicator weight corresponding to each key indicator; determining a demand resource, an effective resource and a resource shortage coefficient of each network node according to the node information of the network node; determining a resource indicator of each network node according to the demand resource, the effective resource and the resource shortage coefficient of each network node; and determining the priority parameter of each network node according to the plurality of key indicators of each network node, the indicator weight corresponding to each key indicator and the resource indicator of each network node.

[0010] In one of the embodiments, the automatic routing of the network node is completed through a path optimization algorithm based on the line width and distance constraint, the network node parameter constraint corresponding to the network node type and the priority parameter of each network node includes: the automatic routing of each network node is performed through an A-star algorithm according to the priority parameter of each network node in descending order based on the line width and distance constraint and the network node parameter constraint corresponding to the network node type.

[0011] In one of the embodiments, the method further includes: constructing a routing constraint and a layout constraint based on the routing result of the circuit principle design; and optimizing the routing result of the circuit principle design through a simulated annealing algorithm based on the routing constraint and the layout constraint to obtain an optimized routing result.

[0012] In one of the embodiments, the constructing the routing constraints and the layout constraints based on the routing result of the circuit schematic design comprises: meshing the routing result of the circuit schematic design; determining the routing density threshold, the device height threshold, the device temperature threshold and the device stress threshold corresponding to each mesh based on the routing result of the circuit schematic design; constructing the routing constraints according to the routing density threshold; and constructing the layout constraints according to the device height threshold, the device temperature threshold and the device stress threshold.

[0013] In one of the embodiments, the optimizing the routing result of the circuit schematic design based on the routing constraints and the layout constraints by the simulated annealing algorithm to obtain the optimized routing result comprises: determining the resource index of each mesh according to the required resource and the effective resource of each mesh; determining the height index, the temperature index and the stress index of each mesh according to the device height, the device temperature and the device stress of each mesh; and optimizing the routing result of the circuit schematic design by the simulated annealing algorithm according to the resource index, the height index, the temperature index, the stress index, the routing constraints and the layout constraints of each mesh to obtain the optimized routing result.

[0014] In the second aspect, the application further provides an automatic routing device, which comprises: an acquisition module configured to determine node information of a plurality of network nodes and routing rules according to a circuit schematic design; a constraint construction module configured to construct line width and distance constraints and network node parameter constraints corresponding to network node types according to the node information and the routing rules; a priority calculation module configured to determine a priority parameter of each network node according to the node information of the network nodes; and a routing module configured to complete automatic routing of the network nodes by a path optimization algorithm based on the line width and distance constraints, the network node parameter constraints corresponding to the network node types and the priority parameter of each network node to obtain a routing result for the circuit schematic design.

[0015] In the third aspect, the application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements any of the automatic routing methods in the first aspect when executing the computer program.

[0016] The automatic wiring method, device and computer equipment described above determine node information of a plurality of network nodes and wiring rules according to a circuit principle design. According to the node information and the wiring rules, line width and line spacing constraints and network node parameter constraints corresponding to network node types are constructed. According to the node information of the network nodes, priority parameters of each network node are determined. Finally, according to the line width and line spacing constraints, the network node parameter constraints corresponding to the network node types and the priority parameters of each network node, automatic wiring of the network nodes is completed through a path optimization algorithm, and a wiring result for the circuit principle design is obtained. By combining the line width and line spacing constraints, the network node parameter constraints and the priority parameters of each network node for automatic wiring, the accuracy of the automatic wiring is improved, and further, it is ensured that the actual circuits after wiring completion can be normally used. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A flowchart of an automatic wiring method in an embodiment;

[0018] Figure 2 A flowchart of a constraint design method in an embodiment;

[0019] Figure 3 A flowchart of a network node priority determination method in an embodiment;

[0020] Figure 4 A flowchart of an automatic wiring optimization method in an embodiment;

[0021] Figure 5 A structural block diagram of an automatic wiring device in an embodiment;

[0022] Figure 6 An internal structure diagram of a computer equipment in an embodiment. DETAILED DESCRIPTION

[0023] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0024] PCB automatic routing is an important function in modern electronic design automation tools. It automatically connects the wires on the circuit board through software algorithms, reducing manual intervention and improving design efficiency and accuracy. In PCB automatic routing, basic information such as circuit board size, number of layers, component layout, and detailed design rules are determined. The network table is extracted from the schematic diagram to determine the electrical connection between pins. According to the specific requirements, choose the appropriate routing strategy and algorithm. Run the automatic routing program to complete the routing task according to the predetermined rules and strategies. Common routing strategies and algorithms include artificial potential field method, grid method, and template model method, etc.

[0025] In the current related technology, PCB automatic routing is mainly used to improve the efficiency and quality of path planning and implementation of wiring. Further, some automatic routing methods improve traditional routing algorithms and introduce cost functions to improve efficiency and quality. However, in related technology, there is a problem of poor routing accuracy, which leads to the actual circuit after routing cannot be used normally.

[0026] In one embodiment, as shown in Figure 1 An automatic routing method is provided, comprising the following steps:

[0027] Step 101, according to the circuit principle design, determine the node information of a plurality of network nodes and the wiring rule.

[0028] Before automatic routing, the circuit principle design needs to be performed first to determine the basic information of the printed circuit board (PCB circuit board). For example: PCB board size, number of layers, number of components, component type, component position, and connection relationship of each pin of the component. For example: the first pin of the first component is connected to the third pin of the fourth component, the second pin of the third component is connected to the first pin of the second component, etc.

[0029] According to all the data corresponding to the circuit principle design, node information and trace rule of the plurality of network nodes are determined. The network node is a connection relationship between pins of each component, for example, a first pin of a first component is connected to a third pin of a fourth component, and the wiring between the corresponding two pins is the network node. The node information of the network node includes: network node type, network node corresponding pin pad information, PCB layer structure information, layer information where the network node corresponding pin pad is located, via impedance, via size, maximum via quantity, copper foil thickness of the trace layer, material coefficient of the copper foil, Manhattan length of the network node, specification allowable noise, target impedance value and specification loss value, etc. The trace rule of the network node includes: line width rule, line spacing rule, trace layer rule, wiring layer priority list and current rule, etc.

[0030] The network node type can be one or more of a power supply network node, a signal transmission network node, a power supply network node, a ground network node, a high-speed signal network node and an analog signal network node; the pin pad information can include the shape, size, identification, position coordinates, etc. of the pad; the PCB layer structure information can be the number of layers of the circuit board and the function of each layer, such as the top layer, the bottom layer or the inner layer; the via parameter can include the via impedance, the via size or the maximum via quantity, etc.; the copper foil attribute can involve the copper foil thickness or the material coefficient; the Manhattan length can be the total distance between two points along the horizontal and vertical directions. The specification allowable noise can be the allowable noise during the circuit principle design; the target impedance value can be the impedance value during the circuit principle design; and the specification loss value can be the loss value during the circuit principle design.

[0031] The trace rule can be a constraint condition defined in the circuit principle design specification, which is obtained by extracting the rule from the design rule library. For example, the trace rule can include line width rule, line spacing rule, trace layer rule, wiring layer priority list or current rule, etc. For example, the line width rule can specify the line width of different signal types; the line spacing rule can limit the spacing of adjacent conductors; the trace layer rule can specify the wiring layer that must be used for a specific network node; the wiring layer priority list can define the priority order of each layer; and the current rule can adjust the line width according to the current size.

[0032] Specifically, when automatic wiring is constructed, the basic attribute unit of the network node is constructed, including: node information and trace rule, so as to establish the association of the basic characteristics of the network node, mainly through the network node to realize the classification of the circuit type, and realize the definition of the wiring attribute of the network node. Specifically as follows:

[0033]

[0034] Wherein, NetNodeInfo represents network node information, that is, the identification of two pins; CircuitType represents node circuit type; NetName represents network name, which is used to represent the network name of the pin; Manhattan Length represents the Manhattan distance between pins, through which the signal type of the network can be determined; PhysicalRule represents the line width rule of the node; SpacingRule represents the line spacing rule of the node; DeleteLineCost represents the line deletion cost of the node; NetNodeLayerStruc represents the layer structure of the node; RecommendRoutingLayer represents the recommended routing layer of the node; RecommendMaxVias represents the recommended maximum number of vias of the node; NetNodeLocation represents the coordinate position information of the node.

[0035] For example, the above table can be represented in the form of a matrix to define the network node automatic routing parameter matrix information. For example:

[0036]

[0037] Wherein, N represents the parameter matrix of the network node; Nct represents the circuit type; Nnn represents the network name; Nml represents the Manhattan distance between pins; Nph represents the line width rule; Nsp represents the line spacing rule; Ncost represents the line deletion cost of the node; Nnl represents the layer structure of the node; Nrl represents the recommended routing layer; Nrv represents the recommended maximum number of vias.

[0038] In step 102, according to the node information of the network node and the routing rule, the line width and spacing constraints and the network node parameter constraints corresponding to the network node type are constructed.

[0039] After obtaining the node information of the network node and the routing rule, the constraint rules during automatic routing are constructed based on the above information. The constraint rules include line width and spacing constraints and network node parameter constraints corresponding to the network node type. The line width and spacing constraints can be the restriction conditions in the mathematical expression or algorithm by converting the line width rule and the line spacing rule in the routing rule. The network node parameter constraint can be a specific parameter limit set for different network node types. For example, the parameter constraint corresponding to the power supply network node designed for the power supply network node; the parameter constraint corresponding to the signal transmission network node designed for the signal transmission network node. For example, the current capacity constraint, loop area constraint and noise constraint can be designed for the power supply network node. The impedance deviation constraint, loss constraint and routing layer constraint can be designed for the signal transmission network node.

[0040] By converting the abstract design rules into computable constraints, the feasibility of the path can be judged in real time during automatic routing, and the violation of the design specification can be avoided.

[0041] In step 103, the priority parameter of each network node is determined according to the node information of the network node.

[0042] After obtaining the node information of the network node, the priority of each network node needs to be determined. Specifically, the key indicators of each network node can be determined according to the node information, and the key indicators can be the current demand rate, the voltage drop indicator, etc. The key indicators are not limited in the embodiment, and can be set according to the actual use demand, as long as the performance parameters of the network node can be reflected. Then, the resource indicators of each network node are determined according to the node information, and the resource indicators are the ratio of the resource demand of the network node to the actual resource in the circuit board. The priority parameter of each network node is determined by comprehensively considering the key indicators and the resource indicators.

[0043] In step 104, the automatic routing of the network node is completed by the path optimization algorithm based on the line width and distance constraint, the network node parameter constraint corresponding to the network node type, and the priority parameter of each network node, and the wiring result for the circuit principle design is obtained.

[0044] The path optimization algorithm can be an algorithm for searching the optimal routing path under the constraint condition. For example, the path optimization algorithm can include improved A-star algorithm, genetic algorithm or artificial potential field method, etc. For example, the A-star algorithm can combine the heuristic function with the constraint condition, and the genetic algorithm can optimize the path by iteration.

[0045] Based on the line width and distance constraint and the network node parameter constraint corresponding to the network node type, the automatic routing of each network node is performed by the A-star algorithm according to the order of the priority parameter of each network node from large to small.

[0046] First, the network node to be routed is selected according to the order of the priority parameter from large to small, and then the feasible path is searched under the constraint condition. The A-star algorithm takes Manhattan distance as the heuristic function, and simultaneously checks whether the path meets the line width, line distance and layer rules in real time. If the path conflicts, it is backtracked and other branches are tried. For impedance-sensitive nodes, the algorithm can dynamically adjust the line width or via number to match the target impedance value. The algorithm continuously verifies whether the candidate path meets all parameter constraints, such as whether the wire resistance is within the allowed range or the via number is not over the limit. The finally generated wiring result needs to meet the connection requirements of all nodes and optimize the overall wiring efficiency as much as possible.

[0047] The embodiment first determines node information of a plurality of network nodes and a routing rule. According to the node information and the routing rule, a line width and distance constraint and a network node parameter constraint corresponding to a network node type are constructed. According to the node information of the network nodes, a priority parameter of each network node is determined. Finally, according to the line width and distance constraint, the network node parameter constraint corresponding to the network node type, and the priority parameter of each network node, automatic routing of the network nodes is completed through a path optimization algorithm, and a routing result for the circuit principle design is obtained. Through automatic routing combined with the line width and distance constraint, the network node parameter constraint, and the priority parameter of each network node, the accuracy of automatic routing is improved, and further, it is ensured that the actual circuit after routing is completed can be normally used.

[0048] In one embodiment, as shown in Figure 2 a constraint design method is provided, comprising the following steps:

[0049] Step 201, according to the line width rule and the line distance rule in the routing rule, a line width and distance constraint is constructed.

[0050] The line width and distance constraint is determined by directly calling the line width rule and the line distance rule in the routing rule. Specifically, for each segment of the to-be-routed path corresponding to the to-be-routed network node, the safety corridor width is calculated as follows:

[0051]

[0052] wherein, safety corridor width; actual routing width, which can refer to the line width rule; minimum distance required by the design rule, which can refer to the line distance rule; process error tolerance. The process error tolerance needs to be set according to actual use requirements, which is not limited in the embodiment. When the constraint is performed, the safety corridor width needs to be within a pre-set threshold range, so as to meet the routing requirement.

[0053] Step 202, if the type of the network node is a power supply network node, a first parameter constraint corresponding to the power supply network node is constructed according to the node information and the routing rule.

[0054] For different network node types, the key performance constraints of each network node type are defined. For example, the current capacity of the network node corresponding to the power supply circuit, the impedance matching of the network node corresponding to the high-speed signal, the spacing requirement of the network node corresponding to the isolation circuit, etc. For example, the network node types include a power supply network node and a signal transmission network node.

[0055] When the type of the network node is a power supply network node, the wiring width, the length of the loop path, and the isolation of the sensitive and noise signals need to be concerned, so as to construct the first parameter constraint corresponding to the power supply network node. For example, the first parameter constraint includes: a current capacity constraint, a loop area constraint, and a noise constraint.

[0056] According to the copper foil thickness of the wiring layer in the node information and the material coefficient of the copper foil and the current rule in the wiring rule, the current capacity constraint is constructed. The current capacity constraint can be the minimum current carrying capacity requirement that the power supply network node must meet, and can be constructed by the copper foil thickness, the material conductivity in the node information, and the current rule in the wiring rule. The current capacity constraint is specifically as follows:

[0057]

[0058]

[0059] wherein I represents the current rule, that is, the required current range; represents the minimum line width; k represents the material coefficient of the copper foil; t represents the copper foil thickness of the wiring layer; represents the product system recommended temperature rise; represents the actual wiring line width; Pc represents the current capacity constraint penalty value. The current rule, the material coefficient of the copper foil, the copper foil thickness of the wiring layer, and the product system recommended temperature rise can be determined according to the design document after the circuit principle design. When using the constraint, the current capacity constraint penalty value is set to have a corresponding threshold range, and the wiring path is continuously adjusted so that the current capacity constraint penalty value meets the threshold range. The threshold range can be set according to the recommendation of the chip manufacturer, or can be set according to the actual use demand, and the embodiment is not limited specifically.

[0060] According to the Manhattan length in the node information, the loop area constraint is constructed. The loop area constraint can be the loop area formed by the power supply network wiring path, and can be calculated by the Manhattan path length in the node information. The loop area constraint is specifically as follows:

[0061]

[0062] wherein, represents the actual length of the power loop; represents the Manhattan length of the power loop; The loop area penalty value represents a loop area penalty value. The Manhattan length refers to the total length of a wire between two points, and the wire follows the horizontal and vertical direction routing rules. The Manhattan length is determined according to the design document after the circuit principle design. When the constraint is used, the loop area penalty value is set to have a corresponding threshold range, and the loop area penalty value is adjusted to meet the preset range. The threshold range can be set according to the recommendations of the chip manufacturer, or can be set according to the actual use requirements, and the embodiment is not limited in detail.

[0063] According to the specification allowable noise in the node information, a noise constraint is constructed. The noise constraint can be the voltage ripple tolerance requirement of the power supply network to the adjacent signal line, which is constructed by the specification allowable noise value in the node information. The noise constraint is specifically as follows:

[0064]

[0065] wherein, The actual estimated noise represents an actual estimated noise; The specification allowable noise represents a specification allowable noise; and Ps represents a noise isolation penalty value. The actual estimated noise can be determined by fast simulation after obtaining a candidate layout result. The specification allowable noise is determined according to the design document after the circuit principle design. When the constraint is used, the noise isolation penalty value is set to have a corresponding threshold range, and the noise isolation penalty value is adjusted to meet the threshold range. The threshold range can be set according to the recommendations of the chip manufacturer, or can be set according to the actual use requirements, and the embodiment is not limited in detail.

[0066] In the embodiment, the first parameter constraint of the power supply network node is decomposed into three dimensions of current capacity, loop area and noise. The current capacity constraint ensures the thermodynamic feasibility through conductor and temperature rise calculation, the loop area constraint reduces the parasitic inductance influence through Manhattan path geometry analysis, and the noise constraint controls the voltage ripple amplitude through the electromagnetic coupling model. The three work together to realize the multi-objective optimization of the power supply path in the aspects of thermal management, electromagnetic compatibility and signal integrity. The performance defects caused by the single dependence on the line width rule in the traditional routing method are solved, thereby significantly improving the routing accuracy and system reliability of the power supply network.

[0067] In step 203, if the type of the network node is a signal transmission network node, a second parameter constraint corresponding to the signal transmission network node is constructed according to the node information and the wire routing rules.

[0068] When the type of the network node is a signal transmission network node, the impedance, loss and consistency of the wiring path in the same group need to be concerned, so as to construct the second parameter constraint corresponding to the signal transmission network node. For example, the second parameter constraint includes impedance deviation constraint, loss constraint and wiring layer constraint.

[0069] According to the target impedance value in the node information, an impedance deviation constraint is constructed. The impedance deviation constraint can be formed by combining the target impedance value with an allowed deviation range to form an impedance constraint interval. The impedance deviation constraint is specifically as follows:

[0070]

[0071] wherein, represents an actual impedance value, represents a target impedance value; and Pz represents an impedance deviation penalty value. The actual impedance value can be determined by means of fast simulation after obtaining a candidate layout result. The target impedance value is determined according to a design document after the principle design of the circuit. When the constraint is used, the impedance deviation penalty value is set with a corresponding threshold range, and the impedance deviation penalty value is adjusted continuously to meet the threshold range. The threshold range can be set according to the recommendations of the chip manufacturer or according to the actual use requirements, and the present embodiment is not limited in detail.

[0072] According to the specification loss value in the node information, a loss constraint is constructed. The loss constraint is specifically as follows:

[0073]

[0074] wherein, represents a conductor loss value; represents a dielectric loss value; represents a specification loss value; and Pa represents a loss penalty value. The conductor loss value and the dielectric loss value can be determined by means of fast simulation after obtaining a candidate layout result. The specification loss value is determined according to a design document after the principle design of the circuit. When the constraint is used, the loss penalty value is set with a corresponding threshold range, and the loss penalty value is adjusted continuously to meet the threshold range. The threshold range can be set according to the recommendations of the chip manufacturer or according to the actual use requirements, and the present embodiment is not limited in detail.

[0075] According to the routing layer rule in the routing rule, a routing layer constraint is constructed. The routing layer constraint indicates that the routing of the same function is set on the same routing layer as possible. The routing layer constraint is specifically as follows:

[0076]

[0077] wherein, represents an actual routing layer of the network node; represents a routing layer of the routing layer rule; represents an actual routing layer of the longest path of the network node; The difference between the actual routing layer of the network node and the routing layer of the routing layer rule is represented. The difference between the actual routing layer of the network node and the routing layer of the routing layer rule is represented. The difference between the actual routing layer of the network node and the routing layer of the routing layer rule is represented.

[0078] In this embodiment, the second parameter constraint is decomposed into three independent constraint conditions, i.e., an impedance deviation constraint, a loss constraint, and a routing layer constraint. The impedance deviation constraint ensures the reflection coefficient control through the target impedance value and the transmission line model. The loss constraint realizes the energy loss limitation through the current, resistance, and path length calculation. The routing layer constraint realizes the physical layer isolation through the layer rule analysis, and can realize multi-dimensional constraint cooperative optimization of signal integrity and improve the algorithm calculation efficiency. Through the modular design of the constraint conditions, the electrical performance requirements such as impedance matching, voltage drop control, and interference suppression are ensured, and the problem of high calculation complexity caused by constraint synthesis in the traditional method is avoided, thereby realizing the precision of resource allocation and the improvement of the reliability of the routing result.

[0079] In one of the embodiments, the key performance of different network nodes is different, and the routing priority is different. In the system, there are various circuit structures, and when the space resource is insufficient, the space resource needs to be reasonably allocated. A priority strategy under the condition of multiple circuits is constructed, and a mutual restriction and driving mechanism between multiple circuits is established, so that the routing performance of the system reaches the optimal state under the requirements of various circuit structures. For example, Figure 3 As shown in the figure, a network node priority determination method is provided, which specifically includes the following steps:

[0080] In step 301, according to the node information of the network node, a plurality of key indicators of each network node are determined.

[0081] The key indicators can be quantitative parameters reflecting the routing difficulty or importance of the network node, which can be obtained through node type, path parameter, or electrical characteristic information. For example, the key indicators can be current demand rate, voltage drop indicator, etc. The key indicators are not limited in this embodiment, and can be set according to actual use requirements, as long as they can reflect the performance parameters of the network node.

[0082] When the key indicator is the current demand rate, it can be calculated by dividing the actual load current by the maximum current capacity of the circuit design. Specifically, S_j1 = (I_actual / I_max) x 100%. Wherein, S_j1 represents the current demand rate; I_actual represents the actual load current; I_max represents the maximum current capacity of the circuit design. Wherein, the actual load current and the maximum current capacity of the circuit design can be determined according to the design document after the circuit principle design.

[0083] When the key indicator is the voltage drop indicator, it can be calculated by subtracting the estimated actual voltage drop from the maximum allowed voltage drop. Specifically, S_j2 = V_drop_max_allowed - V_drop_estimated. Wherein, S_j2 represents the voltage drop indicator; V_drop_max_allowed represents the maximum allowed voltage drop; V_drop_estimated represents the estimated actual voltage drop. The maximum allowed voltage drop and the estimated actual voltage drop can be determined according to the design document after the circuit principle design.

[0084] Step 302, obtaining the indicator weight corresponding to each key indicator.

[0085] The indicator weight can be a pre-set or dynamically adjusted value, which is used to quantify the influence degree of different key indicators on the priority. The indicator weight can be set according to the actual use demand, and the embodiment does not make specific limitation. For example, the indicator weight can be configured by design target or engineering experience. For example, when the key indicators include the current demand rate and the voltage drop indicator, the indicator weight w1 corresponding to the current demand rate and the indicator weight w2 corresponding to the voltage drop indicator are obtained.

[0086] Step 303, determining the demand resource, effective resource and resource shortage coefficient of each network node according to the node information of the network node.

[0087] The demand resource can be the total amount of physical resources required by the network node to complete the wiring. For example, it can be the minimum path length, the number of required vias, and the occupied copper foil area, etc. The effective resource can be the remaining resource available for the network node in the current PCB layout. For example, it can be the unoccupied wiring space, the available number of layers, and the remaining copper foil capacity, etc. The resource shortage coefficient is a pre-set coefficient. The demand resource and the effective resource can be determined according to the design document after the circuit principle design.

[0088] Step 304, determining the resource indicator of each network node according to the demand resource, effective resource and resource shortage coefficient of each network node.

[0089] Specifically as follows:

[0090] Resource index

[0091] wherein, represents demand resource; represents effective resource; represents resource tension coefficient. Specifically, the demand resource is the wiring resource required to be evaluated by the line width and line spacing obtained through the network node rules or other conditions. The demand resource can include general resource, specific layer resource, area resource, and special resource, etc. For example, the line width rule is 5 mil, and the line spacing rule is 5 mil. Then the demand resource is the line width rule plus the line spacing rule, that is, 10 resource points. The effective resource is to identify the maximum continuous space based on image processing technology, calculate the minimum channel width, evaluate the topology value of the channel, and then calculate the effective wiring resource. The ratio of the demand resource to the effective resource represents the proportion of the required resource to the effective resource. When the ratio is less than 1, it means that the demand resource is less than the remaining effective resource, and the wiring is relatively easy; when the ratio is equal to 1, it means that the effective resource just meets the demand resource; when the ratio is less than 1, it means that the demand resource exceeds the effective resource, or there is a wiring conflict, winding, and performance degradation.

[0092] In step 305, according to the plurality of key indicators of each network node, the index weight corresponding to each key indicator, and the resource index of each network node, the priority parameter of each network node is determined.

[0093] Specifically as follows:

[0094]

[0095] wherein, represents the index normalization item; Sj represents the score of the jth index; represents the theoretical minimum value of the jth index; represents the theoretical maximum value of the jth index; wj represents the weight of the jth index; represents the priority parameter. The theoretical minimum value of the index and the theoretical maximum value of the index can be determined according to the design document after the circuit principle design.

[0096] For example, when the key indicators include the current demand rate and the voltage drop indicator, the current demand rate S1, the voltage drop indicator S2, the indicator weight w1 corresponding to the current demand rate, and the indicator weight w2 corresponding to the voltage drop indicator are obtained. Smin,1 represents the theoretical minimum value of the current demand rate, which can be 0%, indicating that the current can be very small in theory; Smax,1 represents the theoretical maximum value of the current demand rate, which can be 100%, indicating that the maximum design current is reached, and the load has reached the limit. Smin,2 represents the theoretical minimum value of the voltage drop indicator, which can be 0, indicating that the actual voltage drop is exactly the maximum allowed value; Smax,2 represents the theoretical maximum value of the voltage drop indicator, which can be the maximum allowed voltage drop, indicating that the minimum voltage drop is 0 and the actual voltage drop is 0.

[0097] Based on S_j1 = (I_actual / I_max) × 100%. When the actual load current I_actual approaches the maximum current capacity I_max, the current demand rate S1 approaches Smax,1, that is, ((S1 - Smin,1) / (Smax,1 - Smin,1)) approaches 1, and the priority of the network node is raised.

[0098] When the power integrity analysis engine of the router estimates that the estimated actual voltage drop V_drop_estimated on a certain module power supply path is large, resulting in a small S2, that is, close to Smin,2, ((S2 - Smin,2) / (Smax,2 - Smin,2)) will become small, that is, close to 0. In order to represent the severity of voltage drop, w2 needs to be increased when the voltage margin is low. When S2 is the actual estimated voltage drop value, Smin,2=0 and Smax,2=the maximum allowed voltage drop V_drop_max_allowed, then (S_j2 - 0) / (V_drop_max_allowed - 0) is larger, the priority is higher.

[0099] After calculating the priority parameters of each network node in the above manner, the network nodes are sorted in descending order of the priority parameters to obtain the wiring priority order of the network nodes.

[0100] In this embodiment, the priority weights of the network nodes are dynamically adjusted according to the design constraints and the performance requirements of the network nodes. For example, the priority of the network node corresponding to the power supply circuit is increased when the current demand is high and the voltage value is reduced; the priority of the network node corresponding to the high-speed signal is increased when the frequency is increased and the driving capability is weak. Thus, the global priority is defined by the analytic hierarchy process (AHP). The path conflicts are reduced through real-time evaluation of the resource shortage coefficient, the electrical and spatial constraints are cooperatively optimized through multi-indicator weighting, the scene adaptability is enhanced through weight configuration, and finally the wiring backtracking times are reduced and the wiring success rate and result reliability are improved.

[0101] In one embodiment, a conflict resolution mechanism can also be established to resolve conflicts between multiple network nodes when their routing requirements conflict, such as spatial overlap or spatial insufficiency, and to arbitrate according to the priorities and constraints of the network nodes to determine which network node to prioritize for routing or to adjust the design parameters to meet the requirements. When adjusting the design parameters, the line width, line spacing, and other parameters can be adjusted to meet the routing requirements. When a power supply network node and a high-speed signal network node conflict, the priority of the power supply network node is lower than that of the high-speed signal network node, and the conflict can be resolved by reducing the routing width of the power supply network node or changing layers. When an isolation zone network node and a routed network node conflict, the priority of the routed network node is lower than that of the isolation zone network node, and the isolation zone distance needs to be ensured first. When a high-speed signal network node and a routed network node conflict, the priority of the high-speed signal network node is lower than that of the routed network node, and the conflict can be resolved by changing layers, appropriately reducing the line spacing, and changing part of the line width.

[0102] In one embodiment, based on the line width and spacing constraints and the network node parameter constraints corresponding to the network node type, each network node is automatically routed in order of priority from high to low using the A-star algorithm. Specifically, the constraint conditions of the A-star algorithm include:

[0103] f(n)=g(n)+h(n)

[0104]

[0105] where g(n) represents the basic cost, including the length cost Lengthi, such as the length of the trace, the priority cost Prioritypenaltyi, such as the priority parameter of the network node described above, and the resource competition cost ResourceCosti, which can be a pre-set value determined according to the conflict conditions; h(n) represents the heuristic cost, which can be the same as the value of the resource competition cost.

[0106] A-star algorithm, also known as A algorithm: (A-Star Algorithm) is a heuristic search algorithm widely used in graph path planning and graph search problems. By considering the actual cost and heuristic estimation, it efficiently finds the shortest path from the starting point to the target point. The core of the A algorithm is its evaluation function f(n)=g(n)+h(n), where g(n) represents the actual cost from the starting point to the current node, and h(n) is the heuristic estimated cost from the current node to the target node.

[0107] In automatic wiring, first, all network nodes are arranged in descending order according to the priority parameter, to ensure that high-weight nodes are wired first; second, a search space containing the PCB wiring layer, via hole position and pad coordinates is constructed, and line width and spacing constraints, parameter constraints and layer rules are embedded as hard constraint conditions in the node expansion process; third, the heuristic function h(n) is defined, which uses Manhattan distance as the basis and dynamically adjusts the weight factor in combination with network node parameter constraints; fourth, in the path expansion process, it is verified in real time whether each step meets all constraint conditions; and finally, the wired path is marked as an occupied area to avoid conflicts with subsequent paths. Through priority-driven sequential planning, real-time embedding of constraint conditions and directional optimization of heuristic search, key path priority protection, multi-dimensional constraint dynamic satisfaction and wiring efficiency improvement are realized.

[0108] In one embodiment, after obtaining the wiring result of the circuit schematic design, the wiring result can be further optimized by a simulated annealing algorithm. As shown in Figure 4 An automatic wiring optimization method is provided, which specifically includes the following steps:

[0109] Step 401, based on the wiring result of the circuit schematic design, wiring constraints and layout constraints are constructed.

[0110] The wiring constraint can be a rule set for quantitatively limiting the wiring path parameter, which is obtained by the wiring density. The layout constraint can be a limitation condition of the device in the circuit and the spatial relationship between the device and the wiring path, which is obtained by the device layout data and the design specification.

[0111] First, the wiring result of the circuit schematic design is gridded.

[0112] Gridding refers to dividing the physical space of the printed circuit board into regular grid cells, each of which records the internal wiring path, device distribution and physical parameters. In this embodiment, the printed circuit board corresponding to the wiring result is gridded, for example, the grid size is set according to the size and design complexity of the printed circuit board, and the printed circuit board is split according to the grid size. Each grid records the wiring path, device distribution and physical parameters.

[0113] Based on the wiring result of the circuit schematic design, the wiring density threshold, device height threshold, device temperature threshold and device stress threshold corresponding to each grid are determined.

[0114] The wiring density threshold represents a maximum wiring density corresponding to each grid. The device height threshold represents a maximum height of a device allowed in each grid. The device temperature threshold represents a maximum temperature of a device allowed in each grid. The device stress threshold represents a maximum stress of a device allowed in each grid. The maximum wiring density, the device height threshold, the device temperature threshold, and the device stress threshold are determined according to a design document after a circuit principle design.

[0115] According to the wiring density threshold, a wiring constraint is constructed. The wiring constraint is specifically as follows:

[0116]

[0117] wherein, represents a required resource; represents an effective resource; and Congestion represents a resource index. The required resource can be a total amount of physical resources required by a network node to complete wiring. The effective resource can be a remaining resource available for the network node in a current PCB layout. When the constraint is used, the resource index needs to be less than the corresponding wiring density threshold.

[0118] According to the device height threshold, the device temperature threshold, and the device stress threshold, a layout constraint is constructed.

[0119] The layout constraint includes a device height constraint, a device temperature constraint, and a device stress constraint. According to the device height threshold, the device height constraint is constructed. According to the device temperature threshold, the device temperature constraint is constructed. According to the device stress threshold, the device stress constraint is constructed.

[0120] The device height constraint is specifically as follows:

[0121] Height Violation = hi - Hmax

[0122] wherein, hi represents an actual height of a device; Hmax represents a maximum height allowed in a region where the device is located; and Height Violation represents a height index of the device. When the constraint is used, the height index needs to be less than the corresponding device height threshold.

[0123] The device temperature constraint is specifically as follows:

[0124] Temp Violation = Ti - Tcrit

[0125] wherein, Ti represents a maximum tolerance temperature of a device; Tcrit represents a critical temperature allowed in a region where the device is located; and Temp Violation represents a temperature index of the device. When the constraint is used, the temperature index needs to be less than the corresponding device temperature threshold.

[0126] Stress Violation

[0127] wherein, represents the maximum tolerable stress of the device; represents the critical stress allowed in the region where the device is located; and Stress Violation represents the stress index of the device. When using this constraint, the stress index needs to be less than the corresponding device stress threshold.

[0128] At step 402, the routing result of the circuit schematic design is optimized by a simulated annealing algorithm based on the routing constraints and the layout constraints, to obtain an optimized routing result.

[0129] The simulated annealing algorithm can be a calculation method for global optimization through a random search mechanism. The routing result is initialized as an initial solution, a neighborhood solution is randomly generated, it is verified whether the candidate solution meets all the constraint conditions, it is decided whether to accept the candidate solution according to the change of the objective function, and the iteration is repeated until the termination condition is met. The simulated annealing algorithm can ensure that the final solution meets the routing and layout constraints.

[0130] According to the required resources and the effective resources of each grid, the resource index of each grid is determined; according to the device height, the device temperature and the device stress of each grid, the height index, the temperature index and the stress index of each grid are determined; according to the resource index, the height index, the temperature index, the stress index, the routing constraints and the layout constraints of each grid, the routing result of the circuit schematic design is optimized by a simulated annealing algorithm, to obtain an optimized routing result.

[0131] According to the required resources and the effective resources of each grid, the resource index of each grid is determined based on the formula in the above embodiment. According to the device height of each grid, that is, the actual height of the device; the device temperature, that is, the maximum tolerable temperature of the device; the device stress, that is, the maximum tolerable stress of the device; based on the formula in the above embodiment, the height index, the temperature index and the stress index of each grid are determined. Based on the above routing constraints and layout constraints, the routing result of the circuit schematic design is optimized by a simulated annealing algorithm, to obtain an optimized routing result.

[0132] Specifically, the simulated annealing algorithm is used to find the global optimal solution by adding wiring constraints and layout constraints. The simulated annealing algorithm (SA) is a random optimization algorithm based on the Monte Carlo iterative solution strategy. The algorithm is inspired by the annealing process of solid materials. By simulating the heating, isothermal and cooling process in physical annealing, the optimization problem with NP complexity is solved. The simulated annealing algorithm can effectively overcome the defect that the traditional optimization method is easy to fall into local minimum, and reduce the dependence on initial value. The simulated annealing algorithm avoids local optimization by accepting the probability of poor solution, and the energy function is the key to design. The constraint is added as a penalty term to the energy function, or the non-solution method is directly excluded when generating a new state.

[0133] The wiring congestion penalty term is set to meet the wiring space requirement, and the definition rule is as follows:

[0134]

[0135] Among them, represents the required resource; represents the effective resource; Congestion represents the wiring congestion penalty term. The required resource can be the total amount of physical resources required by the network node to complete the wiring. The effective resource can be the remaining resource available for the network node in the current PCB layout. If the wiring group or node density is greater than 1, it indicates that the resource is out of limit, and the penalty is counted.

[0136] The layout constraint penalty term is set to meet the layout adjustment requirement, and the definition rule is as follows:

[0137]

[0138] Among them, hi represents the actual height of the device; Hmax represents the maximum height allowed in the region where the device is located; Ti represents the maximum tolerance temperature of the device; Tcrit represents the critical temperature allowed in the region where the device is located; represents the maximum tolerance stress of the device; represents the critical stress allowed in the region where the device is located; ConstraintViolation represents the layout constraint penalty term. All equal to 0 in the layout constraint penalty term indicates that the demand is met, and one of them is not equal to 0, which indicates that the demand is not met, and the penalty is counted.

[0139] The wiring congestion penalty term and the layout constraint penalty term can also be integrated, as follows:

[0140]

[0141] Among them, represents the coefficient of the wiring congestion penalty term; a coefficient representing a layout constraint penalty term; E represents an integrated penalty term.

[0142] In the use of simulated annealing algorithm, the grid of (0, 0) position corresponds to E of 2.6136. At this time, if moving to (0, 1) position, the E of (0, 1) position is 2.25. That is, the E of (0, 1) position is less than the E of (0, 0) position, so it can be moved to (0, 1) position. At this time, if moving to (2, 4) position, the E of (2, 4) position is 0, that is, (2, 4) position can be the optimal solution, so it can be moved to (2, 4) position. It can be understood that in the simulated annealing process, multiple optimal solutions can be determined.

[0143] The application establishes general rules of network nodes through network association attributes, including: network node type, signal line width, line spacing rule, PCB layer structure information, network node pad layer, wiring suggestion layer, wiring layer priority list, via impedance, via size, maximum via quantity, etc., to build basic attribute units of automatic wiring. Based on circuit characteristics, dynamic automatic wiring priority strategies based on circuits are established through network node classification, including: network nodes corresponding to wired modules, network nodes corresponding to isolated circuits, network nodes corresponding to power circuits, and network nodes corresponding to high-speed bus circuits, and priority strategies of circuit-level automatic wiring are established, and multi-objective path planning is performed through path optimization algorithm. According to the spatial relationship between layout and wiring, based on the construction of structure restriction, air duct restriction and electrical rule restriction, the touch layout optimization is confirmed through wiring density and layout density, and the module layout is adjusted through heuristic algorithm (such as simulated annealing). The thinking of only finding the optimal in wiring is avoided, the method of providing circuit-level constraints and process constraints at the system level is provided, and the solution of system-level automatic wiring is provided. Further, the system quality of automatic wiring is improved by more than 3 times, and the efficiency is improved by more than 2 times.

[0144] The embodiment of the application establishes network node attribute parameters and constructs a system-level quantitative evaluation mechanism to evaluate dynamic priorities by balancing network node types and spatial ranges, so as to realize automatic wiring of multiple network nodes in a product according to importance levels and improve the quality of automatic wiring. A system-level dynamic priority wiring strategy is established to guarantee the key performance of each circuit model in automatic wiring according to priority basis and basic rules and to realize multi-objective path planning through a path optimization algorithm. Meanwhile, in actual automatic wiring, the trade-off between wiring and layout is considered to solve the problems of disconnected wiring, poor wiring quality and improper use of design space in traditional automatic wiring systems because wiring and layout are separated and cannot drive and restrict each other. The system-level global optimum is found by identifying suitable areas for layout adjustment, matching and detecting spatial, thermal and stress constraints of the layout, using a simulated annealing algorithm and adding layout penalties and wiring penalties.

[0145] It should be understood that, although each step in the flowchart involved in each of the above embodiments is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each of the above embodiments can include multiple steps or stages, which are not necessarily executed at the same time but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential but can be executed in rotation or alternation with at least part of other steps or stages in other steps.

[0146] Based on the same inventive concept, the embodiment of the application also provides an automatic wiring device for implementing the above-mentioned automatic wiring method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more automatic wiring device embodiments provided below can refer to the limitations of the automatic wiring method in the above text, which will not be repeated here.

[0147] In one embodiment, as shown in Figure 5 An automatic wiring device is provided, comprising: an acquisition module 100, a constraint construction module 200, a priority calculation module 300 and a wiring module 400, wherein:

[0148] The acquisition module 100 is configured to determine node information of multiple network nodes and wiring rules according to a circuit principle design.

[0149] The constraint construction module 200 is configured to construct a line width and distance constraint and a network node parameter constraint corresponding to the network node type according to the node information and the wiring rules.

[0150] The priority calculation module 300 is configured to determine a priority parameter of each network node according to the node information of the network node.

[0151] The wiring module 400 is configured to complete automatic wiring of the network node by using a path optimization algorithm based on the line width and line spacing constraint, the network node parameter constraint corresponding to the network node type, and the priority parameter of each network node, to obtain a wiring result for the circuit principle design.

[0152] The constraint construction module 200 is further configured to construct a line width and line spacing constraint according to a line width rule and a line spacing rule in the wiring rule; if the type of the network node is a power supply network node, construct a first parameter constraint corresponding to the power supply network node according to the node information and the wiring rule; and if the type of the network node is a signal transmission network node, construct a second parameter constraint corresponding to the signal transmission network node according to the node information and the wiring rule.

[0153] The constraint construction module 200 is further configured to: if the first parameter constraint includes a current capacity constraint, a loop area constraint, and a noise constraint; construct the current capacity constraint according to a copper foil thickness of a wiring layer in the node information and a material coefficient of the copper foil and a current rule in the wiring rule; construct the loop area constraint according to a Manhattan length in the node information; and construct the noise constraint according to a specification allowable noise in the node information.

[0154] The constraint construction module 200 is further configured to: if the second parameter constraint includes an impedance deviation constraint, a loss constraint, and a wiring layer constraint; construct the impedance deviation constraint according to a target impedance value in the node information; construct the loss constraint according to a specification loss value in the node information; and construct the wiring layer constraint according to a wiring layer rule in the wiring rule.

[0155] The priority calculation module 300 is further configured to: determine a plurality of key indicators of each network node according to the node information of the network node; obtain an indicator weight corresponding to each key indicator; determine a demand resource, an effective resource, and a resource shortage coefficient of each network node according to the node information of the network node; determine a resource indicator of each network node according to the demand resource, the effective resource, and the resource shortage coefficient of each network node; and determine the priority parameter of each network node according to the plurality of key indicators of each network node, the indicator weight corresponding to each key indicator, and the resource indicator of each network node.

[0156] The wiring module 400 is further configured to perform automatic wiring on each network node by using an A-star algorithm according to the order from large to small of the priority parameters of each network node, based on the line width and line spacing constraints and the network node parameter constraints corresponding to the network node type.

[0157] The wiring module 400 is further configured to construct wiring constraints and layout constraints based on the wiring result of the circuit principle design, and perform optimization on the wiring result of the circuit principle design by using a simulated annealing algorithm based on the wiring constraints and the layout constraints, to obtain an optimized wiring result.

[0158] The wiring module 400 is further configured to grid the wiring result of the circuit principle design, determine the wiring density threshold, the device height threshold, the device temperature threshold and the device stress threshold corresponding to each grid based on the wiring result of the circuit principle design, construct wiring constraints according to the wiring density threshold, and construct layout constraints according to the device height threshold, the device temperature threshold and the device stress threshold.

[0159] The wiring module 400 is further configured to determine the resource index of each grid according to the required resources and the effective resources of each grid, determine the height index, the temperature index and the stress index of each grid according to the device height, the device temperature and the device stress of each grid, and perform optimization on the wiring result of the circuit principle design by using a simulated annealing algorithm according to the resource index, the height index, the temperature index, the stress index, the wiring constraints and the layout constraints of each grid, to obtain an optimized wiring result.

[0160] The above automatic wiring device can be implemented by software, hardware or a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above modules.

[0161] In one embodiment, a computer device is provided, which can be a terminal. The internal structure diagram of the computer device can be as shown in FIG. 1. Figure 6As shown in the figure. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by the processor to implement an automatic wiring method.

[0162] Those skilled in the art can understand that, Figure 6 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0163] In one embodiment, a computer device is provided, including a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement any one of the automatic wiring methods in the above embodiments.

[0164] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement any one of the automatic wiring methods in the above embodiments.

[0165] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0166] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0167] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An automatic wiring method, characterized in that, The method includes: Based on the circuit design principle, determine the node information and routing rules of multiple network nodes; Based on the node information of the network nodes and the routing rules, construct line width and spacing constraints and network node parameter constraints corresponding to the network node type; Based on the node information of the network nodes, determine the priority parameter of each network node; Based on the line width and spacing constraints, the network node parameter constraints corresponding to the network node type, and the priority parameters of each network node, the automatic routing of network nodes is completed through a path optimization algorithm to obtain the routing result designed according to the circuit principle.

2. The method according to claim 1, characterized in that, The step of constructing line width and spacing constraints and network node parameter constraints corresponding to network node types based on the node information and routing rules of the network nodes includes: the network nodes include: power supply network nodes and signal transmission network nodes; Based on the line width and line spacing rules in the routing rules, construct line width and line spacing constraints; If the type of the network node is a power supply network node, then the first parameter constraint corresponding to the power supply network node is constructed according to the node information and routing rules; If the network node is a signal transmission network node, then a second parameter constraint corresponding to the signal transmission network node is constructed based on the node information and routing rules.

3. The method according to claim 2, characterized in that, The first parameter constraint for constructing the power supply network node based on the node information and routing rules includes: the first parameter constraint includes: current capacity constraint, loop area constraint and noise constraint. Based on the copper foil thickness of the routing layer in the node information, the material coefficient of the copper foil, and the current rules in the routing rules, a current capacity constraint is constructed. Based on the Manhattan length in the node information, construct the loop area constraint; Noise constraints are constructed based on the allowable noise in the node information.

4. The method according to claim 2, characterized in that, The second parameter constraint for constructing the signal transmission network node based on the node information and routing rules includes: the second parameter constraint includes: impedance deviation constraint, loss constraint and wiring layer constraint. Based on the target impedance value in the node information, an impedance deviation constraint is constructed. Based on the standardized loss values ​​in the node information, construct loss constraints; Based on the routing layer rules in the routing rules, construct routing layer constraints.

5. The method according to claim 1, characterized in that, Based on the node information of the network nodes, the priority parameters for each network node are determined, including: Based on the node information of the network nodes, determine several key indicators for each network node; Obtain the weight of each key indicator; Based on the node information of the network nodes, determine the required resources, available resources, and resource stress coefficient of each network node; Based on the resource requirements, available resources, and resource scarcity coefficient of each network node, determine the resource indicators for each network node. The priority parameters of each network node are determined based on multiple key indicators of each network node, the indicator weights corresponding to each key indicator, and the resource indicators of each network node.

6. The method according to claim 1, characterized in that, Based on the line width and spacing constraints, the network node parameter constraints corresponding to the network node type, and the priority parameters of each network node, the automatic routing of network nodes is completed through a path optimization algorithm, including: Based on the line width and spacing constraints and the network node parameter constraints corresponding to the network node type, the A* algorithm is used to automatically route each network node according to the order of priority parameters from largest to smallest.

7. The method according to claim 1, characterized in that, The method further includes: Based on the wiring results designed according to the circuit principle, wiring constraints and layout constraints are constructed. Based on the aforementioned wiring constraints and layout constraints, the wiring results of the circuit design are optimized using a simulated annealing algorithm to obtain optimized wiring results.

8. The method according to claim 7, characterized in that, The wiring results designed based on the circuit principle, including the construction of wiring constraints and layout constraints, include: The wiring results of the circuit design are meshed; Based on the wiring results designed according to the circuit principle, the wiring density threshold, device height threshold, device temperature threshold, and device stress threshold corresponding to each grid are determined. Based on the wiring density threshold, wiring constraints are constructed; Layout constraints are constructed based on the device height threshold, device temperature threshold, and device stress threshold.

9. The method according to claim 8, characterized in that, Based on the routing constraints and layout constraints, the routing results of the circuit design are optimized using a simulated annealing algorithm to obtain optimized routing results, including: Based on the resource requirements and available resources of each grid, determine the resource indicators for each grid. Based on the device height, device temperature, and device stress of each grid, determine the height index, temperature index, and stress index of each grid. Based on the resource, height, temperature, stress, wiring constraints, and layout constraints of each grid, the wiring results of the circuit design are optimized using a simulated annealing algorithm to obtain optimized wiring results.

10. An automatic wiring device, characterized in that, The device includes: The acquisition module is used to determine the node information and routing rules of multiple network nodes based on the circuit principle design. The constraint construction module is used to construct line width and spacing constraints and network node parameter constraints corresponding to network node types based on the node information and routing rules. The priority calculation module is used to determine the priority parameters of each network node based on the node information of the network nodes. The routing module is used to automatically route network nodes based on the line width and spacing constraints, network node parameter constraints corresponding to the network node type, and priority parameters of each network node, through a path optimization algorithm, to obtain the routing result designed according to the circuit principle.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 9.

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