Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first scanning signal line, a first power line and a plurality of pixel units arranged in an array; the first scanning signal line is connected with all the pixel units, and the first scanning signal line is used for transmitting a first control signal and a second control signal in a time-sharing manner; the first power line is connected with all the pixel units and is used for transmitting a first power signal and a second power signal in a time-sharing manner; the pixel circuit comprises an initialization module and a driving module. The initialization module is used for responding to conduction of a first control signal on the first scanning signal line so as to transmit an initialization signal on the initialization signal line to the control end of the driving module. The frame of the display panel can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the application of display panel is more and more extensive, and the requirement of display panel is higher and higher.

[0003] However, the frame of the existing display panel is wide. SUMMARY

[0004] The present application provides a display panel and a display device to reduce the frame of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising: a first scan signal line, a first power supply line and a plurality of pixel units arranged in an array; the first scan signal line is connected with all the pixel units, and the first scan signal line is used for transmitting a first control signal and a second control signal in time division; the first power supply line is connected with all the pixel units, and the first power supply line is used for transmitting a first power supply signal and a second power supply signal in time division; wherein each pixel unit comprises a light emitting module and a pixel circuit corresponding to the light emitting module, the pixel circuit comprises an initialization module and a driving module; a first end of the driving module is connected with the first power supply line, and a second end of the driving module is connected with a first end of the light emitting module; the initialization module is connected with an initialization signal line and a control end of the driving module, and the initialization module is used for turning on in response to the first control signal on the first scan signal line, so as to transmit an initialization signal on the initialization signal line to the control end of the driving module.

[0006] Optionally, the working stage of the pixel circuit in a frame time comprises an initialization stage, a compensation stage, a data writing stage and a light emitting stage; the display panel further comprises at least one driving chip, the at least one driving chip is used for providing the first control signal to the first scan signal line in the initialization stage and the compensation stage; the at least one driving chip is used for providing the second control signal to the first scan signal line in the data writing stage and the light emitting stage, and the second control signal is used for turning off the initialization module.

[0007] Optionally, the at least one driving chip is used for providing the first power supply signal to the first power supply line in the initialization stage, and providing the second power supply signal to the first power supply line in the compensation stage, the data writing stage and the light emitting stage.

[0008] Optionally, the at least one driving chip is a single driving chip.

[0009] Optionally, the at least one driving chip comprises a first driving chip and a second driving chip; the first driving chip is connected with all the pixel units through the first scan signal line, and is configured to provide the first control signal and the second control signal to the first scan signal line; the second driving chip is connected with all the pixel units through the first power supply line, and is configured to provide the first power supply signal and the second power supply signal to the first power supply line.

[0010] Optionally, the first power supply signal is a negative voltage, and the second power supply signal is a positive voltage.

[0011] Optionally, the plurality of pixel units are arranged as a plurality of pixel rows in the column direction; the plurality of pixel rows comprise odd rows and even rows; the light emitting module comprises first light emitting elements and second light emitting elements; the first light emitting elements are located in the odd rows, and the second light emitting elements are located in the even rows; a first electrode of the first light emitting element and a first electrode of the second light emitting element are connected to the first node, and the first node serves as a first end of the light emitting module; a second electrode of the first light emitting element is connected to the second power supply line, and a second electrode of the second light emitting element is connected to the third power supply line.

[0012] Optionally, the working stages of the pixel circuit in one frame time comprise an initialization stage, a compensation stage, a data writing stage and a light emitting stage; the display panel further comprises a power supply driving circuit; the power supply driving circuit is connected with the second electrodes of all the first light emitting elements through the second power supply line; the power supply driving circuit is connected with the second electrodes of all the second light emitting elements through the third power supply line; the power supply driving circuit is configured to provide the third power supply signal to the second power supply line in the data writing stage and the light emitting stage in the odd frames; and the power supply driving circuit is configured to provide the fourth power supply signal to the second power supply line in the remaining time; the power supply driving circuit is configured to provide the third power supply signal to the third power supply line in the data writing stage and the light emitting stage in the even frames; and the power supply driving circuit is configured to provide the fourth power supply signal to the third power supply line in the remaining time.

[0013] Optionally, the fourth power supply signal is greater than the first power supply signal, the first power supply signal is less than the second power supply signal, and the second power supply signal is greater than the third power supply signal.

[0014] Optionally, the power supply driving circuit is integrated in the at least one driving chip.

[0015] Optionally, the power supply driving circuit is a power supply driving chip independent of the at least one driving chip.

[0016] Optionally, the display panel further includes a first gate driving circuit and a second gate driving circuit; the first gate driving circuit includes a plurality of cascaded first shift registers, each first shift register being connected to a row of first light-emitting elements through a corresponding second power line; the second gate driving circuit includes a plurality of cascaded second shift registers, each second shift register being connected to a row of second light-emitting elements through a corresponding third power line; wherein, the first shift register is used to provide effective pulses of the gate driving signal to the first light-emitting elements during the data writing phase and the light-emitting phase of odd-numbered frames; the second shift register is used to provide effective pulses of the gate driving signal to the second light-emitting elements during the data writing phase and the light-emitting phase of even-numbered frames.

[0017] Optionally, the initialization module includes a first transistor, the first terminal of which is connected to an initialization signal line, and the gate of which is connected to a first scan signal line; the driving module includes a driving transistor, the gate of which is connected to a second terminal of the first transistor, the first terminal of which is connected to a first power supply line, and the second terminal of which is connected to a first end of the light-emitting module.

[0018] Optionally, the first transistor is a PMOS transistor, and the driving transistor is an NMOS transistor.

[0019] Optionally, the display panel also includes a third gate driving circuit and multiple second scan signal lines. The third gate driving circuit includes multiple cascaded third shift registers, and each third shift register is connected to a row of pixel circuits through a corresponding second scan signal line.

[0020] The pixel circuit also includes a data writing module; the data writing module is connected to the data line and the second scan signal line, and during the data writing stage, it provides a line-by-line scanning strobe signal to the second scan signal line to control the data writing module to write the data signal on the data line to the control terminal of the driver module line by line.

[0021] Optionally, the data writing module includes a second transistor, the first terminal of the second transistor is connected to the data line, the second terminal of the second transistor is connected to the control terminal of the driving module, and the gate of the second transistor is connected to the second scan signal line.

[0022] Optionally, the second transistor is a PMOS transistor.

[0023] Optionally, the pixel circuit further includes a coupling module; the first end of the coupling module is connected to the control terminal of the driving module, and the second end of the coupling module is connected to the first end of the light-emitting module. The coupling module is used to couple the potential of the second end of the coupling module to the control terminal of the driving module.

[0024] Optionally, the coupling module includes a first capacitor, with a first end of the first capacitor serving as the first end of the coupling module and a second end of the first capacitor serving as the second end of the coupling module.

[0025] Optionally, the pixel circuit further includes a holding module; the first end of the holding module is connected to the first end of the light-emitting module, and the second end of the holding module is connected to the first power supply line or the initialization signal line. The holding module is used to hold the potential of the first end of the light-emitting module.

[0026] Optionally, the holding module includes a second capacitor, with the first end of the second capacitor serving as the first end of the holding module and the second end of the second capacitor serving as the second end of the holding module.

[0027] Secondly, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0028] The display panel provided in this embodiment of the invention features a first scan signal line and a first power line designed as global signal lines running through the entire panel, controlled in a time-division manner by only at least one driver chip. This eliminates the need for the two sets of gate drive circuits and their occupied bezel space, which were originally required for progressive driving of these two sets of signals, reducing the layout area of ​​the peripheral drive circuits and consequently decreasing the bezel size of the display panel. Furthermore, reducing the number of gate drive circuits also reduces power consumption. Moreover, the numerous thin-film transistors and their complex interconnections within the gate drive circuits are high-risk areas for manufacturing defects; reducing their number directly lowers the probability of manufacturing defects, thereby improving the panel's process yield and reliability, and simplifying the circuit design and debugging process. Crucially, despite the significantly simplified drive architecture, the initialization and threshold compensation stages are separated from the data writing stage, thus still enabling the achievement of high refresh rates.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of a pixel unit provided in an embodiment of the present invention;

[0033] Figure 3 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0037] Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0038] Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0039] Figure 9 It is a waveform diagram of the gate drive signals output by the first and second shift registers at each stage;

[0040] Figure 10a This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0041] Figure 10b This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention;

[0042] Figure 11 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention;

[0043] Figure 12 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0044] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0047] As described in the background section, existing display panels have relatively wide bezels. The inventors have discovered that this problem arises because, in conventional display panel designs, pixels are arranged in an array, with each sub-pixel containing a light-emitting element and a pixel circuit that provides a driving signal to it. This pixel circuit typically includes a driving module (such as a driving transistor) and an initialization module for initialization. The first end of the driving module is coupled to a power supply line, and the second end is coupled to the first electrode (such as the anode) of the light-emitting element, while the initialization module is controlled by a scan signal line.

[0048] To achieve precise line-by-line initialization, the scan signal lines connected to the initialization module must provide initialization signals for each line scan. This timing requirement necessitates that the corresponding gate integrated driver circuit generate independent control pulses for each row of pixels. Therefore, regardless of whether the peripheral gate integrated driver circuit is designed to drive one or multiple rows of sub-pixels using a shift register, the total number of its circuit modules and signal traces is positively correlated with the number of pixel rows. These essential circuits and traces are densely arranged in the non-display area (i.e., the bezel) around the panel, occupying a significant amount of physical space and directly increasing the bezel width.

[0049] To address the aforementioned issues, embodiments of the present invention provide a display panel and a display device. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel unit structure provided in an embodiment of the present invention. Figure 1 and Figure 2 As shown, the display panel includes: a first scan signal line S1, a first power supply line L1, and a plurality of pixel units 12 arranged in an array;

[0050] The first scan signal line S1 is connected to all pixel units 12. The first scan signal line S1 is used to transmit the first control signal S1L and the second control signal S1H in a time-division manner.

[0051] The first power line L1 is connected to all pixel units 12. The first power line L1 is used to transmit the first power signal Vdd0 and the second power signal VddH in a time-division manner.

[0052] Each pixel unit 12 includes a light-emitting module 13 and a pixel circuit 14 corresponding to the light-emitting module 13. The pixel circuit 14 includes an initialization module 110 and a driving module 120.

[0053] The first end of the driving module 110 is connected to the first power line L1, and the second end of the driving module 120 is connected to the first end of the light-emitting module 13.

[0054] The initialization module 110 connects the initialization signal line Vref1 and the control terminal of the drive module 120. The initialization module 110 is used to respond to the first control signal on the first scan signal line S1 being turned on, so as to transmit the initialization signal on the initialization signal line Vref1 to the control terminal of the drive module 120.

[0055] Specifically, the first scan signal line S1 is a variable voltage signal line, which transmits signals of different voltages in different operating stages to perform different functions. In this embodiment, the first scan signal line S1 can transmit a low-level first control signal S1L or a high-level second control signal S1H in a time-division multiplexing manner. That is, the signal transmitted on the first scan signal line S1 is a global AC signal. For example, in the initialization stage and the compensation stage, the first scan signal line S1 transmits the first control signal, which turns on the initialization modules 110 in all pixel circuits. At this time, the initialization signal line Vref1 can provide an initialization voltage to the control terminal of the driving module 120 to reset the control terminal of the driving module 120. In the data writing stage and the light emission stage, the first scan signal line S1 transmits the second control signal S1H, which turns off the initialization module 110, thereby isolating the control terminal of the driving module 120 from the initialization signal line Vref1 and ensuring that the data writing and light emission processes are not interfered with.

[0056] The first power line L1 is also a variable voltage signal line, meaning the voltage signal transmitted on the first power line L1 can be changed. In this embodiment, the first power line L1 can transmit a low-level first power signal Vdd0 or a high-level second power signal VddH. In other words, the signal transmitted on the first power line L1 is an AC signal. For example, during the initialization phase, the first power line L1 can transmit a low-level first power signal Vdd0 to reset the light-emitting module 13; during the compensation phase, data writing phase, and light-emitting phase, the first power line L1 can transmit a high-level second power signal VddH to perform threshold compensation on the driving module 120 and drive the light-emitting module 13 to emit light.

[0057] In some embodiments, the first scan signal line S1 and the first power supply line L1 are surface electrodes.

[0058] Optionally, multiple pixel units 12 are arranged in a matrix and located in the display area of ​​the display panel.

[0059] The corresponding setup refers to the pixel circuit 14 being functionally associated with the light-emitting module 13 to drive it to emit light. The two can be adjacent in layout or have other topological relationships.

[0060] The display panel provided in this embodiment of the invention features a first scan signal line and a first power line designed as global signal lines running through the entire panel, controlled in a time-division manner by only at least one driver chip. This eliminates the need for the two sets of gate drive circuits and their occupied bezel space, which were originally required for progressive driving of these two sets of signals, reducing the layout area of ​​the peripheral drive circuits and consequently decreasing the bezel size of the display panel. Furthermore, reducing the number of gate drive circuits also reduces power consumption. Moreover, the numerous thin-film transistors and their complex interconnections within the gate drive circuits are high-risk areas for manufacturing defects; reducing their number directly lowers the probability of manufacturing defects, thereby improving the panel's process yield and reliability, and simplifying the circuit design and debugging process. Crucially, despite the significantly simplified drive architecture, the initialization and threshold compensation stages are separated from the data writing stage, thus still enabling the achievement of high refresh rates.

[0061] Figure 3 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. For example... Figure 3 As shown, the pixel circuit's operating phases within one frame include an initialization phase T1, a compensation phase T2, a data writing phase T3, and an emission phase T4; the display panel also includes at least one driver chip 11.

[0062] At least one driver chip 11 is used to provide a first control signal S1L to the first scan signal line L1 during the initialization phase T1 and the compensation phase T2.

[0063] At least one driver chip 11 is used to provide a second control signal S1H to the first scan signal line L1 during the data writing stage T3 and the light emission stage T4. The second control signal S1H is used to turn off the initialization module 110.

[0064] Specifically, at least one driver chip 11 can be an integrated driver chip for simultaneously providing a first control signal S1L, a second control signal S1H, a first power signal Vdd0, and a second power signal VddH; or it can be multiple driver chips. For example, the first scan signal line S1 can be connected to a dedicated display driver chip, while the first power line L1 can be connected to a dedicated power management chip.

[0065] The operation of a pixel circuit within one frame can include four stages executed sequentially: initialization stage T1, compensation stage T2, data writing stage T3, and light emission stage T4.

[0066] During the initialization phase T1 and the compensation phase T2, the driver chip 11 provides a first control signal S1L to the first scan signal line S1. At this time, the first scan signal line S1 acts as a globally effective control line, causing the initialization modules 110 of all pixel units on the panel to be turned on simultaneously. This allows the voltage on the initialization signal line Vref1 to be synchronously written to the control terminals of all driver modules 120, completing the entire panel reset and preparing for subsequent compensation.

[0067] During the data writing phase T3 and the light emission phase T4, the driver chip 11 switches the signal on the first scan signal line S1 to the second control signal S1H. At this time, the first scan signal line S1 acts as a globally invalid control line, causing all initialization modules 110 to be synchronously turned off. The purpose is to isolate the control terminal of the driver module 120 from the initialization signal path during the data writing phase T3, ensuring that the data voltage written line by line is not disturbed; and to maintain this isolation state during the light emission phase T4, ensuring the stability of the light emission process.

[0068] Optionally, continue to refer to Figure 3 At least one driver chip 11 is used to provide a first power signal Vdd0 to the first power line L1 during the initialization phase T1, and to provide a second power signal VddH to the first power line L1 during the compensation phase T2, the data writing phase T3, and the light emission phase T4.

[0069] Specifically, during the initialization phase T1, the driver chip 11 provides a first power signal Vdd0 to the first power line L1, making the anode voltage of the light-emitting element less than or equal to the cathode voltage, thereby clearing the data from the previous frame and resetting the anode of the light-emitting element. This solves the problem of uneven display at low gray levels in traditional 2T1C pixel circuits. Here, T represents a thin-film transistor, and C represents a capacitor.

[0070] Subsequently, during the period from the compensation phase T2 until the end of the frame, the driver chip 11 switches the voltage on the first power line L1 to the second power signal VddH. During the compensation phase T2, the second power signal VddH serves as the source of the drive current, ensuring that the driver module 120 is compensated to the correct voltage at its control terminal. During the data writing phase T3 and the light emission phase T4, the second power signal VddH continuously provides the necessary operating power to the driver module 120 and the light emission module 13.

[0071] Optionally, the first power supply signal Vdd0 is a negative voltage, and the second power supply signal VddH is a positive voltage.

[0072] Optionally, at least one driver chip 11 is a single driver chip. Replacing multiple chips (such as a timing controller and a power management chip) with a single chip directly eliminates the interconnection traces between chips and the required safety spacing. The generation and driving of all critical signals are concentrated at one point, which greatly simplifies the circuit layout complexity around the panel, and the freed-up space can be directly used to narrow the bezel.

[0073] Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 4 As shown, optionally, at least one driver chip 11 includes a first driver chip 111 and a second driver chip 112.

[0074] The first driving chip 111 is connected to all pixel units 12 through the first scan signal line S1, and is used to provide the first control signal S1L and the second control signal S1H to the first scan signal line S1.

[0075] The second driving chip 112 is connected to all pixel units 12 through the first power line L1 and is used to provide the first power line L1 with a first power signal Vdd0 and a second power signal VddH.

[0076] Specifically, the first driver chip 111 (which may be, for example, a dedicated timing controller or display driver chip) focuses on generating timing logic signals and is responsible for providing the first control signal S1L and the second control signal S1H to the first scan signal line S1 for turning the global control initialization module 110 on and off.

[0077] The second driver chip 112 (e.g., a dedicated power management chip or high-voltage driver chip) focuses on providing stable power output, responsible for supplying the first power line L1 with the first power signal Vdd0 and the second power signal VddH required for global reset and light-emitting drive. The main advantages of this discrete design are: firstly, it allows for the selection of the optimal semiconductor process to manufacture two chips separately based on signal characteristics (logic level and power level), thereby achieving a better balance between system cost, performance, and energy efficiency; secondly, separating the high-current power drive section helps reduce noise interference from the logic control section, improving the accuracy of timing control and display stability.

[0078] Figure 5 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention. For example... Figure 5 As shown, optionally, the plurality of pixel units 12 are arranged in the column direction as a plurality of pixel rows, the plurality of pixel rows including odd rows and even rows.

[0079] The light-emitting module 13 includes a first light-emitting element D1 and a second light-emitting element D2; the first light-emitting element D1 is located in the odd-numbered row, and the second light-emitting element D2 is located in the even-numbered row.

[0080] The first electrode of the first light-emitting element D1 and the first electrode of the second light-emitting element D1 are connected to the first node N1, and the first node N1 serves as the first end of the light-emitting module 13.

[0081] The second electrode of the first light-emitting element D1 is connected to the second power supply line L2, and the second electrode of the second light-emitting element D2 is connected to the third power supply line L3. This arrangement halves the total number of pixel circuits 14, directly and significantly reducing the transistors and wiring space required in the display area.

[0082] During odd-numbered display frames, by controlling the second power line L2 (e.g., setting its potential to a low level for illumination) and the third power line L3 (e.g., setting its potential to a high level for non-illumination), only the first light-emitting element D1 located in the odd-numbered rows illuminates. During subsequent even-numbered display frames, the controls are switched, setting the second power line L2 to a high level and the third power line L3 to a low level, thereby causing only the second light-emitting element D2 located in the even-numbered rows to illuminate. Due to the persistence of vision in the human eye, the rapidly alternating odd and even-numbered frames will merge into a complete, continuous, and uniformly bright image.

[0083] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 7 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention. For example... Figure 6 and Figure 7 As shown, optionally, the display panel also includes a power drive circuit 15;

[0084] The power drive circuit 15 is connected to the second terminal of all the first light-emitting elements D1 via the second power line L2. The power drive circuit 15 is connected to the second terminal of all the second light-emitting elements D2 via the third power line L3.

[0085] The power drive circuit 15 is used to provide a third power signal Vss0 to the second power line L2 during the data writing phase T3 and the light emission phase T4 in odd-numbered frames; and to provide a fourth power signal VssH to the second power line L2 at other times.

[0086] The power drive circuit 15 is used to provide a third power signal Vss0 to the third power line L3 during the data writing phase T3 and the light emission phase T4 in even-numbered frames; and to provide a fourth power signal VssH to the third power line L3 at other times.

[0087] Specifically, in this scheme, the second power line L2 and the third power line L3 are not driven by the gate circuit of progressive scanning, but are respectively used as global cathode power lines and centrally controlled by an independent power drive circuit 15.

[0088] The power drive circuit 15 controls the potential of the two cathode power lines uniformly and synchronously according to the parity of the display frame. During odd-numbered frames, the power drive circuit 15 pulls the potential of the second power line L2, which connects the cathodes of all odd-numbered rows of first light-emitting elements D1, down to the third power signal Vss0 (effective light-emitting level, such as low level), while maintaining the potential of the third power line L3, which connects the cathodes of all even-numbered rows of second light-emitting elements D2, at the fourth power signal VssH (non-light-emitting level, such as high level), thereby enabling the first light-emitting elements D1 in all odd-numbered rows to emit light simultaneously. During even-numbered frames, the control logic is completely reversed, pulling the potential of the third power line L3 down to the third power signal Vss0 and setting the potential of the second power line L2 to the fourth power signal VssH, thereby enabling the second light-emitting elements D2 in all even-numbered rows to emit light simultaneously.

[0089] The remaining time includes the initialization phase T1 and the compensation phase T2, during which both cathode lines can be set to the fourth power signal VssH to ensure that the relevant operations are not disturbed.

[0090] A single power driver circuit 15 drives the global second power line L2 and third power line L3, replacing the large-scale gate-integrated driver circuit required in conventional solutions to provide progressive cathode voltages. This power driver circuit 15 directly provides the third power signal Vss0 for controlling illumination and the fourth power signal VssH for non-illumination to the second power line L2 and the third power line L3 in a time-division multiplexing manner. Therefore, the multiple cascaded shift registers used in conventional architectures to generate and shift the output cathode control voltages line by line are removed. These circuits, originally located in the non-display area of ​​the display panel, free up space in the bezel area, further reducing the overall bezel width.

[0091] Optionally, the fourth power signal VssH is greater than the first power signal Vdd0, the first power signal Vdd0 is less than the second power signal VddH, and the second power signal VddH is greater than the third power signal Vss0.

[0092] Optionally, continue to refer to Figure 6 The power drive circuit 15 is a power drive chip that is independent of at least one drive chip 11.

[0093] Specifically, the power drive circuit 15 is a separate semiconductor device and has no physical integration with the drive chip 11, which is responsible for providing the first control signal S1L, the second control signal S1H, the first power signal Vdd0, and the second power signal VddH. The two establish signal connections with the corresponding second power line L2 and third power line L3 through a preset circuit interface to realize the directional transmission of power signals.

[0094] The power drive circuit 15 is independent of the driver chip 11 and can focus on the high stability and high accuracy of the power signal output. It avoids mutual interference with the timing logic control, data processing and other modules inside the driver chip. Especially in high PPI display scenarios, it can effectively reduce the impact of power noise on display uniformity and ensure the synchronization and response speed of power signal switching in different frame stages.

[0095] Optionally, the power drive circuit 15 is integrated into at least one driver chip 11. The integrated design can directly eliminate the physical footprint of a separate power drive chip and the safety spacing required for interconnection traces between chips, making the circuit layout in the non-display area around the panel more compact and further reducing the bezel width.

[0096] Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 8 As shown, the display panel also includes a first gate driving circuit 16 and a second gate driving circuit 17.

[0097] The first gate drive circuit 16 includes a plurality of cascaded first shift registers 160, each of which is connected to a row of first light-emitting elements D1 via a corresponding second power line L2.

[0098] The second gate drive circuit 17 includes multiple cascaded second shift registers 170, each of which is connected to a row of second light-emitting elements D2 via a corresponding third power line L3.

[0099] The first shift register 160 is used to provide effective pulses of the gate drive signal to the first light-emitting element D1 during the data writing stage T3 and the light emission stage T4 of odd frames.

[0100] The second shift register 160 is used to provide effective pulses of the gate drive signal to the second light-emitting element D2 during the data writing phase T3 and the light emission phase of even-numbered frames.

[0101] Specifically, the first shift register 160 and the second shift register 170 may have the structure of any existing shift register.

[0102] The first-stage first shift register 160 is electrically connected to the first light-emitting element D1 of the first row in the odd-numbered rows of the display panel via a corresponding second power line L2. The second-stage first shift register 160 is connected to the first light-emitting element D1 of the second row in the odd-numbered rows via another independent corresponding second power line L2, and so on, with the Nth-stage first shift register 160 connected to the first light-emitting element D1 of the Nth row in the odd-numbered rows via its corresponding second power line L2. This cascaded design of the first shift registers 160 allows the output signal of the previous stage to be used as the input signal of the next stage, ensuring that during the data writing and light-emitting phases of odd-numbered frames, the effective pulses of the gate drive signal can be shifted and output row by row in the order of "first stage → second stage → ... → Nth stage," driving the first light-emitting element D1 of the corresponding row to conduct and emit light. Here, N is an integer greater than or equal to 2.

[0103] Similarly, the first-stage second shift register 170 is electrically connected to the second light-emitting element D2 of the first row in even-numbered rows of the display panel via a corresponding third power line L3; the second-stage second shift register 170 is connected to the second light-emitting element D2 of the second row in even-numbered rows via another corresponding third power line L3, and so on, with the Nth-stage second shift register 170 connected to the second light-emitting element D2 of the Nth row in even-numbered rows via its corresponding third power line L3. This cascaded design of the various stages of the second shift register 170 ensures that the output signal of the previous stage serves as the input signal of the next stage, guaranteeing that during the data writing and light-emitting phases of even-numbered frames, the effective pulses of the gate drive signal can be shifted and output row by row in the order of "first stage → second stage → ... → Nth stage," driving the corresponding row's second light-emitting element D2 to conduct and emit light.

[0104] Figure 9 This is a waveform diagram of the gate drive signals output from the first and second shift registers at each stage. For example... Figure 9 As shown, the second-stage gate drive signal Vout2 output by the second-stage first shift register 160 is shifted by half a clock cycle relative to the first-stage gate drive signal Vout1. In this way, the output of multi-stage gate drive signals is realized, and the output gate signal is only shifted relative to the input signal without changing the waveform. This can achieve good driving of the first light-emitting element D1 in each row.

[0105] Similarly, the second-stage gate drive signal Vout2' output by the second-stage second shift register 170 is shifted by half a clock cycle relative to the first-stage gate drive signal Vout1'. Figure 9 The example uses two gate drive signals, but does not limit the number of gate drive signals output by the display panel.

[0106] Figure 10aThis is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 10a As shown, the display panel also includes a third gate driving circuit 18 and multiple second scan signal lines S2. The third gate driving circuit 18 includes multiple cascaded third shift registers 180, and each third shift register 180 is connected to a row of pixel circuits 14 through a corresponding second scan signal line S2.

[0107] Figure 10b This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention. For example... Figure 10b As shown, the pixel circuit 14 also includes a data writing module 130;

[0108] The data writing module 130 is connected to the data line Vdata and the second scan signal line S2. During the data writing stage T3, it provides a line-by-line scanning strobe signal to the second scan signal line S2 to control the data writing module 130 to write the data signal on the data line Vdata line by line to the control terminal of the driver module 120.

[0109] Optionally, continuing to refer to FIG10, the pixel circuit further includes a coupling module 140. The first end of the coupling module 140 is connected to the control terminal of the driving module 120, and the second end of the coupling module 140 is connected to the first end of the light-emitting module 13. The coupling module 140 is used to couple the potential of the second end of the coupling module 140 to the control terminal of the driving module 120.

[0110] Optionally, continuing to refer to FIG10, the pixel circuit further includes a holding module 150. The first end of the holding module 150 is connected to the first end of the light-emitting module 13, and the second end of the holding module 150 is connected to the first power line L1 or the initialization signal line Vref1. The holding module 150 is used to maintain the potential of the first end of the light-emitting module 13.

[0111] In this embodiment, the potential of the first node N1 can be maintained by the holding module 150, so that the potential difference between the first node N1 and the control terminal of the drive module 120 is always kept at a stable value, and the leakage current is also kept at a stable value. This can prevent the leakage current from increasing as the leakage time increases. In other words, by setting the holding module 150, the leakage current at the control terminal of the drive module 120 can be reduced, thereby improving the flickering phenomenon and enhancing the display effect.

[0112] Figure 11 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention. For example... Figure 11 As shown, the initialization module 110 includes a first transistor M1, the first terminal of the first transistor M1 is connected to the initialization signal line Vref1, and the gate of the first transistor M1 is connected to the first scan signal line S1.

[0113] Optionally, continue to refer to Figure 11 The driving module 120 includes a driving transistor DTFT, the gate of which is connected to the second terminal of the first transistor, the first terminal of the driving transistor DTFT is connected to the first power line L1, and the second terminal of the driving transistor DTFT is connected to the first terminal of the light-emitting module 13.

[0114] Optionally, continue to refer to Figure 11 The data writing module 130 includes a second transistor M2. The first terminal of the second transistor M2 is connected to the data line Vdata, the second terminal of the second transistor M2 is connected to the control terminal of the driving module 110, and the gate of the second transistor M2 is connected to the second scan signal line S2.

[0115] Optionally, continue to refer to Figure 11 The coupling module 140 includes a first capacitor C1, with the first end of the first capacitor C1 serving as the first end of the coupling module 140 and the second end of the first capacitor C1 serving as the second end of the coupling module 140.

[0116] Optionally, continue to refer to Figure 11 The holding module 150 includes a second capacitor C2, the first end of the second capacitor C2 serves as the first end of the holding module 150, and the second end of the second capacitor C2 serves as the second end of the holding module 150.

[0117] Optionally, the first transistor M1 is a PMOS transistor, the second transistor M2 is a PMOS transistor, and the driving transistor DTFT is an NMOS transistor.

[0118] Figure 12 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 12 The driving timing shown can be applied to drive Figure 10 and Figure 11 The pixel circuit shown is working. The following will combine... Figure 11 and Figure 12 The working principle of the pixel circuit provided in the embodiments of the present invention will be explained.

[0119] During the initialization phase T1 of odd-numbered frames, a low-level first control signal is transmitted on the first scan signal line S1, the signal on the second scan signal line S2 is high, a low-level first power signal Vdd0 is transmitted on the first power line L1, and a high-level fourth power signal VssH is transmitted on the second power line L2 and the third power line L3. The initialization module 110 and the data writing module 130 are turned off. That is, the first transistor M1 is turned on, and the second transistor M2 is turned off. The initialization voltage on the initialization signal line Vref1 is written to the gate of the driving transistor DTFT through the first transistor M1, resetting the gate voltage of the driving transistor DTFT to the initialization voltage and controlling the driving transistor DTFT to turn on. Because the driving transistor DTFT is turned on, its second electrode (i.e., source electrode) potential is pulled low to the first power signal Vdd0 on the first power line L1, which is the potential of the first terminal (first node N1) of the light-emitting module 13. Simultaneously, both the second power line L2 and the third power line L3 have a high-level third power signal VssH, causing the cathode potentials of the first light-emitting element D1 and the second light-emitting element D2 to be higher than their anode potentials. The light-emitting elements are in a reverse-biased state and do not emit light. This process clears any residual charge from the previous frame on the anode of the light-emitting elements, thus initializing the light-emitting module 13.

[0120] During the compensation phase T2 of odd-numbered frames, a low-level first control signal is transmitted on the first scan signal line S1, a high-level gating signal is transmitted on the second scan signal line S2, a high-level second power signal VddH is transmitted on the first power line L1, and a high-level fourth power signal VssH is transmitted on the second power line L2 and the third power line L3. At this time, the initialization module 110 is turned on while the data writing module 130 is turned off. Specifically, the low-level first control signal S1L turns on the first transistor M1, allowing the initialization voltage on the initialization signal line Vref1 to be continuously supplied to the gate of the driving transistor DTFT. The high-level gating signal turns off the second transistor M2, which is a PMOS transistor, thereby isolating the data line Vdata from the gate of the driving transistor DTFT. The high-level second power signal VddH provided by the first power line L1 is applied to the drain (first terminal) of the driving transistor DTFT. Since the driving transistor DTFT is an NMOS transistor, its gate is turned on under the action of the initialization voltage, and its source (second terminal) has a low initial potential. As the driving transistor DTFT turns on, its source potential (i.e., the potential of the first node N1) begins to rise due to the current flowing from the drain to the source. This rising potential is coupled to the gate of the driving transistor DTFT through the first capacitor C1, causing the gate potential to rise accordingly. This process continues until the gate-source voltage Vgs of the driving transistor DTFT drops to near its threshold voltage Vth, at which point the driving transistor DTFT tends to turn off. During this stage, the second capacitor C2 helps stabilize the potential of the first node N1, working in conjunction with the first capacitor C1 to achieve accurate threshold voltage compensation.

[0121] During the odd-frame data writing phase T3, a high-level second control signal is transmitted on the first scan signal line S1, a low-level strobe signal is transmitted on the second scan signal line S2, a high-level second power signal VddH is maintained on the first power line L1, the second power line L2 switches to a low-level third power signal Vss0, and the third power line L3 maintains a high-level fourth power signal VssH. At this time, the initialization module 110 is turned off while the data writing module 130 is turned on. The high-level second control signal turns off the first transistor M1, thereby completely isolating the gate of the driving transistor DTFT from the initialization signal line Vref1. The low-level strobe signal turns on the second transistor M2. The data voltage on the data line Vdata is written to the gate of the driving transistor DTFT through the turned-on second transistor M2. Since the first terminal of the first capacitor C1 is connected to the gate, the data voltage Vdata interacts with the voltage stored in the gate during the compensation phase, so that the final gate potential of the driving transistor DTFT is set to be related to the data voltage and includes threshold voltage compensation information; this potential is stored by the first capacitor C1. The first power line L1 continuously provides a high-level operating voltage. Simultaneously, the second power line L2 has switched to the low-level third power signal Vss0, keeping the cathode of the first light-emitting element D1 at a low potential, preparing for the upcoming light-emitting phase. The third power line L3 maintains the high-level fourth power signal VssH, ensuring that the second light-emitting element D2 remains in the off state. The second capacitor C2 continues to maintain the potential of the first node N1, ensuring the stability of the anode potential of the light-emitting module 13 during data voltage writing, avoiding interference with the written data.

[0122] During the light emission phase T4 of the odd-numbered frames, the first scan signal line S1 maintains a high level second control signal, the second scan signal line S2 transmits a high level signal to turn off the data writing module 130, the first power line L1 maintains a high level second power signal VddH, the second power line L2 maintains a low level third power signal Vss0, and the third power line L3 maintains a high level fourth power signal VssH.

[0123] At this time, both the initialization module 110 and the data writing module 130 are turned off. The high-level signal turns off both the first transistor M1 and the second transistor M2, and the gate of the driving transistor DTFT is in a floating state. Its voltage is maintained by the voltage containing data voltage and threshold voltage information stored on the first capacitor C1. The high-level second power signal VddH provided by the first power line L1 is applied to the drain of the driving transistor DTFT as a driving power supply. The driving transistor DTFT generates a corresponding driving current Id according to its gate-source voltage Vgs. This driving current Id flows from the first power line L1 through the driving transistor DTFT and is injected into the first terminal of the light-emitting module 13. Since the second power line L2 maintains a low-level third power signal Vss0, the cathode potential of the first light-emitting element D1 is low, thereby making its anode potential higher than its cathode, forming a forward bias, so the first light-emitting element D1 is driven to emit light; at the same time, the third power line L3 provides a high-level fourth power signal VssH, and the cathode potential of the second light-emitting element D2 is higher than its anode, in a reverse bias state, so the second light-emitting element D2 does not emit light. During this stage, the first capacitor C1 continues to couple the potential between the gate of the driving transistor DTFT and the first node N1, which helps to maintain the stability of the driving current; the second capacitor C2 is used to maintain the potential of the first node N1 and suppress potential fluctuations caused by transistor leakage or signal coupling, thereby improving the uniformity of light emission and display effect.

[0124] In even-numbered frames, the initialization and compensation phases operate in the same way as the corresponding phases in odd-numbered frames, and will not be repeated here.

[0125] During the data writing phase T3 of even-numbered frames, a high-level second control signal is transmitted on the first scan signal line S1, a low-level strobe signal is transmitted on the second scan signal line S2, a high-level second power signal VddH is maintained on the first power line L1, the third power line L3 switches to a low-level third power signal Vss0, and the fourth power signal VssH is maintained at a high level on the second power line L2.

[0126] At this time, the initialization module 110 is turned off while the data writing module 130 is turned on. A high-level second control signal turns off the first transistor M1, thus completely isolating the gate of the driving transistor DTFT from the initialization signal line Vref1. A low-level strobe signal turns on the second transistor M2. The data voltage on the data line Vdata is written to the gate of the driving transistor DTFT through the turned-on second transistor M2, and combined with the gate voltage after the compensation phase to form the final gate potential used for driving, which is stored by the first capacitor C1. The first power line L1 continuously provides a high-level operating voltage. Meanwhile, unlike odd-numbered frames, in the even-numbered frame data writing phase, the third power line L3 has been switched to a low-level third power signal Vss0 in advance, keeping the cathode of the second light-emitting element D2 at a low potential, preparing for the upcoming light-emitting phase; while the second power line L2 maintains a high-level fourth power signal VssH, ensuring that the first light-emitting element D1 remains in the off state. The second capacitor C2 continues to maintain the potential of the first node N1, ensuring the stability of the data writing process.

[0127] During the even-numbered frame illumination phase T4, the first scan signal line S1 maintains a high level second control signal, the second scan signal line S2 transmits a high level signal to turn off the data writing module 130, the first power line L1 maintains a high level second power signal VddH, the third power line L3 maintains a low level third power signal Vss0, and the second power line L2 maintains a high level fourth power signal VssH.

[0128] At this time, both the initialization module 110 and the data writing module 130 are turned off. The first transistor M1 and the second transistor M2 are both off, and the gate voltage of the driving transistor DTFT is maintained by the first capacitor C1. The driving transistor DTFT generates a corresponding driving current Id according to its gate-source voltage Vgs. This current flows from the first power line L1 through the driving transistor DTFT and is injected into the first terminal of the light-emitting module 13. Because the third power line L3 maintains a low-level third power signal Vss0, the cathode potential of the second light-emitting element D2 is low, making its anode potential higher than its cathode, forming a forward bias. Therefore, the second light-emitting element D2 is driven to emit light. Simultaneously, the second power line L2 provides a high-level fourth power signal VssH, making the cathode potential of the first light-emitting element D1 higher than its anode, forming a reverse bias. Therefore, the first light-emitting element D1 does not emit light. During this stage, the first capacitor C1 and the second capacitor C2 continue to function, respectively maintaining driving stability and anode potential, ensuring the uniformity of light emission from the second light-emitting element D2.

[0129] In summary, this invention alternately controls the potentials on the second power line L2 and the third power line L3 through odd-even frames: during the data writing phase T3 and the light emission phase T4 of odd-numbered frames, the second power line L2 provides a low-level fourth power signal Vss0 to make the first light-emitting element D1 emit light; during the corresponding phase of even-numbered frames, the third power line L3 provides a low-level fourth power signal Vss0 to make the second light-emitting element D2 emit light. Combined with the persistence of vision effect of the human eye, the alternately emitting odd-even row pixels are fused into a complete and continuous display image. This design, while achieving pixel circuit sharing and reducing layout space, further reduces the bezel of the display panel by replacing the progressive scan cathode drive circuit with global power line control.

[0130] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 13 As shown, the display device may include a display panel, and the display device may be at least one of wearable devices, cameras, mobile phones, tablets, displays, televisions, and vehicle display terminals.

[0131] The display device includes the display panel, and therefore the display device and the display panel have all the beneficial effects of the aforementioned display panel.

[0132] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: The system comprises a first scan signal line, a first power supply line, and multiple pixel units arranged in an array. The first scan signal line is connected to all the pixel units, and the first scan signal line is used for time-division transmission of the first control signal and the second control signal; The first power line is connected to all the pixel units, and the first power line is used for time-division transmission of the first power signal and the second power signal. Each pixel unit includes a light-emitting module and a pixel circuit corresponding to the light-emitting module. The pixel circuit includes an initialization module and a driving module. The first end of the driving module is connected to the first power line, and the second end of the driving module is connected to the first end of the light-emitting module; The initialization module connects the initialization signal line and the control terminal of the drive module. The initialization module is used to respond to the first control signal on the first scan signal line to transmit the initialization signal on the initialization signal line to the control terminal of the drive module.

2. The display panel according to claim 1, characterized in that, The operation phases of the pixel circuit within one frame include an initialization phase, a compensation phase, a data writing phase, and a light emission phase. The display panel further includes at least one driver chip, which is used to provide a first control signal to the first scan signal line during the initialization phase and the compensation phase. The at least one driver chip is used to provide a second control signal to the first scan signal line during the data writing phase and the light emission phase, and the second control signal is used to turn off the initialization module. Preferably, the at least one driver chip is used to provide a first power signal to the first power line during the initialization phase, and to provide a second power signal to the first power line during the compensation phase, the data writing phase, and the light emission phase. Preferably, the at least one driver chip is a single driver chip; Preferably, the at least one driver chip includes a first driver chip and a second driver chip; The first driver chip is connected to all the pixel units through the first scan signal line, and is used to provide the first control signal and the second control signal to the first scan signal line; The second driver chip is connected to all the pixel units through the first power line and is used to provide the first power signal and the second power signal to the first power line; Preferably, the first power signal is a negative voltage, and the second power signal is a positive voltage.

3. The display panel according to claim 1, characterized in that, Multiple pixel units are arranged in a column direction to form multiple pixel rows, the multiple pixel rows including odd-numbered rows and even-numbered rows; the light-emitting module includes a first light-emitting element and a second light-emitting element; The first light-emitting element is located in the odd-numbered rows, and the second light-emitting element is located in the even-numbered rows; The first electrode of the first light-emitting element and the first electrode of the second light-emitting element are connected to the first node, and the first node serves as the first end of the light-emitting module. The second electrode of the first light-emitting element is connected to the second power line, and the second electrode of the second light-emitting element is connected to the third power line.

4. The display panel according to claim 3, characterized in that, The operation phases of the pixel circuit within one frame include an initialization phase, a compensation phase, a data writing phase, and a light emission phase. The display panel also includes a power drive circuit; The power drive circuit is connected to the second pole of all the first light-emitting elements through the second power line; The power drive circuit is connected to the second pole of all the second light-emitting elements through the third power line; The power drive circuit is used to provide a third power signal to the second power line during the data writing phase and the light emission phase in odd-numbered frames; and to provide a fourth power signal to the second power line at other times. The power drive circuit is used to provide the third power signal to the third power line during the data writing phase and the light emission phase in even-numbered frames; and to provide the fourth power signal to the third power line at other times. Preferably, the fourth power signal is greater than the first power signal, the first power signal is less than the second power signal, and the second power signal is greater than the third power signal. Preferably, the power supply driving circuit is integrated into at least one driver chip; Preferably, the power drive circuit is a power drive chip independent of at least one driver chip.

5. The display panel according to claim 3, characterized in that, It also includes a first gate drive circuit and a second gate drive circuit. The first gate driving circuit includes multiple cascaded first shift registers, each of which is connected to a row of the first light-emitting elements via a corresponding second power line; The second gate driving circuit includes multiple cascaded second shift registers, each second shift register being connected to a row of the second light-emitting elements via a corresponding third power line; Wherein, the first shift register is used to provide effective pulses of the gate drive signal to the first light-emitting element during the data writing phase and the light-emitting phase of the odd-numbered frames; The second shift register is used to provide effective pulses of the gate drive signal to the second light-emitting element during the data writing phase and the light emission phase of even-numbered frames.

6. The display panel according to claim 1, characterized in that, The initialization module includes a first transistor, the first terminal of which is connected to the initialization signal line, and the gate of which is connected to the first scan signal line. The driving module includes a driving transistor, the gate of which is connected to the second terminal of the first transistor, the first terminal of which is connected to the first power line, and the second terminal of which is connected to the first end of the light-emitting module. Preferably, the first transistor is a PMOS transistor, and the driving transistor is an NMOS transistor.

7. The display panel according to claim 1, characterized in that, The display panel further includes a third gate driving circuit and multiple second scan signal lines. The third gate driving circuit includes multiple cascaded third shift registers, and each third shift register is connected to a row of pixel circuits through a corresponding second scan signal line. The pixel circuit also includes a data writing module; the data writing module is connected to the data line and the second scan signal line, and during the data writing stage, it provides a line-by-line scanning strobe signal to the second scan signal line to control the data writing module to write the data signal on the data line to the control terminal of the driving module line by line; Preferably, the data writing module includes a second transistor, the first terminal of the second transistor is connected to the data line, the second terminal of the second transistor is connected to the control terminal of the driving module, and the gate of the second transistor is connected to the second scan signal line; Preferably, the second transistor is a PMOS transistor.

8. The display panel according to claim 1, characterized in that, The pixel circuit also includes a coupling module; The first end of the coupling module is connected to the control terminal of the driving module, and the second end of the coupling module is connected to the first end of the light-emitting module. The coupling module is used to couple the potential of the second end of the coupling module to the control terminal of the driving module. Preferably, the coupling module includes a first capacitor, with a first end of the first capacitor serving as the first end of the coupling module and a second end of the first capacitor serving as the second end of the coupling module.

9. The display panel according to claim 8, characterized in that, The pixel circuit also includes a holding module; The first end of the holding module is connected to the first end of the light-emitting module, and the second end of the holding module is connected to the first power line or the initialization signal line. The holding module is used to maintain the potential of the first end of the light-emitting module. Preferably, the holding module includes a second capacitor, with a first end of the second capacitor serving as a first end of the holding module and a second end of the second capacitor serving as a second end of the holding module.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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