Pixel circuit and display panel

Abstract

The embodiment of the invention discloses a pixel circuit and a display panel, and belongs to the technical field of display. The pixel circuit comprises a light-emitting control circuit, the light-emitting control circuit comprises a memory and a time-delay circuit, the memory is set to store at least one bit of gray scale data, and the time-delay circuit is set to generate a light-emitting control signal capable of being delayed according to the gray scale data; and the light-emitting circuit is set to be conducted to emit light under the control of the light-emitting control signal. According to the embodiment of the invention, the problem that pixels in the same row and different columns are started during line-by-line scanning can be avoided.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular to a pixel circuit and a display panel. BACKGROUND

[0002] At present, the driving mode of line-by-line scanning is widely used in display panels, when a line is turned on, the pixels in each column of the line start lighting at the same time. However, the pixels in different columns of the same line start lighting at the same time will appear a large peak current, thus causing a significant IR drop (voltage drop), and further causing the problem of display unevenness. SUMMARY

[0003] The main purpose of embodiments of the present application is to provide a pixel circuit and a display panel, aiming at solving the technical problem of how to avoid turning on the pixels in different columns of the same line at the same time in line-by-line scanning.

[0004] To achieve the above purpose, embodiments of the present application provide a pixel circuit, which comprises: a light-emitting control circuit, the light-emitting control circuit comprises a memory and a delay circuit, the memory is configured to store at least 1-bit gray scale data, and the delay circuit is configured to generate a delay-transmissible light-emitting control signal according to the gray scale data; a light-emitting circuit, the light-emitting circuit is configured to be turned on for light-emitting under the control of the light-emitting control signal.

[0005] In an embodiment, the memory is a 1-bit memory, and the delay circuit comprises a delay control module. The 1-bit memory, the delay control module and the light-emitting circuit are electrically connected in sequence.

[0006] In an embodiment, the memory is a multi-bit memory, and the delay circuit comprises a delay control module and a PWM (Pulse Width Modulation) controller. The multi-bit memory, the delay control module, the PWM controller and the light-emitting circuit are electrically connected in sequence, or the multi-bit memory, the PWM controller, the delay control module and the light-emitting circuit are electrically connected in sequence.

[0007] In an embodiment, the delay control module comprises: a delay control switch, a controlled end of the delay control switch is connected to a line scanning signal, and a first end of the delay control switch is connected to a delay control signal; A delay selection unit, a first end of the delay selection unit is electrically connected to a second end of the delay control switch, and the delay selection unit is configured to adjust a time length of delay transmission of the light-emitting control signal to the light-emitting circuit according to the delay control signal when the delay control switch is turned on based on the scanning signal.

[0008] In an embodiment, the delay control signal is a serial transmission signal, and the delay selection unit comprises: a plurality of first buffers, each of the first buffers being connected in series; a plurality of first selection switches, a number of the first selection switches being same as a number of the first buffers, each of the first selection switches being connected in parallel to one of the first buffers; a serial-parallel converter, an input end of the serial-parallel converter being connected to the delay control signal, and output ends of the serial-parallel converter being electrically connected to controlled ends of each of the first selection switches.

[0009] In an embodiment, the delay control signal is a parallel transmission signal, and the delay selection unit comprises: a plurality of second buffers, each of the second buffers being connected in series; a plurality of second selection switches, a number of the second selection switches being same as a number of the second buffers, each of the second selection switches being connected in parallel to one of the second buffers, and a controlled end of each of the second selection switches being connected to the delay control signal.

[0010] In an embodiment, the light-emitting circuit comprises: a current source, a first end of the current source being electrically connected to a first preset power supply end; a light-emitting control switch, a controlled end of the light-emitting control switch being electrically connected to an output end of the light-emitting control circuit, and a first end of the light-emitting control switch being electrically connected to a second end of the current source; a light-emitting element, an anode of the light-emitting element being electrically connected to a second end of the light-emitting control switch, and a cathode of the light-emitting element being electrically connected to a second preset power supply end.

[0011] In addition, to achieve the above object, an embodiment of the present application further provides a display panel, the display panel comprising a plurality of sub-pixels arranged in an array, the sub-pixels comprising the pixel circuit as described above, and the display panel further comprising a delay control signal generation circuit, the delay control signal generation circuit being electrically connected to the pixel circuit of each of the sub-pixels.

[0012] In an embodiment, the delay control signal generation circuit is configured to output delay control signals with different time sequences to the pixel circuits of at least part of the sub-pixels in the same row and in different columns.

[0013] In an embodiment, the delay control signal generation circuit is configured to divide a preset number of sub-pixels in a same row in sequence into a same group, and output delay control signals with different time sequences to pixel circuits of the sub-pixels in the same group.

[0014] The embodiment of the present application provides a pixel circuit and a display panel. The pixel circuit comprises: a light-emitting control circuit, the light-emitting control circuit comprising a memory and a delay circuit, the memory being configured to store at least 1 bit of gray scale data, and the delay circuit being configured to generate a light-emitting control signal capable of being delayed transmission according to the gray scale data; and a light-emitting circuit, the light-emitting circuit being configured to turn on light-emitting under the control of the light-emitting control signal. The embodiment of the present application can make the light-emitting control signal delayed transmission to the light-emitting circuit by additionally arranging the delay circuit capable of generating the light-emitting control signal capable of being delayed transmission according to the gray scale data in the light-emitting control circuit of the pixel circuit, so that the time node of turning on light-emitting of the light-emitting circuit is correspondingly delayed, that is, the time of lighting the pixel can be adjusted based on the delay circuit, so that different delays of the light-emitting control signals of at least part of the pixel circuits in the same row and different columns can be configured, the start time of light-emitting of the pixels can be staggered as much as possible, the peak current caused by the simultaneous start of light-emitting of the pixels can be reduced, the obvious IR drop can be reduced, and the problem of display unevenness can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute a part of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0016] Figure 1 A signal time sequence diagram for the same row and different column pixels of the embodiment of the present application to start simultaneously; Figure 2 A structural schematic diagram of a pixel circuit provided by the embodiment of the present application; Figure 3 A structural schematic diagram of a feasible example of a pixel circuit provided by the embodiment of the present application to embody the memory and the delay circuit; Figure 4 A structural schematic diagram of another feasible example of a pixel circuit provided by the embodiment of the present application to embody the memory and the delay circuit; Figure 5 A structural schematic diagram of still another feasible example of a pixel circuit provided by the embodiment of the present application to embody the memory and the delay circuit; Figure 6A structure diagram of a delay control module related to a pixel circuit provided by an embodiment of the present application; Figure 7 A signal timing diagram of a same-row different-column pixel misalignment opening related to a pixel circuit provided by an embodiment of the present application; Figure 8 A structure diagram of a feasible example of a delay selection unit related to a pixel circuit provided by an embodiment of the present application; Figure 9 A structure diagram of another feasible example of a delay selection unit related to a pixel circuit provided by an embodiment of the present application; Figure 10 A structure diagram of a feasible example of a light emitting circuit embodied by a pixel circuit provided by an embodiment of the present application.

[0017] Explanation of reference numerals: 10, light emitting control circuit; 11, memory; 12, delay circuit; 20, light emitting circuit; 111, 1-bit memory; 121, delay control module; 112, multi-bit memory; 122, PWM controller; 1211, delay control switch; Scan(N), row scanning signal; shift, delay control signal; 1212, delay selection unit; T1, first selection switch; T2, second selection switch; 21, current source; 22, light emitting control switch; 23, light emitting element. DETAILED DESCRIPTION

[0018] In the following description, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, persons skilled in the art will understand that the embodiments of the present application can be practiced without these specific details. In other instances, well-known systems, devices, circuits, and methods have not been described in detail so as not to unnecessarily obscure the description of the embodiments of the present application.

[0019] At present, the driving mode of line-by-line scanning is widely used in display panels, when a row is opened, the pixels in each column of the row start lighting at the same time. However, the simultaneous lighting of pixels in the same row and different columns will cause a large peak current, resulting in a significant IR drop (voltage drop), and further causing the problem of display unevenness. Taking four column sub-pixels in the Nth row of the display panel as an example, the pixel circuits of each sub-pixel are electrically connected with the scanning line, respectively connected with 4 data lines (accessing data signals DATA1~DATA4), and respectively including light emitting elements LED1~LED4, such as Figure 1As shown, in the case that the scanning signal Scan(N) is high to make the Nth row open, the DATA of all the sub-pixels of the Nth row enter the pixel circuit at the same time, and the light emitting elements of all the sub-pixels open at the same time, even if the data carried by DATA1, DATA2, DATA3 and DATA4 are different, ILED1, ILED2, ILED3 and ILED4 will also be pulled high at the same time.

[0020] Based on this, the embodiment of the present application provides a pixel circuit and a display panel, by adding a delay circuit capable of generating a light emitting control signal capable of delayed transmission according to gray scale data in the light emitting control circuit of the pixel circuit, the light emitting control signal can be transmitted to the light emitting circuit in a delayed manner, so that the time node of the conduction and light emitting of the light emitting circuit is correspondingly delayed, that is, the time when the pixel is lighted up can be adjusted based on the delay circuit, in this way, different delays can be configured for the light emitting control signals of at least part of the pixel circuits in the same row but different columns, the start-up times of these pixels can be staggered as much as possible, the peak current caused by the simultaneous start-up of the pixels is reduced, the obvious IR drop is reduced, and the problem of display unevenness is improved.

[0021] The pixel circuit and the display panel provided by the embodiment of the present application are specifically described by the following embodiments, first, the pixel circuit in the embodiment of the present application is described.

[0022] The embodiment of the present application provides a pixel circuit, with reference to Figure 2 , Figure 2 The structure schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in Figure 2 , the pixel circuit can include: The light emitting control circuit 10 includes a memory 11 and a delay circuit 12, the memory 11 is configured to store at least 1-bit gray scale data, and the delay circuit 12 is configured to generate a light emitting control signal capable of delayed transmission according to the gray scale data; The light emitting circuit 20 is configured to conduct and emit light under the control of the light emitting control signal.

[0023] The pixel circuit provided by the embodiment can be applied to a display panel, and each sub-pixel in the display panel can be configured with the pixel circuit provided by the embodiment.

[0024] In the embodiment, the gray scale data input to the light emitting control circuit 10 can come from the data line of the column in which the sub-pixel corresponding to the pixel circuit is located, the memory 11 can be a digital memory which can receive and store the gray scale data from the data line, and the bit value (logic level) of at least 1-bit data can be input to the memory 11 according to a preset order. The memory 11 can store only 1-bit data or can store multi-bit data, which can be determined according to actual application requirements and the type of the memory 11, and the embodiment does not limit this. As an example, the memory 11 can be implemented by one or more transistors, and the memory 11 can also be implemented as a random access memory (RAM), such as a static random access memory (SRAM) or a dynamic random access memory (DRAM).

[0025] In the embodiment, the delay circuit 12 can convert the gray scale data from the memory 11 into a light emitting control signal to be provided to the light emitting circuit 20 after receiving the gray scale data, and the light emitting control signal can be transmitted to the light emitting circuit 20 after being delayed for a certain time. Compared with a conventional pixel circuit which does not perform delay processing on the light emitting control signal, the start times of the light emitting of the light emitting circuits 20 of the two pixel circuits are different due to the delay.

[0026] As an example, taking two sub-pixels in the same row of the display panel as an example, one of the sub-pixels includes the delay circuit 12 in the pixel circuit of the embodiment to delay the transmission of the light emitting control signal, and the other sub-pixel does not include the delay circuit 12. Even if the two sub-pixels are simultaneously connected to the data signal under the control of the same scanning signal, the light emitting elements in the two sub-pixels will not emit light at the same time, but there will be a time difference, which can be flexibly adjusted by the delay circuit 12 in the embodiment.

[0027] As an example, the delay circuit 12 can also be configured for multiple sub-pixels in the same row, and the delay times of the delay circuits 12 are adjusted to be different from each other, so that the start times of the light emitting of the light emitting elements in the sub-pixels are staggered.

[0028] Reference Figure 3 In some possible embodiments, the memory 11 is a 1-bit memory 111, the delay circuit 12 can include a delay control module 121, and the 1-bit memory 111, the delay control module 121 and the light emitting circuit 20 are electrically connected in sequence.

[0029] In the embodiment, since the 1-bit memory 111 only stores 1-bit gray scale data, the delay circuit 12 can only include a delay control module 121 for realizing delay transmission, and the 1-bit gray scale data output from the 1-bit memory 111 will not be directly transmitted to the light-emitting circuit 20 to make it turn on the light-emitting, but will be transmitted to the light-emitting circuit 20 after passing through the delay control module 121, and the delay time of the delay control module 121 can be flexibly adjusted by the structural design and parameter configuration of the delay control module 121, which is not limited in the embodiment.

[0030] In some possible embodiments, the memory 11 is a multi-bit memory 112, and the delay circuit 12 can include a delay control module 121 and a PWM controller 122; referring to Figure 4 , the multi-bit memory 112, the delay control module 121, the PWM controller 122 and the light-emitting circuit 20 are electrically connected in sequence; or, referring to Figure 5 , the multi-bit memory 112, the PWM controller 122, the delay control module 121 and the light-emitting circuit 20 are electrically connected in sequence.

[0031] In the embodiment, since the multi-bit memory 112 can store multi-bit gray scale data, the delay circuit 12 can include, in addition to the delay control module 121 for realizing delay transmission, the PWM controller 122 for generating a light-emitting control signal based on the multi-bit gray scale data, and the PWM controller 122 can generate a pulse width modulation signal as the light-emitting control signal based on the input clock signal and the bit value of the corresponding gray scale data. As an example, the PWM controller 122 can include one or more logic circuits implemented by one or more transistors, which is not limited in the embodiment.

[0032] In the embodiment, the delay control module 121 can be arranged between the multi-bit memory 112 and the PWM controller 122, as shown in Figure 4 , by delaying the time of transmitting the gray scale data to the PWM controller 122, indirectly achieving the purpose of delaying the transmission of the light-emitting control signal; the delay control module 121 can also be arranged between the PWM controller 122 and the light-emitting circuit 20, as shown in Figure 5 , after the PWM controller 122 generates the light-emitting control signal based on the gray scale data, directly delaying the time of transmitting the light-emitting control signal to the light-emitting circuit 20.

[0033] Referring to Figure 6 , in some possible embodiments, the delay control module 121 in the above embodiments can include: The delay control switch 1211 has a control end connected to the row scanning signal Scan(N) and a first end connected to the delay control signal shift. The delay selection unit 1212 has a first end electrically connected to the second end of the delay control switch 1211. When the delay control switch 1211 is turned on based on the scanning signal, the delay selection unit 1212 is configured to adjust the time length of the delay transmission of the light-emitting control signal to the light-emitting circuit 20 according to the delay control signal shift.

[0034] In this embodiment, the control end of the delay control switch 1211 is electrically connected to the scanning line for driving the row of pixels, so that the row scanning signal Scan(N) can be connected. In this way, the delay control module 121 starts to work when the row of pixels is turned on. After the delay control switch 1211 is turned on, the delay control signal shift for adjusting the delay time of the delay control module 121 can reach the delay selection unit 1212 through the delay control switch 1211, so that the delay selection unit 1212 can adjust the delay transmission time of the light-emitting control signal based on the delay control signal shift.

[0035] As an example, the delay control switch 1211 in this embodiment can be implemented in the form of a switch transistor, such as a bipolar junction transistor (BJT), a field effect transistor (FET), etc. It can also be implemented by other devices with similar functions, which are not limited in this embodiment.

[0036] As an example, taking four columns of sub-pixels in the Nth row of the display panel as an example, the pixel circuits of the sub-pixels are electrically connected to the same scanning line, respectively connected to four data lines (connected to the data signals DATA1~DATA4), respectively connected to four time-varying delay control signals Shift1~Shift4, and respectively include light-emitting elements LED1~LED4, as shown in FIG. 1C. Figure 7 As shown in FIG. 1C, when the scanning signal Scan(N) is high to turn on the Nth row, the DATA of all sub-pixels in the Nth row enter the pixel circuits at the same time. However, under the delay control of the delay control signals Shift1, Shift2, Shift3 and Shift4, ILED1, ILED2, ILED3 and ILED4 are not pulled up at the same time, i.e., the turn-on time of the light-emitting elements of each sub-pixel is different, which does not cause a too large peak current to appear instantaneously, effectively reduces the IR drop, and improves the display unevenness.

[0037] As an example, the delay selection unit 1212 can be implemented by combining a plurality of buffers and corresponding selection switches, so that the number of buffers that the gray scale data or the light emitting control signal needs to pass through can be flexibly adjusted according to the delay control signal shift. The more the number of buffers that the gray scale data or the light emitting control signal needs to pass through, the longer the delay transmission time. The less the number of buffers that the gray scale data or the light emitting control signal needs to pass through, the shorter the delay transmission time. In particular, the delay control signal shift can also make the delay selection unit 1212 select to short each buffer. At this time, the gray scale data or the light emitting control signal only needs to pass through a piece of wire, and the delay transmission time can be almost negligible, which is equivalent to not needing to perform delay control.

[0038] With reference to Figure 8 In some possible embodiments, the delay control signal shift is a serial transmission signal, and the delay selection unit 1212 can include: a plurality of first buffers, each first buffer being connected in series; a plurality of first selection switches T1, the number of the first selection switches T1 being the same as the number of the first buffers, each first selection switch T1 being connected in parallel with a first buffer; a serial-parallel converter, an input end of the serial-parallel converter being connected to the delay control signal, and an output end of the serial-parallel converter being electrically connected to controlled ends of the first selection switches T1.

[0039] In this embodiment, the delay control signal shift can be a single-line serial signal, which needs to be converted into a parallel signal by the serial-parallel converter and control one first selection switch T1 respectively, so as to select whether the gray scale data or the light emitting control signal passes through the first buffer corresponding to the first selection switch T1, thereby realizing delay control.

[0040] With reference to Figure 9 In some possible embodiments, the delay control signal shift is a parallel transmission signal, and the delay selection unit 1212 can include: a plurality of second buffers, each second buffer being connected in series; a plurality of second selection switches T2, the number of the second selection switches T2 being the same as the number of the second buffers, each second selection switch T2 being connected in parallel with a second buffer, and a controlled end of each second selection switch T2 being connected to the delay control signal.

[0041] In this embodiment, the delay control signal shift can be a parallel transmission signal, such as Figure 9As shown, taking the example of the delay control signal shift including the parallel 4bit signals shift_B0, shift_B1, shift_B2, shift_B3, the shift_B0, shift_B1, shift_B2, shift_B3 respectively control a corresponding second selection switch T2, so as to select whether the gray scale data or the light emitting control signal passes through the second buffer corresponding to the second selection switch T2, to realize delay control.

[0042] As an example, the selection switch in the above embodiments can be realized in the form of a switch transistor, or can be realized by other devices with similar functions, and the embodiments are not limited in this regard.

[0043] With reference to Figure 10 In some possible embodiments, the light emitting circuit 20 includes: A current source 21, a first end of the current source 21 being electrically connected to a first preset power supply end; A light emitting control switch 22, a controlled end of the light emitting control switch 22 being electrically connected to an output end of the light emitting control circuit 10, and a first end of the light emitting control switch 22 being electrically connected to a second end of the current source 21; A light emitting element 23, an anode of the light emitting element 23 being electrically connected to a second end of the light emitting control switch 22, and a cathode of the light emitting element 23 being electrically connected to a second preset power supply end.

[0044] In the embodiment, the light emitting control switch 22 can be turned on or turned off based on the light emitting control signal from the light emitting control circuit 10, and in the case that the light emitting control switch 22 is turned on, the light emitting element 23 can be turned on to emit light based on the driving current provided by the current source 21.

[0045] As an example, the light emitting control switch 22 in the embodiment can be realized in the form of a switch transistor, or can be realized by other devices with similar functions, and the light emitting element 23 can be an LED (Light-Emitting Diode), an OLED (Organic Light-Emitting Diode), etc., and the embodiments are not limited in this regard.

[0046] In addition, the application also provides a display panel, which includes a plurality of sub-pixels arranged in an array, the sub-pixel including the pixel circuit provided in the above embodiments, and the display panel further includes a delay control signal generation circuit, which is electrically connected to the pixel circuit of each sub-pixel.

[0047] In an embodiment, the delay control signal generation circuit is configured to output delay control signals with different time sequences to the pixel circuits of at least part of the sub-pixels in the same row and in different columns.

[0048] In the embodiment, the starting time of the light-emitting of the at least partial sub-pixels in the same row and different columns is not the same, which can avoid the display uneven problem caused by the peak current to the greatest extent.

[0049] In an embodiment, the delay control signal generation circuit is configured to divide the preset number of sub-pixels in the same row and continuous columns into the same group, and output the delay control signals with different time sequences to the pixel circuits of the sub-pixels in the same group.

[0050] In the embodiment, the starting time of the light-emitting of the sub-pixels in the same group is not the same, but the starting time of the light-emitting of the sub-pixels in the same row is the same, which can be used in the case that too many delay levels cannot be provided, and can avoid the display uneven problem caused by the peak current to a certain extent.

[0051] As an example, the display panel in the embodiment can be a TN (Twisted Nematic) display panel, an IPS (In-Plane Switching) display panel, a VA (Vertical Alignment) display panel, an MVA (Multi-Domain Vertical Alignment) display panel, and of course, can also be other types of display panels, such as an OLED display panel.

[0052] As an example, the display panel can be applied to a display device, which can be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0053] The specific structure of the pixel circuit in the embodiment is referred to the above embodiments. Since the display panel in the embodiment adopts all the technical solutions in the above embodiments, which belong to the same technical concept, the embodiment at least has all the beneficial effects brought by the technical solutions in the above embodiments, which will not be repeated here.

[0054] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indications will also change accordingly.

[0055] In addition, the terms "first", "second", and the like in the description of the embodiments of the present application are only used for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features indicated, or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" and "second" can be explicitly or implicitly included at least one of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited. In addition, the meaning of "and / or" appearing throughout the text is to include three parallel schemes, for example, "A and / or B" includes A scheme, or B scheme, or A and B scheme.

[0056] In the embodiments of the present application, unless otherwise specifically defined and limited, the terms "connection", "fixing", and the like should be understood in a broad sense, for example, "fixing" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium, can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise specifically limited. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0057] It should also be understood that the reference "one embodiment" or "some embodiments" and the like described in the specification of the embodiments of the present application means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in other some embodiments" and the like appearing in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "include", "contain", "have" and their variants mean "include but not limited to", unless otherwise specifically emphasized.

[0058] It should be noted that the technical solutions of each embodiment of the embodiments of the present application can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the scope of protection claimed by the embodiments of the present application.

[0059] The above is only an optional embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises: a light-emitting control circuit, the light-emitting control circuit comprising a memory and a delay circuit, the memory being configured to store at least 1-bit gray scale data, and the delay circuit being configured to generate a delay-transmissible light-emitting control signal according to the gray scale data; a light-emitting circuit, the light-emitting circuit being configured to be turned on for light-emitting under the control of the light-emitting control signal.

2. The pixel circuit of claim 1, wherein, The memory is a 1-bit memory, and the delay circuit comprises a delay control module. The 1-bit memory, the delay control module and the light-emitting circuit are electrically connected in sequence.

3. The pixel circuit of claim 1, wherein, The memory is a multi-bit memory, and the delay circuit comprises a delay control module and a PWM controller. The multi-bit memory, the delay control module, the PWM controller and the light-emitting circuit are electrically connected in sequence, or the multi-bit memory, the PWM controller, the delay control module and the light-emitting circuit are electrically connected in sequence.

4. The pixel circuit of claim 2 or 3, wherein, The delay control module comprises: a delay control switch, a controlled end of the delay control switch being connected to a row scanning signal, and a first end of the delay control switch being connected to a delay control signal; a delay selection unit, a first end of the delay selection unit being electrically connected to a second end of the delay control switch, and the delay selection unit being configured to adjust a time length for which the light-emitting control signal is delay-transmitted to the light-emitting circuit according to the delay control signal, in a case where the delay control switch is turned on based on the scanning signal.

5. The pixel circuit of claim 4, wherein, The delay control signal is a serial transmission signal, and the delay selection unit comprises: a plurality of first buffers, each of the first buffers being connected in series; a plurality of first selection switches, the number of the first selection switches being the same as the number of the first buffers, and each of the first selection switches being connected in parallel with one of the first buffers; a serial-parallel converter, an input end of the serial-parallel converter being connected to the delay control signal, and output ends of the serial-parallel converter being electrically connected to controlled ends of the first selection switches.

6. The pixel circuit of claim 4, wherein, The delay control signal is a parallel transmission signal, and the delay selection unit comprises: a plurality of second buffers, each of the second buffers being connected in series; a plurality of second selection switches, the number of the second selection switches being the same as the number of the second buffers, and each of the second selection switches being connected in parallel with one of the second buffers, and controlled ends of the second selection switches being connected to the delay control signal.

7. The pixel circuit of claim 1, wherein, The light-emitting circuit comprises: a current source, a first end of the current source being electrically connected to a first preset power supply end; a light-emitting control switch, a controlled end of the light-emitting control switch being electrically connected to an output end of the light-emitting control circuit, and a first end of the light-emitting control switch being electrically connected to a second end of the current source; a light-emitting element, an anode of the light-emitting element being electrically connected to a second end of the light-emitting control switch, and a cathode of the light-emitting element being electrically connected to a second preset power supply end.

8. A display panel comprising a plurality of sub-pixels arranged in an array, characterized in that, The sub-pixel comprises the pixel circuit according to any one of claims 1 to 7, and the display panel further comprises a delay control signal generation circuit, the delay control signal generation circuit being electrically connected to the pixel circuit of each of the sub-pixels.

9. The display panel of claim 8, wherein, The delay control signal generation circuit is configured to output delay control signals with different time sequences to pixel circuits of at least some of the sub-pixels in the same row and different columns.

10. The display panel of claim 8, wherein, The delay control signal generation circuit is configured to divide a preset number of sub-pixels in the same row and in consecutive columns into the same group, and output delay control signals with different time sequences to pixel circuits of each of the sub-pixels in the same group.

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