Temperature adaptive read circuit for capacitance-free dynamic random access memory and operating method thereof
By employing an adaptive load and sensitive amplifier consistent with the memory cell structure in capacitor-free DRAM, the problem of temperature-dependent read reliability in capacitor-free DRAM has been solved, enabling stable data read at high temperatures and expanding its application range.
Patent Information
- Application Number
- CN202511701719.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-02-27
AI Technical Summary
The read reliability of capacitor-free DRAM is significantly affected by temperature. Traditional read circuits have a high read error rate at high temperatures, which limits their application in high-reliability scenarios.
An adaptive load and sensitive amplifier consistent with the storage cell structure are adopted. Through a read circuit composed of a current mirror, clamping transistor and latch, the reference current and the storage cell current are synchronized with temperature changes to ensure the stability of the voltage difference.
It maintains stable read performance over a wide temperature range, improves the reliability of the read circuit and the maximum operating temperature, and is suitable for industrial and automotive applications.
Smart Images
Figure CN121583307A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of micro-nano electronics, and particularly relates to a temperature adaptive reading circuit for a capacitorless dynamic random access memory (DRAM), which is particularly suitable for a 2T0C (two-transistor capacitorless) DRAM structure based on oxide semiconductor. BACKGROUND
[0002] With the continuous progress of integrated circuit technology, capacitorless DRAMs have shown broad application prospects in embedded storage systems due to their simple structure, low power consumption, and ease of three-dimensional integration. In particular, 2T0C DRAMs based on oxide semiconductor (such as IGZO) have extremely long data retention time and good integration capability. However, the read reliability of capacitorless DRAMs is significantly affected by temperature. As the temperature rises, the current characteristics of the storage unit change, causing the memory window to shrink, which in turn affects the correct discrimination of data by the sense amplifier (SA). Traditional reading circuits use a fixed load resistance (CL) as a reference, which has temperature characteristics that do not match those of the storage unit, resulting in an increase in read error rate at high temperatures, limiting their application in high-reliability scenarios such as industrial-grade (IG) and automotive-grade (AG). Therefore, there is an urgent need for a reading circuit solution that can adapt to temperature changes and improve read reliability. SUMMARY
[0003] The present application aims to provide a temperature adaptive reading circuit for capacitorless DRAMs that can maintain stable read performance over a wide temperature range and improve system reliability and applicable temperature range.
[0004] To achieve the above-mentioned application purposes, the present application adopts the following technical solutions: A temperature adaptive reading circuit for a capacitorless dynamic random access memory, the memory being composed of an array of storage units, characterized in that it comprises an adaptive load using the structure of the storage unit as a reference resistance; the adaptive load is consistent with the storage unit in process, structure, and size, and has matching temperature characteristics; a sense amplifier is added, which is connected to the read node of the memory and the reference node of the adaptive load, respectively, for detecting and amplifying the voltage difference between the two nodes and converting the voltage difference into a digital output signal.
[0005] Further, the memory is an array of 2T0C DRAM storage units, and the 2T0C DRAM storage units are connected through RBL to a multiplexer MUX.
[0006] Further, the sensitive amplifier comprises a current mirror, a clamp tube and a latch, the current mirror is composed of two PMOS transistors P1 and P2, the gates of the transistors P1 and P2 are connected, the drain of the transistor P1 is connected to a storage node X1, and the drain of the transistor P2 is connected to a reference node X2, one end of a capacitor C1 is connected to the storage node X1, and the other end is connected to the ground, the adaptive load is connected to the storage node X1 through a switch, the storage node X1 is connected to the clamp tube, the reference node X2 is located between the adaptive load and a multiplexer, the adaptive load is connected to the reference node X2 through another switch, the clamp tube is composed of two transistors N1 and N2 connected in series, and the storage node X1 and the reference node X2 output data through the latch.
[0007] Further, an operating method of the temperature adaptive reading circuit is provided, and the steps of the method comprise: 1) pre-charging: the transistors N1 and N2 are turned off, and the storage node X1 and the reference node X2 are pre-charged to a fixed high voltage; 2) reference current generation: the transistors N1 and N2 are turned on, and the storage node X1 and the reference node X2 start to discharge, respectively generating I CELL and I REF from the 2T0C DRAM unit and the reference resistance, and forming a voltage difference ΔV; 3) voltage difference detection and logic reconstruction: the latch circuit converts the voltage difference ΔV into a digital "0 / 1" output.
[0008] The application adopts a structure identical to the storage unit as the adaptive load, so that the reference branch and the storage branch generate a synchronous response to the change of temperature. When the ambient temperature changes, the current characteristics of the storage unit and the resistance characteristics of the adaptive load drift in the same direction, so that the difference between the unit current and the reference current is maintained. This adaptive compensation mechanism effectively inhibits the degradation of the memory window with temperature, ensures correct data discrimination in a wide temperature range, and significantly improves the reliability and maximum operating temperature of the reading circuit.
[0009] The application has the following advantages: 1. By adopting the adaptive load identical to the structure of the storage unit, the temperature synchronous change of the reference current and the storage unit current is realized, and the degradation of the memory window caused by temperature is effectively compensated; 2. Reliable reading performance can be maintained in a high-temperature environment, and the maximum reliable operating temperature is improved; It is suitable for high-reliability application scenarios such as industrial and automotive levels, and expands the application range of capacitorless DRAM. BRIEF DESCRIPTION OF DRAWINGS
[0010] Figure 1A temperature adaptive read circuit schematic diagram of the present application; Figure 2 Simulation results of a specific embodiment of the present application. DETAILED DESCRIPTION
[0011] Embodiments of the present application will be described below with reference to the accompanying drawings.
[0012] It should be noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed content, and the scope of the present application is defined by the scope of the claims.
[0013] The temperature adaptive read circuit for a capacitorless dynamic random access memory of the present application is shown in Figure 1 . The memory is composed of an array of 2T0C DRAM memory cells, and a multiplexer MUX is connected between the 2T0C DRAM memory cells through an RBL. The temperature adaptive read circuit includes a sense amplifier and an adaptive load, which is a 2T0C DRAM memory cell structure. The adaptive load is consistent with the memory cell in process, structure and size, and has matching temperature characteristics. It is connected to the storage node X1 through a switch (SW1) and to the reference node X2 through another switch (SW2).
[0014] The sense amplifier includes a current mirror, a clamping tube and a latch. The Clamper (clamping tube) is connected between the storage node X1, the reference node X2 and the adaptive load and the multiplexer. The storage node X1 and the reference node X2 are connected to VDD through a current mirror. This current mirror is composed of two PMOS transistors P1 and P2. The gates of P1 and P2 are connected, the drain of transistor P2 is connected to the reference node X2, and the drain of P1 is connected to the storage node X1. Capacitor C1 is connected to X1 node and grounded. The storage cell generates a current I CELL The adaptive load generates a current I REF . The temperature reliability of the 2T0C DRAM read circuit depends on the current difference between I CELL and I REF . When the adaptive reference load and the memory cell are in the same thermal environment, they exhibit perfect matching temperature-dependent characteristics. At high temperatures, although the device characteristics of the two elements are both shifted due to thermal effects, I CELL and I REFKeep in sync. This inherent thermal tracking feature enables the 2T-based adaptive load to precisely follow the parameter drift of the storage cell, thus enabling the sense amplifier to consistently resolve the current difference under temperature variation, achieving accurate logic reconstruction and data retrieval. Experimental results show that the fixed load-based read circuit has reliability problems at a working temperature of about T1, while the variable load-based read circuit can maintain reliable reading even when the temperature exceeds T2 (T1 < T2). Different storage data, different discharge speeds: store "1": fast discharge → V X1 <V X2 ; store "0": slow discharge → V X1 >V X2 The voltages of the storage node X1 and the reference node X2 are sent to a latch. The clamping tube is a positive feedback circuit composed of two transistors (N1 and N2) connected in series, which can amplify the small voltage difference between X1 and X2 and quickly drive it to a complete logic level ("0" or "1"), and finally output the data.
[0015] To verify the function of the proposed temperature adaptive read circuit, the circuit response of the four working modes is simulated and verified. Under different temperature conditions, each working mode shows the following characteristics: In the precharge phase (stage I), the circuit can effectively precharge the storage node (X1) and the reference node (X2) to the target high level, preparing for the subsequent discharge. The response is stable under different temperatures.
[0016] In the critical reference current generation phase (stage II), the circuit response exhibits its temperature adaptive characteristics. When the temperature changes, the traditional fixed load (CL) circuit causes the reference current to mismatch with the storage cell current, leading to chaotic node voltage relationships; while the adaptive load (AL) circuit used in this invention has consistent temperature characteristics with the storage cell, allowing the reference current to always track the changes in the storage cell current. Therefore, under different temperatures, this stage can produce voltage difference preparation signals that correctly correspond to the storage data ("0" or "1").
[0017] In the voltage difference detection phase (stage III) and the logic reconstruction phase (stage IV), the circuit response directly depends on the voltage difference generated in the previous stage. For the AL circuit, since the voltage difference (ΔV) input to the sense amplifier maintains the correct polarity (for "0" and "1" states) within a wide temperature range, the latch can be reliably triggered and output the correct logic level, ensuring the correctness of the final data reading.
[0018] Figure 2The simulation results show that the four working modes defined in the application work in cooperation, so that the reading circuit makes correct and stable response to temperature change in a wide temperature range, thereby realizing reliable data reading, while the CL circuit has reading error at high temperature. Among them, (a) shows the voltage waveforms of the write word line (WWL) and the write bit line (WBL). By applying a 2V pulse signal to the WWL, +1.2V (representing "1") and -1.2V (representing "0") pulse signals to the WBL, the selected 2T0CDRAM unit is programmed, and at the same time, the adaptive load is configured by V AL =+1.0V. (b) shows the waveform changes of V X1 and V X2 of the conventional reading circuit based on constant load (CL) at different working temperatures. At low temperature conditions (-40°C and 27°C), the current relationship of I CELL "1" >I REF >I CELL "0" is met, at this time, V X1 "0" >V X2 >V X1 "1" . The amplification effect of the latch will quickly pull V X1 to full swing to realize effective data reading. With the increase of temperature, I CELL and I REF synchronously increase to cause the voltage of X1 and X2 nodes to drop. However, due to the difference in growth rate of I CELL and I REF , at high temperature conditions (125°C), the phenomenon of V X2 <V X1 "1" occurs, at this time, V X1 is pulled to high level by mistake, which causes data reading error (see Figure 2 (b) bottom). This shows that in the CL-based reading circuit, the mismatch of I CELL and I REF will intensify with the increase of temperature, thereby reducing the reading reliability. (c) shows the waveforms of V X1 and V X2 in the reading circuit using adaptive load. It can be seen that due to the consistent temperature response characteristics of the load and the storage unit, I CELL and I REF can change synchronously with temperature. Even at high temperature conditions (125°C), V X1 "0" >V X2 >V X1 "1"The relative relationship of the data ensures the reliability of data reading.
[0019] Therefore, the application has higher reliability and higher maximum operating temperature, and meets the requirements of consumer electronics, industrial electronics and automotive electronics.
[0020] Although the application has been disclosed with the preferred embodiments as above, it is not intended to limit the application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the application, or modify equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the application, by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application, without departing from the content of the technical solutions of the application, still belongs to the protection scope of the technical solutions of the application.
Claims
1. A temperature-adaptive readout circuit for a capacitorless dynamic random access memory, wherein the memory is an array of memory cells, characterized in that, It includes an adaptive load that uses the memory cell structure as a reference resistor; the adaptive load is consistent with the memory cell in terms of process, structure and size, and has matching temperature characteristics; a sensitive amplifier is added, which is connected to the read node of the memory and the reference node of the adaptive load respectively, for detecting and amplifying the voltage difference between the two nodes, and converting the voltage difference into a digital output signal.
2. The temperature-adaptive readout circuit for a capacitorless dynamic random access memory as described in claim 1, characterized in that, The memory is an array of 2T0C DRAM memory cells, and the 2T0C DRAM memory cells are connected to a multiplexer (MUX) via an RBL.
3. The temperature-adaptive readout circuit for a capacitorless dynamic random access memory as described in claim 2, characterized in that, The sensitive amplifier includes a current mirror, a clamping transistor, and a latch. The current mirror is composed of two PMOS transistors, P1 and P2, with their gates connected. The drain of P1 is connected to storage node X1, while the drain of P2 is connected to reference node X2. One end of capacitor C1 is connected to storage node X1, and the other end is grounded. The adaptive load is connected to storage node X1 via a switch. Storage node X1 is connected to the clamping transistor. Reference node X2 is located between the adaptive load and the multiplexer. The adaptive load is connected to reference node X2 via another switch. The clamping transistor is composed of two crystals, N1 and N2, connected end-to-end. Storage node X1 and reference node X2 output data through the latch.
4. A method for operating the temperature adaptive reading circuit as described in claim 3, comprising the following steps: 1) Precharge: Transistors N1 and N2 are turned off, and storage node X1 and reference node X2 are precharged to a fixed high voltage; 2) Reference current generation: Transistors N1 and N2 are turned on, and memory node X1 and reference node X2 begin to discharge, generating I from the 2T0CDRAM cells respectively. CELL and I generated from the reference resistor REF This constitutes a voltage difference ΔV; 3) Voltage difference detection and logic reconstruction: The latch circuit converts the voltage difference ΔV into a digital "0 / 1" output.