Asynchronous step-down tube control circuit, method, asynchronous step-down circuit and switching power supply

Abstract

The application provides an asynchronous step-down lower tube control circuit, method, asynchronous step-down circuit and switching power supply. The asynchronous step-down lower tube control circuit comprises a logic control module and a charging logic module, the charging logic module is connected between the logic control module and a lower tube driving unit in an asynchronous step-down module, and the lower tube driving unit is electrically connected with a lower tube in the asynchronous step-down module. When the upper tube in the asynchronous step-down module is turned off and the voltage of a switching node is equal to the output voltage of the asynchronous step-down module, the logic control module outputs a charging enable control signal, the charging logic module decomposes the single continuous conduction time of the lower tube corresponding to the charging enable control signal into a plurality of discrete pulse signals, and the pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductor in the asynchronous step-down module to the conduction impedance of the lower tube. The problem that the prior art scheme is difficult to optimize the area of the lower tube under the premise of guaranteeing the charging amount of the bootstrap capacitor is solved.

Description

Technical Field

[0001] This application belongs to the field of switching power supply technology, and particularly relates to an asynchronous buck converter lower transistor control circuit, method, asynchronous buck converter circuit and switching power supply. Background Technology

[0002] In asynchronous buck switching power supply circuits, the reliable conduction of the upper transistor relies on the boost voltage provided by the bootstrap capacitor, and the charging of the bootstrap capacitor is typically triggered by the conduction of the lower transistor. When the upper transistor of the asynchronous buck module is turned off and the switching node voltage drops back to the output voltage, the lower transistor turns on, and the output inductor generates current to replenish the bootstrap capacitor, thus meeting the driving requirements for the subsequent conduction of the upper transistor. To ensure that the bootstrap capacitor is charged to the required level, traditional technical solutions generally adopt a single long conduction control mode for the lower transistor. However, in this mode, the effective charging time of the lower transistor is determined only by the ratio of the output inductance value to the on-resistance of the lower transistor. Once the conduction time of the lower transistor exceeds the effective charging time, the switching node voltage has already risen back to the output voltage, the inductor current returns to zero, and the subsequent conduction time is ineffective, resulting in extremely low charging efficiency. In order to accumulate sufficient effective charging time within a single long conduction cycle, traditional solutions can only be forced to increase the area of ​​the lower transistor, that is, reduce the on-resistance of the lower transistor by increasing the area, thereby extending the single effective charging time. However, increasing the area of ​​the lower transistor directly leads to a higher chip layout footprint, increasing chip manufacturing costs. Therefore, existing technologies struggle to optimize the lower transistor area while ensuring sufficient bootstrap capacitor charging. Summary of the Invention

[0003] This application provides an asynchronous buck converter lower MOSFET control circuit, method, asynchronous buck converter circuit, and switching power supply, which can solve the problem that existing technical solutions cannot optimize the lower MOSFET area while ensuring the amount of charging of the bootstrap capacitor.

[0004] In a first aspect, embodiments of this application provide an asynchronous buck converter lower MOSFET control circuit, including a logic control module and a charging logic module. The charging logic module is connected between the logic control module and the lower MOSFET driving unit in the asynchronous buck module, and the lower MOSFET driving unit is electrically connected to the lower MOSFET in the asynchronous buck module.

[0005] When the upper transistor in the asynchronous buck module is turned off and the switching node voltage is equal to the output voltage of the asynchronous buck module, the logic control module outputs a charging enable control signal. The charging logic module receives the charging enable control signal and decomposes the single continuous conduction time of the lower transistor corresponding to the charging enable control signal into multiple discrete pulse signals. The pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance of the asynchronous buck module to the conduction impedance of the lower transistor. The lower transistor driving unit drives the lower transistor to alternately turn on and off according to the multiple discrete pulse signals, so that the output inductor generates current to charge the bootstrap capacitor in the asynchronous buck module. The switching node voltage is the voltage of the common node of the upper transistor and the lower transistor.

[0006] In one possible implementation of the first aspect, the pulse width of each of the discrete pulse signals is equal.

[0007] In one possible implementation of the first aspect, each of the discrete pulse signals has the same period, and the period is greater than or equal to the sum of the pulse width of the discrete pulse signal and the down-tube turn-off recovery time.

[0008] In one possible implementation of the first aspect, the cumulative effective charging time of the bootstrap capacitor is equal to the product of the number of discrete pulse signals and the width of a single pulse.

[0009] In one possible implementation of the first aspect, the logic control module is electrically connected to the output terminals of the upper transistor, the lower transistor, and the asynchronous buck module, respectively. The logic control module includes a comparison unit and a signal output unit. The comparison unit is electrically connected to the output terminals of the signal output unit, the upper transistor, the lower transistor, and the asynchronous buck module, respectively. The signal output unit is electrically connected to the charging logic module.

[0010] The comparison unit is used to compare the switching node voltage with the output voltage, and outputs a comparison signal when the switching node voltage is equal to the output voltage. The signal output unit is used to output the charging enable control signal according to the comparison signal.

[0011] In one possible implementation of the first aspect, the charging logic module includes an enable trigger unit and a pulse output unit, wherein the enable trigger unit is electrically connected to the logic control module and the pulse output unit respectively, and the pulse output unit is electrically connected to the logic control module and the lower transistor drive unit respectively.

[0012] The enable trigger unit is used to output a trigger signal when the lower transistor corresponding to the charging enable control signal is continuously turned on for a single time. The pulse output unit is used to decompose the continuous turn-on time of the lower transistor corresponding to the charging enable control signal into multiple discrete pulse signals according to the trigger signal.

[0013] Secondly, embodiments of this application provide an asynchronous buck converter lowering MOSFET control method, applied to the asynchronous buck converter lowering MOSFET control circuit described in any one of the first aspects, the control method comprising:

[0014] The logic control module outputs a charging enable control signal when the upper transistor in the asynchronous buck module is turned off and the switching node voltage is equal to the output voltage of the asynchronous buck module; wherein, the switching node voltage is the voltage of the common node of the upper transistor and the lower transistor;

[0015] The charging logic module receives the charging enable control signal and decomposes the single continuous conduction time of the lower transistor corresponding to the charging enable control signal into multiple discrete pulse signals. The pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance in the asynchronous buck module to the conduction impedance of the lower transistor.

[0016] Thirdly, embodiments of this application provide an asynchronous buck circuit, including an asynchronous buck module and an asynchronous buck lower transistor control circuit as described in any one of the first aspects, wherein the asynchronous buck module is electrically connected to the charging logic module in the asynchronous buck lower transistor control circuit.

[0017] In one possible implementation of the third aspect, the asynchronous buck module includes an upper transistor, a lower transistor, a bootstrap capacitor, an output inductor, a freewheeling diode, a bootstrap diode, an upper transistor driving unit, and a lower transistor driving unit. The gate of the upper transistor is electrically connected to the upper transistor driving unit, and the drain of the upper transistor is used to receive the input voltage. The source of the upper transistor is electrically connected to the drain of the lower transistor, the second terminal of the bootstrap capacitor, the cathode of the freewheeling diode, and the first terminal of the output inductor. The gate of the lower transistor is electrically connected to the lower transistor driving unit. The source of the lower transistor and the anode of the freewheeling diode are both grounded. The second terminal of the output inductor serves as the output terminal of the asynchronous buck module. The first terminal of the bootstrap capacitor is electrically connected to the cathode of the bootstrap diode, and the anode of the bootstrap diode is electrically connected to the power supply.

[0018] Fourthly, embodiments of this application provide a switching power supply, including the asynchronous buck circuit described in any one of the third aspects.

[0019] The beneficial effects of the embodiments in this application compared with the prior art are:

[0020] The asynchronous buck converter lower MOSFET control circuit provided in this application includes a logic control module and a charging logic module. When the upper MOSFET in the asynchronous buck converter is turned off and the switching node voltage is equal to the output voltage of the asynchronous buck converter, it indicates that the lower MOSFET turn-on condition is met, and the bootstrap capacitor needs to be charged. At this time, the logic control module outputs a charging enable control signal. After receiving the charging enable control signal, the charging logic module decomposes the single continuous conduction time of the lower MOSFET corresponding to the charging enable control signal into multiple discrete pulse signals. Since the pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance to the conduction impedance of the lower MOSFET in the asynchronous buck converter, that is, the pulse width of a single pulse is not less than the effective charging time of a single charge. When the lower MOSFET driving unit drives the lower MOSFET to alternately turn on and off according to these discrete pulse signals, the output inductor will generate a continuous current during each lower MOSFET conduction phase, stably charging the bootstrap capacitor. More importantly, through the cyclic charging of multiple discrete pulses, the cumulative effective charging time can be superimposed. Compared to the traditional "one-time long conduction" mode that wastes a lot of invalid conduction time, this solution avoids the loss of invalid time, increases the effective charging ratio per unit of turn-on time, and greatly improves charging efficiency.

[0021] Therefore, this application, while ensuring that the bootstrap capacitor charging capacity fully meets the high-side drive requirements, overcomes the limitations of traditional solutions that "must increase the area of ​​the lower transistor to reduce on-resistance and extend the single effective charging time," allowing for a significant reduction in the layout area of ​​the lower transistor. Even if the reduced lower transistor area leads to an increase in its on-resistance, the shortened single effective charging time can be compensated for by accumulating the effective charging time through multiple pulses, eliminating concerns about insufficient charging capacity. Ultimately, this achieves the dual goals of reducing the lower transistor area, lowering chip layout occupancy and manufacturing costs, and ensuring bootstrap charging reliability, thereby improving the overall efficiency and reliability of the asynchronous buck circuit. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic block diagram of an asynchronous buck converter lower MOSFET control circuit provided in one embodiment of this application;

[0024] Figure 2 This is a waveform diagram provided in an embodiment of this application;

[0025] Figure 3 This is a block diagram of the asynchronous buck converter lower MOSFET control circuit provided in another embodiment of this application.

[0026] In the diagram, 10 is the asynchronous step-down transistor control circuit; 101 is the logic control module; 1011 is the comparator unit; 1012 is the signal output unit; 102 is the charging logic module; 1021 is the enable trigger unit; and 1022 is the pulse output unit. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0029] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0031] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0033] In asynchronous buck switching power supply circuits, the reliable conduction of the upper transistor relies on the boost voltage provided by the bootstrap capacitor, and the charging of the bootstrap capacitor is typically triggered by the conduction of the lower transistor. When the upper transistor of the asynchronous buck module is turned off and the switching node voltage drops back to the output voltage, the lower transistor turns on, and the output inductor generates current to replenish the bootstrap capacitor, thus meeting the driving requirements for the subsequent conduction of the upper transistor. To ensure that the bootstrap capacitor is charged to the required level, traditional technical solutions generally adopt a single long conduction control mode for the lower transistor. However, in this mode, the effective charging time of the lower transistor is determined only by the ratio of the output inductance value to the on-resistance of the lower transistor. Once the conduction time of the lower transistor exceeds the effective charging time, the switching node voltage has already risen back to the output voltage, the inductor current returns to zero, and the subsequent conduction time is ineffective, resulting in extremely low charging efficiency. In order to accumulate sufficient effective charging time within a single long conduction cycle, traditional solutions can only be forced to increase the area of ​​the lower transistor, that is, reduce the on-resistance of the lower transistor by increasing the area, thereby extending the single effective charging time. However, increasing the area of ​​the lower transistor directly leads to a higher chip layout footprint, increasing chip manufacturing costs. Therefore, existing technologies struggle to optimize the lower transistor area while ensuring sufficient bootstrap capacitor charging.

[0034] Based on the above problems, the asynchronous buck converter lower MOSFET control circuit provided in this application includes a logic control module and a charging logic module. When the upper MOSFET in the asynchronous buck converter is turned off and the switching node voltage is equal to the output voltage of the asynchronous buck converter, it indicates that the lower MOSFET turn-on condition is met, and the bootstrap capacitor needs to be charged. At this time, the logic control module outputs a charging enable control signal. After receiving the charging enable control signal, the charging logic module decomposes the single continuous conduction time of the lower MOSFET corresponding to the charging enable control signal into multiple discrete pulse signals. Since the pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance to the conduction impedance of the lower MOSFET in the asynchronous buck converter, that is, the pulse width of a single pulse is not less than the effective charging time of a single charge. When the lower MOSFET driving unit drives the lower MOSFET to alternately turn on and off according to these discrete pulse signals, the output inductor will generate a continuous current during each lower MOSFET conduction phase, stably charging the bootstrap capacitor. More importantly, through the cyclic charging of multiple discrete pulses, the cumulative effective charging time can be superimposed. Compared to the traditional "one-time long conduction" mode that wastes a lot of invalid conduction time, this solution avoids the loss of invalid time, increases the effective charging ratio per unit of turn-on time, and greatly improves charging efficiency.

[0035] Therefore, this application, while ensuring that the bootstrap capacitor charging capacity fully meets the high-side drive requirements, overcomes the limitations of traditional solutions that "must increase the area of ​​the lower transistor to reduce on-resistance and extend the single effective charging time," allowing for a significant reduction in the layout area of ​​the lower transistor. Even if the reduced lower transistor area leads to an increase in its on-resistance, the shortened single effective charging time can be compensated for by accumulating the effective charging time through multiple pulses, eliminating concerns about insufficient charging capacity. Ultimately, this achieves the dual goals of reducing the lower transistor area, lowering chip layout occupancy and manufacturing costs, and ensuring bootstrap charging reliability, thereby improving the overall efficiency and reliability of the asynchronous buck circuit.

[0036] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0037] Figure 1 A schematic block diagram of an asynchronous buck converter lower transistor control circuit 10 according to an embodiment of this application is shown. See also... Figure 1 As shown, the asynchronous buck converter lower MOSFET control circuit 10 includes a logic control module 101 and a charging logic module 102. The charging logic module 102 is connected between the logic control module 101 and the lower MOSFET drive unit in the asynchronous buck converter module. The lower MOSFET drive unit is electrically connected to the lower MOSFET Q2 in the asynchronous buck converter module.

[0038] Specifically, when the upper transistor Q1 in the asynchronous buck module is turned off and the switching node voltage is equal to the output voltage VOUT of the asynchronous buck module, it indicates that the turn-on condition of the lower transistor Q2 is met, and the bootstrap capacitor CBOOT needs to be started charging. At this time, the logic control module 101 outputs a charging enable control signal. After receiving the charging enable control signal, the charging logic module 102 decomposes the single continuous conduction time of the lower transistor Q2 corresponding to the charging enable control signal into multiple discrete pulse signals. Since the pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance L in the asynchronous buck module to the conduction impedance of the lower transistor Q2, that is, the pulse width of a single pulse is not less than the effective charging time of a single charge. When the lower transistor drive unit drives the lower transistor Q2 to alternately turn on and off according to these discrete pulse signals, the output inductor L will generate a continuous current during each conduction phase of the lower transistor Q2, stably charging the bootstrap capacitor CBOOT. More importantly, through the cyclic charging of multiple discrete pulses, the cumulative effective charging time can be superimposed. Compared to the traditional solution that wastes a lot of ineffective conduction time in the "lower tube Q2 long conduction" mode, this solution avoids the loss of ineffective time, increases the effective charging ratio per unit of turn-on time, and greatly improves charging efficiency.

[0039] Therefore, this application, while ensuring that the CBOOT charge of the bootstrap capacitor fully meets the high-side drive requirements, overcomes the limitation of traditional solutions that "must increase the area of ​​the lower transistor Q2 to reduce on-resistance and extend the single effective charging time," allowing for a significant reduction in the layout area of ​​the lower transistor Q2. Even if the reduced area of ​​the lower transistor Q2 leads to an increase in its on-resistance, the shortfall in the single effective charging time can be compensated for by accumulating the effective charging time through multiple pulses, eliminating concerns about insufficient charging capacity. Ultimately, this achieves the dual goals of reducing the area of ​​the lower transistor Q2, lowering chip layout occupancy and manufacturing costs, and ensuring the reliability of bootstrap charging, thereby improving the overall efficiency and reliability of the asynchronous buck circuit.

[0040] It should be noted that the asynchronous buck module includes an upper transistor Q1, a lower transistor Q2, a bootstrap capacitor CBOOT, an output inductor L, a freewheeling diode D1, a bootstrap diode D2, an upper transistor driver unit, and a lower transistor driver unit. The gate of the upper transistor Q1 is electrically connected to the upper transistor driver unit, and the drain of the upper transistor Q1 is used to receive the input voltage. The source of the upper transistor Q1 is electrically connected to the drain of the lower transistor Q2, the second terminal of the bootstrap capacitor CBOOT, the cathode of the freewheeling diode D1, and the first terminal of the output inductor L. The gate of the lower transistor Q2 is electrically connected to the lower transistor driver unit, and the source of the lower transistor Q2 and the anode of the freewheeling diode D1 are both grounded. The second terminal of the output inductor L serves as the output terminal of the asynchronous buck module. The first terminal of the bootstrap capacitor CBOOT is electrically connected to the cathode of the bootstrap diode D2, and the anode of the bootstrap diode D2 is electrically connected to the power supply VCC. In addition, the asynchronous step-down module also includes the parasitic capacitance Cpara to ground of the SW node, the output capacitor COUT, and the load RL. The parasitic capacitance Cpara is connected between the SW node and ground, and the output capacitor COUT and the load RL are both connected between the output terminal and ground.

[0041] It should be noted that in the asynchronous buck circuit of this application, the freewheeling diode D1 still serves as the main freewheeling device, undertaking the freewheeling function during normal circuit operation, consistent with the conventional topology of the asynchronous buck circuit. The lower transistor Q2 in this application is a dedicated functional device for charging the bootstrap capacitor CBOOT. During the normal operation of the asynchronous buck circuit, the lower transistor Q2 is always in the off state and does not participate in the normal voltage conversion and freewheeling process, thus avoiding any conflict with the conventional topology design. When the circuit meets the bootstrap capacitor CBOOT charging start-up conditions, by controlling the directional conduction of the lower transistor Q2, a stable and controllable charging current path is established for the bootstrap capacitor CBOOT, ensuring the charging efficiency and charging amount of the bootstrap capacitor CBOOT, thereby ensuring the reliable driving of the upper transistor Q1. Therefore, the setting of the lower transistor Q2 is solely a dedicated design for achieving efficient charging of the bootstrap capacitor CBOOT.

[0042] The following is combined with Figure 2 The waveform diagram shown provides a detailed description of the overall working process and basic principle of the asynchronous step-down circuit.

[0043] After the upper transistor Q1 is turned off, a voltage is applied to VOUT. Initially, both the upper transistor Q1 and the lower transistor Q2 are off, and the current in the output inductor L is zero. At this time, the voltage at the switching node (SW node) is consistent with the output voltage VOUT, there is no effective potential difference across the bootstrap capacitor CBOOT, and there is no charging current path; the circuit is in a balanced state. When the lower transistor Q2 is turned on, due to the lower impedance of Q2 and the inability of the current in the output inductor L to change abruptly, the SW node is quickly pulled down to ground potential. At this time, a voltage difference is formed across the output inductor L, and the current in the output inductor L gradually increases from zero, providing charge to the bootstrap capacitor CBOOT, which then enters the charging phase.

[0044] The current i of the output inductor L can be calculated using the following formula:

[0045]

[0046]

[0047] Where ton is the turn-on time of the lower transistor Q2, U(t) is the instantaneous voltage of node SW at time t, U(0) is the initial voltage, and t0 is the start time of the lower transistor Q2 conducting.

[0048] As the conduction time of the lower transistor Q2 increases, current flows through the equivalent conduction impedance of the lower transistor Q2 and the parasitic capacitance Cpara of the SW node to ground, causing the voltage of the SW node to gradually rise. Until the voltage of the SW node rises back to the output voltage VOUT, the voltage difference across the output inductor L disappears, the current of the output inductor L returns to zero, and the charging process of the bootstrap capacitor CBOOT terminates.

[0049] Approximating the inductor current linearly and neglecting the parasitic capacitance Cpara, the effective charging time is:

[0050]

[0051] Where Rdson is the on-resistance of the lower transistor Q2.

[0052] In small inductor applications, the effective charging time corresponding to the output inductor L is relatively short; and the charging frequency of the lower transistor Q2 in most traditional solutions is relatively low. In order to ensure that the bootstrap capacitor CBOOT is fully charged, the only way is to increase the layout area of ​​the lower transistor Q2 to reduce its on-resistance, thereby extending the single effective charging time and avoiding the problem of insufficient charging.

[0053] To address the aforementioned issues, this application's solution, upon detecting that the conditions for the lower transistor Q2 to turn on are met, involves the logic control module 101 and the charging logic module 102 working together to decompose the single conduction time of the lower transistor Q2 into multiple discrete pulse signals.

[0054] Taking a normal on-time of 1µs for the lower transistor Q2 as an example, if the output inductance L is 10µH and the on-resistance of the lower transistor Q2 is 100Ω, the effective charging time is:

[0055]

[0056] When the current transistor Q2 is turned on for 100ns, the voltage at node SW is equal to VOUT, the current in the output inductor L is 0, and the charging capability disappears.

[0057] In this application, the pulse width is set to Ton, and the period is Ts. After the pulse ends, the lower transistor Q2 is turned off, and the current in the output inductor L returns to zero. When the lower transistor Q2 is turned on again, a low-resistance path is re-established between the SW node and ground, and the potential of the SW node is pulled down to ground again, thus repeating the charging process. By using this multi-pulse cyclic charging method, the effective charging time is maximized, significantly improving the charging efficiency of the bootstrap capacitor CBOOT.

[0058] During this process, the effective charging time becomes: by resetting multiple discrete pulse signals.

[0059]

[0060] For any teff > ton, its charging capability can be improved.

[0061] It should be noted that the pulse width of each discrete pulse signal can be set to be equal. Specifically, setting the pulse width of each discrete pulse signal to be equal ensures that the charging process of the bootstrap capacitor CBOOT is stable and controllable. A uniform pulse width ensures that the effective charging time of the lower transistor Q2 is consistent each time, so that the current rise of the output inductor L and the charging amount of the bootstrap capacitor CBOOT remain uniform in each pulse cycle, avoiding charging current fluctuations caused by uneven pulse width. At the same time, the equal pulse width makes it easier for the charging logic module 102 to generate pulses through a standardized timing circuit, simplifying the hardware design complexity and reducing the layout area occupied by the module.

[0062] It should be noted that each discrete pulse signal has the same period, and the period is greater than or equal to the sum of the pulse width of the discrete pulse signal and the turn-off recovery time of the lower transistor Q2. Specifically, the identical period of each discrete pulse signal allows the multi-pulse charging process to form a fixed timing cycle, facilitating precise control of the charging rhythm by the charging logic module 102. The constraint that the period is greater than or equal to the sum of the pulse width and the turn-off recovery time of the lower transistor Q2 is to reserve sufficient turn-off recovery time for the lower transistor Q2. During the turn-off phase of the lower transistor Q2, the voltage at the SW node can rise back to the output voltage VOUT, the current in the output inductor L returns to zero, and the circuit returns to the equilibrium state before charging, creating conditions for effective charging for the next pulse turn-on. If the period is too short, the lower transistor Q2 will turn on again before fully recovering, resulting in the SW node voltage not rising sufficiently, compressing the effective charging time, and ultimately affecting the total charging amount of the bootstrap capacitor CBOOT.

[0063] It should be noted that, when each pulse width is equal and equal to the ratio of the output inductance L to the on-resistance of the lower transistor Q2, the cumulative effective charging time of the bootstrap capacitor CBOOT is equal to the product of the number of discrete pulse signals and the width of a single pulse. This application transforms a single long conduction into multiple short pulse conductions, and each pulse width covers the effective charging time; therefore, the cumulative effective charging time can be directly determined by the product of the number of pulses and the width of a single pulse.

[0064] For example, if the output inductance L is 10uH and the on-resistance of the lower transistor Q2 is 100Ω, the effective charging time for a single cycle can be calculated to be 100ns. This application decomposes the on-time of the lower transistor Q2 into multi-pulse control. If the width of a single pulse is set to 100ns, and it is divided into 10 discrete pulse signals, then the cumulative effective charging time of the bootstrap capacitor CBOOT is the product of the width of a single pulse and the number of pulses, thus the cumulative effective charging time can be calculated to be 100ns. 10 = 1us.

[0065] The following is combined with Figure 3 The specific implementation methods of the logic control module 101 and the charging logic module 102 are described in detail.

[0066] In one embodiment of this application, such as Figure 3 As shown, the logic control module 101 is electrically connected to the output terminals of the upper transistor Q1, the lower transistor Q2, and the asynchronous buck module, respectively. The logic control module 101 includes a comparison unit 1011 and a signal output unit 1012. The comparison unit 1011 is electrically connected to the output terminals of the signal output unit 1012, the upper transistor Q1, the lower transistor Q2, and the asynchronous buck module, respectively. The signal output unit 1012 is electrically connected to the charging logic module 102.

[0067] Specifically, the comparison unit 1011 collects the switching node voltage and the output voltage VOUT of the asynchronous buck module in real time, compares their potential magnitudes, and outputs a corresponding comparison signal when it detects that the switching node voltage and the output voltage VOUT are equal. After receiving the comparison signal, the signal output unit 1012 performs a logical judgment based on the conduction states of the upper transistor Q1 and the lower transistor Q2. Only when the charging start condition of "upper transistor Q1 is off and the switching node voltage is equal to the output voltage VOUT" is met, it outputs a valid charging enable control signal to the charging logic module 102, thereby accurately triggering the multi-pulse charging process of the bootstrap capacitor CBOOT.

[0068] It should be noted that the comparison unit 1011 includes a voltage comparator. The first input terminal of the voltage comparator is electrically connected to the upper transistor Q1 and the lower transistor Q2, respectively. The second input terminal of the voltage comparator is electrically connected to the output terminal of the asynchronous buck module, and the output terminal of the voltage comparator is electrically connected to the signal output unit 1012. When the voltage comparator detects that the switching node voltage is consistent with the output voltage VOUT, the voltage comparator immediately outputs a corresponding comparison signal to the signal output unit 1012. This signal serves as the basis for determining the trigger charging enable control signal, ensuring the accuracy of the bootstrap capacitor CBOOT charging start timing.

[0069] In one embodiment of this application, such as Figure 3 As shown, the charging logic module 102 includes an enable trigger unit 1021 and a pulse output unit 1022. The enable trigger unit 1021 is electrically connected to the logic control module 101 and the pulse output unit 1022, respectively. The pulse output unit 1022 is electrically connected to the logic control module 101 and the lower transistor drive unit, respectively.

[0070] Specifically, the enable trigger unit 1021 receives the charging enable control signal output by the logic control module 101, and outputs a stable trigger signal during the single continuous conduction period of the lower transistor Q2 corresponding to the signal; the pulse output unit 1022 decomposes the single continuous conduction time of the lower transistor Q2 into multiple discrete pulse signals (each discrete pulse signal has the same period and the same pulse width) based on the trigger signal, and outputs these pulse signals to the lower transistor drive unit, thereby realizing the multi-pulse alternating conduction and turn-off control of the lower transistor Q2.

[0071] It should be noted that the enable trigger unit 1021 includes a trigger, which is electrically connected to the logic control module 101 and the pulse output unit 1022. When a valid charging enable control signal is received, the trigger immediately outputs a high-level trigger signal to the pulse output unit 1022, ensuring that the pulse output unit 1022 starts the multi-pulse generation process in a timely manner. Before the charging enable control signal fails, the trigger can maintain a stable output of the trigger signal, avoiding interruption of the pulse generation process due to signal fluctuations, thereby ensuring the continuity and reliability of the multi-pulse charging sequence.

[0072] Furthermore, the pulse output unit 1022 can be composed of a monostable multivibrator, a binary counter, a ring oscillator, and a signal buffer. The monostable multivibrator is used to generate discrete pulse signals with a fixed width. Its output pulse width can be precisely configured through an external RC circuit to meet the design requirement that "the pulse width is greater than or equal to the ratio of the output inductance L to the on-resistance of the lower transistor Q2". The ring oscillator provides a stable clock signal for the entire unit to control the output period of adjacent pulses, ensuring that the periods of multiple discrete pulse signals remain consistent. The binary counter is used to count the output pulse signals. When the number of pulses reaches a preset threshold, the counter outputs a reset signal to terminate pulse generation. The signal buffer is responsible for shaping and amplifying the generated pulse signal, so that the output pulse signal can accurately drive the lower transistor drive unit to realize the alternating on and off of the lower transistor Q2.

[0073] It should be noted that the logic control module 101 is also used to receive the conduction status feedback signal of the upper transistor Q1. When the upper transistor Q1 is on, the output of the charging enable control signal is prohibited. This design can effectively avoid circuit failures and energy losses caused by the accidental triggering of the lower transistor Q2 to charge during the conduction phase of the upper transistor Q1. When the upper transistor Q1 is on, the switching node voltage will rise synchronously with the input voltage. If the lower transistor Q2 is triggered to turn on at this time, it will directly cause a shoot-through short circuit between the upper transistor Q1 and the lower transistor Q2, resulting in a large current surge and damage to the power devices. At the same time, by receiving the conduction status feedback signal of the upper transistor Q1 and prohibiting the output of the charging enable control signal, the logic control module 101 can accurately avoid the above risks, ensuring that the charging enable control signal is only output under the condition that the upper transistor Q1 is off and the switching node voltage is equal to the output voltage VOUT. This ensures that the timing of the bootstrap capacitor CBOOT charging process is completely matched with the working sequence of the asynchronous buck circuit, improving the overall working stability and reliability of the circuit.

[0074] Furthermore, the logic control module 101 can also detect the initial current of the output inductor L. Only when the initial current of the output inductor L is 0 will it output a charging enable control signal. This design ensures that the charging process of the bootstrap capacitor CBOOT always starts within the effective charging range, avoiding problems such as charging timing disorder and compressed effective charging time caused by the initial current in the output inductor L. When the output inductor L has an initial current, the switching node voltage cannot stably drop back to the state equal to the output voltage VOUT. If the lower transistor Q2 is turned on for charging at this time, not only will a stable charging current path not be formed, but voltage spikes may also be caused by sudden changes in the inductor current, affecting the stability of the circuit operation. By detecting the critical condition that the initial current of the output inductor L is 0, and then outputting the charging enable control signal, it can be ensured that the circuit is in a balanced initial state each time charging starts. After the lower transistor Q2 is turned on, the switching node voltage can be reliably pulled down, and the output inductor L can establish a stable charging current from zero, maximizing the effective charging ratio of a single pulse and further improving charging efficiency and the controllability of the charging process.

[0075] This application also discloses an asynchronous buck converter control method, including steps S101 to S102.

[0076] In step S101, the logic control module 101 outputs a charging enable control signal when the upper transistor Q1 in the asynchronous buck module is turned off and the switching node voltage is equal to the output voltage VOUT of the asynchronous buck module; wherein, the switching node voltage is the voltage of the common node of the upper transistor Q1 and the lower transistor Q2.

[0077] Specifically, the logic control module 101 comprehensively detects the on / off state of the upper transistor Q1, the switching node voltage, and the output voltage VOUT of the asynchronous buck module. This allows for precise capture of the circuit's real-time operating status, providing a reliable basis for the subsequent output of the charging enable control signal. This avoids false triggering due to incomplete state detection and ensures that the subsequent control process only begins when charging conditions are met, guaranteeing the accuracy and safety of the entire lower transistor Q2 control strategy. When the upper transistor Q1 is detected to be off and the switching node voltage equals the output voltage VOUT, a charging enable control signal is output. This precisely locks the optimal charging time for the bootstrap capacitor CBOOT, avoiding the risk of a shoot-through short circuit caused by the upper transistor Q1 triggering the lower transistor Q2's conduction, and ensuring that the switching node is in a stable balanced state, effectively improving the controllability and reliability of the charging process.

[0078] In step S102, the charging logic module 102 receives the charging enable control signal and decomposes the single continuous conduction time of the lower transistor Q2 corresponding to the charging enable control signal into multiple discrete pulse signals. The pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance L in the asynchronous buck module to the conduction impedance of the lower transistor Q2.

[0079] Specifically, the charging logic module 102 decomposes the single continuous conduction time of the lower transistor Q2 into multiple discrete pulse signals, maximizing the effective charging time of a single conduction and avoiding the invalid time loss in the traditional long conduction mode, thus significantly improving charging efficiency. At the same time, by decomposing the single continuous conduction time of the lower transistor Q2, there is no need to rely on increasing the area of ​​the lower transistor Q2 to extend the effective charging time, thereby optimizing the area of ​​the lower transistor Q2 and reducing chip cost.

[0080] This application also discloses an asynchronous buck converter circuit, including an asynchronous buck module and the aforementioned asynchronous buck lower MOSFET control circuit 10. The asynchronous buck module is electrically connected to the charging logic module 102 in the asynchronous buck lower MOSFET control circuit 10. The asynchronous buck converter circuit, using the aforementioned control circuit, can precisely control the charging timing of the bootstrap capacitor CBOOT. By splitting the conduction time using multiple pulses, it maximizes the effective charging ratio. While ensuring that the charging amount of the bootstrap capacitor CBOOT meets the driving requirements of the upper MOSFET Q1, it significantly optimizes the layout area of ​​the lower MOSFET Q2, reducing the overall chip size and manufacturing cost.

[0081] This application also discloses a switching power supply, including the aforementioned asynchronous buck circuit. By integrating the aforementioned asynchronous buck circuit, the switching power supply can achieve miniaturization, lightweighting, and low-cost production of the power module by leveraging its efficient charging control strategy and simplified device area design. At the same time, it improves the power supply's energy conversion efficiency and long-term operational reliability, giving it stronger application advantages and market competitiveness in fields with stringent requirements for power supply size and energy efficiency, such as consumer electronics, industrial control, and new energy.

[0082] Since the processing and functions implemented by the asynchronous buck circuit and switching power supply in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned asynchronous buck lower transistor control circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0083] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An asynchronous buck converter lower transistor control circuit, characterized in that, The system includes a logic control module and a charging logic module. The charging logic module is connected between the logic control module and the lower transistor drive unit in the asynchronous buck module. The lower transistor drive unit is electrically connected to the lower transistor in the asynchronous buck module. The asynchronous buck module includes a bootstrap capacitor, an output inductor, a freewheeling diode, and a bootstrap diode. The first terminal of the bootstrap capacitor is electrically connected to the cathode of the bootstrap diode. The second terminal of the bootstrap capacitor is electrically connected to the drain of the lower transistor, the cathode of the freewheeling diode, and the first terminal of the output inductor. The anode of the bootstrap diode is electrically connected to the power supply. The anode of the freewheeling diode is grounded. The second terminal of the output inductor serves as the output terminal of the asynchronous buck module. When the upper transistor in the asynchronous buck module is turned off and the switching node voltage is equal to the output voltage of the asynchronous buck module, the logic control module outputs a charging enable control signal. The charging logic module receives the charging enable control signal and decomposes the single continuous conduction time of the lower transistor corresponding to the charging enable control signal into multiple discrete pulse signals. The pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance of the asynchronous buck module to the conduction impedance of the lower transistor. The lower transistor driving unit drives the lower transistor to alternately turn on and off according to the multiple discrete pulse signals, so that the output inductor generates current to charge the bootstrap capacitor in the asynchronous buck module. The switching node voltage is the voltage of the common node of the upper transistor and the lower transistor.

2. The asynchronous buck converter lower transistor control circuit according to claim 1, characterized in that, Each of the discrete pulse signals has the same pulse width.

3. The asynchronous buck converter lower transistor control circuit according to claim 2, characterized in that, Each of the discrete pulse signals has the same period, and the period is greater than or equal to the sum of the pulse width of the discrete pulse signal and the down-tube turn-off recovery time.

4. The asynchronous buck converter lower transistor control circuit according to claim 3, characterized in that, The cumulative effective charging time of the bootstrap capacitor is equal to the product of the number of discrete pulse signals and the width of a single pulse.

5. The asynchronous buck converter lower transistor control circuit according to claim 1, characterized in that, The logic control module is electrically connected to the output terminals of the upper transistor, the lower transistor, and the asynchronous buck module, respectively. The logic control module includes a comparison unit and a signal output unit. The comparison unit is electrically connected to the output terminals of the signal output unit, the upper transistor, the lower transistor, and the asynchronous buck module, respectively. The signal output unit is electrically connected to the charging logic module. The comparison unit is used to compare the switching node voltage with the output voltage, and outputs a comparison signal when the switching node voltage is equal to the output voltage. The signal output unit is used to output the charging enable control signal according to the comparison signal.

6. The asynchronous buck converter lower transistor control circuit according to claim 1, characterized in that, The charging logic module includes an enable trigger unit and a pulse output unit. The enable trigger unit is electrically connected to the logic control module and the pulse output unit, respectively. The pulse output unit is electrically connected to the logic control module and the lower transistor drive unit, respectively. The enable trigger unit is used to output a trigger signal when the lower transistor corresponding to the charging enable control signal is continuously turned on for a single time. The pulse output unit is used to decompose the continuous turn-on time of the lower transistor corresponding to the charging enable control signal into multiple discrete pulse signals according to the trigger signal.

7. An asynchronous buck converter lower MOSFET control method, applied to the asynchronous buck converter lower MOSFET control circuit according to any one of claims 1-6, characterized in that, The control method includes: The logic control module outputs a charging enable control signal when the upper transistor in the asynchronous buck module is turned off and the switching node voltage is equal to the output voltage of the asynchronous buck module; wherein, the switching node voltage is the voltage of the common node of the upper transistor and the lower transistor; The charging logic module receives the charging enable control signal and decomposes the single continuous conduction time of the lower transistor corresponding to the charging enable control signal into multiple discrete pulse signals. The pulse width of each discrete pulse signal is greater than or equal to the ratio of the output inductance in the asynchronous buck module to the conduction impedance of the lower transistor.

8. An asynchronous step-down circuit, characterized in that, It includes an asynchronous buck module and an asynchronous buck lower transistor control circuit as described in any one of claims 1-6, wherein the asynchronous buck module is electrically connected to the charging logic module in the asynchronous buck lower transistor control circuit.

9. The asynchronous step-down circuit according to claim 8, characterized in that, The asynchronous buck module includes an upper transistor, a lower transistor, a bootstrap capacitor, an output inductor, a freewheeling diode, a bootstrap diode, an upper transistor driver unit, and a lower transistor driver unit. The gate of the upper transistor is electrically connected to the upper transistor driver unit, and the drain of the upper transistor is used to receive the input voltage. The source of the upper transistor is electrically connected to the drain of the lower transistor, the second terminal of the bootstrap capacitor, the cathode of the freewheeling diode, and the first terminal of the output inductor. The gate of the lower transistor is electrically connected to the lower transistor driver unit. The source of the lower transistor and the anode of the freewheeling diode are both grounded. The second terminal of the output inductor serves as the output terminal of the asynchronous buck module. The first terminal of the bootstrap capacitor is electrically connected to the cathode of the bootstrap diode, and the anode of the bootstrap diode is electrically connected to the power supply.

10. A switching power supply, characterized in that, Includes the asynchronous buck circuit as described in any one of claims 8-9.

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