De-noising circuit, signal processing method and device, server, medium and product

Abstract

This application discloses a denoising circuit, signal processing method, device, server, medium, and product, relating to the field of server technology. Through the hierarchical and coordinated denoising circuit of this application, pulse width discrimination and pulse continuity discrimination processing can be performed sequentially on the heat dissipation signal, taking into account both denoising effect and signal fidelity, thereby improving the accuracy of signal processing.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to noise reduction circuits, signal processing methods, devices, servers, media and products. Background Technology

[0002] In communications and industrial settings, edge servers, as core devices for data processing and real-time response, are widely used in complex environments such as industrial sites, roadside base stations, water conservancy facilities, and electrical systems. These complex environments pose challenges to the stable operation of these servers.

[0003] In related technologies, a denoised signal is obtained by performing a single denoising process on the server's signal, and the server's operating status is determined based on the denoised signal. However, this method suffers from low accuracy. Summary of the Invention

[0004] This application provides noise reduction circuits, signal processing methods, apparatus, servers, media, and products to at least address the problem of low signal processing accuracy in related technologies.

[0005] This application provides a denoising circuit, including: an edge stabilization circuit, a pulse width detection circuit, and a pulse continuity discrimination circuit. The edge stabilization circuit is connected to the pulse width detection circuit and the pulse continuity discrimination circuit. The edge stabilization circuit receives the original heat dissipation signal and performs edge stabilization processing on the original heat dissipation signal using a high-level threshold and a low-level threshold to obtain a shaped signal. The pulse width detection circuit is connected to the edge stabilization circuit and performs pulse width detection processing on the shaped signal according to a preset pulse window to obtain a preliminary denoised signal. The pulse widths in the preliminary denoised signal are all greater than or equal to the preset pulse window. The pulse continuity discrimination circuit performs pulse continuity discrimination analysis on the preliminary denoised signal to identify isolated noise pulses in the shaped signal and removes isolated noise pulses from the shaped signal to obtain the target denoised signal.

[0006] This application also provides a signal processing method applied to a denoising circuit, comprising: receiving an original heat dissipation signal; performing edge stabilization processing on the original heat dissipation signal using a high-level threshold and a low-level threshold of an edge stabilization circuit to obtain a shaped signal; performing pulse width detection processing on the shaped signal using a pulse width detection circuit according to a preset pulse window to obtain a preliminary denoised signal, wherein the width of the pulses in the preliminary denoised signal is greater than or equal to the preset pulse window; performing pulse continuity discrimination analysis on the preliminary denoised signal using a pulse continuity discrimination circuit to determine isolated noise pulses in the preliminary denoised signal, and removing isolated noise pulses from the preliminary denoised signal to obtain a target denoised signal.

[0007] This application also provides a signal processing apparatus for use in a denoising circuit, comprising: a receiving module for receiving an original heat dissipation signal and performing edge stabilization processing on the original heat dissipation signal using a high-level threshold and a low-level threshold of an edge stabilization circuit to obtain a shaped signal; a filtering module for performing pulse width detection processing on the shaped signal according to a preset pulse window using a pulse width detection circuit to obtain a preliminary denoised signal, wherein the width of the pulses in the preliminary denoised signal is greater than or equal to the preset pulse window; and a discrimination module for performing pulse continuity discrimination analysis on the preliminary denoised signal using a pulse continuity discrimination circuit to determine isolated noise pulses in the preliminary denoised signal and remove isolated noise pulses from the preliminary denoised signal to obtain a target denoised signal.

[0008] This application also provides a server that includes any of the noise reduction circuits described above.

[0009] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described signal processing methods.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described signal processing methods.

[0011] The hierarchical collaborative denoising circuit of this application can sequentially perform pulse width verification and pulse continuity discrimination processing on the heat dissipation signal, taking into account both denoising effect and signal fidelity, thereby improving the accuracy of signal processing. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram illustrating an application scenario of a signal processing method provided in an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of a noise reduction circuit provided in an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of another noise reduction circuit provided in an embodiment of this application;

[0016] Figure 4 This is a schematic diagram of another noise reduction circuit provided in an embodiment of this application;

[0017] Figure 5 A schematic flowchart of a signal processing method provided in an embodiment of this application;

[0018] Figure 6 A schematic flowchart illustrating another signal processing method provided in an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of the structure of a signal processing device provided in an embodiment of this application;

[0020] Figure 8 This is a schematic diagram of another signal processing device provided in an embodiment of this application;

[0021] Figure 9 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] For example, an edge server (hereinafter referred to as a server) is a dedicated computing device deployed in physical proximity to the data source to provide real-time data processing, storage, and application services locally at the data source. By having servers handle localized computing and storage, latency and bandwidth consumption during data transmission to the cloud can be reduced, thus meeting the real-time requirements of business operations.

[0025] However, the complex and harsh environment in which servers are deployed poses significant challenges to their stable operation and heat dissipation control. Therefore, it is necessary to monitor the server's operational status and perform timely maintenance.

[0026] Among these, server heat dissipation signals, such as fan speed signals, directly reflect the operating status of the server's cooling system. The accuracy of these heat dissipation signals directly affects the server's thermal management and fault early warning capabilities.

[0027] With the aid of scenario examples, it is clear that in complex environments, heat dissipation signals are highly susceptible to interference. On the one hand, power supply noise, electromagnetic radiation from nearby circuits, or mechanical vibrations can introduce high-frequency glitches (such as nanosecond-level narrow pulses) into the signal. On the other hand, impedance mismatches, poor connector contact, or aging issues in the signal transmission path can cause ringing or multiple logic threshold crossings (i.e., non-monotonic edge jitter) on the edges of the square wave signal. These interferences may be misinterpreted as actual speed changes, causing the server's Baseboard Management Controller (BMC) to obtain incorrect heat dissipation data, which in turn can trigger malfunctions in the heat dissipation system (such as abnormal fan stoppage or excessive fan startup), potentially leading to server hardware damage or data processing interruption. Therefore, in the complex operating environment of servers, achieving efficient noise reduction of heat dissipation signals and ensuring their stability and real-time performance is crucial for ensuring reliable server operation.

[0028] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] The specific application environment architecture upon which the noise reduction circuitry depends is described here. (References) Figure 1 , Figure 1 The server includes a cooling system to maintain its operating temperature within a standard range. The cooling system generates real-time cooling signals which are sent to the BMC (Battery Management Center), which then adjusts the cooling strategy or issues an alarm to ensure the server functions correctly.

[0030] In related technologies, resistor-capacitor filters are used to denoise the heat dissipation signal in order to suppress high-frequency noise. However, resistor-capacitor filters cannot simultaneously and effectively suppress both high-frequency narrow-pulse glitches (nanosecond level) and wide-pulse isolated noise (microsecond to millisecond level), resulting in low signal processing accuracy. Low signal processing accuracy may lead to misjudgment by the BMC, causing server hardware damage or data processing interruption.

[0031] Figure 2 This is a schematic diagram of a noise reduction circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, it includes: an edge stabilization circuit, a pulse width detection circuit, and a pulse continuity discrimination circuit, wherein,

[0032] The edge stabilization circuit is connected to the pulse width detection circuit and the pulse continuity discrimination circuit. The edge stabilization circuit is used to receive the original heat dissipation signal and perform edge stabilization processing on the original heat dissipation signal through the high-level threshold and low-level threshold of the edge stabilization circuit to obtain the shaped signal.

[0033] The pulse width detection circuit is connected to the edge stabilization circuit. The first timer is used to perform pulse width detection processing on the shaped signal according to the preset pulse window to obtain a preliminary denoised signal. The pulse width in the preliminary denoised signal is greater than or equal to the preset pulse window.

[0034] The pulse continuity discrimination circuit is used to perform pulse continuity discrimination analysis on the preliminary denoised signal, identify isolated noise pulses in the shaped signal, and remove isolated noise pulses from the shaped signal to obtain the target denoised signal.

[0035] Examples of edge-stabilizing circuits include, but are not limited to, Schmitt triggers. A Schmitt trigger is a voltage comparator with hysteresis characteristics. A Schmitt trigger has two different threshold voltages: a higher rising threshold and a lower falling threshold. It can convert slowly changing, noisy, or ringing raw thermal signals into well-shaped signals with sharp edges.

[0036] For example, the edge stabilization circuit solves the edge quality problem of the original heat dissipation signal, providing a high-quality signal basis for the subsequent noise reduction circuit.

[0037] For example, a pulse width discrimination circuit filters out high-frequency narrow glitches, thereby solving the problem of high-frequency narrow pulse interference.

[0038] For example, the pulse continuity discrimination circuit accurately identifies and eliminates isolated noise pulses through decision-making, solving the problem of wide-pulse isolated noise. Through hierarchical collaborative denoising circuits, the complex denoising task can be decomposed, thereby achieving full coverage processing of composite noise.

[0039] Optionally, the denoising circuit is configured to process multiple independent heat dissipation signal channels in parallel. Each channel includes an edge stabilization circuit, a pulse width detection circuit, and a pulse continuity discrimination circuit. Multiple independent heat dissipation signal channels allow for parallel denoising of multiple heat dissipation signals, thereby improving signal processing efficiency.

[0040] Based on the above implementation method, the complex denoising task is decomposed into three optimized dedicated circuits, which respectively solve the three types of interference problems: edge jitter, high-frequency narrow pulse, and wide pulse isolated noise, thereby improving the accuracy of signal processing.

[0041] A feasible implementation method Figure 3 This is a schematic diagram of another noise reduction circuit provided in an embodiment of this application, as shown below. Figure 3 As shown, the pulse width modulation (PWM) detection circuit includes a first timer and a storage circuit; wherein,

[0042] The first timer is connected to the clock input of the edge stabilization circuit and the storage circuit. The first timer is used to output a pulse signal according to the edge change of the shaped signal.

[0043] The edge stabilization circuit is connected to the data input terminal of the storage circuit. The storage circuit is used to read the level state of the edge stabilization circuit through the data input terminal when the clock input terminal receives a rising edge pulse signal.

[0044] The storage circuit is also used to output and latch the level state through the output terminal of the storage circuit until the next rising edge to generate a preliminary denoising signal.

[0045] For example, the first timer includes, but is not limited to, a monostable multivibrator. A monostable multivibrator has a stable state (e.g., low level), enters a temporary quasi-stable state (e.g., high level) after being triggered, and automatically returns to the stable state after a fixed period of time.

[0046] Specifically, the first timer receives the edges (rising or falling) of the shaping signal. Each time an edge is received, the first timer generates a pulse. The width (duration) of this pulse is precisely set by external resistors and capacitors (e.g., 200 nanoseconds), and this width is the preset pulse window. The generated preset pulse window is used to determine whether a pulse in the shaping signal is a valid signal or an invalid signal with "narrow glitches."

[0047] For example, the storage circuit includes, but is not limited to, a D flip-flop. A D flip-flop is a clock-controlled 1-bit memory that selectively samples and holds a pulse signal at a specific time.

[0048] Specifically, the storage circuit determines the sampling time based on the pulse signal output by the first timer, samples the shaped signal at the sampling time, and holds the sample. The sampling result serves as the target denoised signal for output.

[0049] For example, the storage circuit includes two inputs: a clock input and a data input. These two inputs separate the decision process from the data sampling process. Data sampling occurs when the decision condition is met. No data sampling occurs when the decision condition is not met, thus achieving noise filtering.

[0050] Please refer to the following examples and scenarios. Figure 3The data input of the storage circuit is connected to the shaped signal with defined edges, while the clock input is connected to a pulse signal. The storage circuit operates by sampling and latching the data input level only at the rising edge of the pulse signal and outputting it to the output terminal Q. During the ineffective edge of the pulse signal, the output terminal Q remains latched at the previous effective clock edge, unaffected by changes in the data input. If a glitch is narrower than a preset value (e.g., 200ns), it will disappear before the next pulse signal arrives to sample and latch it. Therefore, the storage circuit cannot latch this brief glitch, and it will not be passed to the output terminal Q. Only when the level change of the shaped signal is stable and continues until the pulse signal samples it will this change be considered a valid edge and reflected in the output terminal Q of the storage circuit. Finally, a clean, denoised signal containing only valid edges is obtained, with all useless narrow glitches eliminated.

[0051] In this feasible implementation, by setting the first timer and the storage circuit to work together, the denoising task can be decomposed, taking into account both the denoising effect and the signal fidelity, thereby improving the accuracy of signal processing.

[0052] A feasible implementation method Figure 4 This is a schematic diagram of another noise reduction circuit provided in the embodiments of this application, such as... Figure 4 As shown, the noise reduction circuit also includes a second timer, logic gate circuits, and a delay circuit; among which,

[0053] The input of the second timer is connected to the output of the storage circuit. The second timer is used to generate a status signal in response to the edge change of the preliminary noise reduction signal and send the status signal to the logic gate circuit. The status signal is either an active level or an inactive level.

[0054] The input of the delay circuit is connected to the output of the storage circuit. The delay circuit is used to add a delay duration to the initial denoised signal.

[0055] The logic gate circuit is used to determine that the current preliminary denoising signal is an isolated noise pulse in response to the state signal being invalid, and to block the current preliminary denoising signal until the state signal is valid, so as to output the target denoising signal.

[0056] For example, the second timer includes, but is not limited to, a retriggerable monostable multivibrator. The retriggerable monostable multivibrator generates a single pulse that can be repeatedly triggered. When the retriggerable monostable multivibrator receives a pulse edge (such as a rising edge), it is triggered, the output becomes active (such as high), and internal timing begins. If a new pulse edge is received before the timeout period ends, the timer is reset, starting from zero again, and the output remains active, thus exhibiting the retriggerable characteristic. If no new pulse edge is received after the timeout period ends, the output returns to an inactive level.

[0057] For example, the delay circuit of this application can be composed of delay logic gates and analog delay lines. The delay circuit is used to delay the arrival of the preliminary denoising signal at the logic gate circuit by a fixed propagation delay duration. In this way, before isolated noise pulses in the preliminary denoising signal reach the logic gate circuit, the logic gate has already received an invalid level, thus effectively intercepting and eliminating isolated noise pulses.

[0058] For example, the logic gate circuit in this application is an AND gate circuit. The output circuit is only valid when both inputs of the AND gate circuit are simultaneously at a valid level (e.g., high level). If any one input is at an invalid level (low level), the output circuit is invalid.

[0059] Specifically, the logic gate has two inputs: a delayed preliminary denoised signal and a status signal for decision-making. Based on the status signal, the logic gate determines whether the delayed preliminary denoised signal is valid and whether it should pass through. Only when the status signal is at a valid level can the delayed preliminary denoised signal received by the logic gate pass through, thus filtering isolated noise pulses.

[0060] In this feasible implementation, a delayed decision mechanism is used to ensure that the decision logic takes precedence over signal transmission, thereby achieving the synergy between lossless transmission of effective signals and physical interception of noise, while avoiding the latency problem of software algorithms.

[0061] Figure 5 This is a schematic flowchart of the signal processing method provided in the embodiments of this application, as shown below. Figure 5 As shown, embodiments of this application provide a signal processing method, which is described in detail below:

[0062] S501 receives the original heat dissipation signal and performs edge stabilization processing on the original heat dissipation signal through the high-level threshold and low-level threshold of the edge stabilization circuit to obtain the shaped signal.

[0063] For example, the original heat dissipation signal may experience edge jitter or ringing during transmission due to electromagnetic interference or other reasons. By using an edge stabilization circuit with hysteresis characteristics, the original heat dissipation signal can be shaped by setting a high-level threshold and a low-level threshold (i.e., hysteresis voltage).

[0064] Optionally, when the original heat dissipation signal voltage exceeds the high threshold, the output is high; when the original heat dissipation signal voltage is below the low threshold, the output is low; for voltage jitter between the two thresholds, the output remains unchanged. This process shapes a signal with ambiguous edges into a square wave signal with steep edges, i.e., a shaped signal, thereby avoiding interference from edge jitter or ringing phenomena on the analysis of the working status of the heat dissipation equipment.

[0065] S502. According to the preset pulse window, the shaped signal is processed by the pulse width detection circuit to obtain a preliminary denoised signal. The width of the pulses in the preliminary denoised signal is greater than or equal to the preset pulse window.

[0066] For example, the shaped signal may be subject to high-frequency narrow pulse interference. These high-frequency narrow pulses have extremely narrow widths (e.g., on the nanosecond scale), but their amplitudes may reach logic levels, making them easily misinterpreted as valid signals. Based on a preset pulse window, a pulse width detection circuit is used to detect the pulse width in order to identify the high-frequency narrow pulses.

[0067] Specifically, a pulse with a preset pulse window is triggered by a shaping signal. This pulse acts as a clock command, controlling a storage circuit to sample the shaped signal at the end of the pulse. Only when the pulse duration is longer than the preset pulse window will its level be latched and output by the storage circuit. Narrow pulses with durations shorter than the window are discarded because they cannot maintain a stable level at the sampling time, thus obtaining the initial denoised signal.

[0068] S503. The pulse continuity discrimination circuit performs pulse continuity discrimination analysis on the preliminary denoised signal to determine the isolated noise pulses in the preliminary denoised signal, and removes the isolated noise pulses from the preliminary denoised signal to obtain the target denoised signal.

[0069] For example, isolated noise pulses have a similar width to the valid signal, but they are isolated and lack periodicity. Isolated noise pulses are identified and eliminated by analyzing the continuity of the pulse flow.

[0070] Specifically, the pulse continuity discrimination circuit determines whether the pulses of the preliminary denoising signal are continuous based on a preset continuous duration threshold. Only continuous pulses are allowed to pass through, while non-continuous pulses are blocked, thereby eliminating isolated noise pulses.

[0071] The signal processing method provided in this application optimizes the processing of noise with different characteristics, thereby achieving a full-coverage denoising effect on composite noise that cannot be achieved by existing single technical means, and improving the accuracy of signal processing.

[0072] Based on any of the above embodiments, the following, in conjunction with Figure 6 The detailed process of signal processing is explained.

[0073] Figure 6 This is a schematic flowchart illustrating another signal processing method provided in an embodiment of this application. Figure 6 As shown, the method includes:

[0074] S601 receives the original heat dissipation signal and performs edge stabilization processing on the original heat dissipation signal through the high-level threshold and low-level threshold of the edge stabilization circuit to obtain the shaped signal.

[0075] One feasible implementation method for edge stabilization includes: performing a first-stage filter on the original heat dissipation signal to attenuate high-frequency noise, resulting in a first filtered signal; performing a second-stage filter on the first filtered signal to smooth the signal edges, resulting in a second filtered signal; if the level of the second filtered signal exceeds a high-level threshold from low to high, a high-level signal is output through the edge stabilization circuit; if the level of the second filtered signal exceeds a low-level threshold from high to low, a low-level signal is output through the edge stabilization circuit; if the level of the second filtered signal fluctuates between the high-level and low-level thresholds, the output of the edge stabilization circuit is maintained; and the output of the edge stabilization circuit is determined as a shaped signal.

[0076] For example, preprocessing with two stages of pre-filtering can improve the success rate of edge-stabilized processing.

[0077] Optionally, the ringing amplitude of high-frequency interference noise may exceed the suppression range of the edge stabilization circuit, causing edge stabilization processing to fail. By setting a higher cutoff frequency to coarsely filter the original heat dissipation signal, the high-amplitude high-frequency interference noise can be suppressed, thereby improving the success rate of edge stabilization processing.

[0078] Alternatively, a second-stage filtering process can be performed using a filter with steeper characteristics, such as a second-order Butterworth low-pass filter. This balances the filter cutoff frequency between suppressing ringing and preserving the main characteristics of the signal, making the rising and falling edges of the first-filtered signal smoother and reducing ringing.

[0079] For example, the edge stabilization circuit determines whether the second filtered signal is a rising edge or a falling edge based on the high-level threshold and the low-level threshold.

[0080] Optionally, when the level of the second filtered signal rises from low to high, it is only recognized as a valid rising edge and the output jumps to a high level when the level exceeds the higher high-level threshold. Jitter on the rising edge will not cause false triggering as long as its amplitude does not fall below the low-level threshold.

[0081] Optionally, when the level of the second filtered signal decreases from high to low, it is only recognized as a valid falling edge when the level is lower than the lower low-level threshold, and the output jumps to a low level. For jitter on the falling edge, as long as its amplitude does not exceed the high-level threshold, it will not cause false triggering.

[0082] Optionally, as long as the level of the second filtered signal is between the high-level threshold and the low-level threshold, the output remains unchanged, meaning that the tiny ringing and jitter on the signal edge that are in the hysteresis voltage region will be completely ignored.

[0083] With the help of scenario examples, the hysteresis voltage mechanism ensures that a valid edge change produces only one definite output transition, providing a high-quality signal foundation for subsequent processing.

[0084] In this feasible implementation, after two stages of pre-filtering, the ringing amplitude of the original heat dissipation signal edge is weakened, thereby more effectively traversing the hysteresis voltage range and improving the accuracy of signal processing.

[0085] S602. The edge change of the shaping signal is identified by the first timer, and a pulse signal is generated according to the edge change. The width of the pulse signal is equal to the width of the preset pulse window.

[0086] For example, the first timer triggers when it detects a voltage jump in the shaping signal, generating a pulse signal. This converts the signal edges in the shaping signal into standardized pulse signals with a width equal to a preset pulse window, enabling accurate subsequent decision-making.

[0087] One feasible implementation method is to determine the preset pulse window by: determining multiple historical pulse widths corresponding to multiple historical noise pulse samples; determining the statistical results of multiple historical pulse widths; determining the rated operating conditions of the target heat dissipation equipment corresponding to the original heat dissipation signal; calculating the standard signal pulse width under the rated operating conditions; and determining that the preset pulse window is larger than the statistical results and smaller than the standard signal pulse width.

[0088] For example, in a typical server operating environment, multiple historical noise pulse samples are acquired. The statistical results of the multiple historical pulse widths corresponding to these samples can represent the widest high-frequency narrow pulse noise that may occur under the current environment. The high-frequency narrow pulse noise that exceeds this widest width is the noise that needs to be filtered.

[0089] For example, the standard signal pulse width is the effective signal generated by the heat dissipation device during normal operation. To avoid the effective signal being filtered, the preset pulse window is set to be smaller than the standard signal pulse width.

[0090] Optionally, taking a fan as an example of a heat dissipation device, the rated operating condition can be the rated speed. The standard signal pulse width determined under the rated operating condition conforms to the standard operating state of the heat dissipation device.

[0091] Optionally, the statistical result can be the maximum value or a quantile (e.g., the 99th quantile).

[0092] In this feasible implementation, the preset pulse window is determined according to the operating conditions of the heat dissipation equipment, avoiding the blind setting of parameters and achieving a balance between noise reduction effect and signal fidelity, thereby improving the accuracy of signal processing.

[0093] S603. When the clock input terminal of the storage circuit receives a rising edge of the pulse signal output by the first timer, the storage circuit reads the level state of the shaping signal received at the data input terminal of the storage circuit.

[0094] For example, the storage circuit reads data only when the pulse signal is a rising edge. The rising edge corresponds to the end time of the fixed-width pulse output by the first timer.

[0095] For example, a pulse signal is used as the decision criterion for data reading. The pulse signal determines whether data should be read at the current moment, thereby enabling intermittent data reading from the shaped signal. The intermittently read data are all valid pulses, and their duration is greater than or equal to the preset pulse window. This ensures that all retained pulses meet the minimum width requirement, while narrowband interference pulses with a duration shorter than the preset pulse window are discarded because they cannot maintain a valid level at the sampling time.

[0096] S604. The level state is output to the output terminal of the storage circuit and latched until the next rising edge to generate a preliminary noise reduction signal.

[0097] For example, once the storage circuit samples and outputs at the rising edge of the clock, the output level of the storage circuit will remain stable regardless of changes in the level of the data input until the next rising edge of the clock arrives, thus achieving latching. The latching characteristic of the storage circuit ensures the stability and purity of the output signal, physically removing all noise spikes shorter than the preset pulse window, generating a high-quality preliminary denoised signal.

[0098] S605: In response to the edge change of the preliminary denoised signal, a status signal is generated through the second timer and sent to the logic gate circuit. The status signal is either an active level or an inactive level.

[0099] For example, the second timer starts working when the edge of the preliminary denoising signal is detected, and the second timer outputs a status signal based on the continuity of the pulse.

[0100] For example, the logic for generating the status signal using the second timer is as follows: If the pulses are continuous, the edge of each new pulse will re-trigger the timer before the timer triggered by the previous pulse expires, keeping the second timer output at a high level. This high level is the valid status signal. If a pulse is isolated (i.e., the next pulse does not arrive in time), the second timer will not be re-triggered after the timer expires, and its output will fall back to a low level. This low level is the invalid status signal.

[0101] S606. In response to the status signal being invalid, the current preliminary denoising signal output by the delay circuit is determined to be an isolated noise pulse, and the current preliminary denoising signal is blocked by the logic gate circuit until the status signal is valid.

[0102] For example, logic gates use state signals as the basis for blocking signals. If a logic gate currently receives an invalid state signal, it will block the signal, meaning that the initial denoising signal transmitted to the logic gate cannot pass through the logic gate and will be eliminated.

[0103] Conversely, if the logic gate currently receives a valid level status signal, it will not block the signal. This allows the initial denoised signal to pass intermittently through the logic gate.

[0104] S607 outputs the target noise-reducing signal through logic gate circuits.

[0105] For example, the denoised signal through logic gate circuits is a continuous and valid target pulse sequence, in which all isolated noise pulses have been physically intercepted, and finally a clean and continuous target denoised signal is output, ensuring the accuracy of the analysis of the working status of the heat dissipation equipment.

[0106] One feasible implementation involves generating a status signal via a second timer in response to an edge change in the initial denoised signal. This includes: determining the current pulse period and a preset ratio of the initial denoised signal; determining a current decision window based on the current pulse period and the preset ratio; determining the status signal as valid if an edge change in the initial denoised signal is detected by the second timer within the decision window; and determining the status signal as invalid if no edge change in the initial denoised signal is detected by the second timer after the decision window has expired.

[0107] For example, in practical applications, the operating conditions of heat dissipation equipment are variable, and the current pulse cycle is used to adaptively handle the variable operating conditions.

[0108] For example, the denoising circuit continuously monitors the pulse period of the initial denoised signal, and this period value directly reflects the real-time operating condition of the heat dissipation device. By multiplying the pulse period by a preset scaling factor, the most suitable decision window is dynamically generated. This product relationship ensures that the decision window always maintains a reasonable proportional relationship with the signal period.

[0109] For example, at the implementation level, the timeout duration of the second timer is configured as a dynamically calculated decision window. When pulses are continuous, each newly arriving pulse will re-trigger the second timer within the decision window, keeping its output valid. Once an isolated pulse occurs, due to the lack of re-triggering by subsequent pulses, the second timer will output an invalid level after the decision window expires, thus indicating an interruption of the pulse.

[0110] This feasible implementation addresses the fundamental shortcomings of the fixed-window scheme under varying operating conditions. When the cooling device reduces its frequency, causing the pulse period to lengthen, the dynamic decision window extends synchronously, preventing normal low-speed pulses from being misjudged as noise. Conversely, when the cooling device's frequency increase period shortens, the window automatically shrinks, preventing the omission of isolated interference at high speeds. This adaptive characteristic ensures the accuracy of noise reduction.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0112] Figure 7 This is a schematic diagram of the signal processing device provided in an embodiment of this application. Figure 7 As shown, embodiments of this application also provide a signal processing device 70, which may include a receiving module 71, a filtering module 72, and a discrimination module 73.

[0113] The receiving module 71 is used to receive the original heat dissipation signal and perform edge stabilization processing on the original heat dissipation signal through the high-level threshold and low-level threshold of the edge stabilization circuit to obtain the shaped signal.

[0114] The filtering module 72 is used to perform pulse width verification processing on the shaped signal according to the preset pulse window through the pulse width verification circuit to obtain a preliminary denoised signal. The pulse width in the preliminary denoised signal is greater than or equal to the preset pulse window.

[0115] The discrimination module 73 is used to perform pulse continuity discrimination analysis on the preliminary denoised signal through the pulse continuity discrimination circuit, identify isolated noise pulses in the preliminary denoised signal, and remove isolated noise pulses from the preliminary denoised signal to obtain the target denoised signal.

[0116] Optionally, the receiving module 71 can perform... Figure 5 S501 in the embodiment.

[0117] Optionally, the filtering module 72 can be executed. Figure 5 S502 in the embodiment.

[0118] Optionally, the discrimination module 73 can execute... Figure 5 S503 in the embodiment.

[0119] It should be noted that the signal processing device shown in the embodiments of this application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, so they will not be described again here.

[0120] In one possible implementation, the filtering module 72 is specifically used for:

[0121] The first timer identifies the edge changes of the shaping signal and generates a pulse signal based on the edge changes. The width of the pulse signal is equal to the width of the preset pulse window.

[0122] When the clock input terminal of the storage circuit receives a rising edge of the pulse signal output by the first timer, the storage circuit reads the level state of the shaped signal received at the data input terminal of the storage circuit.

[0123] The level state is output to the output terminal of the storage circuit and latched until the next rising edge to generate a preliminary noise reduction signal.

[0124] In one possible implementation, the discrimination module 73 is specifically used for:

[0125] In response to the edge change of the initial denoised signal, a status signal is generated by the second timer and sent to the logic gate circuit. The status signal is either an active level or an inactive level.

[0126] In response to the status signal being invalid, the current preliminary denoising signal output by the delay circuit is determined to be an isolated noise pulse, and the current preliminary denoising signal is blocked by a logic gate circuit until the status signal is valid.

[0127] The target denoised signal is output through logic gate circuits.

[0128] In one possible implementation, the discrimination module 73 is specifically used for:

[0129] Determine the current pulse period and preset ratio of the initial denoised signal;

[0130] The current decision window is determined based on the current pulse period and the preset ratio;

[0131] If a change in the edge of the preliminary denoised signal is detected by the second timer within the decision window, the status signal is determined to be at a valid level.

[0132] If the edge change of the preliminary denoised signal is not detected by the second timer after the decision window has expired, the status signal is determined to be invalid.

[0133] Figure 8 This is a schematic diagram of another signal processing device provided in an embodiment of this application. Figure 7 Based on the illustrated embodiments, as Figure 8 As shown, the signal processing device 70 also includes a filtering module 74 and an adjustment module 75.

[0134] Filter module 74 is used for:

[0135] The original heat dissipation signal is subjected to a first-stage filter to attenuate high-frequency noise, resulting in a first-filtered signal.

[0136] The first filtered signal is subjected to a second-stage filtering process to smooth the signal edges, resulting in the second filtered signal.

[0137] If the level of the second filtered signal exceeds the high-level threshold as it rises from low to high, a high level is output through the edge stabilization circuit.

[0138] If the level of the second filtered signal exceeds the low-level threshold from high to low, a low level is output through the edge stabilization circuit.

[0139] If the level of the second filtered signal jitters between the high-level threshold and the low-level threshold, the output of the edge-stabilized circuit is maintained.

[0140] The output of the edge-stabilizing circuit is determined as a shaping signal.

[0141] Adjustment module 75 is used for:

[0142] Determine the widths of multiple historical pulses corresponding to multiple historical noise pulse samples;

[0143] Determine the statistical results of multiple historical pulse widths;

[0144] Determine the rated operating conditions of the target heat dissipation equipment corresponding to the original heat dissipation signal;

[0145] Calculate the standard signal pulse width under rated operating conditions;

[0146] The preset pulse window is determined to be larger than the statistical result and smaller than the standard signal pulse width.

[0147] For a description of the features in the embodiment corresponding to the signal processing device, please refer to the relevant description in the embodiment corresponding to the signal processing method, which will not be repeated here.

[0148] Figure 9 This is a schematic diagram of the server structure provided in this application. Figure 9 As shown, the server 90 provided in this embodiment includes at least one noise reduction circuit 901 and a memory 902. Optionally, the server 90 further includes a communication component 903. The noise reduction circuit 901, the memory 902, and the communication component 903 are connected via a bus.

[0149] In the specific implementation process, at least one noise reduction circuit 901 executes the computer execution instructions stored in the memory 902, causing at least one noise reduction circuit 901 to execute the above-described signal processing method embodiment.

[0150] The specific implementation process of the noise reduction circuit 901 can be found in the above method embodiment. Its implementation principle and technical effect are similar, and will not be repeated here.

[0151] In the above embodiments, it should be understood that the denoising circuit can be a central processing unit (CPU), or other general-purpose denoising circuits, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose denoising circuit can be a micro-denoising circuit, or any conventional denoising circuit. The steps of the method disclosed in the application can be directly manifested as the hardware denoising circuit performing the execution, or the combination of hardware and software modules in the denoising circuit performing the execution.

[0152] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0153] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0154] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described signal processing method embodiments when it is run.

[0155] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0156] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described signal processing method embodiments.

[0157] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described signal processing method embodiments.

[0158] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0159] The above provides a detailed description of the noise reduction circuit, signal processing method, apparatus, server, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A noise reduction circuit, characterized in that, include: The circuit includes an edge stabilization circuit, a pulse width detection circuit, and a pulse continuity determination circuit. The edge stabilization circuit is connected to the pulse width detection circuit and the pulse continuity discrimination circuit. The edge stabilization circuit is used to receive the original heat dissipation signal and perform edge stabilization processing on the original heat dissipation signal through the high-level threshold and low-level threshold of the edge stabilization circuit to obtain a shaped signal. The pulse width detection circuit is connected to the edge stabilization circuit. The pulse width detection circuit is used to perform pulse width detection processing on the shaped signal according to the preset pulse window to obtain a preliminary denoised signal. The width of the pulses in the preliminary denoised signal is greater than or equal to the preset pulse window. The pulse continuity discrimination circuit is used to perform pulse continuity discrimination analysis on the preliminary denoised signal, identify isolated noise pulses in the shaped signal, and remove the isolated noise pulses from the shaped signal to obtain the target denoised signal; The pulse width detection circuit includes: a first timer and a storage circuit; The first timer is connected to the clock input of the edge stabilization circuit and the storage circuit, and the first timer is used to output a pulse signal according to the edge change of the shaped signal; The edge stabilization circuit is connected to the data input terminal of the storage circuit. The storage circuit is used to read the level state of the edge stabilization circuit through the data input terminal when the clock input terminal receives the pulse signal as a rising edge. The storage circuit is also used to output the level state through the output terminal of the storage circuit and latch it until the next rising edge to generate the preliminary denoising signal. The pulse continuity discrimination circuit includes: a second timer, a logic gate circuit, and a delay circuit; The input of the second timer is connected to the output of the storage circuit. The second timer is used to generate a status signal in response to the edge change of the preliminary denoising signal and send the status signal to the logic gate circuit. The status signal is an active level or an inactive level. The input terminal of the delay circuit is connected to the output terminal of the storage circuit, and the delay circuit is used to add a delay duration to the preliminary denoising signal; The logic gate circuit is used to determine that the current preliminary denoising signal is an isolated noise pulse in response to the state signal being invalid, and to block the current preliminary denoising signal until the state signal is valid, so as to output the target denoising signal.

2. A signal processing method, characterized in that, The method is applied to the noise reduction circuit of claim 1; the method includes: The original heat dissipation signal is received, and edge stabilization processing is performed on the original heat dissipation signal through the high-level threshold and low-level threshold of the edge stabilization circuit to obtain the shaped signal. According to the preset pulse window, the shaped signal is subjected to pulse width detection processing by the pulse width detection circuit to obtain a preliminary denoised signal. The pulse width in the preliminary denoised signal is greater than or equal to the preset pulse window. The preliminary denoised signal is analyzed by pulse continuity discrimination circuit to identify isolated noise pulses in the preliminary denoised signal, and the isolated noise pulses are removed from the preliminary denoised signal to obtain the target denoised signal.

3. The signal processing method according to claim 2, characterized in that, The pulse width modulation (PWM) processing of the shaped signal includes: The edge changes of the shaping signal are identified by a first timer, and a pulse signal is generated based on the edge changes. The width of the pulse signal is equal to the width of the preset pulse window. When the clock input terminal of the storage circuit receives the rising edge of the pulse signal output by the first timer, the storage circuit reads the level state of the shaped signal received at the data input terminal of the storage circuit. The level state is output to the output terminal of the storage circuit and latched until the next rising edge to generate the preliminary denoising signal.

4. The signal processing method according to claim 2, characterized in that, The preliminary denoised signal is analyzed by pulse continuity discrimination circuit to identify isolated noise pulses in the preliminary denoised signal, and the isolated noise pulses are removed from the preliminary denoised signal to obtain the target denoised signal, including: In response to the edge change of the preliminary denoised signal, a status signal is generated by a second timer and sent to the logic gate circuit. The status signal is either an active level or an inactive level. In response to the status signal being invalid, the current preliminary denoising signal output by the delay circuit is determined to be an isolated noise pulse, and the current preliminary denoising signal is blocked by the logic gate circuit until the status signal is valid. The target denoised signal is output through the logic gate circuit.

5. The signal processing method according to claim 4, characterized in that, In response to edge changes in the initial denoised signal, a status signal is generated via a second timer, including: Determine the current pulse period and preset ratio of the preliminary denoised signal; The current decision window is determined based on the current pulse period and the preset ratio; If a change in the edge of the preliminary denoised signal is detected by the second timer within the decision window, the state signal is determined to be at a valid level. If the edge change of the preliminary denoised signal is not detected by the second timer after the decision window has expired, the status signal is determined to be invalid.

6. The signal processing method according to claim 2, characterized in that, The original heat dissipation signal is edge-stabilized using a high-level and low-level threshold circuit to obtain a shaped signal, including: The original heat dissipation signal is subjected to a first-stage filter to attenuate high-frequency noise, resulting in a first-filtered signal. The first filtered signal is subjected to a second-stage filtering to smooth the signal edges, resulting in a second filtered signal. If the level of the second filtered signal exceeds the high-level threshold as it rises from low to high, a high level is output through the edge stabilization circuit. If the level of the second filtered signal exceeds the low level threshold from high to low, a low level is output through the edge stabilization circuit. If the level of the second filtered signal jitters between the high-level threshold and the low-level threshold, the output of the edge stabilization circuit is maintained. The output of the edge stabilization circuit is determined as the shaping signal.

7. The signal processing method according to claim 2, characterized in that, The process of setting the preset pulse window includes: Determine the widths of multiple historical pulses corresponding to multiple historical noise pulse samples; Determine the statistical results of the widths of the multiple historical pulses; Determine the rated operating conditions of the target heat dissipation device corresponding to the original heat dissipation signal; Calculate the standard signal pulse width under the rated operating conditions; The preset pulse window is determined to be larger than the statistical result and smaller than the standard signal pulse width.

8. A server, characterized in that, include: The noise reduction circuit according to claim 1.

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