Field programmable gate array (FPGA)-based spread spectrum signal acquisition frequency correction method, device and equipment
By using an FPGA-based spread spectrum signal acquisition frequency correction method, the problem of inaccurate Doppler values during satellite signal acquisition was solved. Through filtering, quantization, and peak analysis, the accuracy and acquisition time of satellite signal acquisition were optimized.
Patent Information
- Application Number
- CN202511753620.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-02-27
AI Technical Summary
As the satellite telemetry and control information rate increases, the ratio of the information bit period to the spreading code sequence period is no longer an integer multiple, resulting in inaccurate Doppler values during acquisition, severe spectrum leakage, and affecting the accuracy of satellite signals.
A frequency correction method for spread spectrum signal acquisition based on FPGA is adopted. After multiplying the sampled data with the local intermediate frequency carrier, the data is filtered and quantized. Frequency domain interference is removed by using FFT and IFFT transforms. Combined with partial matched filter and BRAM storage, code phase search and peak analysis are performed to achieve frequency correction.
It improves the frequency accuracy of satellite signal acquisition, reduces the impact of narrowband interference on acquisition peaks, reduces data readout time overhead, and provides a smooth transition from acquisition to tracking.
Smart Images
Figure CN121585199A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of correcting satellite receiving signals, and particularly relates to an FPGA-based spread spectrum signal acquisition frequency correction method, device and equipment. BACKGROUND
[0002] With the gradual increase of satellite measurement and control information rate, the ratio of information bit period to spread spectrum code sequence period is no longer an integer multiple, and the ratio is getting smaller and smaller. When the information is spread spectrum modulated, when the information bit rate is small, an integer period of spread spectrum code sequence can be contained in one bit, and when the information bit rate is large, the integer period of spread spectrum code sequence will be flipped by the information bit to produce spectrum leakage, so that the Doppler value acquired during acquisition is inaccurate. SUMMARY
[0003] Therefore, it is necessary to provide an FPGA-based spread spectrum signal acquisition frequency correction method, device and equipment capable of improving the accuracy of receiver acquisition of satellite signal frequency in view of the above technical problems.
[0004] An FPGA-based spread spectrum signal acquisition frequency correction method, the method comprising: After multiplying the sampling data with the local intermediate frequency carrier, 0 intermediate frequency I / Q data is obtained.
[0005] After filtering the 0 intermediate frequency I / Q data, the data is decimated to an integer multiple of the spread spectrum code rate, so as to perform bit width quantization on the filtered 0 intermediate frequency I / Q data, and perform FFT transformation, assign and cut off the spectrum components exceeding the threshold in the frequency domain, and then perform IFFT transformation on the frequency domain data to obtain time domain I / Q data.
[0006] According to the correlation points of the partial matching filter, the serial time domain I / Q data and the spread spectrum code sequence generated in units of code phase search accuracy and according to the number of correlation points are stored in the BRAM as a group to obtain a plurality of signal search pairs.
[0007] The I / Q data in the BRAM is searched for all code phases in steps of code phase search accuracy, and a partial matching filtering operation is performed according to the signal search pairs to obtain an operation result.
[0008] The output operation result is subjected to FFT transformation processing, the FFT transformation result of the frequency point corresponding to each code phase is analyzed, the maximum peak value and the second maximum peak value are identified, and the frequency point indexes corresponding to the two peak values are recorded, until the complete search is completed, and a search result is obtained.
[0009] The maximum peak value in the search result is compared with a preset acquisition threshold to complete the correction of the acquisition frequency.
[0010] A spread spectrum signal capture frequency correction device based on FPGA, the device comprises: A digital down conversion module is used to multiply the sampling data with a local intermediate frequency carrier to obtain I / Q data of 0 intermediate frequency.
[0011] A filtering and quantization module is used to filter the I / Q data of 0 intermediate frequency, extract the data to an integer multiple of the spread spectrum code rate, perform bit width quantization on the filtered I / Q data of 0 intermediate frequency, perform FFT transform, assign and cut off the spectrum components exceeding the threshold in the frequency domain, perform IFFT transform on the frequency domain data, and obtain time domain I / Q data.
[0012] A serial-to-parallel storage module is used to store the serial time domain I / Q data and the spread spectrum code sequence generated in units of code phase search accuracy and according to the number of correlation points as a group in the BRAM according to the correlation points of the partial matching filter, and obtain a plurality of signal search pairs.
[0013] A PMF module is used to search all code phases of the I / Q data in the BRAM in steps of code phase search accuracy, perform partial matching filtering operation according to the signal search pairs, and obtain operation results.
[0014] A search and analysis module is used to perform FFT transform processing on the output operation results, analyze the frequency domain transform results corresponding to each code phase, identify the maximum peak value and the second maximum peak value, and record the frequency point indexes corresponding to the two peak values, until the entire search is completed, and obtain a search result.
[0015] A frequency correction module is used to compare the maximum peak value in the search result with a preset capture threshold, and complete the correction of the capture frequency.
[0016] A computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program: The sampling data is multiplied with a local intermediate frequency carrier to obtain I / Q data of 0 intermediate frequency.
[0017] The I / Q data of 0 intermediate frequency is filtered, the data is extracted to an integer multiple of the spread spectrum code rate, the filtered I / Q data of 0 intermediate frequency is bit width quantized, FFT transform is performed, spectrum components exceeding the threshold in the frequency domain are assigned and cut off, IFFT transform is performed on the frequency domain data, and time domain I / Q data is obtained.
[0018] The serial time domain I / Q data and the spread spectrum code sequence generated in units of code phase search accuracy and according to the number of correlation points are stored as a group in the BRAM according to the correlation points of the partial matching filter, and a plurality of signal search pairs are obtained.
[0019] All code phase searches are performed on the I / Q data in the BRAM with code phase search precision as a step, and a partial match filtering operation is performed on the signal search to obtain an operation result.
[0020] An FFT transform process is performed on the output operation result, and the FFT frequency domain transform result corresponding to each code phase is analyzed to identify the maximum peak value and the second maximum peak value, and the frequency point indexes corresponding to the two peak values are recorded, until the entire search is completed, and a search result is obtained.
[0021] The maximum peak value in the search result is compared with a preset capture threshold to complete the correction of the capture frequency.
[0022] The above-mentioned FPGA-based spread spectrum signal capture frequency correction method, device and equipment, in the data preprocessing stage, the I / Q data after filtering is extracted to an integer multiple of the spread spectrum code rate, the frequency domain out-of-range value interference is cut off through the FFT transform, the influence of the narrowband interference signal on the capture peak value is reduced, and purer time domain data is provided for subsequent processing. In the storage link, the signal search pairs are configured according to the partial match filter correlation points, the alignment of the spread spectrum code sequence and the I / Q data in phase is ensured, the data reading time overhead caused by the mismatch of the number of storage points is reduced, and the capture time is reduced. In the core processing, the partial match filtering is performed with the code phase search precision step, the parallel calculation of the I / Q data with multiple correlation points is realized through the parallel computing capability of the FPGA, and the pipeline search is performed by utilizing the phase continuity of the I / Q data and the integer multiple relationship of the spread spectrum code rate. After the FFT transform, the maximum / second maximum peak value and the frequency point index corresponding to each code phase are identified, and the interference of the information bit jump on the single peak value is offset through the joint analysis of multiple peak values. In the final frequency correction link, the systematic deviation positively related to the information bit rate is directly weakened based on the median calculation mechanism of the double peak value index. When the information bit rate increases, the complementary characteristics of the double peak values offset each other in the median operation, significantly reducing the frequency offset of the traditional single peak value decision, and providing a key guarantee for the smooth transition of the receiver from capture to tracking. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 A flowchart of the FPGA-based spread spectrum signal capture frequency correction method in one embodiment; Figure 2 A flowchart of the receiver data preprocessing in one embodiment; Figure 3 A flowchart of the frequency offset correction PMF_FFT capture algorithm of one phase search in one embodiment; Figure 4 A flowchart of the phase control in one embodiment; Figure 5 A structural block diagram of the FPGA-based spread spectrum signal capture frequency correction device in one embodiment; Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0025] In one embodiment, such as Figure 1 As shown, an FPGA-based spread spectrum signal acquisition frequency correction method is provided, including the following steps: Step 102: Multiply the sampled data with the local intermediate frequency carrier to obtain the I / Q data of the 0 intermediate frequency.
[0026] Step 104: After filtering, the I / Q data of 0 IF is decimated to an integer multiple of the spreading code rate so that the filtered 0 IF I / Q data is bit-width quantized and FFT transformed. Spectral components in the frequency domain that exceed the threshold are assigned values and removed. Then, IFFT transform is performed on the frequency domain data to obtain the time domain I / Q data.
[0027] Step 106: Based on the correlation points of the partially matched filter, the serial time-domain I / Q data and the spreading code sequence generated according to the number of correlation points and in units of code phase search accuracy are stored in the BRAM as a group to obtain several groups of signal search pairs.
[0028] Step 108: Search all code phases of the I / Q data in the BRAM with the code phase search accuracy as the step, and perform partial matched filtering operation based on the signal search to obtain the operation result.
[0029] Step 110: Perform FFT transformation on the output operation results, analyze the frequency domain transformation results of the FFT corresponding to each code phase, identify the maximum peak and the second largest peak, and record the frequency index corresponding to the two peaks respectively, until the search is completed and the search results are obtained.
[0030] Step 112: Compare the maximum peak value in the search results with the preset capture threshold to complete the correction of the capture frequency.
[0031] In the above-mentioned FPGA-based spread spectrum signal capture frequency correction method, in the data preprocessing stage, the 0 intermediate frequency I / Q data is filtered and extracted to an integer multiple of the spread spectrum code rate, the out-of-range interference in the frequency domain is cut off through FFT transformation, the influence of narrowband interference signals on the capture peak is reduced, and purer time domain data is provided for subsequent processing. In the storage stage, the signal search pairs are configured according to the correlation points of the partial matched filter, ensuring the alignment of the spread spectrum code sequence and the data in phase, reducing the data reading time overhead caused by the mismatch of the number of storage points, and reducing the capture time. In the core processing, the partial matched filtering is performed with code phase search precision steps, the parallel calculation of multiple correlation point I / Q data is realized through the parallel computing capability of FPGA, and the pipeline search is performed by utilizing the phase continuity of I / Q data and the integer multiple relationship of the spread spectrum code rate. After the FFT transformation, the maximum / second maximum peak value and the frequency point index of each code phase are identified, and the interference of information bit transition on a single peak value is offset through the joint analysis of multiple peak values. In the final frequency correction stage, the systematic deviation positively related to the information bit rate is directly weakened based on the median calculation mechanism of the double peak value index. When the information bit rate increases, the complementary characteristics of the double peak values offset each other in the median operation, significantly reducing the frequency offset of the traditional single peak value decision, and providing a key guarantee for the smooth transition of the receiver from capture to tracking.
[0032] In one of the embodiments, after the 0 intermediate frequency I / Q data is filtered, the data is extracted to an integer multiple of the spread spectrum code rate, the filtered 0 intermediate frequency I / Q data is quantized in bit width, the I / Q data with a large bit width is quantized to I / Q data with a small bit width, and the FFT transformation is performed, the energy of each point in the frequency domain is counted, the average power value is obtained, the threshold value obtained by multiplying the average power value by a preset power coefficient is assigned to cut off the frequency domain, and then the IFFT transformation is performed on the frequency domain data to obtain the time domain I / Q data.
[0033] In one of the embodiments, the serial time domain I / Q data and the spread spectrum code sequence generated in code phase search precision units and according to the number of correlation points are stored in the BRAM as a group, the depth of code phase storage is equal to the code length divided by the code phase search precision, and a plurality of signal search pairs are obtained. The signal search pair includes the time domain I / Q data and the spread spectrum code sequence with the same number of correlation points.
[0034] In one of the embodiments, the sampling rate of the sampling data is equal to the chip rate of the pseudo code.
[0035] In one of the embodiments, the I / Q data in the BRAM is searched for all code phases with code phase search precision steps, the partial matched filtering operation is performed according to the signal search pair, the sum of the correlation values of each chip and the corresponding points of the time domain I / Q data is calculated, and the operation result is obtained.
[0036] wherein, is the operation result of the partial matched filter, is the local pseudo code, is the pseudo code of the time domain I / Q data with code phase difference is the Doppler frequency offset of the received signal, is the carrier phase difference value between the local intermediate frequency carrier and the carrier of the received signal. In one embodiment, the output operation result is subjected to FFT transform processing to obtain the capture result of the frequency point data corresponding to the initial code phase as the address. The capture result of the frequency point corresponding to each code phase is analyzed, the maximum peak value and the second maximum peak value of the capture result of all frequency point data corresponding to the initial phase are counted, and the frequency point indexes corresponding to the two peak values are recorded. Taking a group of signal search results of the maximum peak value in the capture result as the search result of the phase search.
[0037] In one embodiment, the maximum peak value of the search result is compared with the capture threshold value. If the maximum peak value is greater than the capture threshold value, the capture is successful; otherwise, the capture fails and the capture is restarted. The frequency point indexes corresponding to the maximum peak value and the second maximum peak value of the threshold value decision are subjected to capture frequency correction to obtain the final capture frequency value:
[0038]
[0039] wherein, is the corrected capture frequency, is equal to the sampling rate after I / Q data extraction, is the frequency point index corresponding to the maximum peak value, is the frequency point index corresponding to the second maximum peak value, N is the number of FFT points, and M is the number of correlation points of the partial matched filter.
[0040] In one embodiment, as shown in FIG. 1, a receiver data preprocessing flow is provided. The purpose of data preprocessing is to transform the intermediate frequency signal to a 0 intermediate frequency signal more suitable for capture and eliminate the influence of narrowband interference on capture. The specific flow is as follows: Figure 2 Direct capture of the intermediate frequency signal requires a larger frequency capture range and a longer capture time. Therefore, the received sampling data is multiplied by the local intermediate frequency carrier to obtain the 0 intermediate frequency I / Q data. The purpose of filtering and extraction is to reduce the sampling rate so that the capture operation is an integer multiple of the pseudo code rate.
[0041]
[0042] In order to make the subsequent capture process more convenient, the non-integer multiple difference problem of the sampling rate and the spread spectrum code rate is solved, and the received sampling data is directly extracted to an integer multiple of the spread spectrum code rate, usually 2, 4 times (the multiple value is equal to the inverse of the capture code interval, 2 for half-chip phase search accuracy, and 4 for 1 / 4-chip search accuracy). Therefore, the received signal needs to be filtered to prevent spectral aliasing, and then the data is extracted to an integer multiple of the spread spectrum code rate.
[0043] If the extraction is not an integer multiple of the spread spectrum code rate here, one sampling point does not correspond to one spread spectrum chip during subsequent capture, and the subsequent operation of aligning the chip and sampling point phase will be more troublesome.
[0044] Quantization refers to quantizing I / Q data of a large bit width to I / Q data of a small bit width.
[0045] The BRAM resources required for subsequent data storage are reduced, and the BRAM resources of 4-bit width can be reduced by more than 40% through analysis. At the same time, the resources required for the calculation process of the quantized data will also be less, and it has been verified that quantization has no effect on the capture performance.
[0046] When the information rate is large, the spread spectrum ratio (the ratio of the spread spectrum pseudo-code rate to the information rate) will also be reduced, and its anti-narrow-band interference ability will also be reduced, so it is necessary to eliminate the interference signal during capture to obtain better capture performance. The process is as follows: 1) First, perform FFT transformation on the quantized I / Q data to transform the signal from the time domain to the frequency domain; 2) Calculate the energy of each point in the frequency domain to obtain an average power value, which is continuously updated to smooth the average power value; 3) Assign a value to cut off the values in the frequency domain that exceed the average power value*power coefficient (the cutting method is to assign a value of 0 or the average power value); 4) Then perform IFFT transformation on the frequency domain data to obtain time domain I / Q data.
[0047] The IFFT data can be used for capture after preprocessing.
[0048] In one embodiment, as shown in Figure 3 A PMF_FFT capture algorithm flow of one phase search is provided, and PMF_FFT belongs to parallel frequency and serial code phase capture, so when a section of I / Q data is stored for capture, all phases need to be searched step by step with chip phase search accuracy as the step in code phase. Each phase search needs to perform one FFT calculation. The specific process is as follows: 1. Store the serial I / Q data every M (partial matched filter correlation point number) points in BRAM as a group until N (FFT point number) groups are stored.
[0049] 2. The spread spectrum code sequence generated in units of code phase search accuracy is also stored in BRAM in groups of M (the number of relevant points of the partially matched filter). The depth of code phase storage is equal to the code length divided by the chip phase search accuracy.
[0050] In one embodiment, such as Figure 4 As shown, a phase control flow is provided, wherein the sampling rate of I / Q data is an integer multiple of the spreading code rate. The main purpose of this operation is to ensure the continuity of phase during calculation by maintaining the continuity of I / Q and pseudo-code data acquisition after the rates of the two are matched. The calculation clock can use a clock frequency much higher than the sampling clock, reducing time overhead. The PMF operation only calculates the sum of the cross-correlation values of the M chips and I / Q data points. The result of the m-th partially matched filter can be expressed as:
[0051] in, This is local pseudocode. For code phase difference The pseudocode of I / Q data, To account for the Doppler frequency offset of the received signal, This represents the phase difference between the local intermediate frequency carrier and the received signal carrier.
[0052] After the calculation results of N PMFs are output, an N*M point data acquisition result with phase i as the initial address can be obtained by performing an N-point FFT. The maximum and second-largest peaks in the N-point FFT results of the initial phase i are statistically analyzed, and their frequency indices are recorded. and Take the largest value among all K phase FFT results as the final result of the phase search. Compare this maximum peak with the capture threshold. If it is greater than the set capture threshold, the capture is considered successful; otherwise, the capture fails and the process restarts.
[0053] The capture frequency is corrected by using the frequency indexes of the largest and second largest peaks determined by the threshold decision, resulting in the final capture frequency value.
[0054] The corrected frequency value is equal to the median of the largest and second largest peaks, as shown below:
[0055] in It equals the sampling rate after I / Q data extraction.
[0056] It should be understood that, although Figures 1-4The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0057] In one embodiment, such as Figure 5 As shown, an FPGA-based spread spectrum signal acquisition frequency correction device is provided, comprising: a digital down-conversion module 502, a filtering and quantization module 504, a serial-to-parallel conversion and storage module 506, a PMF module 508, a search and analysis module 510, and a frequency correction module 512, wherein: The digital downconversion module 502 is used to multiply the sampled data with the local intermediate frequency carrier to obtain I / Q data at 0 intermediate frequency.
[0058] The filtering and quantization module 504 is used to filter the I / Q data at 0 IF, extract the data to an integer multiple of the spreading code rate, so as to perform bit-width quantization on the filtered 0 IF I / Q data, perform FFT transformation, assign values to cut off the spectral components in the frequency domain that exceed the threshold, and then perform IFFT transformation on the frequency domain data to obtain the time domain I / Q data.
[0059] The serial-to-parallel storage module 506 is used to store serial time-domain I / Q data and a spreading code sequence generated according to the number of correlation points in the code phase search unit into the BRAM as a group, so as to obtain several groups of signal search pairs.
[0060] The PMF module 508 is used to search for all code phases of the I / Q data in the BRAM in increments of code phase search accuracy, and to perform partial matched filtering based on the signal search to obtain the operation result.
[0061] The search and analysis module 510 is used to perform FFT transformation on the output operation results, analyze the frequency domain transformation results of the FFT corresponding to each code phase, identify the maximum peak and the second largest peak, and record the frequency index corresponding to the two peaks respectively, until the search results are obtained after all searches are completed.
[0062] The frequency correction module 512 is used to compare the maximum peak value in the search results with the preset capture threshold to correct the capture frequency.
[0063] The specific limitations of the FPGA-based spread spectrum signal capture frequency correction device can refer to the limitations of the FPGA-based spread spectrum signal capture frequency correction method described above, which will not be repeated here. Each module in the FPGA-based spread spectrum signal capture frequency correction device described above can be implemented by software, hardware, and combinations thereof, in whole or in part. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0064] In one embodiment, a computer device, which can be a terminal, has an internal structure diagram as shown in Figure 6 The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is used to communicate with external terminals through network connections. The computer program is executed by the processor to implement a FPGA-based spread spectrum signal capture frequency correction method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball, or touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.
[0065] Those skilled in the art can understand that Figures 5-6 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.
[0066] In one embodiment, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor implements the following steps when executing the computer program: After multiplying the sampling data with the local intermediate frequency carrier, I / Q data at 0 intermediate frequency is obtained.
[0067] After filtering the I / Q data at 0 intermediate frequency, the data is decimated to an integer multiple of the spread spectrum code rate, so that the filtered I / Q data at 0 intermediate frequency is bit-width quantized and subjected to FFT transformation. The frequency spectrum components exceeding the threshold value in the frequency domain are assigned and cut off, and then the IFFT transformation is performed on the frequency domain data to obtain time domain I / Q data.
[0068] According to the correlation point of the partial match filter, the serial time domain I / Q data and the spread spectrum code sequence generated in the code phase search precision unit and according to the correlation point number are stored in the BRAM as a group, and a plurality of groups of signal search pairs are obtained.
[0069] The I / Q data in the BRAM is searched in the code phase unit, and the partial match filtering operation is performed according to the signal search pair, and the operation result is obtained.
[0070] The output operation result is subjected to FFT transform processing, the FFT frequency domain transform result corresponding to each code phase is analyzed, the maximum peak value and the second maximum peak value are identified, and the frequency point indexes corresponding to the two peak values are recorded, until the complete search is completed, and the search result is obtained.
[0071] The maximum peak value in the search result is compared with the preset capture threshold, and the correction of the capture frequency is completed.
[0072] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
[0073] The technical features of the above embodiments can be combined in any way. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.
[0074] The above embodiments only express several implementation ways of the present application, and the description is more specific and detailed, but it should not be understood as a limitation to the scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A method for correcting the acquisition frequency of spread spectrum signals based on FPGA, characterized in that, The method includes: After multiplying the sampled data with the local intermediate frequency carrier, the I / Q data of 0 intermediate frequency is obtained; After filtering, the I / Q data of the 0 intermediate frequency is decimated to an integer multiple of the spreading code rate so that the filtered I / Q data of the 0 intermediate frequency can be bit-width quantized and FFT transformed. The spectral components in the frequency domain that exceed the threshold are assigned and removed. Then, the frequency domain data is transformed by IFFT to obtain the time domain I / Q data. Based on the correlation points of the partially matched filter, the serial time-domain I / Q data and the spreading code sequence generated according to the correlation points in units of code phase search accuracy are stored as a group in the BRAM to obtain several groups of signal search pairs; The code phase search is performed on all code phases of the I / Q data in the BRAM in increments of code phase search accuracy. Based on the signal search, a partial matched filtering operation is performed to obtain the operation result. The output operation results are processed by FFT transformation. The frequency domain results of the FFT transformation corresponding to each code phase are analyzed to identify the maximum peak and the second largest peak. The frequency indexes corresponding to the two peaks are recorded until all searches are completed, and the search results are obtained. The capture frequency is corrected by comparing the maximum peak value in the search results with the preset capture threshold.
2. The method according to claim 1, characterized in that, The 0-IF I / Q data, after filtering, is decimated to an integer multiple of the spreading code rate to enable bit-width quantization of the filtered 0-IF I / Q data. An FFT transform is then performed to remove spectral components exceeding a threshold in the frequency domain. Finally, an IFFT transform is performed on the frequency domain data to obtain the time-domain I / Q data, including: After filtering, the I / Q data at 0 IF is decimated to an integer multiple of the spreading code rate. The filtered I / Q data at 0 IF is then quantized to reduce the bit width from large to small. An FFT is performed to calculate the energy at each point in the frequency domain and obtain the average power value. Data exceeding the product of the average power value and a preset power coefficient in the frequency domain are removed by assigning a value. Finally, the frequency domain data is subjected to an FFT to obtain the time domain I / Q data.
3. The method according to claim 1, characterized in that, Based on the correlation points of the partially matched filter, the serial time-domain I / Q data and the spreading code sequence generated according to the number of correlation points and with code phase search precision are stored as a group in the BRAM, resulting in several signal search pairs, including: Based on the correlation points of the partially matched filter, the serial time-domain I / Q data and the spreading code sequence generated according to the number of correlation points in units of code phase search accuracy are stored as a group in the BRAM. The depth of code phase storage is equal to the code length divided by the chip phase search accuracy, resulting in several groups of signal search pairs. The signal search pair includes: the time-domain I / Q data and a spreading code sequence with the same number of correlation points.
4. The method according to any one of claims 1 to 3, characterized in that, The sampling rate of the time-domain I / Q data is an integer multiple of the spreading code rate.
5. The method according to claim 4, characterized in that, The code phase search is performed on all code phases of the I / Q data in the BRAM in increments of code phase search precision. A partial matched filtering operation is then performed based on the searched signal to obtain the operation results, including: The code phase search is performed on all code phases of the I / Q data in the BRAM in increments of code phase search precision. A partial matched filtering operation is then performed based on the signal search. The sum of the correlation values between each chip and the corresponding point in the time-domain I / Q data is calculated to obtain the operation result. in, For the first The result of partial matched filtering operation. This is local pseudocode. For code phase difference The pseudocode of time-domain I / Q data, To account for the Doppler frequency offset of the received signal, This represents the phase difference between the local intermediate frequency carrier and the received signal carrier.
6. The method according to claim 5, characterized in that, The output results are processed using an FFT. The frequency domain transformation results of the FFT corresponding to each code phase are analyzed to identify the maximum and second-largest peak values. The frequency indices corresponding to the two peak values are recorded. After all searches are completed, the search results are obtained, including: The output operation result is processed by FFT transformation to obtain the acquisition result of the frequency point data corresponding to the initial code phase as the address. The acquisition result of the frequency point corresponding to each code phase is analyzed, and the maximum peak value and the second largest peak value of the acquisition result of all frequency point data corresponding to the initial phase are counted, and the frequency point index corresponding to the two peak values is recorded respectively. The signal search pair with the largest peak value among the maximum values in the captured results is taken as the search result of the phase search.
7. The method according to claim 6, characterized in that, Compare the maximum peak value in the search results with a preset capture threshold to correct the capture frequency, including: The maximum peak value of the search result is compared with the capture threshold. If the maximum peak value is greater than the capture threshold, the capture is successful; otherwise, the capture fails and the capture process restarts. The capture frequency is corrected by using the frequency indexes corresponding to the largest and second largest peak values determined by the threshold decision, resulting in the final capture frequency value: in, The corrected capture frequency. Equal to the sampling rate after I / Q data decimation. This is the frequency index corresponding to the maximum peak value. Here, N is the frequency index corresponding to the second largest peak value, N is the number of FFT points, and M is the number of correlation points of the partially matched filter.
8. A spread spectrum signal acquisition frequency correction device based on FPGA, characterized in that, The device includes: The digital downconversion module is used to multiply the sampled data with the local intermediate frequency carrier to obtain I / Q data with 0 intermediate frequency. The filtering and quantization module is used to filter the 0 IF I / Q data and extract the data to an integer multiple of the spreading code rate so that the filtered 0 IF I / Q data can be bit-width quantized and FFT transformed to remove spectral components in the frequency domain that exceed the threshold. Then, IFFT transformation is performed on the frequency domain data to obtain the time domain I / Q data. The serial-to-parallel storage module is used to store the serial time-domain I / Q data and the spreading code sequence generated according to the number of correlation points in the code phase search precision into the BRAM as a group based on the correlation points of the partially matched filter, thereby obtaining several groups of signal search pairs. The PMF module is used to search for all code phases of the I / Q data in the BRAM in increments of code phase search accuracy, and to perform partial matched filtering operation based on the search signal to obtain the operation result. The search and analysis module is used to perform FFT transformation on the output operation results, analyze the frequency domain transformation results of the FFT corresponding to each code phase, identify the maximum peak and the second largest peak, and record the frequency index corresponding to the two peaks respectively, until the search results are obtained after all searches are completed. The frequency correction module is used to compare the maximum peak value in the search results with a preset capture threshold to correct the capture frequency.
9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.