Phase shift adjustment method, device, equipment, medium and program product in multi-channel system

Abstract

The invention relates to a phase shift adjustment method, device and equipment in a multi-channel system, a medium and a program product. The method comprises the following steps: acquiring a current enabled channel in a multi-channel system; obtaining a fault state of each currently started channel, and counting a first number of the currently started channels without faults based on the fault state; detecting whether standby channels exist in the current starting channels with the faults or not, and counting a second number of the current starting channels with the faults of the standby channels; on the basis of the first number and the second number, target phase shifts corresponding to the non-fault current starting channels and the fault current starting channels with standby channels are obtained; and updating a phase register based on the target phase shift. By adopting the method, the phase shift can be distributed based on the effective non-fault current starting channel, the phase shift distribution is dynamically optimized, the high-frequency noise is reduced, the switching loss and the thermal power consumption are reduced, the service life of the assembly is prolonged, and the EMI suppression effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a phase shift adjustment method, device, equipment, medium and program product in a multi-channel system. BACKGROUND

[0002] Matrix chips (such as multi-channel LED drivers or communication transceivers) usually adopt a fixed phase shift configuration to reduce electromagnetic interference (EMI) and peak current. For example, in an LED driving chip, the fixed phase shift reduces current ripple and system noise by staggering the phase of the switching signals of each channel. A typical implementation is to pre-set a fixed offset in the phase register.

[0003] However, the current fixed phase shift has the following defects: resource waste: when part of the channels are not enabled, the fixed phase shift cannot reallocate the phase difference of the remaining channels, resulting in uneven phase distribution and reduced EMI suppression effect. SUMMARY

[0004] Therefore, it is necessary to provide a phase shift adjustment method, device, equipment, medium and program product in a multi-channel system which can fully utilize resources, evenly distribute phases and improve EMI suppression effect.

[0005] In a first aspect, the present application provides a phase shift adjustment method in a multi-channel system, the method comprising:

[0006] obtaining currently enabled channels in a multi-channel system;

[0007] obtaining a fault state of each of the currently enabled channels, and counting a first number of non-faulty currently enabled channels based on the fault state;

[0008] detecting whether each faulty currently enabled channel has a standby channel, and counting a second number of each faulty currently enabled channel having a standby channel;

[0009] based on the first number and the second number, obtaining a target phase shift corresponding to the non-faulty currently enabled channels and each faulty currently enabled channel having a standby channel;

[0010] updating a phase register based on the target phase shift.

[0011] In one of the embodiments, the method further comprises:

[0012] determining a third number of channels enabled by the slave chip when it is determined that the master chip has the slave chip;

[0013] The target phase shift of each faulted current-enabled channel corresponding to the current-enabled channel without fault and the standby channel is obtained based on the first number and the second number.

[0014] The target phase shift of each channel is determined based on the first number, the second number and a third number of the current-enabled channels of the slave chip.

[0015] In one of the embodiments, the third number of the current-enabled channels of the slave chip is determined in the case that the master chip exists.

[0016] It is detected whether the master chip starts the master-slave mode, and in the case that the master chip starts the master-slave mode, a fourth number of the slave chips corresponding to the master chip is obtained.

[0017] A fifth number of the slave channels corresponding to each of the slave chips is obtained.

[0018] The third number of the current-enabled channels of the slave chip is determined based on the fourth number and the fifth number.

[0019] In one of the embodiments, the detection of whether the master chip starts the master-slave mode comprises:

[0020] When the system is initialized, each chip is configured as the master mode or the master-slave mode according to a preset system topology.

[0021] The synchronization lock state bit of each of the slave chips is polled.

[0022] In the case that each of the slave chips reports the lock success within a predetermined timeout time, it is determined that the master-slave mode is started.

[0023] In one of the embodiments, the current-enabled channels in the multi-channel system are obtained, comprising:

[0024] A global variable is generated, which is used to count the number of the current-enabled channels.

[0025] In the case that there is a write operation to the channel enable register, an interrupt service program is triggered, which is used to analyze whether the write operation enables or disables a certain channel, and update the global variable based on the analysis result.

[0026] The value in the channel enable register inside the chip is read to obtain a first number of the current-enabled channels.

[0027] The second number of the current-enabled channels is obtained based on the global variable.

[0028] In a case where the first number of currently enabled channels is equal to the second number of currently enabled channels, a channel state of each channel in the chip is determined based on a value in the channel enable register; in a case where the channel state is on, it is determined that the channel is a currently enabled channel;

[0029] In a case where the first number of currently enabled channels is not equal to the second number of currently enabled channels, a value of a new channel enable register is generated in combination with a system expected state or a safety state value, and the channel enable register and the global variable are updated, a channel state of each channel in the chip is determined based on the generated value of the new channel enable register; in a case where the channel state is on, it is determined that the channel is a currently enabled channel.

[0030] In one of the embodiments, the obtaining of the fault state of each of the currently enabled channels comprises:

[0031] reading a value of a chip internal fault state register, the value of the fault state register being used to indicate a fault state of a corresponding channel;

[0032] determining the fault value of the currently enabled channel from the value of the fault state register;

[0033] determining the fault state of the currently enabled channel based on the fault value.

[0034] In a second aspect, the application further provides a phase shift adjustment device in a multi-channel system, the device comprising:

[0035] a channel obtaining module, configured to obtain currently enabled channels in a multi-channel system;

[0036] a first statistical module, configured to obtain a fault state of each of the currently enabled channels, and to statistically obtain a first number of non-faulty currently enabled channels based on the fault state;

[0037] a second statistical module, configured to detect whether a standby channel exists for each of the faulty currently enabled channels, and to statistically obtain a second number of each of the faulty currently enabled channels with a standby channel;

[0038] a target phase shift calculation module, configured to obtain a target phase shift corresponding to each of the non-faulty currently enabled channels and each of the faulty currently enabled channels with a standby channel based on the first number and the second number;

[0039] an updating module, configured to update a phase register based on the target phase shift.

[0040] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0041] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0042] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0043] The phase shift adjustment method, apparatus, device, medium, and program products in the aforementioned multi-channel system acquire the currently active channels in the multi-channel system; acquire the fault status of each currently active channel, and count a first number of non-faulty currently active channels based on the fault status; detect whether there is a backup channel for each faulty currently active channel, and count a second number of faulty currently active channels with backup channels; based on the first number and the second number, obtain the target phase shift corresponding to the non-faulty currently active channels and the faulty currently active channels with backup channels; update the phase register based on the target phase shift. This allows phase shift to be allocated based on effective non-faulty currently active channels, dynamically optimizing phase shift distribution, reducing high-frequency noise, lowering switching losses and heat dissipation, extending component life, and improving EMI suppression. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a diagram illustrating the application environment of a phase shift adjustment method in a multi-channel system in one embodiment.

[0046] Figure 2 This is a flowchart illustrating a phase shift adjustment method in a multi-channel system in one embodiment;

[0047] Figure 3 This is a flowchart of the master-slave collaborative control steps in one embodiment;

[0048] Figure 4This is a flowchart illustrating a phase shift adjustment method in a multi-channel system in another embodiment;

[0049] Figure 5 This is a structural block diagram of a phase shift adjustment device in a multi-channel system in one embodiment;

[0050] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0053] The phase shift adjustment method in the multi-channel system provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, the LED driver module is used to drive an LED array. The LED driver module inputs switching signals to the LED array to control the on and off states of the LEDs in the array. The LED driver module may include at least one LED driver chip, which may include multiple channels, such as an 8-channel LED driver chip, which includes eight independent internal current sources or switching circuits. Each channel can control at least one LED.

[0054] In some alternative embodiments, to improve control efficiency, multiple LED driver chips can be set, with each LED driver chip driving a portion of the LEDs. In other embodiments, master-slave control can be set, with one master LED driver chip driving at least two slave LED driver chips, and each slave LED driver chip driving a portion of the LEDs.

[0055] In some other alternative embodiments, each LED driver chip may include a backup driver chip, which can be activated in the event of a failure of the LED driver chip.

[0056] However, current drivers pre-set a fixed phase shift for each LED driver chip. This means that even if there is a fault, other LED driver chips will not use that part of the phase, resulting in wasted resources. Furthermore, uneven phase shift distribution reduces EMI suppression capability.

[0057] In one exemplary embodiment, such as Figure 2 As shown, a phase shift adjustment method is provided in a multi-channel system, which can be applied to... Figure 1 Taking the LED driver module as an example, the explanation includes the following steps S202 to S210. Wherein:

[0058] S202: Get the currently enabled channel in the multi-channel system.

[0059] The multi-channel system includes multiple channels. For example, each LED driver chip can include multiple channels. Therefore, the currently enabled channels in the LED driver chip are obtained. For example, an LED driver chip can include 8 channels. If 4 channels are currently enabled, then the number of currently enabled channels is 4.

[0060] In some optional embodiments, obtaining the currently enabled channels in a multi-channel system includes: generating a global variable to count the number of currently enabled channels; triggering an interrupt service routine when a write operation to the channel enable register exists, the interrupt service routine analyzing whether the write operation enabled or disabled a channel, and updating the global variable based on the analysis results; reading the value in the channel enable register inside the chip to obtain the first number of currently enabled channels; obtaining the second number of currently enabled channels based on the global variable; if the first number of currently enabled channels is equal to the second number of currently enabled channels, determining the channel status of each channel in the chip based on the value in the channel enable register; if the channel status is enabled, determining the channel as the currently enabled channel; if the first number of currently enabled channels is not equal to the second number of currently enabled channels, generating a new value for the channel enable register based on the expected system status or security status value, updating the channel enable register and the global variable, and determining the channel status of each channel in the chip based on the generated new value of the channel enable register; if the channel status is enabled, determining the channel as the currently enabled channel.

[0061] The chip includes a channel enable register. The number of bits in the channel enable register can be equal to the number of channels. In this way, each bit in the channel enable register corresponds to one channel. When a bit in the channel enable register is 1, it means that the corresponding channel is enabled. If a bit is 0, it means that the corresponding channel is not enabled. The LED driver chip reads the entire register periodically or as needed (e.g., after receiving a dimming command). Then, it determines the number of currently enabled channels and the currently enabled channels by determining the number of bits in the register that are 1.

[0062] In other embodiments, the LED driver chip can maintain a global variable to record the number of currently enabled channels. Any write operation to the channel enable register will trigger an interrupt service routine. In the interrupt service routine, the global variable is updated by analyzing whether the write operation enabled or disabled a channel. When it is necessary to obtain the number of currently enabled channels, the global variable can be read directly to get the number of currently enabled channels. Subsequently, the value in the channel enable register can be read to determine the number of currently enabled channels. The two counts are compared. If they are the same, it means that the count is correct. The channel enabled based on the value in the channel enable register is taken as the currently enabled channel. If the counts are different, it means that there is an error. An error can be reported and the error context can be recorded. Phase shift adjustment is paused to avoid phase shift chaos caused by calculation based on the incorrect count. In addition, the existing state (on or off) of all channels is maintained to avoid impacting the load.

[0063] Furthermore, it should be noted that discrepancies between the two values ​​may be due to corrupted global variable memory, vulnerabilities in the interrupt service routine, or asynchronous register read / write operations. In such cases, the current channel enable register value, CurrentReg, is read. Based on g_active_channel_count and CurrentReg, and considering the system's expected state (if recorded in the software), a correct register value, CorrectReg, is calculated. If it cannot be calculated, a safe state value (such as all-off or the previously known correct value) is used. CorrectReg is written to the channel enable register, and the global variable is updated. Subsequent uses of the correct register value, CorrectReg, will determine the currently enabled channel.

[0064] The number of currently enabled channels can be used to generate threads for detecting the fault status of the currently enabled channels, or the number of currently enabled channels can be used to generate the number of read operations for reading the fault status register. For example, each currently enabled channel corresponds to one read operation to read the value of the corresponding bit in the fault status register.

[0065] S204: Obtain the fault status of each currently enabled channel, and count the first number of non-faulty currently enabled channels based on the fault status.

[0066] The fault status of the currently enabled channel can be determined by reading the value of the fault status register.

[0067] In some optional embodiments, obtaining the fault status of each currently enabled channel includes: reading the value of an internal fault status register, the value of which indicates the fault status of the corresponding channel; determining the fault value of the currently enabled channel from the value of the fault status register; and determining the fault status of the currently enabled channel based on the fault value.

[0068] The fault status register indicates the fault status of the corresponding channel. The number of bits in the fault status register can be equal to the number of channels, so each bit in the register corresponds to one channel. A bit in the register being 1 indicates that the corresponding channel is faulty, while a bit being 0 indicates that the corresponding channel is not faulty. Since the currently enabled channel is already determined by the channel enable register, when reading the fault status register, only the bit value corresponding to the currently enabled channel needs to be read, rather than reading the bits for all channels, thus reducing the amount of data read.

[0069] In practical applications, the chip internally provides a fault status flag for each channel, typically located in a dedicated status register. These registers can be read directly via communication interfaces such as I2C, SPI, or SQI. The specific flag in the register indicates whether the corresponding channel is "normal," "overcurrent," "open circuit," or "overheating."

[0070] S206: Detect whether there is a backup channel for the currently active channel of each fault, and count the second number of currently active channels for each fault that have a backup channel.

[0071] The backup channel is a substitute for the currently active channel. If a currently active channel fails, the corresponding backup channel can be activated to ensure the normal operation of the channel. For example, an LED driver chip includes 8 channels, of which 4 are currently active channels, and the other 4 channels serve as backup channels for their respective active channels. Alternatively, there are 6 currently active channels, with the other 2 channels serving as backup channels for 2 of them, or as backup channels for all 6 channels. In other words, if the number of failed currently active channels is less than or equal to the number of backup channels, the normal operation of the channel can be guaranteed. Otherwise, a certain number of channels need to be shut down. This target number is calculated by subtracting the number of backup channels from the number of failed channels, and then shutting down that target number of currently active channels.

[0072] S208: Based on the first quantity and the second quantity, obtain the target phase shift corresponding to each faulty currently enabled channel that is not faulty and each faulty currently enabled channel that has a backup channel.

[0073] The first number represents the initial number of currently active, non-faulty channels. If a faulty channel exists among the active channels, it needs to be shut down. If a faulty channel has a backup channel, it does not need to be shut down. Therefore, the final number of channels that can still function normally is the first number plus the second number. This fault tolerance mechanism dynamically detects the number of currently active channels and determines whether a channel is faulty, adjusting the number of channels participating in phase allocation accordingly to improve the accuracy of phase allocation.

[0074] For ease of understanding, assume N is the initial number of channels: after shutting down a faulty channel, the remaining number of channels is updated to N′ = NL (the number of faulty channels). If there are backup channels for A faulty channels, then N′ = N - L + A, where NL is the first number of currently active, non-faulty channels, and A is the second number.

[0075] Finally, the phase shift was calculated based on the first and second quantities, Δφ = 360° / N′.

[0076] S210: Update the phase register based on the target phase shift.

[0077] Once the target phase shift is determined, the phase of each non-faulty currently active channel and the backup channel corresponding to the faulty currently active channel can be determined based on the target phase shift.

[0078] For example, in the initial state: 8 channels are enabled, with a phase shift of 45° (360° / 8). After channel 2 fails, 7 channels remain, and the phase shift is adjusted to approximately 51.4° (360° / 7). If a backup channel is enabled, 8 channels are maintained, and the phase shift remains at 45°.

[0079] The phase shift adjustment method in the above multi-channel system involves: obtaining the currently active channels in the multi-channel system; obtaining the fault status of each currently active channel and counting the first number of non-faulty currently active channels based on the fault status; detecting whether there are backup channels for each faulty currently active channel and counting the second number of faulty currently active channels with backup channels; obtaining the target phase shift corresponding to the non-faulty currently active channels and the faulty currently active channels with backup channels based on the first and second numbers; and updating the phase register based on the target phase shift. This allows phase shift to be allocated based on the effective non-faulty currently active channels, dynamically optimizing the phase shift distribution, reducing high-frequency noise, lowering switching losses and heat dissipation, extending component life, and improving EMI suppression.

[0080] In some of these alternative embodiments, combined with Figure 3As shown, Figure 3 Here is a flowchart of the master-slave collaborative control steps in one embodiment. The method further includes:

[0081] S302: If it is determined that there is a slave chip in the master chip, determine the third number of channels enabled by the slave chip.

[0082] Once it is determined that there are slave chips in the master chip, the number of slave chips and the number of channels enabled by each slave chip can be determined, thus obtaining the third number of channels enabled by the slave chips.

[0083] In some optional embodiments, detecting whether the master chip has enabled master-slave mode includes: during system initialization, configuring each chip into master mode or master-slave mode according to a preset system topology; polling the synchronization lock status bit of each slave chip; and determining that master-slave mode is enabled if each slave chip reports successful locking within a predetermined timeout period.

[0084] After configuration, the system can confirm successful collaboration through a status register or handshake protocol. The master chip, after starting the synchronization clock, polls or waits for the slave chip's "ready" response. The slave chip, after successfully locking the master clock and completing its own configuration, sets a "synchronization lock" status bit or sends a "handshake successful" message to the master chip via the communication bus. The slave chip's "synchronization status register" is read. If the register displays "locked," it indicates that master-slave collaboration has been successfully initiated. The master chip's "slave response register" is checked to see if all expected slave devices have responded.

[0085] In some optional embodiments, when it is determined that there are slave chips in the master chip, a third number of channels enabled by the slave chips is determined, including: detecting whether the master chip has enabled master-slave mode, and when the master chip has enabled master-slave mode, obtaining a fourth number of slave chips corresponding to the master chip; obtaining a fifth number of slave channels corresponding to each slave chip; and determining a third number of channels enabled by the slave chips based on the fourth number and the fifth number.

[0086] In a true multi-chip master-slave system, the master chip must know the global information of the entire system, including the number of channels enabled on all slave chips, not just its own local channel count. During the system design phase, it is assumed that there is a total of 1 master chip and M slave chips, with a fixed number of channels enabled on each chip. This information (number of slave chips, number of channels per slave chip) is pre-written into the master chip's firmware or configuration registers. In other embodiments, the number of master chips and slave chips can be other values. The master chip queries each slave chip via a communication bus (such as I2C). The master chip iterates through all possible slave chip addresses, sending a "handshake" or "status request" command. Addresses receiving valid responses are considered online slave chips. For each discovered slave chip, the master chip sends a command to read the number of active channels. Upon receiving the command, the slave chip reads its own channel enable register, calculates its local active channel count N_local, and returns this value to the master chip. The master chip adds the N_local reported by each slave chip to its own number of activated channels N_master to obtain the total number of activated channels in the system.

[0087] First, the fourth number of slave chips corresponding to the master chip is determined. Then, a command to read the number of activated channels is sent to the fourth number of slave chips, and the fifth number of slave channels returned by each slave chip is obtained. Finally, the third number of channels enabled by the slave chips is obtained based on the fourth and fifth numbers.

[0088] S306: Determine the target phase shift for each channel based on the first number, the second number, and the third number of channels enabled by the slave chip.

[0089] Thus, all the opened channels include B = first quantity + second quantity + third quantity, and finally the target phase shift is obtained by 360 / B.

[0090] To make it easier to understand, when master-slave synchronization is enabled, the master chip's master clock is started, so that all chip clocks are synchronized, and the slave chips synchronize the offset.

[0091] Phase superposition rule:

[0092] Main chip phase shift allocation: φmain = (360° / N) × k (k = 0, 1, ..., N-1).

[0093] Slave chip phase shift allocation: φslave = φmaster + 360° / (2N).

[0094] Effect: When M chips are cascaded, the equivalent phase shift resolution is 360° / (M×N).

[0095] For example, each of the master and slave chips uses 4 channels: Master chip phase shifts: 0°, 90°, 180°, and 270°. Slave chip phase shifts: 45°, 135°, 225°, and 315°. That is, it is equivalent to 8 channels with uniform phase shifts, spaced 45° apart.

[0096] For ease of understanding, combined with Figure 4 As shown, this application specifically includes the following steps:

[0097] The number of active channels and fault flags are detected, and the input is obtained: number of active channels N.

[0098] Calculate the phase shift output: Phase shift φk for each channel = (360° / N) × k (k = 0, 1, ..., N-1).

[0099] If the fault flag is true, close the fault channel and update the N value.

[0100] In a multi-chip system, a synchronization signal is sent to the slave chip to synchronize the phases of the multiple chips: Master chip phase: φmaster[i] = (360° / N) × i. Slave chip phase: φslave[j] = φmaster[i] + 360° / (2N).

[0101] Write the phase shift configuration.

[0102] The above embodiments can improve EMI suppression capabilities by dynamically optimizing phase shift distribution and reducing high-frequency noise. They also improve system efficiency by reducing switching losses and heat dissipation, thus extending component lifespan. Furthermore, they enhance adaptability, making them suitable for scenarios with frequent changes in the number of channels (such as dimming and load switching).

[0103] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0104] Based on the same inventive concept, this application also provides a phase shift adjustment device for implementing the phase shift adjustment method in a multi-channel system as described above. The solution provided by this device is similar to the implementation described in the above method. Therefore, the specific limitations in one or more embodiments of the phase shift adjustment device in a multi-channel system provided below can be found in the limitations of the phase shift adjustment method in the multi-channel system described above, and will not be repeated here.

[0105] In one exemplary embodiment, such as Figure 5 As shown, a phase shift adjustment device for a multi-channel system is provided, comprising: a channel acquisition module 501, a first statistics module 502, a second statistics module 503, a target phase shift calculation module 504, and an update module 505, wherein:

[0106] Channel acquisition module 501 is used to acquire the currently enabled channels in a multi-channel system;

[0107] The first statistics module 502 is used to obtain the fault status of each currently enabled channel and to count the first number of non-faulty currently enabled channels based on the fault status.

[0108] The second statistics module 503 is used to detect whether there is a backup channel for the currently active channel of each fault, and to count the second number of currently active channels for each fault that has a backup channel.

[0109] The target phase shift calculation module 504 is used to obtain the target phase shift of each faulty currently active channel and each faulty currently active channel with a backup channel based on the first quantity and the second quantity.

[0110] Update module 505 is used to update the phase register based on the target phase shift.

[0111] In some optional embodiments, the above-described apparatus further includes:

[0112] The cross-chip synchronization module is used to determine the third number of channels enabled by the slave chip when it is determined that there is a slave chip in the master chip.

[0113] The aforementioned target phase shift calculation module is specifically used to determine the target phase shift of each channel based on the first number, the second number, and the third number of channels enabled by the slave chip.

[0114] In some optional embodiments, the cross-chip synchronization module is specifically used to detect whether the master chip has enabled master-slave mode, and when the master chip has enabled master-slave mode, to obtain the fourth number of slave chips corresponding to the master chip; to obtain the fifth number of slave channels corresponding to each slave chip; and to determine the third number of channels enabled by the slave chip based on the fourth number and the fifth number.

[0115] In some optional embodiments, the cross-chip synchronization module is specifically used during system initialization to configure each chip into master mode or master-slave mode according to a preset system topology; poll the synchronization lock status bit of each slave chip; and determine to enable master-slave mode if each slave chip reports successful locking within a predetermined timeout period.

[0116] In some optional embodiments, the channel acquisition module is specifically used to generate a global variable to count the number of currently enabled channels; in the event of a write operation to the channel enable register, an interrupt service routine is triggered, which analyzes whether the write operation enabled or disabled a channel and updates the global variable based on the analysis results; the value in the channel enable register inside the chip is read to obtain the first number of currently enabled channels; the second number of currently enabled channels is obtained based on the global variable; if the first number of currently enabled channels is equal to the second number of currently enabled channels, the channel status of each channel in the chip is determined based on the value in the channel enable register; if the channel status is enabled, the channel is determined to be a currently enabled channel; if the first number of currently enabled channels is not equal to the second number of currently enabled channels, a new value for the channel enable register is generated by combining the expected system status or security status value, and the channel enable register and global variable are updated; based on the generated new value for the channel enable register, the channel status of each channel in the chip is determined; if the channel status is enabled, the channel is determined to be a currently enabled channel.

[0117] In some optional embodiments, the first statistics module is specifically used to read the value of the internal fault status register of the chip, the value of the fault status register being used to indicate the fault status of the corresponding channel; determine the fault value of the currently enabled channel from the value of the fault status register; and determine the fault status of the currently enabled channel based on the fault value.

[0118] The various modules in the phase shift adjustment device of the aforementioned multi-channel system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0119] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a phase shift adjustment method in a multi-channel system. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0120] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0121] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0122] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0123] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0124] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0125] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A phase shift adjustment method in a multi-channel system, characterized in that, The method includes: Get the currently active channels in the multi-channel system; Obtain the fault status of each of the currently enabled channels, and count the first number of non-faulty currently enabled channels based on the fault status; Detect whether there is a backup channel for each fault's currently active channel, and count the second number of currently active channels for each fault that have a backup channel; Based on the first quantity and the second quantity, the target phase shifts corresponding to the non-faulty currently enabled channels and the faulty currently enabled channels with backup channels are obtained; The phase register is updated based on the target phase shift.

2. The method according to claim 1, characterized in that, The method further includes: If it is determined that there are slave chips in the master chip, determine the third number of channels enabled by the slave chips; The step of obtaining the target phase shift corresponding to each faulty currently active channel and each faulty currently active channel with a backup channel based on the first quantity and the second quantity includes: The target phase shift for each channel is determined based on the first quantity, the second quantity, and the third quantity of channels enabled by the slave chip.

3. The method according to claim 2, characterized in that, The third step of determining the number of channels enabled by the slave chip when it is determined that the master chip has a slave chip includes: Detect whether the master chip is in master-slave mode, and if the master chip is in master-slave mode, obtain the fourth number of slave chips corresponding to the master chip; Obtain the fifth number of slave channels corresponding to each slave chip; Based on the fourth and fifth quantities, a third quantity of channels enabled by the slave chip is determined.

4. The method according to claim 3, characterized in that, The detection of whether the main chip is in master-slave mode includes: During system initialization, each chip is configured to master mode or master-slave mode according to the preset system topology. Poll the synchronization lock status bits of each slave chip; If each of the slave chips reports a successful lock within a predetermined timeout period, then the master-slave mode is determined to be enabled.

5. The method according to any one of claims 1 to 4, characterized in that, The acquisition of currently active channels in the multi-channel system includes: Generate a global variable, which is used to count the number of currently enabled channels; In the event of a write operation to the channel enable register, an interrupt service routine is triggered. The interrupt service routine is used to analyze whether the write operation enables or disables a channel, and updates the global variable based on the analysis results. Read the value in the channel enable register inside the chip to obtain the number of currently enabled channels; The number of second currently enabled channels is obtained based on the global variables; When the number of the first currently enabled channels is equal to the number of the second currently enabled channels, the channel status of each channel in the chip is determined based on the value in the channel enable register; when the channel status is enabled, the channel is determined to be the currently enabled channel. If the number of the first currently enabled channels is not equal to the number of the second currently enabled channels, a new channel enable register value is generated based on the expected system state or security state value, and the channel enable register and global variables are updated. Based on the generated new channel enable register value, the channel state of each channel in the chip is determined; if the channel state is enabled, the channel is determined to be the currently enabled channel.

6. The method according to any one of claims 1 to 4, characterized in that, The step of obtaining the fault status of each of the currently enabled channels includes: Read the value of the fault status register inside the chip, the value of which is used to indicate the fault status of the corresponding channel; The fault value of the currently enabled channel is determined from the value of the fault status register; The fault status of the currently enabled channel is determined based on the fault value.

7. A phase shift adjustment device in a multi-channel system, characterized in that, The device includes: The channel acquisition module is used to acquire the currently enabled channels in a multi-channel system; The first statistics module is used to obtain the fault status of each of the currently enabled channels, and to count the first number of non-faulty currently enabled channels based on the fault status. The second statistics module is used to detect whether there is a backup channel for each fault's currently active channel, and to count the second number of currently active channels for each fault that has a backup channel. The target phase shift calculation module is used to obtain the target phase shift corresponding to each faulty currently active channel and each faulty currently active channel with a backup channel, based on the first quantity and the second quantity. An update module is used to update the phase register based on the target phase shift.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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