Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the first epitaxial layer is located on the surface of one side of the substrate; the electric field modulation regions are located in the first epitaxial layer, and the top surfaces of the electric field modulation regions are located on the top surface of the first epitaxial layer; the doping type of the electric field modulation region is opposite to that of the first epitaxial layer; the second epitaxial layer is positioned on one side, away from the substrate, of the first epitaxial layer; the doping type of the second epitaxial layer is the same as that of the first epitaxial layer; the trench gate and the first source region are located in the second epitaxial layer, and the top surfaces of the trench gate and the first source region are located on the top surface of the second epitaxial layer; the doping type of the first source region is opposite to that of the second epitaxial layer; the first masking layer and the second masking layer are located in the second epitaxial layer; the doping type of the first masking layer is the same as that of the second masking layer and is opposite to that of the second epitaxial layer; the first masking layer is located between the second masking layer and the bottom surface of the second epitaxial layer, and a distance is formed between the first masking layer and the second masking layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor structures, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] In recent years, wide-bandgap semiconductor materials such as SiC, GaN, gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have more advantages than Si in terms of band gap, breakdown field strength, and electron saturation drift speed. The prepared power devices such as diodes, transistors, and power modules have more excellent electrical properties, can overcome the defects of silicon-based devices that cannot meet the application requirements of high power, high voltage, high frequency, and high temperature, and are one of the breakthrough paths that can surpass Moore's Law, and are widely used in new energy fields (photovoltaic, energy storage, charging piles, electric vehicles, etc.).

[0003] Super junction structure, as an important structure design to break the one-dimensional limit of power device performance, has been verified and widely used in Si-based devices, and is currently being researched in wide-bandgap semiconductor materials. However, in wide-bandgap semiconductors, the high doping concentration of super junction devices can cause excessive electric field in the gate oxide layer, thereby affecting the reliability of the device. SUMMARY

[0004] In view of the above problems, the present application provides a semiconductor structure and a preparation method thereof to reduce the electric field of the gate oxide layer. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a semiconductor structure, comprising:

[0006] a substrate;

[0007] a first epitaxial layer located on one side surface of the substrate;

[0008] a plurality of electric field modulation regions located in the first epitaxial layer, the top surface of the electric field modulation region being located at the top surface of the first epitaxial layer; the doping type of the electric field modulation region being opposite to that of the first epitaxial layer;

[0009] a second epitaxial layer located on the side of the first epitaxial layer away from the substrate; the doping type of the second epitaxial layer being the same as that of the first epitaxial layer;

[0010] a trench gate and a first source region located in the second epitaxial layer, the top surface of the trench gate and the first source region being located at the top surface of the second epitaxial layer; the doping type of the first source region being opposite to that of the second epitaxial layer;

[0011] The first mask layer and the second mask layer are located in the second epitaxial layer; the first mask layer and the second mask layer have the same doping type and the opposite doping type of the second epitaxial layer; the first mask layer is located between the second mask layer and the bottom surface of the second epitaxial layer, and the first mask layer has a spacing with the second mask layer.

[0012] Optionally, in the semiconductor structure, the first mask layer and the second mask layer are both located between the trench gate and the bottom surface of the second epitaxial layer, and the top surface of the second mask layer is in contact with the bottom of the trench gate.

[0013] Alternatively, the trench gate comprises two-stage trenches; the first mask layer is located below the trench gate and in contact with the bottom of the trench gate; and the second mask layer is located below the step of the two-stage trenches.

[0014] Optionally, in the semiconductor structure, the depth of the first source region is greater than the depth of the trench gate.

[0015] The semiconductor structure comprises at least two first source regions; between two adjacent first source regions, there are a trench gate, a first mask layer and a second mask layer; the first mask layer and the second mask layer are both in contact with the first source region on one side and have a spacing with the first source region on the other side.

[0016] Alternatively, the first mask layer and the second mask layer have a spacing with the adjacent first source region at both ends; and the second epitaxial layer has a ground-doped region connecting the first mask layer and the second mask layer.

[0017] Optionally, in the semiconductor structure, for the first mask layer and the second mask layer between two adjacent first source regions, the first mask layer and the second mask layer are both in contact with the first source region on the same side, or the first mask layer and the second mask layer are respectively in contact with the first source region on different sides.

[0018] Optionally, in the semiconductor structure, the first mask layer and the second mask layer each comprise a plurality of strip-shaped doped regions arranged at intervals in a first direction, the first direction being parallel to the plane in which the substrate lies; in a second direction, the strip-shaped doped regions of the first mask layer and the strip-shaped doped regions of the second mask layer are in one-to-one correspondence, the second direction being perpendicular to the plane in which the substrate lies.

[0019] The two strip-shaped doped regions in the second direction are connected by a plurality of ground-doped regions arranged at intervals in a third direction.

[0020] Optionally, in the semiconductor structure, the bottom surface of the electric field modulation region has a spacing with the bottom surface of the first epitaxial layer, or the bottom surface of the electric field modulation region is located at the bottom surface of the first epitaxial layer.

[0021] Optionally, in the semiconductor structure, the bottom surface of the first source region is spaced apart from the bottom surface of the second epitaxial layer, or the bottom surface of the first source region extends to the bottom surface of the second epitaxial layer and contacts the top surface of the electric field modulation region.

[0022] Optionally, in the semiconductor structure, the electric field modulation region at least partially overlaps the first source region in a direction perpendicular to the plane on which the substrate lies, or the electric field modulation region does not overlap the first source region.

[0023] In a second aspect, the present application provides a method for manufacturing any of the semiconductor structures described above, comprising:

[0024] forming a first epitaxial layer on one side surface of a substrate;

[0025] forming an electric field modulation region in the first epitaxial layer, the top surface of the electric field modulation region being located at the top surface of the first epitaxial layer; the electric field modulation region being opposite in doping type to the first epitaxial layer;

[0026] forming a second epitaxial layer on the side surface of the first epitaxial layer away from the substrate;

[0027] forming a first source region, a first masking layer, a second masking layer and a trench gate in the second epitaxial layer; the top surface of the trench gate and the top surface of the first source region being located at the top surface of the second epitaxial layer; the first source region being opposite in doping type to the second epitaxial layer; the first masking layer and the second masking layer being the same in doping type and opposite in doping type to the second epitaxial layer; the first masking layer being located between the bottom surface of the second masking layer and the second epitaxial layer, and the first masking layer and the second masking layer being spaced apart.

[0028] Optionally, in the method for manufacturing, the forming of the first source region, the first masking layer, the second masking layer and the trench gate in the second epitaxial layer comprises:

[0029] forming the first source region, the first masking layer and the second masking layer in the second epitaxial layer by an ion implantation process;

[0030] forming a trench in the surface of the second epitaxial layer by an etching process, and forming the trench gate based on the trench.

[0031] By employing the above technical solution, the semiconductor structure and its fabrication method provided in this application form multiple electric field modulation regions within the first epitaxial layer. Since the doping types of the electric field modulation regions and the first epitaxial layer are opposite—one is N-type doped and the other is P-type doped—multiple alternating N-type and P-type doped regions are formed in the first epitaxial layer to create a superjunction structure. Therefore, in the first epitaxial layer, holes in the P-type doped region and electrons in the N-type doped region can be precisely matched, achieving charge balance and breaking the one-dimensional limit of the semiconductor structure. Furthermore, the first source region, the first masking layer, and the second masking layer in the second epitaxial layer can constitute a triple electric field masking structure for the trench gate, preventing breakdown of the gate oxide layer in the trench gate due to excessive electric field and improving the reliability of the semiconductor structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0033] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0034] Figure 1 A cross-sectional view of a semiconductor structure provided in an embodiment of this application;

[0035] Figure 2 A top view of a semiconductor structure provided in an embodiment of this application, on the plane where the second masking layer is located;

[0036] Figure 3 A cross-sectional view of another semiconductor structure provided in an embodiment of this application;

[0037] Figure 4 for Figure 3 The semiconductor structure shown is a top view of the plane where the second masking layer is located;

[0038] Figure 5 A top view of a semiconductor structure in the second epitaxial layer provided in an embodiment of this application;

[0039] Figure 6 Fig. 1 is a sectional view of a semiconductor structure along a middle A-A' direction according to an embodiment of the present application; Figure 5 Fig. 2 is a sectional view of the semiconductor structure along a middle B-B' direction according to the embodiment of the present application;

[0040] Figure 7 Fig. 3 is a sectional view of another semiconductor structure according to an embodiment of the present application; Figure 5 Fig. 4 is a sectional view of the semiconductor structure along a middle C-C' direction according to the embodiment of the present application;

[0041] Figure 8 Fig. 5 is a sectional view of another semiconductor structure according to an embodiment of the present application; Fig. 6 is a sectional view of the semiconductor structure along a middle D-D' direction according to the embodiment of the present application;

[0042] Figure 9 Fig. 7 is a sectional view of another semiconductor structure according to an embodiment of the present application;

[0043] Figure 10 Fig. 8 is a sectional view of another semiconductor structure according to an embodiment of the present application;

[0044] Figure 11 Fig. 9 is a sectional view of another semiconductor structure according to an embodiment of the present application;

[0045] Figures 12-17 Fig. 10 is a device structure schematic diagram of a preparation method of a semiconductor structure according to an embodiment of the present application at different process steps;

[0046] Figure 18 Fig. 11 is an electric field curve of a semiconductor structure according to an embodiment of the present application at different positions;

[0047] Figure 19 Fig. 12 is a top view of an electric field modulation region in a semiconductor structure according to an embodiment of the present application;

[0048] Figure 20 Fig. 13 is a top view of an electric field modulation region in another semiconductor structure according to an embodiment of the present application.

[0049] Reference signs:

[0050] 100 - substrate; 101 - first epitaxial layer; 102 - second epitaxial layer; 103 - electric field modulation region; 104 - first source region; 105 - trench gate; 106 - first masking layer; 107 - second masking layer; 108 - well region; 109 - second source region; 110 - gate oxide layer; 111 - ground doped region; 112 - bar doped region; 113 - sub-region; 114 - back electrode; 115 - trench; 116 - bar element; X - first direction; Y - third direction; Z - second direction. DETAILED DESCRIPTION

[0051] The embodiments in the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Those skilled in the art can know that the technical solutions provided by the embodiments in the present application are also applicable to similar technical problems with the development of technology and the appearance of new scenarios.

[0052] As described in the background, although the formation of the super junction structure in the semiconductor structure can improve the performance of the semiconductor structure to a certain extent, the super junction structure needs high-concentration doped regions, which in turn can cause the electric field in the gate oxide layer to be too large, easily leading to the gate oxide layer being broken down by the electric field, thereby affecting the reliability of the semiconductor structure.

[0053] Therefore, the embodiments of the present application provide a semiconductor structure, comprising:

[0054] a substrate;

[0055] a first epitaxial layer located on one side surface of the substrate;

[0056] a plurality of electric field modulation regions located in the first epitaxial layer, the top surface of the electric field modulation region being located on the top surface of the first epitaxial layer; the doping type of the electric field modulation region being opposite to that of the first epitaxial layer;

[0057] a second epitaxial layer located on the side of the first epitaxial layer away from the substrate; the doping type of the second epitaxial layer being the same as that of the first epitaxial layer;

[0058] a trench gate and a first source region located in the second epitaxial layer, the top surface of the trench gate and the first source region being located on the top surface of the second epitaxial layer; the doping type of the first source region being opposite to that of the second epitaxial layer;

[0059] a first mask layer and a second mask layer located in the second epitaxial layer; wherein the doping type of the first mask layer is the same as that of the second mask layer, and is opposite to that of the second epitaxial layer; the first mask layer is located between the bottom surface of the second mask layer and the second epitaxial layer, and the first mask layer and the second mask layer have a spacing therebetween.

[0060] On the one hand, the electric field modulation region opposite to the doping type of the first epitaxial layer is formed in the first epitaxial layer, which not only forms a super junction structure in the first epitaxial layer to achieve accurate matching of electric charges through the super junction structure, realizes charge balance, and converts the electric field distribution from the traditional vertical dominance to the horizontal dominance, solves the problem that the on-resistance of the traditional semiconductor structure increases exponentially with the breakdown voltage, and improves the performance of the semiconductor structure.

[0061] On the other hand, the first source region, the first mask layer and the second mask layer in the second epitaxial layer can constitute a triple electric field shielding structure of the trench gate, which can prevent the high-concentration doped region in the super-junction structure from forming an electric field concentration in the gate oxide layer of the trench gate, avoid the breakdown problem of the gate oxide layer caused by excessive electric field, and improve the reliability of the semiconductor structure.

[0062] In order to make the above objectives, characteristics and advantages of the present application more apparent, more comprehensible and more understandable, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0063] Reference Figure 1 , Figure 1 A sectional view of a semiconductor structure provided by an embodiment of the present application is shown, and the semiconductor structure comprises:

[0064] a substrate 100;

[0065] a first epitaxial layer 101 located on one side surface of the substrate 100;

[0066] a plurality of electric field modulation regions 103 located in the first epitaxial layer 101, the top surface of the electric field modulation region 103 being located at the top surface of the first epitaxial layer 101; the electric field modulation region 103 is opposite in doping type to the first epitaxial layer 101;

[0067] a second epitaxial layer 102 located on the side of the first epitaxial layer 101 away from the substrate 100; the second epitaxial layer 102 is the same in doping type as the first epitaxial layer 101;

[0068] a trench gate 105 and a first source region 104 located in the second epitaxial layer 102, the top surface of the trench gate 105 and the top surface of the first source region 104 being located at the top surface of the second epitaxial layer 102; the first source region 104 is opposite in doping type to the second epitaxial layer 102;

[0069] a first mask layer 106 and a second mask layer 107 located in the second epitaxial layer 102; wherein the first mask layer 106 and the second mask layer 107 are the same in doping type and opposite in doping type to the second epitaxial layer 102; the first mask layer 106 is located between the second mask layer 107 and the bottom surface of the second epitaxial layer 102, and the first mask layer 106 and the second mask layer 107 have a spacing therebetween.

[0070] wherein the first mask layer 106 and the second mask layer 107 are arranged at intervals in the thickness direction of the second epitaxial layer 102, and the first mask layer 106 and the bottom surface of the second epitaxial layer 102 have a spacing therebetween.

[0071] In an embodiment of the present application, the same doping type means N-type doping or P-type doping, and the opposite doping type means N-type doping and P-type doping.

[0072] In the semiconductor structure, the first epitaxial layer 101 and the second epitaxial layer can be N-type doped, and the electric field modulation region 103, the first source region 104, the first masking layer 106 and the second masking layer 107 can be P-type doped.

[0073] On the one hand, an electric field modulation region 103 with the opposite doping type to the first epitaxial layer 101 is formed in the first epitaxial layer 101. This not only allows the formation of a superjunction structure in the first epitaxial layer 101 to achieve precise charge matching and charge balance, but also allows the electric field distribution to be transformed from the traditional vertical dominance to the horizontal dominance. This solves the problem of the on-resistance of traditional semiconductor structures increasing exponentially with breakdown voltage, and improves the performance of semiconductor structures.

[0074] On the other hand, the first source region 104, the first masking layer 106, and the second masking layer 107 in the second epitaxial layer 102 can form a triple electric field masking structure for the trench gate 105. This triple electric field masking structure can prevent the high-concentration doped region in the superjunction structure from forming an electric field concentration in the gate oxide layer 110 of the trench gate 105, avoid the breakdown problem of the gate oxide layer 110 due to excessive electric field, and improve the reliability of the semiconductor structure.

[0075] Optionally, such as Figure 1 As shown, the second epitaxial layer 102 has a well region 108 and a second source region 109 with opposite doping types. The second source region 109 has the same doping type as the second epitaxial layer 102. The depth of the well region 108 within the second epitaxial layer 102 can be less than the depth of the trench gate 105. The second source region 109 is located on the top surface of the well region 108, and the top surface of the second source region 109 is located on the top surface of the second epitaxial layer 102. The substrate 100 has a back electrode 114 on the side surface opposite to the first epitaxial layer 101.

[0076] In the semiconductor structure, trench gate 105 and first source region 104 are arranged at intervals within a second epitaxial layer 102. A well region 108 and a second source region 109 are stacked within the second epitaxial layer 102 between adjacent trench gates 105 and first source regions 104. Optionally, the depth of the well region 108 is less than the depth of the trench gate 105.

[0077] In some embodiments of this application, such as Figure 1 As shown, the first masking layer 106 and the second masking layer 107 are both located between the trench gate 105 and the bottom surface of the second epitaxial layer 102, and the top surface of the second masking layer 107 is in contact with the bottom surface of the trench gate 105.

[0078] like Figure 1As shown, when the top surface of the second masking layer 107 contacts the bottom of the trench gate 105, the second masking layer 107 completely covers the bottom of the trench gate 105 to better protect the gate oxide layer 110 at the bottom of the trench gate 105.

[0079] Reference Figure 2 , Figure 2 A top view of a semiconductor structure provided by an embodiment of the present application in a plane of the second masking layer is shown in FIG. 1, which is based on the embodiments shown in FIGS. 1A-1C and FIGS. 2A-2C. Figure 1 and Figure 2 As shown, the depth of the first source region 104 is greater than the depth of the trench gate 105; the semiconductor structure includes at least two first source regions 104; the two adjacent first source regions 104 have the trench gate 105, the first masking layer 106, and the second masking layer 107 therebetween; the first masking layer 106 and the second masking layer 107 both contact the first source region 104 on one side and have a spacing from the first source region 104 on the other side. In this mode, the first masking layer 106 and the second masking layer 107 both contact the sidewall of the first source region 104 on one side, and the first masking layer 106 and the second masking layer 107 can not only be grounded through the first source region 104 on one side, but also enable current to flow through the space between the second masking layers 107, thereby improving the reliability and stability of the semiconductor structure.

[0080] In Figure 1 and Figure 2 the mode shown, for the first masking layer 106 and the second masking layer 107 between the two adjacent first source regions 104, the first masking layer 106 and the second masking layer 107 both contact the first source region 104 on the same side. As shown in Figure 1 and Figure 2 the first masking layer 106 and the second masking layer 107 between the two adjacent first source regions 104 both contact the first source region 104 on the right end and have a spacing from the first source region 104 on the left end.

[0081] Reference Figure 3 and Figure 4 , Figure 3 A sectional view of another semiconductor structure provided by an embodiment of the present application is shown in FIG. 3, which is based on the embodiments shown in FIGS. 1A-1C and FIGS. 2A-2C. Figure 4 As shown in the semiconductor structure shown in FIG. 3, the first masking layer 106 and the second masking layer 107 both contact the first source region 104 on one side and have a spacing from the first source region 104 on the other side. Figure 3 As shown in the semiconductor structure shown in FIG. 3, the first masking layer 106 and the second masking layer 107 both contact the first source region 104 on one side and have a spacing from the first source region 104 on the other side. Figure 1 and Figure 2 the difference between the mode shown in FIG. 3 and the mode shown in FIGS. 1A-1C and FIGS. 2A-2C is that, Figure 3 and Figure 4 in the semiconductor structure shown in FIG. 3, the first masking layer 106 and the second masking layer 107 respectively contact the first source region 104 on different sides.

[0082] In Figure 3 and Figure 4In the illustrated configuration, for the first masking layer 106 and the second masking layer 107 between two adjacent first source regions 104, the first masking layer 106 is in contact with the first source region 104 adjacent to the right, and the second masking layer 107 is in contact with the first source region 104 adjacent to the left. In other configurations, for the first masking layer 106 and the second masking layer 107 between two adjacent first source regions 104, the second masking layer 107 may be configured to contact the first source region 104 adjacent to the right, and the first masking layer 106 may be in contact with the first source region 104 adjacent to the left.

[0083] When the first masking layer 106 and the second masking layer 107 contact the sidewalls of adjacent first source regions 104 to achieve grounding, a plurality of first source regions 104 are spaced apart in the first direction X. The first masking layer 106 and the second masking layer 107 are disposed opposite each other in the second direction Z. The first direction X is parallel to the plane of the substrate 100. The second direction Z is perpendicular to the plane of the substrate 100. Between two adjacent first source regions 104, as shown... Figure 4 As shown, both the first masking layer 106 and the second masking layer 107 include multiple sub-regions 113 spaced apart along a third direction Y. The third direction Y is parallel to the plane containing the substrate 100 and perpendicular to the first direction X. The sub-regions 113 of the first masking layer 106 and the second masking layer 107 are arranged opposite each other in the third direction Y.

[0084] refer to Figures 5-7 , Figure 5 This is a top view of a semiconductor structure in the second epitaxial layer provided in an embodiment of this application. Figure 6 for Figure 5 The diagram shows a cross-sectional view of the semiconductor structure along the A-A' direction. Figure 7 for Figure 5 The cross-sectional view of the semiconductor structure shown is along the B-B' direction. Based on other embodiments, Figures 5-7 In the semiconductor structure shown, for the first masking layer 106 and the second masking layer 107 between two adjacent first source regions 104, both ends of the first masking layer 106 and the second masking layer 107 are spaced from the adjacent first source region 104; the second epitaxial layer 102 has a ground doped region 111 connecting the first masking layer 106 and the second masking layer 107.

[0085] exist Figures 5-7In the semiconductor structure shown, the first mask layer 106 and the second mask layer 107 are not grounded through the first source region 104, and are connected with the ground doped region 111 and grounded through the ground doped region 111. The ground doped region 111 is in an integrated structure with the first mask layer 106 and the second mask layer 107, and the top surface of the ground doped region 111 is located at the top surface of the second epitaxial layer 102, so as to facilitate grounding through the corresponding metal electrode at the top surface of the second epitaxial layer 102.

[0086] Optionally, in Figures 5-7 In the semiconductor structure shown, the first mask layer 106 and the second mask layer 107 each include a plurality of strip-shaped doped regions 112 arranged at intervals along a first direction X, the first direction X being parallel to the plane in which the substrate 100 lies; in a second direction Z, the strip-shaped doped regions 112 of the first mask layer 106 are opposite to the strip-shaped doped regions 112 of the second mask layer 107, the second direction Z being perpendicular to the plane in which the substrate 100 lies; and in the second direction Z, the two strip-shaped doped regions 112 opposite to each other are connected through a plurality of ground doped regions 111 arranged at intervals along a third direction Y.

[0087] In Figures 5-7 In the semiconductor structure shown, along the third direction Y, the first mask layer 106 and the second mask layer 107 are continuous integrated structures, which can further improve the voltage resistance performance of the device.

[0088] Optionally, the strip-shaped doped regions 112 of the first mask layer 106 and the second mask layer 107 opposite to each other are arranged opposite to the trench gate 105, and the ground doped regions 111 extend from the sidewall of the trench gate 105 to the top surface of the second epitaxial layer 102. The strip-shaped doped regions 112 of the first mask layer 106 and the second mask layer 107 can not only be connected and grounded through the ground doped regions 111, but also surround the trench gate 105 through the ground doped regions 111 connecting the first mask layer 106 and the second mask layer 107, so as to further improve the voltage resistance performance of the gate oxide layer 110 in the trench gate 105 and prevent the gate oxide layer 110 from being broken down.

[0089] In some embodiments of the embodiments of the present application, as shown in any one of Figure 1 , Figure 3 , Figure 6 and Figure 7 , the bottom surface of the electric field modulation region 103 and the bottom surface of the first epitaxial layer 101 have a spacing therebetween.

[0090] Referring to Figure 8 , Figure 8 , another sectional view of a semiconductor structure provided by the embodiments of the present application is provided on the basis of the other embodiments, Figure 8In the shown semiconductor structure, the bottom surface of the electric field modulation region 103 is located at the bottom surface of the first epitaxial layer 101, and the bottom surface of the electric field modulation region 103 is electrically connected with the substrate 100.

[0091] In some embodiments of the present application, as shown in any of Figure 1 , Figure 3 , Figures 6-8 The bottom surface of the first source region 104 is spaced apart from the bottom surface of the second epitaxial layer 102.

[0092] Referring to Figure 9 , Figure 9 In some embodiments of the present application, as shown in any of Figure 9 the bottom surface of the first source region 104 extends to the bottom surface of the second epitaxial layer 102, and is in contact with the top surface of the electric field modulation region 103.

[0093] In some embodiments of the present application, as shown in any of Figure 9 the electric field modulation region 103 is electrically connected with the first source region 104, and can be grounded through the first source region 104, so that the device has better switching characteristics.

[0094] In some embodiments of the present application, as shown in any of Figure 1 , Figure 3 , Figures 6-9 In the direction perpendicular to the plane on which the substrate 100 is located, the electric field modulation region 103 at least partially overlaps with the first source region 104. In the second direction Z, the electric field modulation region 103 and the first source region 104 are one-to-one opposite.

[0095] In some embodiments of the present application, as shown in any of Figure 10 , Figure 10 In some embodiments of the present application, as shown in any of Figure 10 In the direction perpendicular to the plane on which the substrate 100 is located, the electric field modulation region 103 does not overlap with the first source region 104. In the second direction Z, the electric field modulation region 103 and the first source region 104 are misaligned. In the first direction X, there is one electric field modulation region 103 between two adjacent first source regions 104, and there is one first source region 104 between two adjacent electric field modulation regions 103.

[0096] In some embodiments of the present application, as shown in any of Figure 11 , Figure 11 In some embodiments of the present application, as shown in any of Figure 11In the semiconductor structure shown, the trench gate 105 includes two levels of trenches; the first masking layer 106 is located below the trench gate 105 and is in contact with the bottom of the trench gate 105; the second masking layer 107 is located below the steps of the two levels of trenches, and the top surface of the second masking layer 107 can be in contact with the bottom of the steps.

[0097] exist Figure 11 In the illustrated configuration, along the third direction Y, both the first masking layer 106 and the second masking layer 107 can include multiple spaced sub-regions, and both the first masking layer 106 and the second masking layer 107 can be connected to the sidewall of the first source region 104 adjacent to one side.

[0098] As described above, in the semiconductor structure provided in this application embodiment, a first source region 104 is provided in the first epitaxial layer 101, and a superjunction structure can be formed in the first epitaxial layer 101. The first epitaxial layer 101 with the superjunction structure serves as the breakdown layer of the device. A trench gate 105, two source regions, a well region 108, and two masking layers are formed in the second epitaxial layer 102, thereby forming the switching structure of the device in the second epitaxial layer 102.

[0099] Based on the semiconductor structure provided in the above embodiments, another embodiment of this application provides a preparation method for preparing the semiconductor structure provided in any of the above embodiments. This preparation method can be as follows: Figures 12-17 As shown.

[0100] refer to Figures 12-17 , Figures 12-17 This application provides a method for fabricating a semiconductor structure, illustrating the device structure at different process steps. The fabrication method includes:

[0101] Step S11: As Figure 12 As shown, a first epitaxial layer 101 is formed on one side surface of the substrate 100.

[0102] Step S12: As Figure 13 As shown, an electric field modulation region 103 is formed within the first epitaxial layer 101, with its top surface located on the top surface of the first epitaxial layer 101; the doping type of the electric field modulation region 103 is opposite to that of the first epitaxial layer 101. In this step, the electric field modulation region 103 can be formed by ion implantation, trenching, or filling with doped material.

[0103] Step S13: As Figure 14 As shown, a second epitaxial layer 102 is formed on the surface of the first epitaxial layer 101 facing away from the substrate 100.

[0104] Step S14: As Figures 15-17As shown, the first source region 104, the first mask layer 106, the second mask layer 107 and the trench gate 105 are formed in the second epitaxial layer 102.

[0105] The top surface of the trench gate 105 and the top surface of the first source region 104 are located at the top surface of the second epitaxial layer 102; the doping type of the first source region 104 is opposite to the doping type of the second epitaxial layer 102; the doping type of the first mask layer 106 and the second mask layer 107 is the same and opposite to the doping type of the second epitaxial layer 102; the first mask layer 106 is located between the second mask layer 107 and the bottom surface of the second epitaxial layer 102, and the first mask layer 106 and the second mask layer 107 have a spacing.

[0106] Optionally, in step S14, the first source region 104, the first mask layer 106, the second mask layer 107 and the trench gate 105 are formed in the second epitaxial layer 102, including:

[0107] First, as shown in FIG. 1, the first source region 104, the first mask layer 106 and the second mask layer 107 are formed in the second epitaxial layer 102 by an ion implantation process; in this step, the second source region 109 and the well region 108 can also be formed in the second epitaxial layer 102 by an ion implantation process. Figure 15 Then, as shown in FIG. 2, the trench 115 is formed in the surface of the second epitaxial layer 102 by an etching process, and then, as shown in FIG. 3, the trench gate 105 is formed based on the trench 115. When the trench gate 105 is formed in the trench 115, the gate oxide layer 110 is first formed on the surface of the trench 115, and then the polysilicon is filled in the trench with the gate oxide layer 110. Finally, the back electrode 114 is formed on the other side surface of the substrate 100, and the semiconductor structure as shown in FIG. 4 is formed.

[0108] Figure 16 Figure 17 Figure 10

[0109] In the preparation method as shown in FIG. 1, the semiconductor structure as shown in FIG. 4 is prepared as an example for illustration, and the preparation methods of the semiconductor structures of other embodiments in the above embodiments can be prepared based on the same process principle, and the embodiments of the present application will not be described separately. Figures 12-17 Figure 10 In the semiconductor structure prepared by the preparation method provided in the embodiments of the present application, not only the super-junction structure can be formed in the first epitaxial layer 101, but also the triple electric field shielding structure can be formed by the first source region 104 and the two mask layers in the second epitaxial layer, so that the strong electric field influence of the high-concentration doped region in the super-junction structure on the gate oxide layer 110 is solved by the triple electric field shielding structure, and the reliability of the device is improved.

[0110] In the semiconductor structure prepared by the preparation method provided in the embodiments of the present application, not only the super-junction structure can be formed in the first epitaxial layer 101, but also the triple electric field shielding structure can be formed by the first source region 104 and the two mask layers in the second epitaxial layer, so that the strong electric field influence of the high-concentration doped region in the super-junction structure on the gate oxide layer 110 is solved by the triple electric field shielding structure, and the reliability of the device is improved. ​​​​​

[0111] In addition, since the two layers of mask layers in the second epitaxial layer 102 are opposite to the doping type of the second epitaxial layer 102, the two layers of mask layers spaced apart in the second epitaxial layer 102 can also have a certain super-junction effect, changing the electric field distribution in the second epitaxial layer 102, thereby improving the breakdown voltage of the device.

[0112] Reference Figure 18 , Figure 18 The semiconductor structure provided in the embodiment of the present application has electric field curves at different positions. Figure 18 In the figure, the left graph is a semiconductor structure as shown in the figure, and the right graph is an electric field curve of the semiconductor structure at different positions in the second direction Z. In the figure, the thick dashed line electric field curve is an electric field curve of the semiconductor structure as shown in the figure, and the solid line is an electric field curve of the semiconductor structure after removing the two layers of mask layers. In the right graph, the horizontal axis is an electric field E, and the vertical axis is a different depth H relative to the second epitaxial layer 102. The area enclosed between the electric field curve and the vertical axis represents the voltage resistance of the device. By comparing the two electric field curves, it can be seen that the two layers of mask layers arranged in the second epitaxial layer 102 can improve the voltage resistance. Figure 1 Figure 1 In the figure, the left graph is a semiconductor structure as shown in the figure, and the right graph is an electric field curve of the semiconductor structure at different positions in the second direction Z. In the figure, the thick dashed line electric field curve is an electric field curve of the semiconductor structure as shown in the figure, and the solid line is an electric field curve of the semiconductor structure after removing the two layers of mask layers. In the right graph, the horizontal axis is an electric field E, and the vertical axis is a different depth H relative to the second epitaxial layer 102. The area enclosed between the electric field curve and the vertical axis represents the voltage resistance of the device. By comparing the two electric field curves, it can be seen that the two layers of mask layers arranged in the second epitaxial layer 102 can improve the voltage resistance. Figure 18

[0113] Reference Figure 19 , Figure 19 The top view of the electric field modulation region in the semiconductor structure provided in the embodiment of the present application is based on the other embodiments, and the semiconductor structure as shown in the figure has a plurality of electric field modulation regions 103 arranged in a dot array in the first epitaxial layer 101. Figure 19 In the semiconductor structure as shown in the figure, the electric field modulation region 103 is a strip-shaped unit 116 extending in the third direction Y. A plurality of strip-shaped units 116 are arranged at intervals along the first direction X. Optionally, along the first direction X, there is a trench gate 105 between any two adjacent strip-shaped units 116.

[0114] Reference Figure 20 , Figure 20 The top view of the electric field modulation region in another semiconductor structure provided in the embodiment of the present application is based on the other embodiments, and the semiconductor structure as shown in the figure has a plurality of electric field modulation regions 103 arranged in a dot array in the first epitaxial layer 101. Figure 20 In the semiconductor structure as shown in the figure, the first epitaxial layer 101 has a plurality of electric field modulation regions 103 arranged in a dot array. The electric field modulation region 103 can be any one of a rectangular structure, a circular structure, a triangular structure, and a regular polygon structure. Optionally, there is a column of electric field modulation regions 103 arranged at intervals along the third direction Y between any two adjacent strip-shaped units 116.

[0115] The embodiments in the specification of the present application are described in a progressive, or parallel, or progressive and parallel combination manner. Each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other. The embodiments provided in the embodiments of the present application can be combined with each other without contradiction. ​​

[0116] It is to be understood that the drawings and description are illustrative of exemplary embodiments and are not intended to be limiting. Like numbers in different drawings identify the same, similar, or corresponding elements. Additionally, for the purpose of understanding the descriptions of the drawings, it can be that the thicknesses of some layers, films, panels, regions, etc. have been exaggerated or have been drawn in an exaggerated manner. It is also to be understood that, whenever terms like "on", "under", "right", "left", "over", "below", "upper" and "lower" are used, they are used for convenience and are to be understood only in the context of the illustrations under discussion. None of these additional terms modify or change the meaning of the words, phrases or terms used to describe the subject application except in the instances of clearly defined words or phrases.

[0117] The terms "on", "under", "top", "bottom", "inner", "outer" and the like, indicate relative positions for purposes of illustration and description and are not meant to limit or confine the scope of the application to only the positions specified within the description of the illustrative embodiments nor is it meant to limit or confine the scope of the application to only the positions that are described in the claims. When one component is said to be "connected" to another component it can be directly connected to the other component or intervening components can be present.

[0118] It is also to be understood that the terminology and phraseology employed herein are for the purpose of description and illustration and are not of limitation. The use of terms such as first and second do not connote any priority, but rather the terms serve only to distinguish one component from another. As well, the use of "including", "containing", or "comprising" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless otherwise indicated herein, the use of relational terms and / or adjectives such as "one", "approximately", "about", and the like are used broadly and encompass substantially identical and / or equivalent conditions.

[0119] The above description of disclosed embodiments provides information sufficient to understand how to make and use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without the use of the innovation falling outside the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a first epitaxial layer on one side surface of the substrate; a plurality of electric field modulation regions in the first epitaxial layer, the top surface of the electric field modulation regions being on the top surface of the first epitaxial layer; the electric field modulation regions being opposite to the doping type of the first epitaxial layer; a second epitaxial layer on the side of the first epitaxial layer away from the substrate; the second epitaxial layer being the same as the doping type of the first epitaxial layer; a trench gate and a first source region in the second epitaxial layer, the top surface of the trench gate and the first source region being on the top surface of the second epitaxial layer; the doping type of the first source region being opposite to the doping type of the second epitaxial layer; a first mask layer and a second mask layer in the second epitaxial layer; wherein the doping type of the first mask layer and the second mask layer is the same, and opposite to the doping type of the second epitaxial layer; the first mask layer is between the second mask layer and the bottom surface of the second epitaxial layer, and the first mask layer and the second mask layer have a spacing.

2. The semiconductor structure of claim 1, wherein, The first mask layer and the second mask layer are both between the trench gate and the bottom surface of the second epitaxial layer, and the top surface of the second mask layer is in contact with the bottom of the trench gate. Or, the trench gate comprises two-stage trenches. The first mask layer is below the trench gate and in contact with the bottom of the trench gate; the second mask layer is below the step of the two-stage trenches.

3. The semiconductor structure of claim 1, wherein, The depth of the first source region is greater than the depth of the trench gate. The semiconductor structure comprises at least two first source regions; between two adjacent first source regions, there are the trench gate, the first mask layer and the second mask layer; the first mask layer and the second mask layer are both in contact with the first source region adjacent to one side, and both have a spacing with the first source region adjacent to the other side. Or, both ends of the first mask layer and the second mask layer have a spacing with the first source region adjacent to one side; the second epitaxial layer has a ground doping region connecting the first mask layer and the second mask layer.

4. The semiconductor structure of claim 3, wherein, For the first mask layer and the second mask layer between two adjacent first source regions, the first mask layer and the second mask layer are both in contact with the first source region adjacent to the same side, or the first mask layer and the second mask layer are respectively in contact with the first source region adjacent to different sides.

5. The semiconductor structure of claim 3, wherein, The first mask layer and the second mask layer each comprise a plurality of strip-shaped doping regions arranged at intervals in a first direction, the first direction being parallel to the plane in which the substrate lies; in a second direction, the strip-shaped doping regions of the first mask layer and the strip-shaped doping regions of the second mask layer are opposite to each other, the second direction being perpendicular to the plane in which the substrate lies; The two strip-shaped doping regions opposite to each other in the second direction are connected by a plurality of ground doping regions arranged at intervals in a third direction.

6. The semiconductor structure of claim 1, wherein, The bottom surface of the electric field modulation region has a spacing with the bottom surface of the first epitaxial layer, or the bottom surface of the electric field modulation region is on the bottom surface of the first epitaxial layer.

7. The semiconductor structure of claim 1, wherein, The bottom surface of the first source region has a spacing from the bottom surface of the second epitaxial layer, or the bottom surface of the first source region extends to the bottom surface of the second epitaxial layer and contacts the top surface of the electric field modulation region.

8. The semiconductor structure of claim 1, wherein, The electric field modulation region at least partially overlaps the first source region in a direction perpendicular to the plane in which the substrate lies, or the electric field modulation region does not overlap the first source region.

9. A method of producing a semiconductor structure as claimed in any one of claims 1-8, characterized in that The method comprises: forming a first epitaxial layer on one side surface of a substrate; forming an electric field modulation region in the first epitaxial layer, the top surface of the electric field modulation region being located at the top surface of the first epitaxial layer; the electric field modulation region is opposite to the doping type of the first epitaxial layer; forming a second epitaxial layer on the side surface of the first epitaxial layer away from the substrate; forming a first source region, a first masking layer, a second masking layer and a trench gate in the second epitaxial layer; the top surface of the trench gate and the top surface of the first source region are located at the top surface of the second epitaxial layer; the doping type of the first source region is opposite to the doping type of the second epitaxial layer; the doping type of the first masking layer and the second masking layer is the same and opposite to the doping type of the second epitaxial layer; the first masking layer is located between the bottom surface of the second masking layer and the second epitaxial layer, and the first masking layer has a spacing from the second masking layer.

10. The method of claim 9, wherein, forming a first source region, a first masking layer, a second masking layer and a trench gate in the second epitaxial layer comprises: forming the first source region, the first masking layer and the second masking layer in the second epitaxial layer by an ion implantation process; forming a trench in the surface of the second epitaxial layer by an etching process, and forming a trench gate based on the trench.

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