Dynamic grid for augmented reality (AR) glasses

Abstract

An apparatus has a power management integrated circuit (PMIC) that includes a number of power sources. The apparatus also has a power multiplexer that is coupled to each of the power sources. The device is further provided with a plurality of core devices. At least one of the core devices is coupled to the power multiplexer to receive power from at least one of the power sources. The apparatus has a machine learning model configured to control the selection of the power sources based on the current utilization of each of the power sources and the amount of current consumed by the core device.

Description

Cross Reference to Related Applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 363,462, filed August 1, 2023, entitled “DYNAMIC POWER GRID FOR AUGMENTED REALITY (AR) GLASSES,” the disclosure of which is expressly incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure generally relates to a dynamic power grid for a wearable device, such as an augmented reality (AR) glasses, for power optimization. BACKGROUND

[0003] Augmented reality (AR) merges the real world with virtual objects to support a reality, smart, and personalized experience. Conventional augmented reality applications provide a real-time view of a real-world environment, the elements of which can be augmented by computer-generated sensory inputs, such as video, sound, graphics, or global positioning system (GPS) data. With such applications, the reality view can be modified by a computing device to enhance a user’s perception of reality and provide more information about the user’s environment. Virtual reality (VR) simulates physical presence in a real or imagined world and enables a user to interact within that world. Implementing AR and VR requires implementing next-level artificial intelligence (AI) and connectivity within the thermal envelope and power envelope of a wearable device, such as glasses. SUMMARY

[0004] Aspects of the present disclosure relate to an apparatus. The apparatus has a power management integrated circuit (PMIC) comprising a number of power sources. The apparatus also has a power multiplexer coupled to each of the power sources. The apparatus further has a number of core devices. At least one of the core devices is coupled to the power multiplexer to receive power from at least one of the power sources. The apparatus has a machine learning model configured to control selection of each of the power sources based on a current utilization of the power source and an amount of power consumed by the at least one core device.

[0005] In other aspects of the disclosure, a method for multiplexing power for augmented reality (AR) glasses includes receiving, at a machine learning model, a first input. The first input includes a current limit for each of a number of power sources coupled to a power multiplexer and a current drawn from each of the power sources. The method also includes receiving, at the machine learning model, a second input. The second input includes an amount of power specified for a core device coupled to the power multiplexer. The method further includes controlling, by the machine learning model, the multiplexer to select at least one of the number of power sources based on the current limit for each of the power sources, the current drawn from each of the power sources, and the amount of power specified for the core device.

[0006] Other aspects of the disclosure relate to an apparatus. The apparatus includes means for receiving, at a machine learning model, a first input. The first input includes a current limit for each of a number of power sources coupled to a power multiplexer and a current drawn from each of the power sources. The apparatus also includes means for receiving, at the machine learning model, a second input. The second input includes an amount of power specified for a core device coupled to the power multiplexer. The apparatus further includes means for controlling, by the machine learning model, the multiplexer to select at least one of the power sources based on the current limit for each of the power sources, the current drawn from each of the power sources, and the amount of power specified for the core device.

[0007] In another aspect of the disclosure, a non-transitory computer-readable medium having program code recorded thereon is disclosed. The program code is executed by a processor and includes program code to receive, at a machine learning model, a first input including a current limit for each of a number of power sources coupled to a power multiplexer and a current drawn from each of the power sources. The program code also includes program code to receive, at the machine learning model, a second input including an amount of power specified for a core device coupled to the power multiplexer. The program code further includes program code to control, by the machine learning model, the multiplexer to select at least one of the power sources based on the current limit for each of the power sources, the current drawn from each of the power sources, and the amount of power specified for the core device.

[0008] These and other features and advantages of the present disclosure will be more readily understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: It should, of course, be understood that the description and specific examples, while indicating certain embodiments of the disclosure, are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0009] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

[0010] Figure 1 An example implementation of a system on chip (SoC) is illustrated.

[0011] Figure 2 is a block diagram illustrating an example content generation and coding system for implementing an extended reality (XR) or virtual reality (VR) application in accordance with various aspects of the present disclosure.

[0012] Figure 3 is a block diagram illustrating an augmented reality or virtual reality subsystem in accordance with various aspects of the present disclosure.

[0013] Figure 4 is a diagram illustrating the location of components in a wearable device having a glasses form factor in accordance with various aspects of the present disclosure.

[0014] Figure 5A , Figure 5B and Figure 5C is a diagram illustrating a neural network in accordance with various aspects of the present disclosure.

[0015] Figure 5D is a diagram illustrating an example deep convolutional network (DCN) in accordance with various aspects of the present disclosure.

[0016] Figure 6 is a block diagram illustrating an example deep convolutional network (DCN) in accordance with various aspects of the present disclosure.

[0017] Figure 7 is a block diagram illustrating an example software architecture that can modularize artificial intelligence (AI) functionality in accordance with various aspects of the present disclosure.

[0018] Figure 8 is a diagram illustrating an augmented reality printed circuit board (PCB) according to various aspects of the present disclosure.

[0019] Figure 9 is a diagram illustrating a constraint of an augmented reality printed circuit board (PCB) according to various aspects of the present disclosure.

[0020] Figure 10 is a diagram illustrating an augmented reality power grid.

[0021] Figure 11A is a diagram illustrating an augmented reality power grid with additional phases.

[0022] Figure 11B is a diagram illustrating a dynamic power grid according to aspects of the present disclosure.

[0023] Figure 12A is a diagram illustrating an augmented reality power grid with additional phases.

[0024] Figure 12B is a diagram illustrating a dynamic power grid with power multiplexers according to various aspects of the present disclosure.

[0025] Figure 13 is a diagram illustrating a dynamic power grid with machine learning controlled power multiplexers according to various aspects of the present disclosure.

[0026] Figure 14 is a diagram illustrating a dynamic power grid for switching between power sources under overload conditions according to various aspects of the present disclosure.

[0027] Figure 15 is a diagram illustrating a dynamic power grid for switching between power sources to reduce power consumption according to various aspects of the present disclosure.

[0028] Figure 16 is a diagram illustrating a dynamic power grid for switching between power sources of a power collapse core according to various aspects of the present disclosure.

[0029] Figure 17 is a diagram illustrating a dynamic power grid for switching between power sources to reduce power consumption according to various aspects of the present disclosure.

[0030] Figure 18 is a flow diagram illustrating a dynamic power control method according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0031] Various aspects of systems, apparatuses, computer program products, and methods will be described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosed systems, apparatuses, computer program products, and methods, whether implemented as individual aspects or in combination with other aspects. For example, the apparatus can be implemented using any number of the aspects described. In addition, the scope of the disclosure is intended to cover such apparatuses or methods which are practiced using, as complementary or additional to the aspects of the disclosure described, other structure, functionality, or structure and functionality. Any aspect disclosed can be embodied by one or more elements of a claim.

[0032] While various aspects have been described, many variations and permutations of these aspects fall within the scope of the disclosure. Although some potential benefits and advantages of aspects of the disclosure have been mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and description below. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

[0033] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in the detailed description that follows, in reference to the drawings, and with reference to the appended claims. Elements of the described aspects can be implemented in electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

[0034] For example, an element, or any portion of an element, or any combination of elements can be implemented as a "processing system" that includes one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SoC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system can execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application can be used to refer to software. As described, one or more techniques can refer to an application (e.g., software) configured to perform one or more functions. In such examples, the application can be stored on memory (e.g., on-chip memory of a processor, system memory, or any other memory). The described hardware, such as a processor, can be configured to execute the application. For example, the application can be described as including code that, when executed by the hardware, causes the hardware to perform one or more of the described techniques. As an example, the hardware can access the code from memory and execute the code accessed from memory to perform one or more of the described techniques. In some examples, components are identified in the disclosure. In such examples, a component can be hardware, software, or a combination thereof. Components can be separate components or sub-components of a single component.

[0035] Accordingly, in one or more described examples, the functions described can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise a random-access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), compact disk ROM (CD-ROM), diskette, a hard disk drive, magnetic tape, other magnetic media, a flash memory, other solid-state memories, or any other medium that can be used to store desired computer instructions or data in a form accessible by a computer.

[0036] In general, this disclosure describes techniques for integrating subsystems or modules that are located on physically separate printed circuit boards (PCBs). For example, an augmented reality or virtual reality (AR / VR) device can have modules that are physically remote from each other. However, the present disclosure is equally applicable to any type of system having modules or PCBs that are spaced apart but electrically connected (e.g., with flexible cables, flexible PCBs, coaxial cables, rigid PCBs, etc.). In some aspects, these solutions integrate at least one slave subsystem with a master subsystem by implementing all control and status monitoring functions between the at least one slave subsystem and the master subsystem. For example, certain bidirectional functions can be implemented between the master subsystem and the slave subsystem, such as power-on triggers, reset triggers, shutdown triggers, fault propagation, and fail-safe reset triggers.

[0037] As used, the term "coder" can refer generally to an encoder and / or a decoder. For example, a reference to a "content coder" can include a reference to a content encoder and / or a content decoder. Similarly, as used, the term "coding" can refer generally to encoding and / or decoding. As used, the terms "encoding" and "compression" can be used interchangeably. Similarly, the terms "decoding" and "decompression" can be used interchangeably.

[0038] As used, examples of the term "content" can refer to the terms "video," "graphics content," "image," and vice versa. This is true regardless of whether the terms are used as adjectives, nouns, or other parts of speech. For example, a reference to a "content coder" can include a reference to a "video coder," a "graphics content coder," or an "image coder," and a reference to a "video coder," a "graphics content coder," or an "image coder" can include a reference to a "content coder." As another example, a reference to a processing unit providing content to a content coder can include a reference to the processing unit providing graphics content to a video encoder. In some examples, the term "graphics content" can refer to content produced by one or more processes of a graphics processing pipeline. In some examples, the term "graphics content" can refer to content produced by a processing unit configured to perform graphics processing. In some examples, the term "graphics content" can refer to content produced by a graphics processing unit.

[0039] Examples of the term "content" can refer to graphics content or display content. In some examples, the term "graphics content" can refer to content generated by a processing unit configured to perform graphics processing. For example, the term "graphics content" can refer to content generated by one or more processes of a graphics processing pipeline. In some examples, the term "graphics content" can refer to content generated by a graphics processing unit. In some examples, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. In some examples, the term "display content" can refer to content generated by a display processing unit. Graphics content can be processed to become display content. For example, a graphics processing unit can output graphics content, such as a frame, to a buffer (which can be referred to as a frame buffer). A display processing unit can read graphics content, such as one or more frames, from the buffer and perform one or more display processing techniques on the display processing unit to generate display content. For example, a display processing unit can be configured to perform compositing on one or more render layers to generate a frame. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers together into a single frame. A display processing unit can be configured to perform scaling (e.g., zooming in or out) on a frame. In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form the frame (e.g., the frame includes two or more layers, and the frame including the two or more layers can subsequently be blended).

[0040] As referenced, a first component (e.g., a processing unit) can provide content, such as graphics content, to a second component (e.g., a content translator). In some examples, a first component can provide content to a second component by storing the content in a memory that is accessible to the second component. In such examples, the second component can be configured to read the content stored in the memory by the first component. In other examples, a first component can provide content to a second component without any intermediary components (e.g., without a memory or another component). In such examples, the first component can be described as providing content directly to the second component. For example, a first component can output content to a second component, and the second component can be configured to store the content received from the first component in a memory, such as a buffer.

[0041] For mobile devices such as mobile phones, a single printed circuit (PCB) can support multiple components including CPUs, GPUs, DSPs, etc. For augmented reality (AR) or virtual reality (VR) devices, due to the form factor of the AR or VR device, these components can be located on different PCBs. For example, the AR or VR device can be in the form of glasses. In example implementations, a primary SoC (also referred to as a primary processor) and a primary power management integrated circuit (PMIC) can reside on a first PCB in one arm of the glasses. A camera and sensor coprocessor and associated PMIC can reside on a second PCB near the glasses bridge. A connectivity processor and associated PMIC can reside on a third PCB on the other arm of the glasses.

[0042] To achieve wider market adoption, augmented reality (AR) glasses should be lightweight and have a small form factor (e.g., a sleek form factor). In fact, original equipment manufacturers (OEMs) can specify maximum size limits to achieve a sleek form factor. However, a small form factor limits the chip count, chip package size, battery size, and battery capacity. The printed circuit board (PCB) inside the side arms of the AR glasses determines the overall product size. The primary system on chip (SoC) and power management integrated circuit (PMIC) package size determines the overall PCB size on each arm of the AR glasses. To achieve the size target, only one PMIC with associated passive devices can be placed on the PCB due to the Y dimension limit. Although primarily discussed for AR glasses, the present disclosure is applicable to any type of wearable or hearable device such as a smart watch, fitness tracker, or earbuds.

[0043] For next generation augmented reality chips, the SoC feature set is increasing. However, the PCB size specifications are very tight. In fact, the SoC package size specifications will decrease over time, forcing the PMIC size to decrease. As the feature set increases, the power consumption of each core device and associated power rail will increase accordingly, which in turn requires additional power supplies or regulators. To provide more regulators, either multiple PMICs are added or a larger single PMIC is introduced. Both of these solutions increase the Y dimension of the PCB, which is detrimental to the goal of achieving a sleek glass.

[0044] Another solution is to throttle the core devices to limit the peak current instead of adding PMICs. However, this solution negatively impacts the user experience. Lower power consumption would improve the user experience by allowing lower battery capacity, resulting in a smaller size. Another option to achieve a small battery with lower power consumption is to split each rail into multiple rails, which again increases the regulator requirement and PCB area. It is desirable to be able to deliver the specified peak current at low power consumption without increasing the number of regulators and PCB area to achieve full performance.

[0045] According to aspects of the present disclosure, during peak current loading on a particular rail or from a particular core device, current capacity from underutilized power supplies is used instead of adding more power supplies. In some aspects, a multiplexer (MUX) is employed for power distribution. By using a power MUX, a load can draw current from different regulators based on which regulator can supply the full current specified by the load.

[0046] According to aspects of the present disclosure, machine learning facilitates MUX switching. Since there can be many regulators that are underloaded at any point, a machine learning module decides which regulator is best suited to deliver current at a given point in time. The machine learning module can accept multiple inputs and select a regulator for delivering the specified peak current.

[0047] According to aspects of the present disclosure, full performance is achieved with a reduced number of power supply rails. In existing systems, when peak current exceeds the power supply limit, either additional power supplies are provided or performance is throttled to keep the peak current within the limit. Instead of throttling the cores, the techniques of the present disclosure intelligently power the cores to achieve full performance without additional regulators. With the proposed techniques, unused power from various power supplies will be used to power the cores to achieve full performance.

[0048] According to aspects of the present disclosure, a power model is employed as part of machine learning for controlling MUX switching. In a shared rail system, each core can specify a different operating voltage. If one core on a power rail specifies a higher voltage, all cores on the same rail will run at the higher voltage, impacting power consumption. If a core moves from a higher voltage supply to a lower voltage supply, improved power efficiency can be achieved. According to the voltage requirements of each core, a core power supply can be moved to an underloaded power supply or a power supply with a lower voltage to reduce the impact of days of use (DoU). Aspects of the present disclosure use a power MUX to dynamically switch cores to lower voltage power supplies to achieve lower power consumption.

[0049] According to further aspects of the present disclosure, a minimum point sleep current (RBSC) saving can be achieved by moving cores that do not need to be powered to an off supply. In a shared rail system, even though one of the cores can be powered off, there will be a leakage current since the main rail is kept at a minimum voltage to preserve data. Switching the collapsible rail to an off supply can provide an RBSC saving.

[0050] Particular aspects of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In some examples, the described techniques for dynamic power management can be used for sleek form factor AR and VR designs, or any wearable or hearable device design. Advantages of the proposed solution include elimination of additional power planes for powering cores with higher feature sets. Thus, the PCB area does not increase even with increased capacity. Further, full performance of the cores is achieved without using extreme management or adding additional planes, thereby preventing negative impact on user experience. Additionally, power improvements enable smaller batteries. In a shared rail system, power multiplexing can enable lower power consumption by switching cores to low voltage power supply. Minimum point sleep current (RBSC) can be reduced by moving cores that stay on in system on chip (SoC) sleep to an off power supply.

[0051] Figure 1 An example implementation of a system on chip (SoC) 100 on a single printed circuit board (PCB) is illustrated. The host SoC 100 includes processing blocks customized for particular functions, such as a connectivity block 110. The connectivity block 110 can include fifth generation (5G) new radio (NR) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth ® connectivity, secure digital (SD) connectivity, and the like.

[0052] In this configuration, the SoC 100 includes various processing units that support multi-threaded operations. For example, the SoC 100 can include a multi-core central processing unit (CPU) 102, a graphics processor unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processor unit (NPU) 108. Figure 1 For the illustrated configuration, the SoC 100 includes a multi-core CPU 102, a GPU 104, a DSP 106, and an NPU 108. The SoC 100 can also include a sensor processor 114, an image signal processor (ISP) 116, a navigation module 120, which can include a global positioning system, and a memory 118. The multi-core CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions, such as video, audio, graphics, extended reality (XR) gaming, artificial networks, and the like. Each processor core of the multi-core CPU 102 can be a reduced instruction set computing (RISC) machine, an advanced RISC machine (ARM), a microprocessor, or some other type of processor. The NPU 108 can be based on an ARM instruction set.

[0053] Figure 2is a block diagram illustrating an example extended reality (XR) or virtual reality (VR) system 200 configured to implement an extended reality (XR) or virtual reality (VR) application in accordance with aspects of the present disclosure. The system 200 includes a source device 202 and a destination device 204. In accordance with the described techniques, the source device 202 can be configured to encode graphical content generated by a processing unit 206 using a content encoder 208 prior to transmission to the destination device 204. The content encoder 208 can be configured to output a bitstream having a bit rate. The processing unit 206 can be configured to control and / or influence the bit rate of the content encoder 208 based on how the processing unit 206 generates the graphical content.

[0054] The source device 202 can include one or more components (or circuits) for performing the various functions described herein. The destination device 204 can include one or more components (or circuits) for performing the various functions described. In some examples, one or more components of the source device 202 can be components of a system on a chip (SoC). Similarly, in some examples, one or more components of the destination device 204 can be components of a SoC.

[0055] The source device 202 can include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the source device 202 can include a processing unit 206, a content encoder 208, a system memory 210, and a communication interface 212. The processing unit 206 can include an internal memory 209. The processing unit 206 can be configured to perform graphics processing, such as in a graphics processing pipeline 207-1. The content encoder 208 can include an internal memory 211.

[0056] Memory external to the processing unit 206 and the content encoder 208, such as the system memory 210, can be accessible to the processing unit 206 and the content encoder 208. For example, the processing unit 206 and the content encoder 208 can be configured to read from and / or write to the external memory, such as the system memory 210. The processing unit 206 and the content encoder 208 can be communicatively coupled to the system memory 210 by a bus. In some examples, the processing unit 206 and the content encoder 208 can be communicatively coupled to each other by the bus or a different connection.

[0057] The content encoder 208 can be configured to receive graphical content from any source, such as the system memory 210 and / or the processing unit 206. The system memory 210 can be configured to store graphical content generated by the processing unit 206. For example, the processing unit 206 can be configured to store graphical content in the system memory 210. The content encoder 208 can be configured to receive graphical content in the form of pixel data (e.g., from the system memory 210 and / or the processing unit 206). Described otherwise, the content encoder 208 can be configured to receive pixel data of graphical content produced by the processing unit 206. For example, the content encoder 208 can be configured to receive a value of each component (e.g., each color component) of one or more pixels of the graphical content. As an example, a pixel in a red, green, blue (RGB) color space can include a first value for a red component, a second value for a green component, and a third value for a blue component.

[0058] The internal memory 209, the system memory 210, and / or the internal memory 211 can include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 209, the system memory 210, and / or the internal memory 211 can include random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data media or an optical storage media, or any other type of memory.

[0059] According to some examples, the internal memory 209, the system memory 210, and / or the internal memory 211 can be a non-transitory storage medium. The term “non-transitory” can indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that the internal memory 209, the system memory 210, and / or the internal memory 211 are inoperative or that their contents are static. As one example, the system memory 210 can be removed from the source device 202 and moved to another device. As another example, the system memory 210 can not be removable from the source device 202.

[0060] The processing unit 206 can be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 206 can be integrated into a motherboard of the source device 202. In some examples, the processing unit 206 can be present on a graphics card that is installed in a port of the motherboard of the source device 202, or can be otherwise incorporated within a peripheral device that is configured to interoperate with the source device 202.

[0061] The processing unit 206 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, a processing unit 206 can store instructions for the software in a suitable, non- transitory computer-readable storage medium (e.g., an internal memory 209) and execute the instructions in hardware to implement the techniques of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered one or more processors.

[0062] The content encoder 208 can be any processing unit configured to perform content encoding. In some examples, the content encoder 208 can be integrated into a motherboard of the source device 202. The content encoder 208 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder 208 can store instructions for the software in a suitable, non-transitory computer-readable storage medium (e.g., an internal memory 211) and execute the instructions in hardware to implement the techniques of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered one or more processors.

[0063] The communication interface 212 can include a receiver 214 and a transmitter 216. The receiver 214 can be configured to perform any receiving functions described with respect to the source device 202. For example, the receiver 214 can be configured to receive information from the destination device 204, which can include a request for content. In some examples, in response to receiving the request for content, the source device 202 can be configured to perform one or more techniques described, such as generating or otherwise producing graphical content for delivery to the destination device 204. The transmitter 216 can be configured to perform any transmitting functions described herein with respect to the source device 202. For example, the transmitter 216 can be configured to transmit encoded content, such as encoded graphical content produced by the processing unit 206 and the content encoder 208 (e.g., the graphical content was produced by the processing unit 206, the content encoder 208 received the graphical content as input to produce or otherwise generate the encoded graphical content), to the destination device 204. The receiver 214 and the transmitter 216 can combine into a transceiver 218. In such examples, the transceiver 218 can be configured to perform any receiving functions and / or transmitting functions described with respect to the source device 202.

[0064] The destination device 204 can include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the destination device 204 can include a processing unit 220, a content decoder 222, a system memory 224, a communication interface 226, and one or more displays 231. Reference to the display 231 can refer to one or more displays 231. For example, the display 231 can include a single display or multiple displays. The display 231 can include a first display and a second display. The first display can be a left eye display and the second display can be a right eye display. In some examples, the first display and the second display can receive different frames for presentation on the first display and the second display. In other examples, the first display and the second display can receive the same frames for presentation on the first display and the second display.

[0065] The processing unit 220 can include internal memory 221. The processing unit 220 can be configured to perform graphics processing, such as in the graphics processing pipeline 207-2. The content decoder 222 can include internal memory 223. In some examples, the destination device 204 can include a display processor, such as display processor 227, to perform one or more display processing techniques on one or more frames generated by the processing unit 220 prior to being rendered by one or more displays 231. The display processor 227 can be configured to perform display processing. For example, the display processor 227 can be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 220. The one or more displays 231 can be configured to display content generated using decoded content. For example, the display processor 227 can be configured to process one or more frames generated by the processing unit 220, where the one or more frames are generated by the processing unit 220 by using decoded content derived from encoded content received from the source device 202. In turn, the display processor 227 can be configured to perform display processing on the one or more frames generated by the processing unit 220. The one or more displays 231 can be configured to display or otherwise render the frames processed by the display processor 227. In some examples, the one or more display devices can include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0066] Memory external to the processing unit 220 and the content decoder 222, such as system memory 224, can be accessible to the processing unit 220 and the content decoder 222. For example, the processing unit 220 and the content decoder 222 can be configured to read from and / or write to the external memory, such as system memory 224. The processing unit 220 and the content decoder 222 can be communicatively coupled to the system memory 224 by a bus. In some examples, the processing unit 220 and the content decoder 222 can be communicatively coupled to each other by the bus or a different connection.

[0067] The content decoder 222 can be configured to receive graphics content from any source, such as system memory 224 and / or communication interface 226. The system memory 224 can be configured to store received encoded graphics content, such as encoded graphics content received from the source device 202. The content decoder 222 can be configured to receive encoded graphics content in the form of encoded pixel data (e.g., from system memory 224 and / or communication interface 226). The content decoder 222 can be configured to decode the encoded graphics content.

[0068] The internal memory 221, system memory 224, and / or internal memory 223 can include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 221, system memory 224, and / or internal memory 223 can include random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data medium, or an optical storage medium, or any other type of memory.

[0069] According to some examples, the internal memory 221, system memory 224, and / or internal memory 223 can be non-transitory storage media. The term “non-transitory” can indicate that the storage media is not embodied in a carrier wave or a propagating signal. However, the term “non-transitory” should not be interpreted to mean that the internal memory 221, system memory 224, and / or internal memory 223 are inoperative or that their contents are static. As one example, the system memory 224 can be removed from the destination device 204 and moved to another device. As another example, the system memory 224 can not be removable from the destination device 204.

[0070] The processing unit 220 can be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 220 can be integrated into a motherboard of the destination device 204. In some examples, the processing unit 220 can be present on a graphics card that is installed in a port of the motherboard of the destination device 204, or can be otherwise incorporated within a peripheral device that is configured to interoperate with the destination device 204.

[0071] The processing unit 220 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, a processor - such as the processing unit 220 - can store instructions for the software in suitable, non- transitory computer-readable storage media (e.g., internal memory 221) and execute the instructions in hardware to perform the techniques of this disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered a processor.

[0072] The content decoder 222 can be any processing unit configured to perform content decoding. In some examples, the content decoder 222 can be integrated into a motherboard of the destination device 204. The content decoder 222 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content decoder 222 can store instructions for the software in a suitable, non- transitory computer-readable storage medium (e.g., the internal memory 223) and can execute the instructions in hardware to perform the techniques of this disclosure. Any of the aforementioned

[0073] The communication interface 226 can include a receiver 228 and a transmitter 230. The receiver 228 can be configured to perform any receiving functions described herein for the destination device 204. For example, the receiver 228 can be configured to receive information from the source device 202, which can include encoded content, such as encoded graphical content produced or otherwise generated by the processing unit 206 and the content encoder 208 of the source device 202 (e.g., the graphical content was produced by the processing unit 206, which the content encoder 208 received as input to produce or otherwise generate the encoded graphical content). As another example, the receiver 228 can be configured to receive position information from the source device 202, which can be encoded or unencoded (e.g., not encoded). In some examples, the destination device 204 can be configured to decode encoded graphical content received from the source device 202 in accordance with the techniques described herein. For example, the content decoder 222 can be configured to decode the encoded graphical content to produce or otherwise generate decoded graphical content. The processing unit 220 can be configured to use the decoded graphical content to produce or otherwise generate one or more frames for presentation on one or more displays 231. The transmitter 230 can be configured to perform any transmitting functions described herein for the destination device 204. For example, the transmitter 230 can be configured to transmit information to the source device 202, which can include a request for content. The receiver 228 and the transmitter 230 can be combined into a transceiver 232. In such examples, the transceiver 232 can be configured to perform any receiving functions and / or transmitting functions described herein for the destination device 204.

[0074] The content encoder 208 and content decoder 222 of the XR gaming system 200 represent examples of computing components (e.g., processing units) that can be configured to perform one or more techniques for encoding and decoding content, respectively, according to various examples described in this disclosure. In some examples, the content encoder 208 and content decoder 222 may be configured to operate according to content decoding standards, such as video decoding standards, display streaming compression standards, or image compression standards.

[0075] like Figure 2 As shown, source device 202 can be configured to generate encoded content. Therefore, source device 202 can be referred to as a content encoding device or content encoding apparatus. Destination device 204 can be configured to decode the encoded content generated by source device 202. Therefore, destination device 204 can be referred to as a content decoding device or content decoding apparatus. In some examples, source device 202 and destination device 204 can be separate devices, as shown. In other examples, source device 202 and destination device 204 can be on the same computing device, or can be part of the same computing device. In any example, the graphics processing pipeline can be distributed between the two devices. For example, a single graphics processing pipeline can include multiple graphics processes. Graphics processing pipeline 207-1 can include one or more of the multiple graphics processes. Similarly, graphics processing pipeline 207-2 can include one or more of the multiple graphics processes. In this respect, graphics processing pipeline 207-1, cascaded with graphics processing pipeline 207-2 or otherwise configured as graphics processing pipeline 207-2, can produce a complete graphics processing pipeline. Alternatively, graphics processing pipeline 207-1 can be a partial graphics processing pipeline, and graphics processing pipeline 207-2 can be a partial graphics processing pipeline; when combined, they produce a distributed graphics processing pipeline.

[0076] In some examples, the graphics processing performed in graphics processing pipeline 207-1 can not be performed or otherwise repeated in graphics processing pipeline 207-2. For example, graphics processing pipeline 207-1 can include receiving first position information corresponding to a first orientation of a device. Graphics processing pipeline 207-1 can also include generating first graphics content based on the first position information. Additionally, graphics processing pipeline 207-1 can include generating motion information for warping the first graphics content. Graphics processing pipeline 207-1 can also include encoding the first graphics content. Additionally, graphics processing pipeline 207-1 can include providing the motion information and the encoded first graphics content. Graphics processing pipeline 207-2 can include providing first position information corresponding to a first orientation of a device. Graphics processing pipeline 207-2 can also include receiving encoded first graphics content generated based on the first position information. Further, graphics processing pipeline 207-2 can include receiving motion information. Graphics processing pipeline 207-2 can also include decoding the encoded first graphics content to generate decoded first graphics content. Additionally, graphics processing pipeline 207-2 can include warping the decoded first graphics content based on the motion information. By distributing the graphics processing pipeline between source device 202 and destination device 204, the destination device can be able to present, in some examples, graphics content that it would otherwise not be able to render, and thus present. Other example benefits are described throughout this disclosure.

[0077] As described, a device, such as source device 202 and / or destination device 204, can refer to any device, apparatus, or system configured to perform one or more of the described techniques. For example, a device can be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), an end product, an appliance, a telephone, a smartphone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smartwatch, an augmented reality device, or a virtual reality device), a non-wearable device, an augmented reality device, a virtual reality device, a display (e.g., a display device), a television, a television set-top box, an intermediary network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more of the techniques described herein.

[0078] Source device 202 can be configured to communicate with destination device 204. For example, destination device 204 can be configured to receive encoded content from source device 202. In some examples, the communicative coupling between source device 202 and destination device 204 is shown as a link 234. Link 234 can include any type of medium or device capable of moving the encoded content from source device 202 to destination device 204.

[0079] In Figure 2 In examples where link 234 includes a communication medium, source device 202 can be configured to transmit encoded content to destination device 204 in real-time. The encoded content can be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 204. The communication medium can comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium can form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium can include routers, switches, base stations, or any other equipment that can be useful to facilitate communication from source device 202 to destination device 204. In other examples, link 234 can be a point-to-point connection between source device 202 and destination device 204, such as a wired or wireless display link connection (e.g., a High-Definition Multimedia Interface (HDMI) link, a DisplayPort link, a Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) link, or another link through which encoded content can traverse from source device 202 to destination device 204).

[0080] In another example, link 234 can include a storage medium configured to store encoded content generated by source device 202. In this example, destination device 204 can be configured to access the storage medium. The storage medium can include various local access data storage media such as Blu-ray discs, DVDs, CD-ROMs, flash memory, or other suitable digital storage media for storing encoded content.

[0081] In another example, link 234 can include a server or another intermediate storage device configured to store encoded content generated by source device 202. In this example, destination device 204 can be configured to access encoded content stored at the server or other intermediate storage device. The server can be a type of server capable of storing encoded content and transmitting the encoded content to destination device 204.

[0082] The described devices, such as source device 202 and destination device 204, can be configured to communicate with one another. Communication can include transmission and / or reception of information. Information can be carried in one or more messages. As an example, a first device in communication with a second device can be described as communicatively coupled to the second device or otherwise communicatively coupled with the second device. For example, a client device and a server can be communicatively coupled. As another example, a server can be communicatively coupled to multiple client devices. As another example, any of the described devices configured to perform one or more techniques of the present disclosure can be communicatively coupled to one or more other devices configured to perform one or more techniques of the present disclosure. In some examples, when communicatively coupled, two devices can actively transmit or receive information, or can be configured to transmit or receive information. If not communicatively coupled, any two devices can be configured to communicatively couple with one another, such as according to one or more communication protocols that comply with one or more communication standards. A reference to “any two devices” does not mean that only two devices can be configured to communicatively couple with one another; rather, any two devices includes more than two devices. For example, a first device can be communicatively coupled with a second device, and the first device can be communicatively coupled with a third device. In this example, the first device can be a server.

[0083] Reference Figure 2The source device 202 can be described as being communicatively coupled to the destination device 204. In some examples, the term "communicatively coupled" can refer to a communication connection, which can be direct or indirect. In some examples, the link 234 can represent a communicative coupling between the source device 202 and the destination device 204. The communication connection can be wired and / or wireless. A wired connection can refer to a conductive path, trace, or physical medium through which information can travel (excluding wireless physical mediums). A conductive path can refer to any conductor of any length, such as a conductive pad, conductive via, conductive plane, conductive trace, or any conductive medium. A direct communication connection can refer to a connection in which no intermediate components reside between two communicatively coupled components. An indirect communication connection can refer to a connection in which at least one intermediate component resides between two communicatively coupled components. Two devices that are communicatively coupled can communicate with each other over one or more different types of networks (e.g., wireless networks and / or wired networks) according to one or more communication protocols. In some examples, two devices that are communicatively coupled can associate with each other through an association procedure. In other examples, two devices that are communicatively coupled can communicate with each other without engaging in an association procedure. For example, a device such as the source device 202 can be configured to unicast, broadcast, multicast, or otherwise send information (e.g., encoded content) to one or more other devices (e.g., one or more destination devices, including the destination device 204). The destination device 204 in this example can be described as being communicatively coupled to each of the one or more other devices. In some examples, a communication connection can enable transmission and / or reception of information. For example, a first device communicatively coupled to a second device can be configured to transmit information to and / or receive information from the second device according to the techniques of this disclosure. Similarly, the second device in this example can be configured to transmit information to and / or receive information from the first device according to the techniques of this disclosure. In some examples, the term "communicatively coupled" can refer to a temporary, intermittent, or permanent communication connection.

[0084] Any of the described devices, such as the source device 202 and the destination device 204, can be configured to operate in accordance with one or more communication protocols. For example, the source device 202 can be configured to communicate (e.g., receive information from and / or send information to) with the destination device 204 using one or more communication protocols. In such examples, the source device 202 can be described as communicating with the destination device 204 over a connection. The connection can comply or otherwise conform to the communication protocol(s). Similarly, the destination device 204 can be configured to communicate (e.g., receive information from and / or send information to) with the source device 202 using one or more communication protocols. In such examples, the destination device 204 can be described as communicating with the source device 202 over a connection. The connection can comply or otherwise conform to the communication protocol(s).

[0085] The term “communication protocol” can refer to any communication protocol, such as a communication protocol that complies with a communication standard, etc. As used herein, the term “communication standard” can include any communication standard, such as a wireless communication standard and / or a wired communication standard. A wireless communication standard can correspond to a wireless network. As an example, a communication standard can include any wireless communication standard corresponding to a wireless personal area network (WPAN) standard, such as Bluetooth (e.g., IEEE 802.15), Bluetooth Low Energy (BLE) (e.g., IEEE 802.15.4). As another example, a communication standard can include any wireless communication standard corresponding to a wireless local area network (WLAN) standard, such as WI-FI (e.g., any 802.11 standard, such as 802.11a, 802.11b, 802.11c, 802.11n, or 802.11ax). As another example, a communication standard can include any wireless communication standard corresponding to a wireless wide area network (WWAN) standard, such as 3G, 4G, 4G LTE, 5G, or 6G.

[0086] With reference to Figure 2Content encoder 208 can be configured to encode graphical content. In some examples, content encoder 208 can be configured to encode the graphical content as one or more video frames of extended reality (XR) or virtual reality (VR) content. When content encoder 208 encodes content, content encoder 208 can generate a bitstream. The bitstream can have a bit rate, such as bits per time unit, where the time unit is any unit of time, such as seconds or minutes. The bitstream can include a sequence of bits that forms a coded representation of the graphical content and associated data. To generate the bitstream, content encoder 208 can be configured to perform encoding operations on pixel data, such as pixel data corresponding to a shadow texture atlas. For example, when content encoder 208 performs encoding operations on image data provided as input to content encoder 208 (e.g., one or more blocks of a shadow texture atlas), content encoder 208 can generate a series of coded images and associated data. The associated data can include a set of coding parameters, such as quantization parameters (QPs).

[0087] As shown in Figure 1 A single printed circuit (PCB) can support multiple components of SoC 100, including CPU 102, GPU 104, DSP 106, and the like. For AR or VR devices, these components can be located on different PCBs. Figure 3 is a block diagram illustrating an augmented reality or virtual reality subsystem in accordance with aspects of the present disclosure. As seen in the example of Figure 3 Destination device 204 can be in the form of glasses, and source device 202 can be in the form of a mobile device, as seen in the example of Due to the separate locations of PCBs 302, 304, 306, the length of connectors between PCBs 302, 304, 306 can exceed design specifications. Moreover, the connectors can be arranged in a multi-point configuration, which also impedes performance due to stubs and reflections. Flexible PCBs can also be used between PCBs 302, 304, 306, which can further impact signal integrity.

[0088] Figure 4 is a diagram illustrating placement of components in a device with a glasses form factor in accordance with aspects of the present disclosure. As seen in the example of Figure 4As seen in the example of FIG. 3, the host SoC 308 and host power management IC (PMIC) 310 can reside on a first PCB 302 (also referred to as a CCA circuit card assembly) in one arm of the glasses, the camera and sensor co-processor 312 and associated PMIC 314 can reside on a second PCB 304 on the glasses bridge, and the connectivity processor 316 and associated PMIC 318 can reside on a third PCB 306 on the other arm of the glasses. The locations of the battery and speaker are also shown in FIG. 3. Board-to-board (B2B) flexible printed circuit (FPC) connectors 402 couple the first, second, and third PCBs 302, 304, and 306 across the hinges 404 (only one labeled) of the glasses. Throughout this disclosure, the augmented reality chip can be referred to as “Aurora.” Figure 4

[0089] Due to the small form factor of the device, small PCBs are provided, and thus there is small PCB area availability. Signal integrity can be impacted due to the signals traveling across the hinges. Furthermore, long channels (e.g., up to 20-25 cm from one arm of the glasses to the other) and channels over flexible cables with high insertion loss can cause high-speed signals, such as system power management interface (SPMI) protocol signals, to have signal integrity issues. The small form factor of the glasses dictates small board-to-board connectors. The small size places strict constraints on the wires that pass through the hinges. For example, the number of signals that can be communicated across the hinges can be limited. Furthermore, the small volume of the glasses frame constrains the trace thickness, which limits the sharing of power rails across the subsystems.

[0090] According to aspects of the present disclosure, machine learning techniques can be used for dynamic power grids. In some implementations, neural networks can be employed. The connections between layers of a neural network can be fully connected, or locally connected. Figure 5A An example of a fully connected neural network 502 is illustrated. In the fully connected neural network 502, a neuron in a first layer can communicate its output to every neuron in a second layer, such that every neuron in the second layer will receive input from every neuron in the first layer. Figure 5B An example of a locally connected neural network 504 is illustrated. In the locally connected neural network 504, a neuron in a first layer can be connected to a limited number of neurons in a second layer. More generally, locally connected layers of a locally connected neural network 504 can be configured such that every neuron in a layer will have the same or similar connectivity pattern, but the connection strengths can have different values (e.g., 510, 512, 514, and 516). The locally connected connectivity pattern can result in spatially distinct receptive fields in higher layers, as higher layer neurons in a given region can receive input that is tuned through training to characteristics of a restricted portion of the total input to the network.​

[0091] One example of a locally connected neural network is a convolutional neural network. Figure 5C An example of a convolutional neural network 506 is illustrated. The convolutional neural network 506 can be configured such that the connection strengths associated with the inputs to each neuron in a second layer are shared (e.g., 508). Convolutional neural networks can be well suited for problems in which the spatial location of the inputs is meaningful.

[0092] One type of convolutional neural network is a deep convolutional network (DCN). Figure 5D A detailed example of a DCN 500 designed to recognize visual features from an image 526 input by an image capture device 530, such as a vehicle-mounted camera, is illustrated. The DCN 500 of the current example can be trained to identify traffic signs and the numbers provided on the traffic signs. Of course, the DCN 500 can be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0093] The DCN 500 can be trained using supervised learning. During training, the DCN 500 can be presented with an image, such as the image 526 of a speed limit sign, and a forward pass can then be computed to produce an output 522. The DCN 500 can include a feature extraction portion and a classification portion. Upon receiving the image 526, a convolutional layer 532 can apply convolutional kernels (not shown) to the image 526 to generate a first set of feature maps 518. As an example, the convolutional kernels for the convolutional layer 532 can be 5x5 kernels that generate 28x28 feature maps. In the present example, four different convolutional kernels are applied to the image 526 at the convolutional layer 532 since four different feature maps are generated in the first set of feature maps 518. The convolutional kernels can also be referred to as filters or convolutional filters.

[0094] The first set of feature maps 518 can be sub-sampled by a max-pooling layer (not shown) to generate a second set of feature maps 520. The max-pooling layer reduces the size of the first set of feature maps 518. That is, the size of the second set of feature maps 520, such as 14x14, is smaller than the size of the first set of feature maps 518, such as 28x28. The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 520 can be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0095] In Figure 5DIn the example of FIG. 5, a second set of feature maps 520 is convolved to generate a first feature vector 524. In addition, the first feature vector 524 is further convolved to generate a second feature vector 528. Each feature of the second feature vector 528 can include a number corresponding to a possible feature of the image 526, such as "sign," "60," and "100." A softmax function (not shown) can convert the numbers in the second feature vector 528 into probabilities. As such, the output 522 of the DCN 500 can be the probabilities that the image 526 includes one or more of the features.

[0096] In the present example, the probabilities for "sign" and "60" in the output 522 are higher than the probabilities of the other numbers (such as "30," "40," "50," "70," "80," "90," and "100") of the output 522. Prior to training, the output 522 produced by the DCN 500 can be incorrect. Thus, an error between the output 522 and a target output can be computed. The target output is the ground truth value of the image 526 (e.g., "sign" and "60"). The weights of the DCN 500 can then be adjusted so that the output 522 of the DCN 500 more closely aligns with the target output.

[0097] To adjust the weights, a learning algorithm can compute a gradient vector for the weights. The gradient can indicate the amount by which the error will increase or decrease if the weights are adjusted. At the top layer, the gradient can directly correspond to the value of the weight connecting the activation neuron in the penultimate layer and the neuron in the output layer. In lower layers, the gradient can depend on the value of the weight and the computed error gradient of the higher layer. The weight can then be adjusted to reduce the error. This way of adjusting the weights can be referred to as "backpropagation" because it involves a "backward pass" through the neural network.

[0098] In practice, the error gradient for the weights can be computed over a small number of examples so that the computed gradient approximates the true error gradient. This approximation method can be referred to as stochastic gradient descent. The stochastic gradient descent can be repeated until the achievable error rate of the overall system stops decreasing or until the error rate reaches a target level. After learning, the DCN 500 can be presented with new images and the forward pass through the DCN 500 can produce an output 522 that can be considered an inference or prediction of the DCN 500.

[0099] A deep belief network (DBN) is a probabilistic model that includes multiple layers of hidden nodes. DBNs can be used to extract a hierarchical representation of a training dataset. DBNs can be obtained by stacking layers of restricted Boltzmann machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution without information about the class to which each input should be classified, RBMs are often used for unsupervised learning. Using a mixed paradigm of supervised and unsupervised learning, the bottom RBMs of a DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBMs can be trained in a supervised manner (on the joint distribution of inputs from the previous layer and target classes) and can be used as a classifier.

[0100] A deep convolutional network (DCN) is a network of convolutional networks configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning, where both input targets and output targets are known for many examples and are used to modify the weights of the network by using a gradient descent method.

[0101] A DCN can be a feedforward network. Furthermore, as described above, connections from a neuron in a first layer of a DCN to a group of neurons in a next higher layer are shared across the neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational burden of a DCN can be much less than that of a similar-sized neural network that includes recurrent or feedback connections.

[0102] The processing of each layer of a convolutional network can be thought of as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then a convolutional network trained on that input can be thought of as three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The output of a convolutional connection can be viewed as forming a feature map in the next layer, where each element in the feature map (e.g., 520) receives input from a range of neurons in the previous layer (e.g., feature map 518) and from each of the multiple channels. The values in the feature map can be further processed with a nonlinearity, such as a rectification, max(0, x). Values from neighboring neurons can be further pooled, which corresponds to downsampling, and can provide additional local invariance and dimensionality reduction. Normalization, corresponding to whitening, can also be applied through lateral inhibition between neurons in the feature map.

[0103] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are typically trained with computing resources that are thousands of times the computing resources available to a typical researcher just fifteen years ago. New architectures and training paradigms can further boost the performance of deep learning. Rectified linear units can reduce a training problem known as vanishing gradients. New training techniques can reduce overfitting and thus enable larger models to achieve better generalization. Encapsulation techniques can extract data in a given receptive field and further improve overall performance.

[0104] Figure 6 is a block diagram illustrating a deep convolutional network (DCN) 650. The DCN 650 can include multiple different types of layers based on connectivity and weight sharing. As shown, the DCN 650 includes convolutional blocks 654A, 654B. Each of the convolutional blocks 654A, 654B can be configured with a convolutional layer (CONV) 656, a normalization layer (LNorm) 658, and a max pooling layer (MAX POOL) 660. Although only two of the convolutional blocks 654A, 654B are shown, the present disclosure is not so limited and any number of convolutional blocks 654A, 654B can be included in the DCN 650 according to design preference. Figure 6

[0105] The convolutional layer 656 can include one or more convolutional filters that can be applied to input data to generate a feature map. The normalization layer 658 can normalize the output of the convolutional filters. For example, the normalization layer 658 can provide whitening or lateral inhibition. The max pooling layer 660 can provide a spatially down-sampling aggregation to achieve local invariance and dimensionality reduction.

[0106] For example, a parallel filter bank of a deep convolutional network can be loaded onto the CPU 102 or GPU 104 of the SoC 100 (e.g., to achieve high performance and low power consumption). In alternative embodiments, the parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SoC 100. Further, the DCN 650 can access other processing blocks that can be present on the SoC 100 (e.g., the sensor processor 114 and the navigation module 120 that are specialized for sensors and navigation, respectively). Figure 1

[0107] ​​The DCN 650 can also include one or more fully connected layers 662 (FC1 and FC2). The DCN 650 can also include a logistic regression (LR) layer 664. Between each layer 656, 658, 660, 662, 664 of the DCN 650 are weights (not shown) to be updated. The output of each of the layers (e.g., 656, 658, 660, 662, 664) can be used as input to a next one of the layers (e.g., 656, 658, 660, 662, 664) in the DCN 650 to learn hierarchical feature representations from input data 652 (e.g., images, audio, video, sensor data, and / or other input data) supplied at a first convolutional block of the convolutional blocks 654A. The output of the DCN 650 is a classification score 666 for the input data 652. The classification score 666 can be a set of probabilities, where each probability is a probability that the input data includes a feature in a set of features.

[0108] Figure 7 is a block diagram illustrating an example software architecture 700 that can modularize artificial intelligence (AI) functionality. Using the architecture 700, according to aspects of the present disclosure, various processing blocks of a SoC 720 (e.g., CPU 722, DSP 724, GPU 726, and / or NPU 728) can be designed to support power multiplexer control by AI applications 702. The architecture 700 may, for example, be included in a computing device such as a smartphone or AR glasses.

[0109] The AI applications 702 can be configured to call functions defined in a user space 704 that may, for example, provide detection and recognition of a scene that indicates a location at which the computing device (including the architecture 700) is currently operating. For example, the AI applications 702 can configure microphones and cameras differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI applications 702 can make a request for compiled program code associated with a library defined in an AI function application programming interface (API) 706. The request can ultimately rely on an output of a deep neural network configured to provide an inference response based on, for example, video and positioning data.

[0110] A runtime engine 708, which can be compiled code of a runtime framework, can further be accessible by the AI application 702. The AI application 702 can cause the runtime engine 708 to request inferences, for example, at specific time intervals or triggered by events detected by a user interface of the AI application 702. In causing the runtime engine 708 to provide inference responses, the runtime engine can in turn transmit signals to an operating system (such as a kernel 712) in an operating system (OS) space 710 running on the SoC 720. In some examples, the kernel 712 can be a LINUX kernel. The operating system can in turn cause continuous quantization relaxation to be performed on the CPU 722, DSP 724, GPU 726, NPU 428, or some combination thereof. The CPU 722 can be directly accessible by the operating system, while the other processing blocks can be accessed through drivers, such as drivers 714, 716, or 718 for the DSP 724, GPU 726, or NPU 728, respectively. In an example, a deep neural network can be configured to run on a combination of processing blocks, such as the CPU 722, DSP 724, and GPU 726, or can run on the NPU 728.

[0111] The AI application 702 can be configured to call functions defined in the user space 704, which can for example provide detection and recognition of a scene indicating a location at which the computing device, including the framework 700, is currently operating. For example, the application 702 can configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI application 702 can make a request to compiled program code associated with a library defined in a scene detection application programming interface (API) 706 to provide an estimate of the current scene. The request can ultimately rely on an output of a differential neural network configured to provide a scene estimate based on, for example, video and positioning data.

[0112] A runtime engine 708 (which may be compiled code of a runtime framework) may further be accessible to an application 702. The application 702 may cause the runtime engine 708 to request scene estimation, for example, at specific time intervals or triggered by events detected by the application's user interface. When causing the runtime engine 708 to estimate the scene, the runtime engine may then signal to an operating system 710 (such as kernel 712) running on the SoC 720. The operating system 710 may then enable computation to be performed on a CPU 722, DSP 724, GPU 426, NPU 728, or some combination thereof. The CPU 722 may be directly accessible by the operating system, and other processing blocks may be accessible via drivers (such as drivers 714-718 for the DSP 724, GPU 726, or NPU 728). In an exemplary example, a differential neural network may be configured to run on a combination of processing blocks (such as CPU 722 and GPU 726) or may run on the NPU 728.

[0113] To achieve wider market adoption, augmented reality (AR) glasses should be lightweight with a small form factor (e.g., a smooth form factor). In fact, original equipment manufacturers (OEMs) can specify maximum size limits to achieve a smooth form factor. However, a smooth form factor limits the number of chips, chip package size, battery size, and battery capacity. The printed circuit board (PCB) inside the side arms determines the overall product size. The package size of the main system-on-chip (SoC) and power management integrated circuit (PMIC) determines the overall PCB size on each arm. To achieve size targets, only one PMIC with associated passive devices can be placed on the PCB due to Y-size limits. Furthermore, lower power consumption improves the user experience by allowing for a lower battery capacity and a smaller battery as a result.

[0114] For next-generation augmented reality chips, SoC feature sets are increasing. However, PCB size specifications are very tight. In fact, SoC package sizes will decrease over time, forcing PMIC sizes to shrink. As feature sets increase, the power consumption of each core device and its associated power rails will increase accordingly, which in turn requires additional power supplies or regulators. To accommodate more regulators, either multiple PMICs are added or a larger single PMIC is introduced. Both solutions increase the Y-axis dimension of the PCB, which is detrimental to smooth glass.

[0115] Figure 8 This is an illustration of an augmented reality printed circuit board (PCB) according to various aspects of this disclosure. Figure 8In the example of FIG. 8, an augmented reality PMIC 802 (e.g., an Aurora PMIC) and an augmented reality SoC 804 (e.g., an Aurora SoC) are provided on a PCB 806.

[0116] Figure 9 is a diagram illustrating limitations of an augmented reality printed circuit board (PCB) in accordance with aspects of the disclosure. As Figure 9 As seen in the example of FIG. 8, due to space on the PCB being limited, an additional PMIC (PMIC2) cannot be placed on the PCB 806.

[0117] Instead of adding a PMIC, the core can be throttled to limit the peak current. However, throttling the core impacts the user experience. Another option to achieve lower power for a small battery is to split each rail into multiple rails, which again increases the regulator requirements and PCB area. It is desirable to provide the peak current required to achieve full performance at low power consumption without increasing the number of regulators and PCB area.

[0118] Figure 10 is a diagram illustrating an augmented reality power grid. In Figure 10 In the example of FIG. 10, the augmented reality power grid 1002 has some power supplies (e.g., switched mode power supplies (SMPS) or low dropout (LDO) regulators (not shown)) close to their current limits. The multimedia core device draws 4.5 amperes (A) from a second power supply S2, which has a 4.5 A limit. The neural signal processor (NSP) draws 4.2 A, close to the 4.5 A limit of a third power supply S3. The crashable memory rail (MXC) draws 3.8 A from a sixth power supply S6, close to its 4.5 A limit. Other power supplies are underutilized. The graphics core draws 1.8 A from a first power supply S1, which has a 4.5 A limit. The central processing unit (CPU) core draws 2.3 A from a fourth power supply S4, which has a 4.5 A limit. The always-on memory rail (MXA) draws 1.2 A from a fifth power supply S5, which has a 4.5 A limit. The core logic rail (CX) draws 2.4 A from a seventh power supply S7, which has a 4.5 A limit.

[0119] Although the term “core” is used primarily throughout the description, the term “rail” can be used interchangeably if the meaning of the sentence is not altered.

[0120] Augmented reality (AR) chips will see a generation upgrade in cores such as graphics cores, multimedia cores, NSP cores, and static random access memory (SRAM). Newer cores with higher performance require higher peak current, and thus multiple SMPS phases (or phases of another type of power supply) can be designated. More SMPS phases result in more PMICs or a single larger PMIC, resulting in a larger PCB area. AR power grid 1004 includes seven power supplies (e.g., buck regulators) in a first PMIC (PMICA) and three power supplies in a second PMIC (PMICB). Each power supply has a limit of 4.5 A. The fourth and fifth power supplies S4 and S5 and the second and third power supplies S2 and S3 in the first PMIC (PMICA) are dual-phase power supplies that provide 7 A and 6 A to NSP core devices and multimedia core devices, respectively. In the second PMIC (PMICB), the first and second power supplies S1 and S2 are dual-phase SMPS that provide 6 A to MXC. The first power supply S1 of the first PMIC (PMICA) and the third power supply S3 of the second PMIC (PMICB) provide 2.5 A to a graphics core and a CX rail, respectively. The sixth and seventh power supplies S6 and S7 provide 4 A and 2 A to a CPU core and an MXA rail, respectively. However, as stated above, additional phases and extra PMICs increase the size of the PCB, making it difficult to achieve a sleek form factor for wearable devices (e.g., AR glasses).

[0121] According to aspects of the disclosure, during peak current loading on a particular rail or from a particular core device, instead of adding more power supplies (e.g., like Figure 11A the SMPS phases shown), the current capacity from underutilized power supplies is used, as Figure 11B shown. Figure 11A is a diagram illustrating an augmented reality power grid with additional phases. Figure 11B is a diagram illustrating a dynamic power grid according to aspects of the disclosure. In Figure 11A the example of , power supplies S2 and S3 represent two phases that provide 6 A to camera cores and display cores of a multimedia rail. A graphics core and a CX rail each receive 2.5 A from first power supply S1 and fourth power supply S4, respectively.

[0122] In Figure 11B , a power multiplexer (MUX) 1102 is provided to select a power supply (e.g., SMPS phase or LDO regulator) to power a particular core / rail when the total peak current of all cores / rails exceeds the rated capacity. In Figure 11B the example of , power multiplexer 1102 selectively receives power as input from all three power supplies S1, S2, and S3. The output of power multiplexer 1102 is coupled to a camera core. In Figure 11BIn the example, the graphics core and CX track receive 2.5A from the first power supply S1 and the third power supply S3, respectively. The display core receives 4A from the second power supply S2. The camera core selectively receives a combination of 2.5A from the third power supply S3, 2.5A from the first power supply S1, and / or 2A from the second power supply S2.

[0123] In some scenarios, underutilized power supplies may exist. Based on utilization, the power multiplexer 1102 intelligently selects the correct power inputs S1, S2, and / or S3. Therefore, the power multiplexer control decision is based on a machine learning process that accepts multiple inputs, such as: the current load current of all power supplies, the current operating voltage of all power supplies, the specified core / rail voltage, and a usage days (DoU) (or power) model. The final power supply selection via the power multiplexer ensures that load current specifications are met and power is optimized. Because the MUX selection is based on a set of inputs, a machine learning model can be employed.

[0124] The advantages of the proposed solution include eliminating the need for additional power phases to power cores with higher feature sets. Therefore, the PCB area does not increase even with increased capacity. Furthermore, full core performance is achieved without using limit management or adding additional phases, preventing negative impacts on user experience. Additionally, power improvements enable smaller batteries. In shared-rail systems, power multiplexing allows for lower power consumption by switching cores to low-voltage power supplies. Minimum point sleep current (RBSC) can be reduced by moving cores that remain on during system-on-chip (SoC) sleep to off-power.

[0125] According to various aspects of this disclosure, a MUX is used for power distribution. Traditionally, additional power phases are added to meet load current requirements if the capacity of a single phase is insufficient. Figure 12A This is a diagram illustrating an augmented reality power grid with additional phases. Figure 12A In the example, the first power supply SMPS1 is limited to 5A and provides 3A to the first power domain (power domain A), which includes cores A, B, and C. The second power supply SMPS2 and the third power supply SMPS3 include additional SMPS phases, each limited to 5A. The second power supply SMPS2 and the third power supply SMPS3 provide 7A to the second power domain (power domain B, which includes cores X, Y, and Z). Although not shown, Figure 12A In this case, a limit management scheme can be adopted instead of using an additional phase to solve the current overload of the second power supply SMPS2 and the third power supply SMPS3.

[0126] By using a power MUX, a load can draw current from different regulators based on which regulator can supply the full current specified by the load.Figure 12B is a diagram illustrating a dynamic power grid with a power multiplexer according to aspects of the present disclosure. In Figure 12B In an example of, a power multiplexer (MUX) (also referred to as a power switch) 1202 is provided. The power MUX 1202 receives input from a first power supply SMPS 1 and a second power supply SMPS 2. The current required by the second power domain (power domain B) is 7A, which exceeds the 5A limit of the second power supply SMPS 2. The core X of the second power domain (power domain B) receives power via the power MUX 1202. The power MUX 1202 switches between the first power supply SMPS 1 and the second power supply SMPS 2 based on the peak current load. These aspects employ the power MUX 1202 to deliver the peak current requirement of the load by utilizing the underloaded SMPS and deliver the peak current requirement without adding additional phases.

[0127] According to aspects of the present disclosure, machine learning facilitates MUX switching. Since there can be many regulators that are underloaded at any point in time, the machine learning module decides which regulator is best suited to deliver the current at a given point in time. The machine learning module can accept multiple inputs and outputs that the regulators use to deliver the required peak current.

[0128] Figure 13 is a diagram illustrating a dynamic power grid with a power multiplexer with machine learning control according to aspects of the present disclosure. In Figure 13 In an example of, the power multiplexer 1302 receives a control signal from the machine learning module 1304. The machine learning module 1304 controls the MUX selection based on various inputs. Exemplary inputs to the machine learning module 1304 include the current voltage and current load of each regulator, core / rail current requirements, and a power model (e.g., a DoU model) for estimating power dissipation or advantage. The power model estimates the power consumed based on the current usage. The power MUX 1302 receives power from a power supply (e.g., a SMPS or LDO regulator (not shown)) in the PMIC 1306. In this example, the power MUX 1302 provides power to a first core (core A). The cores (core A, core B, core C, and core D) along with the machine learning module 1304 and the power MUX 1302 all reside in the SoC 1308 (e.g., an augmented reality SoC).

[0129] The constraints of the machine learning module 1304 can include meeting the peak current requirement. In addition, the DoU or power model impact should be minimal. In some examples, the machine learning module 1304 outputs a MUX selection signal.

[0130] According to aspects of the disclosure, full performance is achieved with a limited number of power supplies. In existing systems, when peak current exceeds the power limit, either additional power supplies are provided or performance is throttled to keep the peak current within the limit. Instead of throttling the cores, the techniques of the disclosure intelligently power the cores to achieve full performance without additional regulators. With the proposed techniques, the unused power supply power will be utilized to power the cores to achieve full performance.

[0131] Figure 14 is a diagram illustrating a dynamic power grid for switching between power supplies under overload conditions, in accordance with aspects of the disclosure. In Figure 14 In an example, three power supplies SMPS1, SMPS2, and SMPS3 each have a current limit of 5A. The camera core draws 2A, the video core draws 3A, and the display core draws 1A. Since the total current specified by the cores exceeds the 5A limit of the first power supply SMPS1, the camera core switches to either the second power supply SMPS2 or the third power supply SMPS3. The second power supply SMPS2 supplies 3A to the other rails, while the third power supply SMPS3 supplies 2.5A to the other rails. Thus, the second power supply SMPS2 and the third power supply SMPS3 are each underutilized.

[0132] According to aspects of the disclosure, a power model is employed as part of a machine learning model. In a shared rail system, each core can specify a different operating voltage. If one core on a power rail specifies a higher voltage, all cores on the same rail will run at the higher voltage, affecting the power consumption. If a core device moves from a higher voltage supply to a lower voltage supply, improved power efficiency can be achieved. According to the voltage requirements of each core, the core power supply can be moved to an underloaded power supply or a power supply with a lower voltage to reduce the DoU impact. Aspects of the disclosure use a power MUX to dynamically switch the cores to lower voltage power supplies to achieve lower power consumption.

[0133] Figure 15 is a diagram illustrating a dynamic power grid for switching between power supplies to reduce power consumption, in accordance with aspects of the disclosure. In Figure 15 In an example, the multimedia rail requires 0.8V, which is the agreed voltage for the associated power supply based on the maximum specification of all individual cores on the multimedia power rail. In Figure 15 In an example, the camera core operates at 0.8V, while the video core and the display core operate at 0.75V and 0.65V, respectively. By moving the camera core to another power supply that operates at 0.8V, the voltage of the first power supply SMPS1 can be reduced to 0.75V. In Figure 15In the example, the second power supply SMPS2 and the third power supply SMPS3 operate at 0.8V and 0.9V, respectively. Therefore, both the second power supply SMPS2 and the third power supply SMPS3 are candidates for powering the camera rail.

[0134] According to another aspect of this disclosure, minimum point sleep current (RBSC) savings can be achieved by moving cores that do not require power to a power-off state. In shared-rail systems, even if one of these cores is de-energized, leakage current will exist because the primary rail is kept at a minimum voltage to retain data (e.g., reserve voltage). Switching the faulty rail to a power-off state can provide RBSC savings.

[0135] Figure 16 This is a diagram illustrating a dynamic power grid for switching between power sources at a power failure core, according to various aspects of this disclosure. Figure 16 In the example, the CX rail operates at 0.5V, which is a convention voltage for the first power supply SMPS1 based on the maximum specified voltage of all cores associated with the CX rail. If the video core and display core enter sleep mode and therefore operate at 0V in their lowest point sleep (RBS) mode, the camera core can be moved to another power supply operating at 0.5V or higher. Therefore, the first power supply SMPS1 can be turned off to conserve RBS current.

[0136] Now about Figure 11B Describe the example operation. In this example, the multimedia peak current exceeds the 4.5A limit. That is, when operating concurrently with the display core (drawing 4A) and the camera core (drawing 2A), the multimedia core requires 6A. The second power supply S2 has a capacity of 4.5A. Instead of introducing an additional phase to meet the current specifications, a smart power MUX 1102 is added, which accepts inputs from the power supplies S1, S2, and S3 already available in the PMIC. When a multimedia-intensive usage scenario is triggered, if the estimated load current exceeds the 4.5A power supply limit, the machine learning module (e.g., Figure 13 As shown in 1304, the system decides to switch the camera core's input from the second power supply S2 to either the first power supply S1 or the third power supply S3. Both the first power supply S1 and the third power supply S3 have sufficient capacity to meet the 2A current requirement from the camera core. Depending on the current operating conditions and the voltages of the first and third power supplies S1 and S3, the machine learning module switches to one of them. It can be assumed that the first power supply S1 operates at 0.7V, the third power supply S3 operates at 0.9V, and the camera core requires 0.65V. Under these assumptions, the machine learning module switches the camera core power supply to the first power supply S1 because it provides the required current at the lowest required voltage. Full performance of the multimedia core is achieved without any throttling of the core.

[0137] Another example operation will now be described with respect to Figure 11B Another example operation will now be described with respect to Figure 11B In the example, it can be assumed that there is no peak current load on any power supply due to the particular use case. It can also be assumed that the camera core requires 0.9V to operate and the display core requires only 0.75V. The second power supply S2 operates at 0.9V, therefore, the display core power consumption increases the power consumption of the entire SoC. If the first power supply S1 or the third power supply S3 operates at 0.9V or higher voltage, then the camera core can switch to the first power supply S1 or the third power supply S3. The second power supply voltage can be reduced to 0.75V, which is required by the display core. Therefore, the power consumption of the display core is optimal. The power consumption of the camera core is continuously monitored and the core switches between power supplies S1, S2, or S3 depending on which power supply provides the best power benefit.

[0138] Another example operation will now be described with respect to Figure 17 Another example operation will now be described with respect to

[0139] Figure 17 is a diagram illustrating a dynamic power grid for switching between power supplies to reduce power consumption in accordance with aspects of the present disclosure. In Figure 17 In this example, core B and core C share the same rail. In this example, core A and core B can be turned off in RBS mode, while core C needs to remain on. Since core C is on, core B will also remain on, thus increasing leakage. By utilizing the power MUX 1702 to move core B to the first power supply S1, which is off, the RBSC is reduced.

[0140] Figure 18 is a flowchart illustrating a dynamic power control method in accordance with aspects of the present disclosure. As Figure 18As shown, in some aspects, the process 1800 can include receiving, at the machine learning model, a first input. The first input includes a current limit of each of a number of power sources coupled to a power multiplexer and a current drawn from each of the power sources (block 1802). In some aspects, the process can include receiving, at the machine learning model, a third input including a voltage operating level of each of the plurality of power sources, receiving, at the machine learning model, a fourth input including a voltage amount specified for the core device, and controlling, by the machine learning model, the multiplexer to select at least one of the power sources based on the third input and the fourth input.

[0141] In some aspects, the process 1800 can include receiving, at the machine learning model, a second input. The second input includes an amount of current specified for a core device coupled to a power multiplexer (block 1804). In some aspects, the process includes receiving, at the machine learning model, a first sleep input including a sleep state of the core device, receiving, at the machine learning model, a second sleep input including an operating state of each of the power sources, and controlling, by the machine learning model, the multiplexer to select at least one of the power sources based on the first sleep input and the second sleep input.

[0142] In some aspects, the process 1800 can include controlling, by the machine learning model, the multiplexer to select at least one of the power sources based on the current limit of each of the power sources, the current drawn from each of the power sources, and the amount of current specified for the core device (block 1806). In some aspects, the process includes receiving, at the machine learning model, a power model input including a power model for estimating power loss and power advantage, and controlling, by the machine learning model, the multiplexer to select at least one of the power sources based on the power model input. In still other aspects, the process includes controlling the multiplexer to select an underutilized power source in response to the core device requesting more power than is available from another of the power sources. In further aspects, the process includes receiving, at the machine learning model, a first sleep input including a sleep state of the core device, receiving, at the machine learning model, a second sleep input including an operating state of each of the plurality of power sources, and controlling, by the machine learning model, the multiplexer to select at least one of the power sources based on the first sleep input and the second sleep input.

[0143] Aspect 1 : An apparatus comprising: a power management integrated circuit (PMIC) comprising a plurality of power supplies; a power multiplexer coupled to each of the plurality of power supplies; a plurality of core devices, at least one of the core devices coupled to the power multiplexer to receive power from at least one of the plurality of power supplies; and a machine learning model configured to control selection of the at least one of the power supplies based on a current utilization of each of the plurality of power supplies and an amount of current consumed by the at least one core device.

[0144] Aspect 2: The apparatus of aspect 1, wherein the machine learning model is further configured to control selection based on an amount of voltage specified by the at least one core device and a voltage operating level of each of the plurality of power supplies.

[0145] Aspect 3: The apparatus of aspect 1 or 2, wherein the machine learning model is further configured to control selection based on a power model for estimating power loss and power advantage.

[0146] Aspect 4: The apparatus of any of the preceding aspects, wherein the machine learning model is further configured to control selection based on a sleep state of the at least one core device and an operating state of each of the plurality of power supplies.

[0147] Aspect 5: The apparatus of any of the preceding aspects, wherein the apparatus is a wearable device.

[0148] Aspect 6: The apparatus of any of the preceding aspects, wherein the wearable device comprises an augmented reality (AR) glasses.

[0149] Aspect 7: The apparatus of any of the preceding aspects, wherein the plurality of power supplies comprises a switched mode power supply (SMPS).

[0150] Aspect 8: The apparatus of any of the preceding aspects, wherein the plurality of power supplies comprises a low dropout (LDO) regulator.

[0151] Aspect 9: A method for multiplexing power for augmented reality (AR) glasses, the method comprising: receiving, at a machine learning model, a first input comprising a current limit for each power supply of a plurality of power supplies coupled to a power multiplexer and a current drawn from each power supply of the plurality of power supplies; receiving, at the machine learning model, a second input comprising an amount of current specified for a core device coupled to the power multiplexer; and controlling, by the machine learning model, a multiplexer to select at least one power supply of the plurality of power supplies based on the current limit for each power supply of the plurality of power supplies, the current drawn from each power supply of the plurality of power supplies, and the amount of current specified for the core device.

[0152] Aspect 10: The method of aspect 9, further comprising: receiving, at the machine learning model, a third input comprising a voltage operating level for each power supply of the plurality of power supplies; receiving, at the machine learning model, a fourth input comprising an amount of voltage specified for the core device; and controlling, by the machine learning model, the multiplexer to select the at least one power supply of the plurality of power supplies based on the third input and the fourth input.

[0153] Aspect 11 : The method of aspect 9 or 10, further comprising: receiving, at the machine learning model, a power model input comprising a power model for estimating power loss and power advantage; and controlling, by the machine learning model, the multiplexer to select the at least one power supply of the plurality of power supplies based on the power model input.

[0154] Aspect 12: The method of any one of aspects 9-11, further comprising: receiving, at the machine learning model, a first sleep input comprising a sleep state of the core device; receiving, at the machine learning model, a second sleep input comprising an operating state of each power supply of the plurality of power supplies; and controlling, by the machine learning model, the multiplexer to select the at least one power supply of the plurality of power supplies based on the first sleep input and the second sleep input.

[0155] Aspect 13: The method of any one of aspects 9-12, further comprising controlling the multiplexer to select an underutilized power supply of the plurality of power supplies in response to the core device requesting more power than is available from another power supply of the plurality of power supplies.

[0156] Aspect 14: An apparatus for multiplexing power for augmented reality (AR) glasses, the apparatus comprising: means for receiving, at a machine learning model, a first input comprising a current limit of each power source of a plurality of power sources coupled to a power multiplexer and a current drawn from each power source of the plurality of power sources; means for receiving, at the machine learning model, a second input comprising an amount of current specified for a core device coupled to the power multiplexer; and means for controlling, by the machine learning model, a multiplexer to select at least one power source of the plurality of power sources based on the current limit of each power source of the plurality of power sources, the current drawn from each power source of the plurality of power sources, and the amount of current specified for the core device.

[0157] Aspect 15: The apparatus of aspect 14, further comprising: means for receiving, at the machine learning model, a third input comprising a voltage operating level of each power source of the plurality of power sources; means for receiving, at the machine learning model, a fourth input comprising an amount of voltage specified for the core device; and means for controlling, by the machine learning model, the multiplexer to select the at least one power source of the plurality of power sources based on the third input and the fourth input.

[0158] Aspect 16: The apparatus of aspect 14 or 15, further comprising: means for receiving, at the machine learning model, a power model input comprising a power model for estimating power loss and power advantage; and means for controlling, by the machine learning model, the multiplexer to select the at least one power source of the plurality of power sources based on the power model input.

[0159] Aspect 17: The apparatus of any of aspects 14 to 16, further comprising: means for receiving, at the machine learning model, a first sleep input comprising a sleep state of the core device; means for receiving, at the machine learning model, a second sleep input comprising an operating state of each power source of the plurality of power sources; and means for controlling, by the machine learning model, the multiplexer to select the at least one power source of the plurality of power sources based on the first sleep input and the second sleep input.

[0160] Aspect 18: The apparatus of any of aspects 14 to 17, further comprising means for controlling the multiplexer to select an underutilized power source of the plurality of power sources in response to the core device requesting more power than is available from another power source of the plurality of power sources.

[0161] Aspect 19: A non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor and comprising: program code to receive, at a machine learning model, a first input comprising a current limit of each power supply of a plurality of power supplies coupled to a power multiplexer and a current drawn from each power supply of the plurality of power supplies; program code to receive, at the machine learning model, a second input comprising an amount of current specified for a core device coupled to the power multiplexer; and program code to control, by the machine learning model, a multiplexer to select at least one power supply of the plurality of power supplies based on the current limit of each power supply of the plurality of power supplies, the current drawn from each power supply of the plurality of power supplies, and the amount of current specified for the core device.

[0162] Aspect 20: The non-transitory computer-readable medium of aspect 19, wherein the program code further comprises: program code to receive, at the machine learning model, a third input comprising a voltage operating level of each power supply of the plurality of power supplies; program code to receive, at the machine learning model, a fourth input comprising an amount of voltage specified for the core device; and program code to control, by the machine learning model, the multiplexer to select the at least one power supply of the plurality of power supplies based on the third input and the fourth input.

[0163] Aspect 21 : The non-transitory computer-readable medium of aspect 19 or 20, wherein the program code further comprises: program code to receive, at the machine learning model, a power model input comprising a power model to estimate power loss and power advantage; and program code to control, by the machine learning model, the multiplexer to select the at least one power supply of the plurality of power supplies based on the power model input.

[0164] Aspect 22: The non-transitory computer-readable medium of any one of aspects 19 to 21, wherein the program code further comprises: program code to receive, at the machine learning model, a first sleep input comprising a sleep state of the core device; program code to receive, at the machine learning model, a second sleep input comprising an operating state of each power supply of the plurality of power supplies; and program code to control, by the machine learning model, the multiplexer to select the at least one power supply of the plurality of power supplies based on the first sleep input and the second sleep input.

[0165] Aspect 23: The non-transitory computer-readable medium of any one of aspects 19-22, wherein the program code further includes program code to control the multiplexer to select an underutilized power source of the plurality of power sources in response to the core device requesting more power than is available from another power source of the plurality of power sources.

[0166] According to the present disclosure, the term "or" can be construed as "and / or" unless the context otherwise dictates. Additionally, while the phrase "one or more" or "at least one" can have been used to describe some features, it is not to be construed to exclude the presence of zero of the feature or a singular number of the feature, unless the context otherwise dictates. Further, although the terms "one" or "another" can have been used to describe some features, it is not to be construed to exclude the presence of zero of the feature or a singular number of the feature, unless the context otherwise dictates.

[0167] In one or more examples, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. Though described in the context of particular examples, the functions described within this disclosure can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media can include computer data storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally can correspond to (1) tangible computer- readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media can be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, cache memory, register storage, portable computer disks, and other storage devices that are tangible rather than signal per se (e.g., disk and durable, nonvolatile, and / or non-transitory media). Combinations of the above should also be included within the scope of computer-readable media. A computer program product can include a computer-readable medium.

[0168] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term "processor," as used herein can refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, the techniques could be fully implemented in one or more circuits or logic elements.

[0169] The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described herein as being configured to perform a particular function or task. However, such components, modules, or units can be configured to perform a variety of tasks that are not explicitly described or that are different than the tasks explicitly described. In other words, the descriptions of various components, modules, or units herein is intended to be included within the scope of the functions described by the various components, modules, or units.

[0170] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. An apparatus, the apparatus comprising: A power management integrated circuit (PMIC) comprising multiple power supplies; A power multiplexer coupled to each of the plurality of power supplies; Multiple core devices, at least one of which is coupled to the power multiplexer to receive power from at least one of the multiple power sources; and A machine learning model configured to control the selection of at least one of the plurality of power sources based on the current utilization rate of each of the plurality of power sources and the amount of current consumed by at least one of the core devices.

2. The apparatus of claim 1, wherein the machine learning model is further configured to control selection based on a voltage amount specified by the at least one core device in the core devices and the voltage operating level of each of the plurality of power supplies.

3. The apparatus of claim 1, wherein the machine learning model is further configured to control the selection based on a power model used to estimate power loss and power advantage.

4. The apparatus of claim 1, wherein the machine learning model is further configured to control selection based on the sleep state of at least one of the core devices and the operating state of each of the plurality of power supplies.

5. The device according to claim 1, wherein the device is a wearable device.

6. The device of claim 5, wherein the wearable device includes augmented reality (AR) glasses.

7. The apparatus of claim 1, wherein the plurality of power supplies comprises switch-mode power supplies (SMPS).

8. The apparatus of claim 1, wherein the plurality of power supplies includes a low dropout (LDO) regulator.

9. A method for multiplexing power, the method comprising: The machine learning model receives a first input, which includes the current limit of each of a plurality of power sources coupled to the power multiplexer and the current drawn from each of the plurality of power sources. A second input is received at the machine learning model, the second input including a current quantity specified for the core device coupled to the power multiplexer; as well as The machine learning model controls a multiplexer to select at least one of the plurality of power supplies based on the current limit of each of the plurality of power supplies, the current drawn from each of the plurality of power supplies, and the amount of current specified for the core device.

10. The method according to claim 9, further comprising: A third input is received at the machine learning model, the third input including the voltage operating level of each of the plurality of power sources; A fourth input is received at the machine learning model, the fourth input including a voltage quantity specified for the core device; as well as The machine learning model controls the multiplexer to select at least one of the plurality of power sources based on the third and fourth inputs.

11. The method according to claim 9, further comprising: The machine learning model receives a power model input, which includes a power model for estimating power loss and power advantage. as well as The machine learning model controls the multiplexer to select at least one of the plurality of power sources based on the power model input.

12. The method according to claim 9, further comprising: The machine learning model receives a first sleep input, which includes the sleep state of the core device. A second sleep input is received at the machine learning model, the second sleep input including the operating state of each of the plurality of power supplies; as well as The machine learning model controls the multiplexer to select at least one of the plurality of power supplies based on the first sleep input and the second sleep input.

13. The method of claim 9, further comprising controlling the multiplexer to select an underutilized power source from the plurality of power sources in response to a request from the core device for more power than is available from another power source among the plurality of power sources.

14. An apparatus for multiplexing power, the apparatus comprising: A component for receiving a first input at a machine learning model, the first input including the current limit of each of a plurality of power sources coupled to a power multiplexer and the current drawn from each of the plurality of power sources; A component for receiving a second input at the machine learning model, the second input including a current quantity specified for a core device coupled to the power multiplexer; and A component for controlling a multiplexer by the machine learning model to select at least one of the plurality of power supplies based on the current limit of each of the plurality of power supplies, the current drawn from each of the plurality of power supplies, and the amount of current specified for the core device.

15. The apparatus of claim 14, further comprising: A component for receiving a third input at the machine learning model, the third input including the voltage operating level of each of the plurality of power supplies; A component for receiving a fourth input at the machine learning model, the fourth input including a voltage quantity specified for the core device; and A component for controlling the multiplexer by the machine learning model to select at least one of the plurality of power sources based on the third and fourth inputs.

16. The apparatus of claim 14, further comprising: A component for receiving power model input at the machine learning model, the power model input including a power model for estimating power loss and power advantage; and A component for controlling the multiplexer by the machine learning model to select at least one of the plurality of power sources based on the power model input.

17. The apparatus of claim 14, further comprising: A component for receiving a first sleep input at the machine learning model, the first sleep input including the sleep state of the core device; A component for receiving a second sleep input at the machine learning model, the second sleep input including the operating state of each of the plurality of power supplies; and A component for controlling the multiplexer by the machine learning model to select at least one of the plurality of power supplies based on the first sleep input and the second sleep input.

18. The apparatus of claim 14, further comprising means for controlling the multiplexer to select an underutilized power source among the plurality of power sources in response to a request from the core device for more power than that available from another power source among the plurality of power sources.

19. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code for receiving a first input at a machine learning model, the first input including the current limit of each of a plurality of power sources coupled to a power multiplexer and the current drawn from each of the plurality of power sources; Program code for receiving a second input at the machine learning model, the second input including a current quantity specified for a core device coupled to the power multiplexer; and Program code for controlling a multiplexer by the machine learning model to select at least one of the plurality of power supplies based on the current limit of each of the plurality of power supplies, the current drawn from each of the plurality of power supplies, and the amount of current specified for the core device.

20. The non-transitory computer-readable medium of claim 19, wherein the program code further comprises: Program code for receiving a third input at the machine learning model, the third input including the voltage operating level of each of the plurality of power supplies; Program code for receiving a fourth input at the machine learning model, the fourth input including a voltage quantity specified for the core device; and Program code for controlling the multiplexer by the machine learning model to select at least one of the plurality of power sources based on the third and fourth inputs.

21. The non-transitory computer-readable medium of claim 19, wherein the program code further comprises: Program code for receiving power model inputs at the machine learning model, the power model inputs including a power model for estimating power loss and power advantage; and Program code for controlling the multiplexer by the machine learning model to select at least one of the plurality of power sources based on the power model input.

22. The non-transitory computer-readable medium of claim 19, wherein the program code further comprises: Program code for receiving a first sleep input at the machine learning model, the first sleep input including the sleep state of the core device; Program code for receiving a second sleep input at the machine learning model, the second sleep input including the operating state of each of the plurality of power supplies; and Program code for controlling the multiplexer by the machine learning model to select at least one of the plurality of power supplies based on the first sleep input and the second sleep input.

23. The non-transitory computer-readable medium of claim 19, wherein the program code further comprises program code for controlling the multiplexer to select an underutilized power source among the plurality of power sources in response to a request from the core device for more power than that available from another power source among the plurality of power sources.

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