Machine learning model training method for random substrate
By training neural networks using an in-loop simulator and a mapping-reduction method, the problem of optimization for each device in existing technologies is solved, achieving efficient deployment and applicability across multiple hardware instances.
Patent Information
- Application Number
- CN202480046669.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-11
- Filing Date
- 2024-07-10
- Publication Date
- 2026-02-27
AI Technical Summary
Existing technologies cannot effectively generalize to a range of target device instances when training neural networks on analog mixed-signal acceleration platforms. They require additional optimization or remapping for each device, resulting in low efficiency.
The In-Loop Simulator (SITL) method is adopted to avoid using the target device in the loop through high-fidelity digital reconstruction. The automatic differentiation framework is used to handle backpropagation, and the neural network is trained by combining the mapping-reduction method to make it applicable to multiple target hardware instances.
This enables the deployment of neural networks on a large number of chips without retraining, improving training efficiency and applicability while reducing optimization costs.
Smart Images
Figure CN121586907A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to parameter optimization of programmable architectures, specifically for artificial neural networks and spiking neural networks implemented in hardware devices as analog circuits (at least in part), where the optimization process must take into account the random variability of the hardware devices. Background Technology
[0002] Analog mixed-signal systems, fuzzy logic devices, approximate computing devices, or in-material accelerators (optical or generated by the properties of deposited materials) can output results with lower latency and energy consumption compared to comparable deterministic digital solutions. However, these solutions have historically been more susceptible to device-level mismatches compared to traditional digital systems.
[0003] For neural networks deployed on analog mixed-signal acceleration platforms, the traditional training mechanism involves hardware-in-the-loop (HITL). For example, see the paper "Neuromorphic Hardware InThe Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-ScaleSystem" by Schmitt et al., 2017, arXiv:1703.01909.
[0004] In the HITL scheme, gradient-based optimization mechanisms are used in conjunction with forward propagation performed on the device (through neural network input data to generate neuron activations and network-level predictions), and error backpropagation (adjusting neural network parameters based on the calculated error) is performed via an alternative computation graph maintained on the host. The HITL process requires injecting observable data from the neural network into the alternative computation graph to simulate forward propagation.
[0005] While this training process is efficient in extracting performance from target devices, it cannot be generalized to a range of target device instances, thus requiring additional optimization or remapping for each device. Summary of the Invention
[0006] To address the aforementioned problems, the subject matter covered by the claims of this application is proposed.
[0007] The proposed method avoids using the target device in loops by utilizing high-fidelity digital reconstruction of the target device. Therefore, an In-Loop Simulator (SITL) method is employed, where the inner loop (forward propagation of the computation graph) is performed in a high-fidelity simulator, and the outer loop (backward propagation of the computation graph, parameter updates) is handled by an automatic differentiation framework. PyTorch can be used as an example of an automatic differentiation framework.
[0008] The method described here can train a set of parameters that can be deployed on a large number of chips without retraining, thereby accelerating the operation of neural networks.
[0009] This method first trains the main neural network using a map-reduce approach. In the mapping phase, the main neural network is mapped onto many independent analog chips, each with different network parameters, and a forward computation graph is performed. This phase includes error gradient calculation. In the reduction phase, the calculated gradients are applied to the main network. The map-reduce phase continues iteratively until convergence is achieved. The resulting network (defined as a combination of topology, neuron, and synaptic parameters) can be represented in binary or textual form and deployed across multiple instances of the target hardware.
[0010] According to a first aspect of the invention, a method for training a signal processing pipeline, the pipeline including a neural network, for deployment into a programmable architecture of a target device is disclosed. The method may include one or more of the following steps.
[0011] In the first step, models of multiple components of the target device are acquired, describing information about the components and how they interact. In the second step, programmable parameter values for multiple programmable parameters of the signal processing pipeline are acquired, ensuring these values are compatible with both the signal processing pipeline and the target device. In the third step, characteristic data for multiple components of the target device is acquired, including measured component information for at least a subset of components in multiple instances of the target device, and / or random variability information for at least a subset of components in multiple instances of the target device. In the fourth step, multiple instances of the target device are simulated using a model, where the model for each instance of the target device is configured with the programmable parameter values and characteristic data for that instance. In the fifth step, updates to the programmable parameter values of the programmable parameters for each simulated instance of the target device are independently computed using one or more optimization methods. In the sixth step, the updates to the programmable parameter values of each simulated instance of the target device are reduced to a single update to the programmable parameter values of the signal processing pipeline. In the eighth step, the programmable parameter values of the signal processing pipeline are updated using this single update.
[0012] In an embodiment of the first aspect, the method may further include: using a signal processing pipeline with updated programmable parameter values to check whether a target device performance threshold has been reached or convergence has been achieved; if the target device performance threshold has not been reached or convergence has not been achieved, then repeating the above steps.
[0013] In an embodiment of the first aspect, the method may further include: if a target device performance threshold or convergence is reached, deploying a signal processing pipeline with updated programmable parameter values into the programmable architecture of the target device.
[0014] In an embodiment of the first aspect, the model of each target device instance may be configured with characteristic data of the target device instance, such that the simulated target device instance represents a digital twin of multiple target device instances, and / or represents the random variability of multiple target device instances.
[0015] In an embodiment of the first aspect, the step of obtaining programmable parameter values may include: initializing programmable parameters of a signal processing pipeline; and optimizing the programmable parameters by performing a higher-order simulation until an initial acceptance threshold is reached or convergence occurs.
[0016] In an embodiment of the first aspect, the step of obtaining programmable parameter values further includes: quantizing the programmable parameters to conform to an available parameter resolution when deploying the signal processing pipeline to the programmable architecture of the target device; and, preferably, further optimizing the quantized set of programmable parameter values by performing higher-order simulations until a second initial acceptance threshold or convergence is reached to compensate for any performance loss caused by the quantization step.
[0017] In an embodiment of the first aspect, the step of acquiring characteristic data includes operating and observing the behavior of at least one of a plurality of target devices.
[0018] In an embodiment of the first aspect, the random variability of multiple components of the target device may include random variability between multiple target hardware devices and / or random variability of each target hardware device over time; such random variability may be caused by device-level mismatch, which may be due to inaccurate manufacturing or analog circuit behavior under process, voltage and temperature variations.
[0019] In an embodiment of the first aspect, at least one simulated target device instance implemented in the simulation may be a twin of a non-simulated target device instance by replicating the behavior of the individual components in the non-simulated target device instance in the simulation; and / or at least one simulated target device instance implemented in the simulation may be a twin of a potential but fictitious target device instance by abstracting the behavior of the individual components into one or more distributions, from which the behavior of the simulated components in the simulated target device instance is extracted.
[0020] In an embodiment of the first aspect, the step of using one or more optimization methods to compute the update of the programmable parameter value of the programmable parameter includes using a gradient-based optimization method or a derivative-free optimization method.
[0021] In an embodiment of the first aspect, the step of using one or more optimization methods (107) to calculate the update of the programmable parameter value of the programmable parameter may include forward propagation and error calculation backpropagation through a simulated target device (in particular a simulated programmable architecture); the forward propagation may be performed on a high-fidelity system-on-chip simulator, while the error calculation backpropagation is handled by a computational framework that implements automatic differentiation.
[0022] In an embodiment of the first aspect, the step of reducing the programmable parameter value update for each simulated target device may include: averaging each programmable parameter value update across all simulated target devices, or selecting from optional updates an update that reduces the variability of the simulated target device to an acceptable value plus or minus two or three standard deviations.
[0023] In embodiments of the first aspect, the programmable architecture may include a spiking neural network or an artificial neural network; and / or the target device may include an analog mixed-signal system, a fuzzy logic device, an approximate computing device, or an in-material accelerator.
[0024] In an embodiment of the first aspect, the programmable architecture may include a spiking neural network, and the target device includes an analog mixed-signal system. More preferably, the target device may include an analog mixed-signal system having an on-chip spiking neural network accelerated architecture.
[0025] In embodiments of the first aspect, the programmable parameters may include at least one of the following: spiking neuron model parameters, such as membrane potential threshold, membrane time constant, resting potential, refractory period, and adaptive factor (e.g., threshold adaptive time constant); synaptic weight parameters, such as synaptic weight, synaptic time constant, and adaptive factor (e.g., short-term synaptic weight scaling); network topology parameters, such as number of neurons, connection pattern, and network architecture; learning rule parameters, such as pulse time-dependent plasticity (STDP) parameter and optimizer hyperparameter learning rate; and input encoding parameters, such as pulse encoder mapping between data and pulse frequency and pulse encoder threshold.
[0026] In an embodiment of the first aspect, the programmable parameters may include weights of synaptic elements of a spiking neural network, and the programmable parameter values may include weight values; the step of using the optimization method (107) to calculate the programmable parameter value update of the programmable parameters may include obtaining the error of each weight among all weights of each simulated target device instance.
[0027] According to a second aspect of the invention, an apparatus including a programmable architecture is disclosed, wherein the programmable architecture is trained according to the first aspect of the invention and subsequently deployed into the apparatus.
[0028] According to a third aspect of the invention, a computer system for training a signal processing pipeline, the pipeline including a neural network, is disclosed for deployment in a programmable architecture of a target device. The computer system may include memory, a processor, and outputs.
[0029] The memory may include: models of multiple components of the target device, information describing the multiple components and how these components interact; programmable parameter values of programmable parameters of a signal processing pipeline, wherein the programmable parameter values are compatible with the target device and the signal processing pipeline; and characteristic data (200) of multiple components of the target device, wherein the characteristic data includes measured component information of at least a portion of the components of multiple instances of the target device and / or random variability information of at least a portion of the components of multiple instances of the target device.
[0030] The processor can execute a method according to a first aspect of the invention, wherein the steps of acquiring the model, programmable parameter values, and characteristic data can be performed by acquiring the model, programmable parameter values, and characteristic data from memory, respectively.
[0031] In an embodiment of the third aspect, when the processor performs the step of deploying a signal processing pipeline with updated programmable parameter values to the programmable architecture of the target device, the deployment step may be performed by saving the updated programmable parameter values to a memory or permanent storage device and using the output to initialize the programmable architecture on the target device with the updated programmable parameter values. Attached Figure Description
[0032] Embodiments will now be described by way of example, with reference to the accompanying drawings, wherein corresponding reference numerals denote corresponding parts, and: Figure 1 This illustrates the neural network development lifecycle, with the goal of deployment on multiple physical instances of the device. Specific Implementation Certain embodiments will be described in more detail below. However, it should be understood that these embodiments should not be considered as limiting the scope of protection of the present invention.
[0034] This invention relies on an optimizer responsible for tuning model parameters to reduce the error compared to a predefined objective function. One feasible implementation is to utilize frameworks that support automatic differentiation, such as PyTorch (see https: / / pytorch.org / ) or TensorFlow (see https: / / www.tensorflow.org / ), to implement supervised and gradient-based learning. In the absence of a gradient-based optimization scheme, a gradient-free approach can be used as an alternative.
[0035] Furthermore, a general-purpose optimization platform is combined with a high-fidelity system simulation environment capable of capturing the salient features of a System-on-Chip (SoC). There are no restrictions on the heterogeneity or complexity of the SoC; however, increased complexity may incur additional costs in terms of training duration.
[0036] The hardware used in this invention may be, for example, an Innatera spiking neural processor, which is an analog mixed-signal device with an on-chip spiking neural network acceleration architecture, but this system choice is not a limiting use case.
[0037] It is assumed that the chip used to deploy the main network has been calibrated, although this is not strictly required. The calibration process involves modifying the control parameters on the chip to make the operating ranges of the individual components similar to each other or within specified operating ranges. This process also ensures that the behavior of the neural network remains within nominally guaranteed limits.
[0038] Figure 1 The process 100 for training a neural network or equivalent parameterized machine learning or artificial intelligence model and deploying it on an accelerator device is described. Specifically, it demonstrates a development lifecycle for a neural network deployed on multiple physical instances of the device.
[0039] For ease of reading, the components before (such as preprocessing or encoding) and after (postprocessing or decoding) of the network, including the network itself, are all referred to as the "main network" or "network" and the two terms are used interchangeably.
[0040] This process 100 includes high-level simulation 100A, system simulation 100B, and hardware deployment 100C.
[0041] In the first step 101, select and instantiate the model's topology. Any topology can be selected here, such as a shallow feedforward network, a recurrent network, a deep network with residual connections, or even a convolutional neural network. It should be noted that this list of examples is not exhaustive and is for illustrative purposes only.
[0042] After selecting and instantiating the model's topology, the model's parameters will be initialized in step 102. For example, weights can be initialized using a standard Xavier initializer, or a more specialized initialization technique for SNNs (Spiking Neural Networks), while other synaptic parameters can be initialized manually.
[0043] After the model parameters are initialized, these parameters are optimized sequentially in step 103 until convergence or an acceptance threshold is reached (i.e., test A, used to check whether the model performance passes the acceptability threshold, returns "No (N)," and the process returns to step 103). During this learning or optimization process, a lower-precision simulator can be used to simulate network operation. This simulator executes faster but provides a higher level of abstraction of the target deployment hardware. Therefore, this optimization phase can serve as the initialization phase for the next step of network optimization.
[0044] Once the model performance passes the acceptability threshold (i.e., test A, which checks whether the model performance passes the acceptability threshold, returns "Yes (Y)"), the parameters involved in its operation are quantized in step 104 to conform to the available on-chip parameter resolution and range. For example, the weights can be 6-bit quantized, while other synaptic parameters (such as neuronal input current gain or refractory period, or synaptic peak amplitude or decay) can be quantized with an additional 6-bit or 7-bit quantization.
[0045] The quantized network or model can be further optimized to compensate for the performance loss caused by the quantization step.
[0046] The network consisting of some or all of the steps in steps 101-104 (steps 101-104 constitute a high-order simulation 100A) is considered as the main network (which may have been pre-trained by steps 102-104) and is intended to be deployed on multiple devices for optimization.
[0047] This method may include simply acquiring programmable parameter values of programmable parameters of a signal processing pipeline, for example by loading these parameter values from a description on disk, and acquiring characteristic data 200 of multiple components of the target device, instead of performing steps 101-104.
[0048] The models of multiple components of the target device describe information about these components and how they interact. Programmable parameter values are compatible with the target device and signal processing pipeline.
[0049] Programmable values that are compatible with the target device and signal processing pipeline mean that the values of these parameters meet specific criteria to function correctly in a given hardware (target device) and software (signal processing pipeline) environment. For example, parameter values should be within the constraints of the target device's resources, such as memory size, processing power, and available computing units. Furthermore, parameter values should be in a format or data type that the hardware can process. As another example, parameters should enable the pipeline to meet the timing requirements of the target device. This includes processing time limits per operation and overall latency limits. Additionally, parameter values should correctly align with the algorithms used in the signal processing pipeline. This means, for example, that they should help neural networks and other components perform their intended functions without causing errors or poor performance. As another example, parameters should conform to the configuration standards and protocols expected by the pipeline components. This includes conforming to the expected range, size, and initialization conditions. Furthermore, for example, parameters should be adapted to the target device's programmable architecture. This means that they should be consistent with the configuration and usage of the programmable architecture for signal processing tasks.
[0050] Characterization data includes identified component information of multiple components of multiple target devices and / or random variability information of multiple components of multiple target devices; In step 105, the main network is prepared by performing any additional checks or operations required to simulate the network within the system simulation platform. For example, signal processing pipelines may be represented using different formats or notations for use by the system simulator, or timing and bandwidth requirements may be verified here, as the upstream simulator may not have sufficient data or precision to perform these operations.
[0051] Next, in step 106, N devices are simulated. These devices represent the random variability of the hardware required to deploy the main network. They can also be digital twins of real target devices, obtained through measurement. Alternatively, they can be digital twins of fictional target devices. The main network is fine-tuned by mapping and simulating its operation on the N simulated devices. The same mapping can be used for all devices, or a fine-grained mapping can be provided for each device. A single mapping solution may require creating a single profile for many devices, which implements fixed partitioning, placement, and routing for the network. A fine-grained mapping solution may require different placements, partitions, and even routing, thus generating a profile for each device. Fine-grained mapping can be created by applying additional optimization algorithms to the mapper to minimize the error between the desired component behavior and the available physical component range.
[0052] To simulate N devices, characterization data 200 is used. Characterization data 200 is generated by appropriately driving and subsequently observing the behavior of the device under test (such as a component or circuit). Each possible value of the control current on the device can be iteratively set, and its effect on the observed parameters can be recorded. The relationship between the control current and parameter behavior, as well as the parameter mismatch on the chip over time, can all be referred to as characterization data. To generate characterization data, an iterative configuration and then estimation process is employed; for example, the control signal is scanned from its minimum range to its maximum range, and its effect on the implemented parameters is estimated. This process provides information about the range and mismatch of parameters implemented on a particular physical device. The resulting characterization data 200 (also referred to as device information) can be utilized in two exemplary ways.
[0053] First, the characteristic data 200 is used verbatim. The behavior of each component is replicated in the simulation, so each of the N simulated devices is a twin of the real physical chip. Second, the characteristic data is used statistically. The behavior of each component is abstracted as a parameter distribution, from which the simulated components are extracted, so each of the N simulated devices is a twin of a potential but hypothetical chip.
[0054] The interpretation of the characteristic data 200 allows for flexibility in the applicability and performance of the solution. One approach is to leverage the characteristic data 200 to create highly optimized neural networks for a relatively small number of known devices. Another approach is to leverage the characteristic data 200 to deploy the target network across a large number of devices, thereby creating a general-purpose network.
[0055] The characteristic data 200 or device information may include statistical information about how a single device operates. This allows the statistical information to be used to simulate a number of devices N. For example, the statistical information may indicate that certain parameters of the device follow a specific statistical distribution during manufacturing. The device can then be simulated based on this statistical distribution.
[0056] For example, an accelerator (an accelerator is a hardware device designed to perform specific computations more efficiently than a general-purpose processor) can implement a specific spiking neural network in hardware. Therefore, an accelerator contains synaptic elements and neurons, implemented, for example, in the form of (analog) circuits. Due to manufacturing and operational limitations, certain parameters of such circuits will follow a statistical distribution during manufacturing (between multiple devices or within a single device, or varying over time).
[0057] Taking synaptic elements as an example, the damping or gain factor can be nonlinear, and therefore has a statistical distribution. For instance, a (spiking) neuron uses an activation function that takes a pulse as input, integrates the input over time within its internal state parameters, compares the internal state to a threshold function, and then triggers when the threshold is reached or exceeded. However, since it is implemented as an analog circuit, the threshold function is not a static function but can vary, for example, to 10% of the actual threshold function value. Therefore, the threshold function can also follow a statistical distribution.
[0058] Therefore, real statistical information can be extracted from multiple devices and used as characteristic data 200. Then, the characteristic data 200 can be used to generate virtual devices and simulate a specific number N of virtual devices.
[0059] For example, the random variability of the target hardware device is described in applications PCT / EP2019 / 081662 and PCT / EP2021 / 077323.
[0060] In step 107, the parameter updates for the main network of each simulation device are independently computed using optimization methods (e.g., gradient-based optimization or derivative-free optimization). Gradient-based optimization methods can update parameters to reduce the derivative or gradient of the provided target loss function. Meanwhile, derivative-free methods (such as evolutionary algorithms) define a non-differentiable fitness function that increases through random mutations. Both techniques can be applied to the proposed method to modify the parameters of the signal processing pipeline for optimization of a specific objective, such as minimizing the loss when deploying the main network across N simulation devices. In the gradient-based case, the steps followed include forward propagation (data injected at the network input stage is propagated through network activations), loss computation (the output prediction is compared to the true label using a loss function (such as negative log-likelihood or classification cross-entropy) to quantify the difference between the prediction and the true value), backpropagation (the gradient of the loss with respect to each parameter in the network is computed), and a parameter update phase (the parameters are adjusted proportionally based on the gradients calculated in the previous step).
[0061] The cost function, also known as the loss function, plays a crucial role in quantifying the difference between the network's predicted output and the actual target output. Therefore, the cost function can be used in one or more optimization methods to determine the updates of programmable parameters. The goal of training a neural network is to minimize this cost function, thereby improving the network's ability to make accurate predictions.
[0062] For spiking neural networks (SNNs), the choice of cost function can differ from that of traditional neural networks. SNNs operate in discrete time steps, and the temporal sequence of the spikes carries significant information. Therefore, when comparing the predicted result with the target output, the cost function should consider the temporal dynamics of the spike sequence. In SNNs, synaptic connections between neurons can be modified according to the temporal sequence of spikes, following principles such as Short-Term Enhancement Difference (STDP). Cost functions suitable for SNNs can incorporate these synaptic plasticity rules to guide learning and adjust the network's connectivity over time. SNNs typically use event-based encoding, where information is represented by the temporal sequence and frequency of spikes. The cost function should be designed to appropriately evaluate the fidelity of this encoding scheme and encourage the network to generate spike patterns that accurately represent the input data. Depending on the task, the cost function of SNNs can be customized for classification tasks (e.g., spike-based input pattern classification) or regression tasks (e.g., spike-based prediction of continuous variables). The choice of cost function will depend on the specific requirements of the current task. Since SNNs are often considered models inspired by biological neurons, energy efficiency is a crucial consideration. The cost function can be designed to encourage sparse spurious activity or minimize energy consumption while achieving the desired task performance. Common cost function choices in SNNs include variations of impulse-based error metrics, such as burst distance metrics, impulse timing prediction errors, or metrics based on the similarity of impulse patterns between the network output and the target burst. Next, in step 108, these parameter updates are applied to a single master network by reducing the parameter updates to that of the entire master network.
[0063] For example, in step 107, a gradient can be obtained, such as the error of each weight of all weights in each of the N devices. In step 108, the error of each weight of the main network in step 105 can be updated by, for example, averaging the errors of specific weights in all the N devices and using the average error to update the corresponding specific weights of the main network in step 105.
[0064] For example, in step 107, a gradient can be obtained, which can be used to update the value of a specific programmable value for the simulated programmable architecture on each of the N simulation devices. The error of this value can then be reduced to a single error (e.g., by averaging the errors obtained for that specific value across all devices), and this single error can then be used to update the value of the main network that began in step 105. Acceptability of 2σ or 3σ can also be achieved by minimizing the variability of the devices to a level that differs from the acceptable value by two or three standard deviations (σ).
[0065] The single master network updated in step 108 can be used again as the master network to be optimized in steps 105-108 (steps 105-108 constitute system simulation 100B) until the system performance threshold is exceeded or convergence is achieved (test B returns "yes (Y)" instead of "no (N)").
[0066] Therefore, this method can be described as training a main neural network in a map-reduce manner. In the mapping phase, the main neural network is mapped onto many independent analog chips, each with different network parameters, and a forward computation graph is performed. This phase includes error gradient calculation. In the reduction phase, the calculated gradients are applied to the main network. The mapping and reduction steps can be repeated, and this map-reduce cycle continues until convergence is achieved. The resulting network is defined as a combination of topology, neuron, and synaptic parameters, which can be represented in binary or textual form and deployed across multiple instances of the target hardware.
[0067] In this primary optimization phase, the forward pass of the network can be performed on a high-fidelity system-on-chip (SoC) simulator, while the backward pass for error computation is handled by the computational framework for implementing automatic differentiation described earlier. The forward pass of a neural network essentially involves creating a data architecture representing the neural network (e.g., neuron and synaptic parameters, and their hidden internal states) and computing neuron and synaptic state updates in a time-step manner. Furthermore, to achieve periodic accuracy (highest fidelity) or half-periodic accuracy (high fidelity) for the SoC simulator, it may need to include information about the number of clock cycles required for each operation of each digital component on the device or the time required for each analog component on the device. Clock-controlled or synchronized digital systems are characterized by the presence of one or more on-chip periodic events that drive the evolution of the device state. Multiple clocks can be synchronized or desynchronized. At each time step, the network state is updated based on the inputs (spikes) provided to the network and the activations generated by neurons in the previous time step. The number of time steps, i.e., the number of network iterations, is provided to the simulation platform. For example, a two-layer feedforward network would involve simulating one or more of the following steps: the simulation device's memory contains mini-batches of data samples i (the entire dataset consists of m predefined mini-batches, the last of which can be of different sizes); data is transferred from memory to the encoder block; spikes are transferred from the encoder to the input stage of the programmable architecture that accelerates SNN operations; spikes are shaped, broadcast, and integrated within neurons; spikes generated by neurons in the first hidden layer are transferred to the input stage of the rest of the programmable architecture responsible for modeling the input; the network output layer undergoes synaptic scaling and integration; spikes generated by the network output layer are transferred to the decoder block, which, for example, counts the asynchronous spike activity of each output neuron to make a classification decision by selecting the class corresponding to the neuron that generates the most spikes. Different observables from the aforementioned computational chain, such as spikes generated by all neurons in the network, can be stored for replay on the computational graph generated during backpropagation. Backpropagation requires constructing a computational graph equivalent to the one used in the forward propagation. For this purpose, PyTorch can be used; PyTorch stores the computational graph in memory, and the observables of the system simulator are injected into the computational graph. This means that the states and outputs of computational elements in the system simulator (such as spikes, internal potentials, and currents of neurons and synapses) are tracked over time. Their impact on computation, the so-called credit assignment problem, can be estimated.
[0068] After the system performance threshold is exceeded or convergence is reached, in step 109, the complete description of the main network can be deployed to any number of target hardware devices to form hardware deployment 100C.
[0069] This invention enables a single neural network or parameterized model to be deployed on multiple accelerators by strategically modeling device randomness, competition conditions (the presence of synchronization or barriers) or noise sources (such as process, voltage, and temperature (PVT)).
[0070] A race condition refers to a situation where system behavior depends on the temporal or sequential order of events. Race conditions can occur when multiple processes or threads simultaneously attempt to access a shared resource, leading to unpredictable results. Similarly, different parts of a neural network accelerator architecture may complete computations at different rates, potentially resulting in different pulse sequences that can be misinterpreted on some devices. Examples include synchronization (coordination) between processes or threads, or barriers (such as locks or semaphores) used to control access to shared resources. A noise source refers to interference or disturbances within a hardware device. PVT stands for process, voltage, and temperature variations, which can affect the performance and behavior of electronic circuitry within a hardware device.
[0071] This process implements a single-map strategy on edge devices. That is, it generates a single mapped output, which is used to implement a neural network on an accelerator containing random components.
[0072] Furthermore, this process maximizes chip manufacturing yield. That is, a single network can contain sufficient redundancy to bypass malfunctioning or non-compliant components.
[0073] This invention can be applied to analog mixed-signal systems, fuzzy logic devices, approximate computing devices, or in-material accelerators, and is particularly suitable for devices implementing one or more signal processing pipelines in a programmable architecture incorporating artificial neural networks (ANNs) or spiking neural networks (SNNs). A programmable architecture is a computational architecture that performs a series of operations based on a provided configuration set. The provided configuration set is applied to the programmable architecture to control, for example, the weights and connections between two layers of units (neurons) provided by the user. A signal processing pipeline is a series of processing stages or steps applied to an input signal to achieve a desired result or extract relevant information. This is a systematic approach applicable to multiple fields, including audio processing, image processing, telecommunications, and sensor data analysis. If feature processing in a signal processing pipeline is performed using a neural network, it means that instead of using traditional signal processing techniques for feature extraction and transformation, the neural network architecture automatically learns and extracts relevant features directly from the input signal.
[0074] If the programmable architecture is or contains a spiking neural network, the parameters that can be optimized in the manner described above include: (1) spiking neuron model parameters, such as membrane potential threshold, membrane time constant, resting potential, refractory period, threshold adaptive time constant, and other adaptive factors; (2) synaptic weight parameters, such as synaptic weight, synaptic time constant, short-term synaptic weight scaling, and other adaptive factors; (3) network topology parameters, such as the number of neurons, connection pattern, and network architecture; (4) learning rule parameters, such as pulse time-dependent plasticity (STDP) parameters, rate-based optimizer hyperparameters, and learning rate; and (5) input parameters, such as the input pulse encoder mapping between data and pulse frequency, and the pulse encoder threshold. It should be noted that hyperparameters are configuration settings used to control the learning process; they are not learned from the data but are set before training begins.
[0075] If the programmable architecture is or contains an artificial neural network, the parameters that can be optimized in the manner described above include: (1) neuron activation function parameters, such as activation function type (e.g., sigmoid, ReLU, tanh), parameters specific to the selected activation function (e.g., the slope of the sigmoid function); (2) synaptic weight parameters, such as initial synaptic weights, synaptic weight scaling factor, learning rate; (3) network topology parameters, such as number of layers, number of neurons per layer, connection mode (e.g., fully connected, convolutional); (4) learning rule parameters, such as learning algorithm (e.g., stochastic gradient descent, reinforcement learning, evolutionary algorithm), regularization parameters (e.g., L1 / L2 regularization, dropout rate); and (5) input parameters, such as input scaling and normalization, mini-batch size, learning rate scheduling.
[0076] It should be noted that features of any of the embodiments disclosed herein can be combined in a suitable manner.
Claims
1. A method (100) for training a signal processing pipeline containing a neural network, the signal processing pipeline being deployed to a programmable architecture of a target device, the method comprising the following steps: Obtain models of multiple components of the target device, wherein the models describe information about the multiple components and how the components interact with each other; Obtain programmable parameter values of multiple programmable parameters of the signal processing pipeline, wherein the programmable parameter values are compatible with the signal processing pipeline and the target device; Acquire characteristic data of multiple components of the target device (200), wherein the characteristic data includes measured component information of at least a portion of the components in multiple instances of the target device and / or random variability information of at least a portion of the components in multiple instances of the target device; The model is used to simulate (106) multiple instances of the target device, wherein the model of each target device instance is configured with programmable parameter values and characteristic data of the target device instance; One or more optimization methods (107) are used to independently compute the programmable parameter value update of the programmable parameters for each simulated target device instance; The update of the programmable parameter values for each simulated target device instance is reduced (108) to a single update of the programmable parameter values for the signal processing pipeline; and The programmable parameter values of the signal processing pipeline are updated using this set of updates to the programmable parameter values of the signal processing pipeline.
2. The method according to claim 1, further comprising: The signal processing pipeline with updated programmable parameter values is used to check whether (B) has reached the target device performance threshold or convergence. as well as If the target device performance threshold is not reached or convergence is not achieved, repeat the above steps (105, 106, 107, 108).
3. The method according to claim 1 or 2, further comprising: If the target device performance threshold is reached or convergence is achieved, the signal processing pipeline with updated programmable parameter values is deployed (109) into the programmable architecture of the target device.
4. The method according to any one of the preceding claims, wherein, Each target device instance's model is configured with the characteristic data of that target device instance, such that the simulated target device instance represents a digital twin of multiple target device instances, and / or represents the random variability of multiple target device instances.
5. The method according to any one of the preceding claims, wherein, The steps to obtain programmable parameter values include: Initialize (102) the programmable parameters of the signal processing pipeline; The programmable parameters (103) are optimized by performing higher-order simulations until the initial acceptance threshold is reached or convergence is achieved.
6. The method according to any one of the preceding claims, wherein, The steps for obtaining programmable parameter values also include: When deploying the signal processing pipeline to the programmable architecture of the target device, the programmable parameters are quantized (104) to be compatible with the available parameter resolution; and preferably, The set of values for the quantized programmable parameters is further optimized by performing higher-order simulations until a second initial acceptance threshold is reached or convergence is achieved, in order to compensate for any performance loss caused by the quantization step.
7. The method according to any of the preceding claims, wherein, The steps of acquiring characteristic data (200) include: operating and observing the behavior of at least one of a plurality of target devices.
8. The method according to any one of the preceding claims, wherein, The random variability of the multiple components of the target device includes: random variability among the multiple target hardware devices and / or random variability of each target hardware device over time; and The random variability is caused by device-level mismatch, which arises from inaccurate manufacturing or the behavior of analog circuits under variations in process, voltage, and temperature.
9. The method according to any one of the preceding claims, wherein, At least one of the simulated target device instances implemented in the simulation is a twin of a non-simulated target device instance, which is achieved by replicating the behavior of the various components of the non-simulated target device instance in the simulation; and / or In this simulation, at least one of the simulated target device instances is a twin of a potential but fictitious target device instance, which is achieved by abstracting the behavior of the individual components into one or more distributions and extracting the behavior of the simulated components of the simulated target device instance from the distributions.
10. The method according to any one of the preceding claims, wherein, The steps of using one or more optimization methods (107) to compute the programmable parameter value update of the programmable parameter include: using a gradient-based optimization method or a derivative-free optimization method.
11. The method according to any one of the preceding claims, wherein, The steps of using one or more optimization methods (107) to calculate the programmable parameter value update of the programmable parameters include: performing forward propagation and error calculation backward propagation through a simulated target device, particularly a simulated programmable architecture; and wherein, The forward pass is performed on a high-fidelity on-chip system simulator, and the error calculation backward pass is handled by a computational framework that implements automatic differentiation.
12. The method according to any one of the preceding claims, wherein, The steps of reducing (108) the update of the programmable parameter value of each simulated target device include: averaging the update of each programmable parameter value for each programmable parameter value of all simulated target devices, or selecting from optional updates an update that reduces the variability of the simulated target device to an acceptable value plus or minus two or three standard deviations.
13. The method according to any one of the preceding claims, wherein, The programmable architecture includes a spiking neural network or an artificial neural network; and / or The target device includes an analog mixed-signal system, a fuzzy logic device, an approximate computing device, or an in-material accelerator.
14. The method according to claim 13, wherein, The programmable architecture includes a spiking neural network, and the target device includes an analog mixed-signal system, more preferably, the target device includes an analog mixed-signal system with an on-chip spiking neural network acceleration architecture.
15. The method according to claim 14, wherein, The programmable parameters include at least one of the following: Spiking neuron model parameters, such as membrane potential threshold, membrane time constant, resting potential, refractory period, and adaptive factors such as threshold adaptive time constant; Synaptic weight parameters, such as synaptic weights, synaptic time constants, and adaptive factors such as short-term synaptic weight scaling; Network topology parameters, such as the number of neurons, connection patterns, and network architecture; Learn rule parameters, such as the Impulse Timing Dependency Plasticity (STDP) parameter and the optimizer hyperparameter learning rate; as well as Input encoding parameters, such as the pulse encoder mapping between data and pulse frequency and the pulse encoder threshold.
16. The method according to claim 15, wherein, The programmable parameters include the weights of the synaptic elements of the spiking neural network, and wherein the programmable parameter values include the weight values of the weights; and The step of using the optimization method (107) to calculate the programmable parameter value update of the programmable parameter includes: obtaining the error of each weight in all weights of each simulated target device instance.
17. An apparatus including a programmable architecture, wherein, The programmable architecture is trained according to the method of any one of the preceding claims and then deployed to the device.
18. A computer system for training a signal processing pipeline, the signal processing pipeline including a neural network with a programmable architecture for deployment to a target device, the computer system including a memory, a processor, and an output terminal; in, The memory includes: A model of multiple components of the target device, the model describing information about the multiple components and how the components interact with each other; The programmable parameter values of the programmable parameters of the signal processing pipeline, wherein the programmable parameter values are compatible with the target device and the signal processing pipeline; Characterization data (200) of multiple components of the target device, wherein the characterization data includes measured component information of at least a portion of the components in multiple instances of the target device and / or random variability information of at least a portion of the components in multiple instances of the target device; The processor executes the method according to any one of claims 1 to 16, wherein the step of acquiring (105) the model, the programmable parameter values and the characteristic data (200) is performed by acquiring the model, the programmable parameter values and the characteristic data from the memory respectively.
19. The computer system according to claim 18, wherein, When the processor executes the deployment (109) of the signal processing pipeline with updated programmable parameter values to the programmable architecture of the target device, the deployment step is performed by saving the updated programmable parameter values to the memory or permanent storage device and using the updated programmable parameter values to initialize the programmable architecture on each target device with the output.