Graphic size compensation method and system, equipment, storage medium and computer program product

Abstract

A pattern size compensation method and system, device, storage medium and computer program product, the method comprising: providing a design layout of a plurality of chip units, the design layout comprising a plurality of design patterns, the plurality of chip units forming an exposure unit, the exposure unit being an exposure area divided on a wafer; obtaining the pattern density distribution condition of each chip unit by taking the whole design patterns of the plurality of chip units in the exposure unit as a calculation reference; and according to the pattern density distribution condition of the chip unit, performing pattern size compensation on the design pattern of the chip unit to obtain a compensation pattern. According to the invention, accurate graph size compensation can be realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method and system, device, storage medium and computer program product for pattern size compensation. Background Technology

[0002] Currently, immersion lithography machines can provide half-pitch resolution of 36nm to 40nm. For sizes smaller than this, double or even multiple exposure techniques are required. Double or multiple exposure techniques require multiple independent exposures, each producing a portion of the pattern. These patterns are then transferred together to the substrate via etching. The advantage is that there are no special requirements for the regularity of the design layout, but the disadvantage is the need for two or more independent exposures. In comparison, self-aligned double (SADP) or self-aligned quadruple (SAQP) imaging techniques require only one exposure, using non-lithographic processes to achieve spatial frequency doubling of the photolithographic pattern. However, this requires the design layout to conform to certain rules. Furthermore, the severe imbalance in pattern density in the SAQP region causes significant dimensional differences in the same critical dimension (CD) at different locations within the SADP / SAQP region on the actual wafer, leading to degraded device performance or even device failure. Summary of the Invention

[0003] The problem solved by the embodiments of the present invention is to provide a graphic size compensation method and system, device, storage medium and computer program product, which is conducive to achieving more accurate graphic size compensation.

[0004] To address the aforementioned problems, embodiments of the present invention provide a pattern size compensation method, comprising: providing a design layout of multiple chip units, the design layout including multiple design patterns, the multiple chip units constituting an exposure unit, the exposure unit being an exposure area divided on a wafer; using the overall design patterns of the multiple chip units in the exposure unit as a calculation benchmark, obtaining the pattern density distribution of each chip unit; and performing pattern size compensation on the design patterns of the chip units according to the pattern density distribution of the chip units to obtain a compensated pattern.

[0005] Optionally, the design patterns of multiple chip units in the exposure unit are used as the overall calculation benchmark to obtain the pattern density of each chip unit, including: splicing the design patterns of multiple chip units in the exposure unit according to the position of the chip units on the wafer to obtain the target layout of the exposure unit; obtaining the pattern density distribution of the target layout; and obtaining the pattern density distribution of the chip units based on the pattern density distribution of the target layout.

[0006] Optionally, obtaining the graphic density distribution of the target map includes: setting a region of a preset size as a target point in the target map; obtaining the graphic density of each target point in the target map to form a graphic density distribution map as the graphic density distribution.

[0007] Optionally, the graphic density of each target point in the target map can be obtained, including: setting a target window centered on the target point; and obtaining the proportion of the area of ​​the design graphic in the target window as the graphic density.

[0008] Optionally, the proportion of the design graphic of the target layout in the target window can be obtained by the expression Density = Area(pattern) / Area(window) as the graphic density, where Density is the graphic density, Area(pattern) is the area of ​​the design graphic in the target window, and Area(window) is the total area of ​​the target window.

[0009] Optionally, before obtaining the pattern density distribution of each chip unit by using the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark, the method further includes: obtaining the target size of the layout range corresponding to the pattern density of the target point; setting a target window centered on the target point, and setting the area of ​​the target size centered on the target point as the target window.

[0010] Optionally, the target size of the layout range corresponding to the graphic density of the target point is obtained, including: taking any point of the design graphic in the design layout as the reference point; obtaining the graphic density corresponding to the reference point under different sized calculation windows; performing corresponding graphic size compensation on the design graphic of the reference point according to different graphic densities; obtaining the etched graphic corresponding to the design graphic after different graphic size compensation; obtaining the correlation coefficient corresponding to different graphic densities by combining the correlation between the graphic size of the etched graphic and the graphic size of the design graphic; and obtaining the size of the calculation window corresponding to the graphic density with the largest correlation coefficient as the target size.

[0011] Optionally, based on the pattern density distribution of the target layout, the pattern density distribution of the chip unit is obtained, including: dividing the pattern density distribution map according to the position and size of the chip unit in the exposure unit to obtain a pattern density sub-distribution map corresponding to each chip unit, as the pattern density distribution of the chip unit.

[0012] Optionally, based on the pattern density distribution of the chip unit, pattern size compensation is performed on the design pattern of the chip unit to obtain a compensated pattern, including: obtaining the size deviation compensation value corresponding to the design pattern in the chip unit based on the pattern density sub-distribution map of each chip unit; obtaining the sum of the pattern size of the design pattern and the size deviation compensation value as the compensation size to form a compensated pattern.

[0013] Optionally, before obtaining the pattern density distribution of the chip unit based on the pattern density distribution of the target layout, the method further includes: establishing a mapping relationship between pattern density and size deviation compensation value under different pattern sizes of the design pattern; obtaining the size deviation compensation value corresponding to the design pattern in the chip unit based on the pattern density sub-distribution map of each chip unit, including: combining the design pattern of each chip unit and the pattern density sub-distribution map corresponding to the chip unit, and obtaining the size deviation compensation value corresponding to the pattern density under the pattern size of each design pattern in the mapping relationship.

[0014] Optionally, based on the pattern density distribution of the chip unit, the design pattern of the chip unit is compensated for in terms of pattern size. After obtaining the compensated pattern, the method further includes: performing optical proximity correction processing on the compensated pattern.

[0015] Optionally, a design layout may be provided, in which design graphics include self-aligned double-patterned graphics and / or self-aligned quadruple-patterned graphics.

[0016] Accordingly, embodiments of the present invention also provide a pattern size compensation system, comprising: a design layout providing module, used to provide a design layout of multiple chip units, the design layout including multiple design patterns, the multiple chip units constituting an exposure unit, the exposure unit being an exposure area divided on a wafer; a pattern density distribution acquisition module, used to obtain the pattern density distribution of each chip unit using the overall design patterns of the multiple chip units in the exposure unit as a calculation benchmark; and a compensation pattern acquisition module, used to perform pattern size compensation on the design patterns of the chip units according to the pattern density distribution of the chip units to obtain a compensation pattern.

[0017] Accordingly, embodiments of the present invention also provide a device including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the graphics size compensation method provided in the embodiments of the present invention.

[0018] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the graphic size compensation method provided in the embodiments of the present invention.

[0019] Accordingly, embodiments of the present invention also provide a computer program product, including computer instructions, which, when executed by a processor, implement the graphics size compensation method provided in the embodiments of the present invention.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0021] The pattern size compensation method provided in this embodiment of the invention provides a design layout of multiple chip units, the design layout including multiple design patterns, the multiple chip units constituting an exposure unit, and the exposure unit being an exposure area divided on a wafer. Using the overall design patterns of the multiple chip units in the exposure unit as a calculation benchmark, the pattern density distribution of each chip unit is obtained. Based on the pattern density distribution of the chip units, pattern size compensation is performed on the design patterns of the chip units to obtain a compensated pattern. In this embodiment of the invention, using the overall design patterns of the multiple chip units in the exposure unit as a calculation benchmark to obtain the pattern density distribution of each chip unit is more efficient than calculating the pattern density distribution of each chip unit individually. This scheme proposes a method for calculating pattern density. When obtaining the pattern density distribution of the current chip unit, this scheme takes into account the influence of other chip units adjacent to the current chip unit in the exposure unit. In particular, for the calculation of pattern density at the edge of the chip unit, the influence of surrounding chip units is taken into account, which helps to avoid the problem of pattern density calculation distortion at the edge of the chip unit as much as possible. This makes the pattern density distribution of each chip unit more accurate. Accordingly, based on the pattern density distribution of the chip unit, the pattern size compensation of the chip unit design pattern is more accurate, which in turn helps to achieve more accurate pattern size compensation. Attached Figure Description

[0022] Figure 1 This is a flowchart of a graphic size compensation method;

[0023] Figure 2 This is a schematic diagram showing the steps involved in a graphic size compensation method.

[0024] Figure 3 This is a flowchart of an embodiment of the graphic size compensation method of the present invention;

[0025] Figures 4 to 6 This is a schematic diagram of each step in one embodiment of the graphic size compensation method of the present invention;

[0026] Figure 7 This is a functional block diagram of an embodiment of the graphic size compensation system of the present invention;

[0027] Figure 8 This is a hardware structure diagram of an embodiment of the device provided by the present invention. Detailed Implementation

[0028] The accuracy of current graphic size compensation methods needs improvement. This paper analyzes the reasons why the accuracy of graphic size compensation needs to be improved, using one such method as an example.

[0029] Figure 1 This is a flowchart of a graphic size compensation method. Figure 2 This is a schematic diagram of each step in a graphic size compensation method.

[0030] Reference Figures 1 to 2 Graphic size compensation methods include:

[0031] Step s1: Provide a design layout of chip unit 12. The design layout includes multiple design patterns. Multiple chip units 12 constitute an exposure unit 11. The exposure unit 11 is an exposure area divided on the wafer 10.

[0032] Step s2: Independently acquire the pattern density distribution of chip unit 12;

[0033] Step s3: Perform graphic size compensation on the design graphic of chip unit 12 according to the graphic density distribution.

[0034] The design patterns in the design layout of an exposure unit 11 are exposed together. The design patterns between adjacent chip units 11 affect each other. However, for an exposure unit 11, the pattern density distribution of chip units 12 is obtained independently. When obtaining the pattern density of each chip unit 12, the influence of other surrounding chip units 12 on the pattern density is not taken into account. This leads to the problem of distorted calculation of the pattern density of chip units 12. Consequently, when performing pattern size compensation on the design pattern of chip unit 12 based on the pattern density distribution, the pattern size compensation of the design pattern is deviated, making it difficult to perform accurate pattern size compensation.

[0035] To address the technical problem, embodiments of the present invention provide a method for graphic size compensation. (See reference...) Figure 3 The flowchart of an embodiment of the graphic size compensation method of the present invention is shown.

[0036] In this embodiment, the graphic size compensation method includes the following basic steps:

[0037] Step S1: Provide a design layout of multiple chip units. The design layout includes multiple design patterns. The multiple chip units constitute an exposure unit. The exposure unit is an exposure area divided on the wafer.

[0038] Step S2: Using the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark, obtain the pattern density distribution of each chip unit;

[0039] Step S3: Based on the pattern density distribution of the chip unit, perform pattern size compensation on the design pattern of the chip unit to obtain the compensated pattern.

[0040] In this embodiment of the invention, the overall design pattern of multiple chip units in the exposure unit is used as the calculation benchmark to obtain the pattern density distribution of each chip unit. Compared with the scheme of calculating the pattern density of each chip unit independently, this scheme can take into account the influence of other chip units adjacent to the current chip unit when obtaining the pattern density distribution of the current chip unit. In particular, for the calculation of the pattern density at the edge of the chip unit, the influence of the surrounding chip units is taken into account, which helps to avoid the problem of pattern density calculation distortion at the edge of the chip unit as much as possible. This makes the pattern density distribution of each chip unit more accurate. Accordingly, the pattern size compensation of the chip unit design pattern is more accurate based on the pattern density distribution of the chip unit, which is conducive to achieving more accurate pattern size compensation.

[0041] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 6 This is a schematic diagram of each step in one embodiment of the graphic size compensation method of the present invention.

[0043] refer to Figure 4 , Figure 4 (b) is Figure 4 (a) is a partial enlarged view. Step S1 is performed: a design layout of multiple chip units 120 is provided. The design layout includes multiple design patterns. The multiple chip units 120 constitute an exposure unit 110. The exposure unit 110 is an exposure area divided on the wafer 100.

[0044] The design pattern is for subsequent transfer onto wafer 100.

[0045] Specifically, after the graphic size compensation process is performed on the design pattern, the resulting graphic is used to make a photomask, which is then used for photolithography to form the corresponding graphic structure on the wafer.

[0046] In this embodiment, the wafer 100 is divided into a grid-like plurality of exposure units 110.

[0047] When the design pattern of the design layout is exposed and formed on the wafer, each exposure unit 110 is exposed and developed as a whole.

[0048] In this embodiment, each exposure unit 110 is composed of multiple chip units 120, and each chip unit 120 is used to form a chip that realizes the device function.

[0049] In this embodiment, the design layout is provided, and the design graphics include self-aligned double-patterned graphics and / or self-aligned quadruple-patterned graphics.

[0050] In a design layout, areas with self-aligned double patterned graphics (SADP) and self-aligned quadruple patterned graphics (SAQP) and areas without self-aligned double patterned graphics (SADP) and self-aligned quadruple patterned graphics (SAQP) are prone to uneven distribution of graphic density. Therefore, the graphic size compensation method of this embodiment is particularly suitable for design layouts with self-aligned double patterned graphics and / or self-aligned quadruple patterned graphics.

[0051] Reference Figures 5 to 6 Step S2: Using the overall design pattern of multiple chip units 120 in the exposure unit 110 as the calculation benchmark, obtain the pattern density distribution of each chip unit 120.

[0052] The graphic density distribution of each chip unit 120 is obtained, which is used for subsequent graphic size compensation of the design graphics of the chip unit 120.

[0053] In this embodiment, the overall design pattern of multiple chip units 120 in the exposure unit 110 is used as the calculation benchmark to obtain the pattern density distribution of each chip unit 120. Compared with the scheme of calculating the pattern density of each chip unit independently, this scheme can take into account the influence of other chip units 120 adjacent to the current chip unit 120 when obtaining the pattern density distribution of the current chip unit 120. In particular, for the calculation of the pattern density at the edge position of the chip unit 120, the influence of the surrounding chip units 120 is taken into account, which helps to avoid the problem of pattern density calculation distortion at the edge position of the chip unit 120 as much as possible. This makes the pattern density distribution of each chip unit 120 more accurate. Accordingly, the subsequent pattern size compensation of the design pattern of the chip unit 120 based on the pattern density distribution of the chip unit 120 is more accurate, which is conducive to achieving more accurate pattern size compensation.

[0054] refer to Figure 5 Using the overall design pattern of multiple chip units 120 in the exposure unit 110 as the calculation benchmark, the pattern density of each chip unit 120 is obtained, including: splicing the design patterns of multiple chip units 120 in the exposure unit 110 according to the position of the chip units 120 on the wafer 100 to obtain the target layout 130 of the exposure unit 110.

[0055] The target layout 130 is used as the layout for calculating the graphics density. Specifically, multiple chip units 120 are spliced ​​together according to their positions in the design layout. In this way, the original design layout is not changed during the graphics density calculation, thus obtaining an accurate graphics density.

[0056] In this embodiment, the graphic density distribution of the target layout 130 is obtained.

[0057] Obtain the graphic density distribution of the target layout 130 to obtain the graphic density distribution of each chip unit 120.

[0058] In this embodiment, obtaining the graphic density distribution of the target layout 130 includes: setting a region of a preset size as a target point in the target layout 130.

[0059] It should be noted that the target point is a tiny region. In the target layout 130, the graphic density of each target point is calculated to obtain the graphic density distribution of the entire target layout 130.

[0060] As an example, in this embodiment, the target point is set as a 1μm×1μm area.

[0061] In this embodiment, the graphic density of each target point in the target map 130 is obtained to form a graphic density distribution map as the graphic density distribution.

[0062] Outputting the graphic density distribution of the target layout 130 as a graphic density distribution map (layer map) clearly represents the graphic density of each target point in the target layout 130 and facilitates subsequent calculations.

[0063] In this embodiment, obtaining the graphic density of each target point in the target layout 130 includes: setting a target window centered on the target point.

[0064] The target window centered on the target point is the map area for calculating the graphic density of the target point.

[0065] In this embodiment, the area of ​​the design graphic within the target window is taken as the graphic density.

[0066] Specifically, the proportion of the area of ​​the design graphic in the target window is the ratio of the area of ​​the design graphic to the total area of ​​the target window.

[0067] In this embodiment, the proportion of the design graphic of the target layout 130 in the target window is obtained by the expression Density = Area(pattern) / Area(window) as the graphic density, where Density is the graphic density, Area(pattern) is the area of ​​the design graphic in the target window, and Area(window) is the total area of ​​the target window.

[0068] In this embodiment, before using the overall design pattern of multiple chip units 120 in the exposure unit 110 as the calculation benchmark to obtain the pattern density distribution of each chip unit 120, the method further includes: obtaining the target size of the layout range corresponding to the pattern density of the target point.

[0069] The target size is the optimal size for calculating the graphic density of the target point.

[0070] In this embodiment, obtaining the target size of the layout range corresponding to the graphic density of the target point includes: taking any point of the design graphic in the design layout as the reference point.

[0071] Specifically, a 1μm×1μm point in the design layout is used as the reference point.

[0072] In this embodiment, the graphic density corresponding to the reference point under different sized calculation windows is obtained.

[0073] Calculate the corresponding graphic density under different calculation window sizes to select the optimal calculation window size later.

[0074] In this embodiment, the design graphics of the reference point are compensated for according to different graphic densities.

[0075] The design pattern of the reference point is compensated for according to different pattern densities, and the etched structure is formed accordingly.

[0076] In this embodiment, the etched pattern corresponding to the design pattern after different pattern size compensations is obtained.

[0077] Obtain the etched graphics corresponding to the design graphics after different graphic size compensations, so as to obtain the optimal calculation window based on the graphic size of the etched graphics.

[0078] In this embodiment, the correlation coefficient corresponding to different pattern densities is obtained by combining the correlation between the pattern size of the etched pattern and the design pattern.

[0079] Specifically, the correlation coefficient characterizes the degree of correlation between the etched pattern and the design pattern. The larger the correlation coefficient, the higher the degree of correlation between the etched pattern and the design pattern, that is, the smaller the difference between the etched pattern and the design pattern. The smaller the correlation coefficient, the lower the degree of correlation between the etched pattern and the design pattern, that is, the larger the difference between the etched pattern and the design pattern.

[0080] In this embodiment, the size of the calculation window corresponding to the graph density with the highest correlation coefficient is obtained as the target size.

[0081] The calculation window corresponding to the graphic density with the highest correlation coefficient is the one within which the graphic size of the etched graphic is most accurate. Therefore, the size of the calculation window corresponding to the graphic density with the highest correlation coefficient is selected as the target size.

[0082] Accordingly, in this embodiment, a target window centered on the target point is defined, and a target area of ​​the target size centered on the target point is defined as the target window.

[0083] By setting a target area centered on the target point as the target window, the calculated graphic density within the target window becomes more accurate.

[0084] In this embodiment, the pattern density distribution of the chip unit 120 is obtained based on the pattern density distribution of the target layout 130.

[0085] Specifically, refer to Figure 6 Based on the pattern density distribution of the target layout 130, the pattern density distribution of the chip unit 120 is obtained, including: dividing the pattern density distribution map according to the position and size of the chip unit 120 in the exposure unit 110 to obtain a pattern density sub-distribution map 140 corresponding to each chip unit 120, as the pattern density distribution of the chip unit 120.

[0086] A pattern density sub-distribution map 140 corresponding to each chip unit 120 is obtained, and the pattern size compensation of the chip unit 120 is subsequently performed based on this map.

[0087] In this embodiment, before obtaining the pattern density distribution of the chip unit 120 based on the pattern density distribution of the target layout 130, the method further includes: establishing a mapping relationship between pattern density and size deviation compensation value under different pattern sizes of the design pattern.

[0088] A mapping relationship is established between graphic density and size deviation compensation value under different graphic sizes of the design graphic, which is used to subsequently compensate the graphic size of the design graphic based on the mapping relationship.

[0089] Specifically, in this embodiment, machine learning is used to establish a mapping relationship between graphic density and size deviation compensation value under different graphic sizes of the designed graphic.

[0090] Step S3: Based on the pattern density distribution of the chip unit 120, perform pattern size compensation on the design pattern of the chip unit 120 to obtain the compensated pattern.

[0091] Based on the pattern density distribution of the chip cell 120, pattern size compensation is performed on the design pattern of the chip cell 120 to compensate for the influence of the environment on the design pattern when transferring the design pattern in the chip cell 120 to the wafer. The compensated pattern is then used for subsequent optical proximity correction processing.

[0092] In this embodiment, the design pattern of the chip unit 120 is compensated for according to the pattern density distribution of the chip unit 120 to obtain the compensated pattern, including: obtaining the size deviation compensation value corresponding to the design pattern in the chip unit 120 based on the pattern density sub-distribution map 140 of each chip unit 120.

[0093] Based on the pattern density sub-distribution map 140 of each chip unit 120, the size deviation compensation value corresponding to the design pattern in the chip unit 120 is obtained to compensate for the pattern size of the design pattern.

[0094] In this embodiment, based on the pattern density sub-distribution map 140 of each chip unit 120, the size deviation compensation value corresponding to the design pattern in the chip unit 120 is obtained, including: combining the design pattern of each chip unit 120 and the pattern density sub-distribution map 140 corresponding to the chip unit 120, in the mapping relationship, the size deviation compensation value corresponding to the pattern density under the pattern size of each design pattern is obtained.

[0095] Specifically, in this embodiment, the sum of the graphic size and the size deviation compensation value of the design graphic is obtained as the compensation size to form the compensation graphic.

[0096] As an example, Table 1 shows the mapping relationship between a graphic density and a size deviation compensation value (Bias) under a graphic size (CD). The sum of the graphic size (CD) and the size deviation compensation value of the design graphic is obtained as the compensation size (retarget).

[0097] Table 1

[0098] Density Bias retarget 0<D<=X1 a1 CD+a1 X1 <D<=X2 a2 CD+a2 X3 <D<=X4 a3 CD+a3 … ... … Xn<D<1 an CD+an

[0099] In this embodiment, based on the pattern density distribution of the chip unit 120, the design pattern of the chip unit 120 is compensated for in terms of pattern size. After obtaining the compensated pattern, the method further includes: performing optical proximity correction processing on the compensated pattern.

[0100] Optical proximity correction (OPC) is applied to the compensation pattern to reduce the impact of optical proximity effect when the design pattern is transferred to the wafer.

[0101] Accordingly, the present invention also provides a graphic size compensation system. Figure 9 is a functional block diagram of an embodiment of the graphic size compensation system of the present invention.

[0102] In this embodiment, the pattern size compensation system 50 includes: a design layout providing module 501, used to provide a design layout of multiple chip units, the design layout including multiple design patterns, the multiple chip units constituting an exposure unit, and the exposure unit being an exposure area divided on a wafer; a pattern density distribution acquisition module 502, used to obtain the pattern density distribution of each chip unit using the overall design patterns of the multiple chip units in the exposure unit as a calculation benchmark; and a compensation pattern acquisition module 503, used to perform pattern size compensation on the design patterns of the chip units according to the pattern density distribution of the chip units to obtain a compensation pattern.

[0103] The design layout module 501 provides a design layout for multiple chip units. The design layout includes multiple design patterns, and the multiple chip units constitute an exposure unit, which is an exposure area divided on the wafer.

[0104] The design pattern is used for subsequent transfer onto the wafer.

[0105] Specifically, after the graphic size compensation process is performed on the design pattern, the resulting graphic is used to make a photomask, which is then used for photolithography to form the corresponding graphic structure on the wafer.

[0106] In this embodiment, the wafer is divided into multiple exposure units in a grid pattern.

[0107] When the design pattern of the design layout is exposed and formed on the wafer, each exposure unit is treated as a whole for exposure and development.

[0108] In this embodiment, each exposure unit is composed of multiple chip units, and each chip unit is used to form a chip that realizes the device function.

[0109] In this embodiment, the design layout is provided, and the design graphics include self-aligned double-patterned graphics and / or self-aligned quadruple-patterned graphics.

[0110] In a design layout, areas with self-aligned double patterned graphics (SADP) and self-aligned quadruple patterned graphics (SAQP) and areas without self-aligned double patterned graphics (SADP) and self-aligned quadruple patterned graphics (SAQP) are prone to uneven distribution of graphic density. Therefore, the graphic size compensation method of this embodiment is particularly suitable for design layouts with self-aligned double patterned graphics and / or self-aligned quadruple patterned graphics.

[0111] The pattern density distribution acquisition module 502 is used to obtain the pattern density distribution of each chip unit by taking the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark.

[0112] Obtain the pattern density distribution of each chip unit, which will be used for subsequent pattern size compensation of the chip unit design.

[0113] In this embodiment, the overall design pattern of multiple chip units in the exposure unit is used as the calculation benchmark to obtain the pattern density distribution of each chip unit. Compared with the scheme of calculating the pattern density of each chip unit independently, this scheme can take into account the influence of other chip units adjacent to the current chip unit when obtaining the pattern density distribution of the current chip unit. In particular, for the calculation of the pattern density at the edge of the chip unit, the influence of the surrounding chip units is taken into account, which helps to avoid the problem of pattern density calculation distortion at the edge of the chip unit as much as possible. This makes the pattern density distribution of each chip unit more accurate. Accordingly, the subsequent pattern size compensation of the chip unit design pattern based on the pattern density distribution of the chip unit is more accurate, which is conducive to achieving more accurate pattern size compensation.

[0114] In this embodiment, the overall design pattern of multiple chip units in the exposure unit is used as the calculation benchmark to obtain the pattern density of each chip unit, including: splicing the design patterns of multiple chip units in the exposure unit according to the position of the chip units on the wafer to obtain the target layout of the exposure unit.

[0115] The target layout is used as the layout for graphics density calculation. Specifically, multiple chip units are spliced ​​together according to their positions in the design layout. This way, the original design layout is not changed during graphics density calculation, thus obtaining an accurate graphics density.

[0116] In this embodiment, the graphic density distribution of the target map is obtained.

[0117] Obtain the graphic density distribution of the target layout to obtain the graphic density distribution of each chip unit.

[0118] In this embodiment, obtaining the graphic density distribution of the target map includes: setting a region of a preset size as a target point in the target map.

[0119] It should be noted that the target point is a tiny region. In the target map, the graphic density of each target point is calculated to obtain the graphic density distribution of the entire target map.

[0120] As an example, in this embodiment, the target point is set as a 1μm×1μm area.

[0121] In this embodiment, the graphic density of each target point in the target map is obtained to form a graphic density distribution map as the graphic density distribution.

[0122] Outputting the graphic density distribution of the target layout as a graphic density distribution map (layer map) clearly represents the graphic density of each target point in the target layout and facilitates subsequent calculations.

[0123] In this embodiment, obtaining the graphic density of each target point in the target map includes setting a target window centered on the target point.

[0124] The target window centered on the target point is the map area for calculating the graphic density of the target point.

[0125] In this embodiment, the area of ​​the design graphic within the target window is taken as the graphic density.

[0126] Specifically, the proportion of the area of ​​the design graphic in the target window is the ratio of the area of ​​the design graphic to the total area of ​​the target window.

[0127] In this embodiment, the proportion of the design graphic of the target layout in the target window is obtained by the expression Density = Area(pattern) / Area(window) as the graphic density, where Density is the graphic density, Area(pattern) is the area of ​​the design graphic in the target window, and Area(window) is the total area of ​​the target window.

[0128] In this embodiment, before using the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark to obtain the pattern density distribution of each chip unit, the method further includes: obtaining the target size of the layout range corresponding to the pattern density of the target point.

[0129] The target size is the optimal size for calculating the graphic density of the target point.

[0130] In this embodiment, obtaining the target size of the layout range corresponding to the graphic density of the target point includes: taking any point of the design graphic in the design layout as the reference point.

[0131] Specifically, a 1μm×1μm point in the design layout is used as the reference point.

[0132] In this embodiment, the graphic density corresponding to the reference point under different sized calculation windows is obtained.

[0133] Calculate the corresponding graphic density under different calculation window sizes to select the optimal calculation window size later.

[0134] In this embodiment, the design graphics of the reference point are compensated for according to different graphic densities.

[0135] The design pattern of the reference point is compensated for according to different pattern densities, and the etched structure is formed accordingly.

[0136] In this embodiment, the etched pattern corresponding to the design pattern after different pattern size compensations is obtained.

[0137] Obtain the etched graphics corresponding to the design graphics after different graphic size compensations, so as to obtain the optimal calculation window based on the graphic size of the etched graphics.

[0138] In this embodiment, the correlation coefficient corresponding to different pattern densities is obtained by combining the correlation between the pattern size of the etched pattern and the design pattern.

[0139] Specifically, the correlation coefficient characterizes the degree of correlation between the etched pattern and the design pattern. The larger the correlation coefficient, the higher the degree of correlation between the etched pattern and the design pattern, that is, the smaller the difference between the etched pattern and the design pattern. The smaller the correlation coefficient, the lower the degree of correlation between the etched pattern and the design pattern, that is, the larger the difference between the etched pattern and the design pattern.

[0140] In this embodiment, the size of the calculation window corresponding to the graph density with the highest correlation coefficient is obtained as the target size.

[0141] The calculation window corresponding to the graphic density with the highest correlation coefficient is the one within which the graphic size of the etched graphic is most accurate. Therefore, the size of the calculation window corresponding to the graphic density with the highest correlation coefficient is selected as the target size.

[0142] Accordingly, in this embodiment, a target window centered on the target point is defined, and a target area of ​​the target size centered on the target point is defined as the target window.

[0143] By setting a target area centered on the target point as the target window, the calculated graphic density within the target window becomes more accurate.

[0144] In this embodiment, the pattern density distribution of the chip unit is obtained based on the pattern density distribution of the target layout.

[0145] Specifically, in this embodiment, the pattern density distribution of the chip unit is obtained based on the pattern density distribution of the target layout, including: dividing the pattern density distribution map according to the position and size of the chip unit in the exposure unit to obtain a pattern density sub-distribution map corresponding to each chip unit, which serves as the pattern density distribution of the chip unit.

[0146] A pattern density sub-distribution map corresponding to each chip cell is obtained, and the pattern size compensation of the chip cell is then performed based on this map.

[0147] In this embodiment, before obtaining the pattern density distribution of the chip unit based on the pattern density distribution of the target layout, the method further includes: establishing a mapping relationship between pattern density and size deviation compensation value under different pattern sizes of the design pattern.

[0148] A mapping relationship is established between graphic density and size deviation compensation value under different graphic sizes of the design graphic, which is used to subsequently compensate the graphic size of the design graphic based on the mapping relationship.

[0149] Specifically, in this embodiment, machine learning is used to establish a mapping relationship between graphic density and size deviation compensation value under different graphic sizes of the designed graphic.

[0150] The compensation pattern acquisition module 503 is used to perform pattern size compensation on the design pattern of the chip unit according to the pattern density distribution of the chip unit, and obtain the compensation pattern.

[0151] Based on the pattern density distribution of the chip cell, pattern size compensation is performed on the design pattern of the chip cell to compensate for the influence of the environment on the design pattern when transferring the design pattern in the chip cell to the wafer. The compensated pattern is then used for subsequent optical proximity correction processing.

[0152] In this embodiment, the design pattern of the chip unit is compensated for according to the pattern density distribution of the chip unit to obtain the compensated pattern, including: obtaining the size deviation compensation value corresponding to the design pattern in the chip unit based on the pattern density sub-distribution map of each chip unit.

[0153] Based on the pattern density sub-distribution map of each chip cell, the size deviation compensation value corresponding to the design pattern in the chip cell is obtained to compensate for the pattern size of the design pattern.

[0154] In this embodiment, based on the pattern density sub-distribution map of each chip unit, the size deviation compensation value corresponding to the design pattern in the chip unit is obtained, including: combining the design pattern of each chip unit and the pattern density sub-distribution map corresponding to the chip unit, and in the mapping relationship, obtaining the size deviation compensation value corresponding to the pattern density under the pattern size of each design pattern.

[0155] Specifically, in this embodiment, the sum of the graphic size and the size deviation compensation value of the design graphic is obtained as the compensation size to form the compensation graphic.

[0156] As an example, Table 1 shows the mapping relationship between a graphic density and a size deviation compensation value (Bias) under a graphic size (CD). The sum of the graphic size (CD) and the size deviation compensation value of the design graphic is obtained as the compensation size (retarget).

[0157] Table 1

[0158] Density Bias retarget 0<D<=X1 a1 CD+a1 X1 <D<=X2 a2 CD+a2 X3 <D<=X4 a3 CD+a3 … ... … Xn<D<1 an CD+an

[0159] In this embodiment, the design pattern of the chip unit is compensated for in terms of pattern size according to the pattern density distribution of the chip unit. After obtaining the compensated pattern, the method further includes optical proximity correction processing on the compensated pattern.

[0160] Optical proximity correction (OPC) is applied to the compensation pattern to reduce the impact of optical proximity effect when the design pattern is transferred to the wafer.

[0161] This invention also provides a device that can implement the graphic size compensation method provided in this invention by loading a program, as described above. An optional hardware structure of the terminal device provided in this invention can be as follows: Figure 8 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0162] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and the processor 01, communication interface 02, and memory 03 communicate with each other through communication bus 04. Communication interface 02 can be an interface of a communication module for network communication, such as the interface of a GSM module. Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. Memory 03 may include high-speed RAM and may also include non-volatile memory (NVM), such as at least one disk storage device. Memory 03 stores one or more computer instructions, which are executed by processor 01 to implement the graphics size compensation method provided in this embodiment of the present invention.

[0163] It should be noted that the aforementioned terminal device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential for understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.

[0164] This invention also provides a storage medium storing one or more computer instructions for implementing the graphic size compensation method provided in this invention.

[0165] This invention also provides a computer program product, including computer instructions, which, when executed by a processor, implement the graphics size compensation method provided in this invention.

[0166] In this embodiment of the invention, the overall design pattern of multiple chip units in the exposure unit is used as the calculation benchmark to obtain the pattern density distribution of each chip unit. Compared with the scheme of calculating the pattern density of each chip unit independently, this scheme can take into account the influence of other chip units adjacent to the current chip unit when obtaining the pattern density distribution of the current chip unit. In particular, for the calculation of the pattern density at the edge of the chip unit, the influence of the surrounding chip units is taken into account, which helps to avoid the problem of pattern density calculation distortion at the edge of the chip unit as much as possible. This makes the pattern density distribution of each chip unit more accurate. Accordingly, the pattern size compensation of the chip unit design pattern is more accurate based on the pattern density distribution of the chip unit, which is conducive to achieving more accurate pattern size compensation.

[0167] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise stated, elements or features may be considered optional. Individual elements or features may be practiced without combination with other elements or features. Furthermore, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any embodiment may be included in another embodiment and may be replaced by corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that are not expressly referenced in each other may be combined to form embodiments of the present invention, or may be included as new claims in amendments made after the filing of this application.

[0168] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in memory units and executed by a processor. The memory units are located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0169] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0170] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for compensating graphic dimensions, characterized in that, include: A design layout of multiple chip units is provided, the design layout including multiple design patterns, the multiple chip units constituting an exposure unit, the exposure unit being an exposure area divided on a wafer; Using the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark, the pattern density distribution of each chip unit is obtained; Based on the pattern density distribution of the chip unit, the design pattern of the chip unit is compensated for in terms of pattern size to obtain a compensated pattern.

2. The graphic size compensation method as described in claim 1, characterized in that, Using the overall design pattern of multiple chip units in the exposure unit as a calculation benchmark, the pattern density of each chip unit is obtained, including: splicing the design layout of multiple chip units in the exposure unit according to the position of the chip units on the wafer to obtain the target layout of the exposure unit; Obtain the graphic density distribution of the target layout; Based on the graphic density distribution of the target layout, the graphic density distribution of the chip unit is obtained.

3. The graphic size compensation method as described in claim 2, characterized in that, Obtaining the graphic density distribution of the target map includes: setting a region of a preset size as a target point in the target map; Obtain the graphic density of each target point in the target map and construct a graphic density distribution map as the graphic density distribution.

4. The graphic size compensation method as described in claim 3, characterized in that, Obtaining the graphic density of each target point in the target map includes: setting a target window centered on the target point; The area of ​​the design graphic within the target window is taken as the graphic density.

5. The graphic size compensation method as described in claim 4, characterized in that, The proportion of the design graphic of the target layout in the target window is obtained by the expression Density = Area(pattern) / Area(window), which is used as the graphic density. Here, Density is the graphic density, Area(pattern) is the area of ​​the design graphic in the target window, and Area(window) is the total area of ​​the target window.

6. The graphic size compensation method as described in claim 4, characterized in that, Before obtaining the pattern density distribution of each chip unit by using the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark, the method further includes: obtaining the target size of the layout range corresponding to the pattern density of the target point; Set a target window centered on the target point, and set the target size area centered on the target point as the target window.

7. The graphic size compensation method as described in claim 6, characterized in that, Obtaining the target size of the layout range corresponding to the graphic density of the target point includes: taking any point of the design graphic in the design layout as a reference point; Obtain the graphic density corresponding to the reference point under different sized calculation windows; The design graphics of the reference point are compensated for corresponding graphic dimensions according to different graphic densities; Obtain the etched graphics corresponding to the design graphics after different graphic size compensations; By combining the correlation between the etched pattern and the design pattern size, correlation coefficients corresponding to different pattern densities are obtained; The size of the calculation window corresponding to the graph density with the highest correlation coefficient is obtained as the target size.

8. The graphic size compensation method as described in claim 3, characterized in that, Based on the graphic density distribution of the target layout, the graphic density distribution of the chip unit is obtained, including: dividing the graphic density distribution map according to the position and size of the chip unit in the exposure unit to obtain a graphic density sub-distribution map corresponding to each chip unit, as the graphic density distribution of the chip unit.

9. The graphic size compensation method as described in claim 8, characterized in that, Based on the pattern density distribution of the chip unit, the design pattern of the chip unit is compensated for in terms of pattern size to obtain a compensated pattern, including: obtaining the size deviation compensation value corresponding to the design pattern in the chip unit based on the pattern density sub-distribution map of each chip unit; The sum of the graphic dimensions of the design graphic and the size deviation compensation value is obtained as the compensation dimension, and the compensation graphic is formed.

10. The graphic size compensation method as described in claim 9, characterized in that, Before obtaining the pattern density distribution of the chip unit based on the pattern density distribution of the target layout, the method further includes: Establish the mapping relationship between graphic density and size deviation compensation value under different graphic sizes of the design graphics; Based on the pattern density sub-distribution map of each chip unit, the size deviation compensation value corresponding to the design pattern in the chip unit is obtained, including: combining the design pattern of each chip unit and the pattern density sub-distribution map corresponding to the chip unit, in the mapping relationship, obtaining the size deviation compensation value corresponding to the pattern density under the pattern size of each design pattern.

11. The graphic size compensation method as described in claim 1, characterized in that, Based on the pattern density distribution of the chip unit, the design pattern of the chip unit is compensated for in terms of pattern size. After obtaining the compensated pattern, the method further includes: performing optical proximity correction processing on the compensated pattern.

12. The graphic size compensation method as described in claim 1, characterized in that, The design layout provided includes self-aligned double-patterned graphics and / or self-aligned quadruple-patterned graphics.

13. A graphic size compensation system, characterized in that, include: A design layout providing module is used to provide a design layout of multiple chip units, the design layout including multiple design patterns, the multiple chip units constituting an exposure unit, the exposure unit being an exposure area divided on a wafer; The pattern density distribution acquisition module is used to acquire the pattern density distribution of each chip unit by taking the overall design pattern of multiple chip units in the exposure unit as the calculation benchmark. The compensation pattern acquisition module is used to perform pattern size compensation on the design pattern of the chip unit according to the pattern density distribution of the chip unit, and obtain the compensation pattern.

14. A device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the graphics size compensation method as described in any one of claims 1-12.

15. A storage medium, characterized in that, The storage medium stores one or more computer instructions, which are used to implement the graphic size compensation method as described in any one of claims 1-12.

16. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the graphic size compensation method according to any one of claims 1-12.

Images