Voltage regulator

Abstract

The invention provides a voltage regulator. The voltage regulator comprises a voltage division circuit, a switching circuit and a control circuit. The voltage division circuit divides a voltage of a source node to generate a plurality of voltages through a plurality of nodes. A switching circuit couples a source node to a switching node of the plurality of nodes in response to a switching control signal. The control circuit activates the switching control signal during at least a portion of the initialization period.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0109166, filed on August 14, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to a voltage regulator included in a semiconductor device. Background Technology

[0004] Semiconductor devices are core components of electronic devices and have a wide range of modern applications, such as in computing, communications, artificial intelligence, and memory technologies. Semiconductor devices can include transistors, diodes, integrated circuits (ICs), and so on.

[0005] Semiconductor devices may require a constant voltage to operate reliably under various operating conditions. For this purpose, voltage regulators can convert external voltages into internal voltages with the various levels required by the semiconductor device. In particular, techniques have been continuously researched to enable voltage regulators to quickly stabilize the level of the voltage output from the voltage regulator during the initial operation of the semiconductor device, in order to optimize the performance of the semiconductor device. Summary of the Invention

[0006] In embodiments of this disclosure, a voltage regulator may include a voltage divider circuit, a switching circuit, and a control circuit. The voltage divider circuit may be configured to divide the voltage of a source node to generate multiple voltages through multiple nodes. The switching circuit may be configured to connect a source node to a switching node among the multiple nodes in response to a switching control signal. The control circuit may be configured to activate the switching control signal during at least a portion of an initialization period.

[0007] In embodiments of this disclosure, a voltage regulator may include a voltage divider circuit and an output circuit. The voltage divider circuit may be configured to divide the voltage of a source node to generate multiple voltages through multiple nodes. The output circuit may be connected to a first node among the multiple nodes and may be configured to output the voltage of the node among the first nodes that corresponds to a selection code. During an initialization period, the node among the first nodes that corresponds to the selection code may have the lowest voltage level.

[0008] In embodiments of this disclosure, a voltage regulator may include a voltage divider circuit, an output circuit, and a selection code generation circuit. The voltage divider circuit may be configured to divide the voltage of a source node to generate multiple voltages through multiple nodes. The output circuit may be connected to a first node among the multiple nodes and may be configured to output the voltage of the node among the first nodes corresponding to a selection code. The selection code generation circuit may be configured to output an initial code as a selection code in response to an initialization period signal, regardless of the input selection code, and to output the pattern of the input selection code as a selection code in response to an inverted initialization period signal. Attached Figure Description

[0009] Figure 1 This is a circuit diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0010] Figure 2 This is a circuit diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This is a block diagram illustrating a control circuit according to an embodiment of the present disclosure.

[0012] Figure 4A This is a circuit diagram illustrating a level shifter of a first type according to an embodiment of the present disclosure.

[0013] Figure 4B This is a circuit diagram illustrating a second type of level shifter according to an embodiment of the present disclosure.

[0014] Figure 5 This is a signal timing diagram illustrating the operation of a voltage regulator according to an embodiment of the present disclosure.

[0015] Figure 6 This is a signal timing diagram illustrating the operation of a voltage regulator according to an embodiment of the present disclosure. Detailed Implementation

[0016] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0017] Figure 1 This is a circuit diagram showing a voltage regulator 100 according to an embodiment of the present disclosure.

[0018] Reference Figure 1 The voltage regulator 100 may include a control circuit 110, a comparator circuit 120, a current supply circuit (i.e., a current source) 130, a voltage divider circuit 140, a first output circuit 150, a second output circuit 160, and a switching circuit SU.

[0019] The control circuit 110 can output an enable signal EN, an inverted enable signal ENB, a switch control signal SW, a first selection code SL1, and a second selection code SL2 to control the operation of the voltage regulator 100.

[0020] The enable signal EN can be a signal activated when the voltage regulator 100 performs an operation. The inverted enable signal ENB can be the inverted signal of the enable signal EN. Immediately after the enable signal EN is activated, an initialization period can begin. The initialization period can be a period used to stabilize each of the first output voltage OV1 and the second output voltage OV2 output from the first output circuit 150 and the second output circuit 160 to a corresponding initial level.

[0021] The switch control signal SW can be a signal used to control the conduction of the switch circuit SU. When the enable signal EN transitions to the active state, the switch control signal SW can also transition to the active state. The switch control signal SW can be activated during the initialization period. The switch control signal SW can also be activated during a portion of the initialization period.

[0022] The first selection code SL1 can be a signal used to control the first output circuit 150 to output the voltage of the node corresponding to the first selection code SL1 in the first node ND1 of the voltage divider circuit 140 as the first output voltage OV1. During the initialization period, the control circuit 110 can generate the first selection code SL1 as a predetermined initial code. As used herein with respect to parameters such as predetermined timing, time, or voltage level, the term "predetermined" means that the value of the parameter is determined before the parameter is used in the process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm. After the initialization period, the control circuit 110 can generate the first selection code SL1 as the predetermined code.

[0023] The second selection code SL2 can be a signal used to control the second output circuit 160 to output the voltage of the node corresponding to the second selection code SL2 in the second node ND2 of the voltage divider circuit 140 as the second output voltage OV2. During the initialization period, the control circuit 110 can generate the second selection code SL2 as a predetermined initial code. After the initialization period, the control circuit 110 can generate the second selection code SL2 as a predetermined code.

[0024] Comparator circuit 120 can respond to enable signal EN by outputting comparison signal CP by comparing the level of reference voltage REF with the voltage level of feedback node FN. For example, comparator circuit 120 can be configured with an operational amplifier (OPamp) and can receive the reference voltage REF at the non-inverting input "+" and the voltage of feedback node FN at the inverting input "-". The voltage level of comparison signal CP can increase when the voltage level of reference voltage REF is higher than the voltage level of feedback node FN, and the voltage level of comparison signal CP can decrease when the voltage level of feedback node FN is higher than the voltage level of reference voltage REF.

[0025] The current supply circuit 130, in response to the enable signal EN, the inverting enable signal ENB, and the comparator signal CP, generates a voltage at the source node MN by supplying current to the source node MN between the current supply circuit 130 and the voltage divider circuit 140. The source voltage VE can be, for example, an external input voltage. When the voltage level of the comparator signal CP increases, the current supply circuit 130 can increase the voltage level of the source node MN by supplying more current to the source node MN; conversely, when the voltage level of the comparator signal CP decreases, the current supply circuit 130 can decrease the voltage level of the source node MN by supplying less current to the source node MN.

[0026] Voltage divider circuit 140 divides the voltage at source node MN to generate multiple voltages at multiple nodes. Voltage divider circuit 140 may include multiple resistors R connected in series between source node MN and ground node. The multiple nodes between resistors R may include a switching node SN and a feedback node FN. Switching node SN may be closer to source node MN than feedback node FN. Switching node SN may be located between source node MN and feedback node FN, and the voltage level of switching node SN may be higher than the voltage level of feedback node FN. At least one resistor R may be connected between source node MN and switching node SN, at least one resistor R may be connected between switching node SN and feedback node FN, and at least one resistor R may be connected between feedback node FN and ground node.

[0027] The switching circuit SU can be connected in parallel with the resistor R between the source node MN and the switching node SN. The switching circuit SU can connect the source node MN and the switching node SN by turning on in response to the switching control signal SW. The switching circuit SU can reduce the resistance and capacitance between the source node MN and the switching node SN by turning on in response to the switching control signal SW.

[0028] A first output circuit 150 can be connected to a first node ND1, which is selected from a plurality of nodes connected to a voltage divider circuit 140. In response to a first selection code SL1, the first output circuit 150 can output the voltage of the node in the first node ND1 corresponding to the first selection code SL1 as a first output voltage OV1. The first node ND1 can correspond to a pattern of the first selection code SL1. The node in the first node ND1 that is electrically closest to the ground node can be referred to as the first minimum voltage node. The first minimum voltage node can be the node in the first node ND1 that outputs the lowest voltage. The first minimum voltage node can be a node located between the switch node SN and the ground node. The first minimum voltage node can correspond to a predetermined pattern of the first selection code SL1, such as code 0. The first output circuit 150 can output the voltage of the first minimum voltage node in the first node ND1 as the first output voltage OV1 in response to the first selection code SL1 being code 0.

[0029] During the initialization period, a first selection code SL1 can be generated as an initial code. When the first selection code SL1 is used as the initial code input, the first output voltage OV1 can be stabilized to a predetermined initial level. In an embodiment, the node in the first node ND1 corresponding to the initial code of the first selection code SL1 can be a node located between the switch node SN and the ground node.

[0030] In this embodiment, the initial code of the first selection code SL1 can be 0. The node in the first node ND1 corresponding to the initial code of the first selection code SL1 can be the first minimum voltage node.

[0031] After the initialization period, the first selection code SL1 can be changed to a predetermined code corresponding to a predetermined target level of the first output voltage OV1. When the first selection code SL1 is input with the predetermined code, the first output voltage OV1 can be output at the target level.

[0032] In an embodiment, the target level of the first output voltage OV1 can be equal to or higher than the initial level of the first output voltage OV1.

[0033] The first output circuit 150 may include a first selection circuit 151 and a first filter circuit 152.

[0034] The first selection circuit 151 can be connected to the first node ND1. The first selection circuit 151 can respond to the first selection code SL1 by outputting the voltage of the node in the first node ND1 corresponding to the first selection code SL1 to the first output node ON1.

[0035] The first filter circuit 152 may include a resistor R1 and a capacitor C1. The resistor R1 may be connected between the first output node ON1 and the first filter node FN1. The capacitor C1 may be connected between the first filter node FN1 and a ground node. The first filter circuit 152 can remove noise from the voltage at the first output node ON1 and output a first output voltage OV1 to the first filter node FN1. In an embodiment, the first filter circuit 152 may be omitted.

[0036] The second output circuit 160 can be connected to a second node ND2, which is selected from a plurality of nodes connected to the voltage divider circuit 140. The second output circuit 160 can respond to a second selection code SL2 by outputting the voltage of the node in the second node ND2 corresponding to the second selection code SL2 as a second output voltage OV2. The second node ND2 can correspond to a specific mode of the second selection code SL2. The node in the second node ND2 that is electrically closest to the ground node can be referred to as the second minimum voltage node. The second minimum voltage node can be the node in the second node ND2 that outputs the lowest voltage. The second minimum voltage node can be a node located between the switching node SN and the ground node. The second minimum voltage node can correspond to a predetermined mode of the second selection code SL2, for example, code 0. The second node ND2 can be different from the first node ND1.

[0037] The second output circuit 160 may include a second selection circuit 161 and a second filter circuit 162. The second filter circuit 162 may include a resistor R2 and a capacitor C2. The configuration and operation of the second output circuit 160 may be similar to the configuration and operation described for the first output circuit 150.

[0038] In an embodiment, the voltage regulator 100 may not include one of the first output circuit 150 and the second output circuit 160.

[0039] In an embodiment, in addition to the first output circuit 150 and the second output circuit 160, the voltage regulator 100 may also include at least one other output circuit configured similarly to the first output circuit 150.

[0040] Figure 2 This is a circuit diagram showing a current supply circuit 130 according to an embodiment of the present disclosure.

[0041] Reference Figure 2 The current supply circuit 130 may include PMOS transistors P1 to P6, resistor R0, and NMOS transistors N1 and N2.

[0042] PMOS transistor P1 may include a source connected to the source voltage VE and a gate connected to the first gate node GN1. PMOS transistor P2 may include a source connected to the drain of PMOS transistor P1, a drain connected to the first gate node GN1, and a gate connected to the second gate node GN2. PMOS transistor P3 may include a source connected to the source voltage VE and a gate connected to the first gate node GN1. PMOS transistor P4 may include a source connected to the drain of PMOS transistor P3, a drain connected to the source node MN, and a gate connected to the second gate node GN2. Resistor R0 may be connected between the first gate node GN1 and the second gate node GN2. PMOS transistors P1 to P4 and resistor R0 may form a current mirror 135.

[0043] PMOS transistor P5 may include a source connected to the source voltage VE, a drain connected to the first gate node GN1, and a gate that receives the enable signal EN. PMOS transistor P6 may include a source connected to the source voltage VE, a drain connected to the second gate node GN2, and a gate that receives the enable signal EN.

[0044] NMOS transistor N1 may include a drain connected to a second gate node GN2, a source connected to a ground node, and a gate connected to a comparator node CN for the input comparator signal CP. NMOS transistor N2 may include a drain connected to the comparator node CN, a source connected to a ground node, and a gate for receiving an inverted enable signal ENB.

[0045] When the enable signal EN is activated as logic high, the driving force of the NMOS transistor N1 can increase as the voltage level of the comparator signal CP increases. Therefore, the current flowing at the first gate node GN1 and the second gate node GN2 can increase, and the current flowing through the current mirror 135 at the source node MN can also increase. Consequently, the voltage level of the source node MN can increase.

[0046] Conversely, when the enable signal EN is activated as logic high, the voltage level of the comparator signal CP decreases, thus reducing the driving force of the NMOS transistor N1. Therefore, the current flowing at the first gate node GN1 and the second gate node GN2 can be reduced, and the current flowing through the current mirror 135 at the source node MN can also be reduced. Consequently, the voltage level at the source node MN can be reduced.

[0047] Figure 3 This is a block diagram illustrating a control circuit 110 according to an embodiment of the present disclosure.

[0048] Reference Figure 3The control circuit 110 may include a signal combination circuit 115, a first selection code generation circuit 111, and a second selection code generation circuit 112.

[0049] The signal combination circuit 115 can respond to the initialization signal INIT and the switch control signal SW, and output the initialization period signal INIT_SW and the inverted initialization period signal INIT_SW_N.

[0050] The initialization signal INIT can be used to control the first output voltage OV1 and the second output voltage OV2 to stabilize at their respective initial levels, regardless of the operation of the switching circuit SU. The initialization signal INIT can also be activated when the enable signal EN transitions to the active state.

[0051] When at least one of the initialization signal INIT and the switch control signal SW is activated, the signal combination circuit 115 can output an activated initialization period signal INIT_SW. The signal combination circuit 115 can invert the initialization period signal INIT_SW to output an inverted initialization period signal INIT_SW_N. The initialization period can be the period during which the initialization period signal INIT_SW is activated. During the initialization period, the initialization period signal INIT_SW can be activated, and the inverted initialization period signal INIT_SW_N can be deactivated. After the initialization period, the initialization period signal INIT_SW can be deactivated, and the inverted initialization period signal INIT_SW_N can be activated.

[0052] The activation times of the initialization signal INIT and the switching control signal SW can be determined based on the time taken for each of the first output voltage OV1 and the second output voltage OV2 to stabilize to the corresponding initial level from the start of operation of the voltage regulator 100.

[0053] The signal combination circuit 115 may include an OR gate 116 and an inverter 117. The OR gate 116 can receive an initialization signal INIT and a switch control signal SW, and can perform an OR operation on the initialization signal INIT and the switch control signal SW to output an initialization period signal INIT_SW. The inverter 117 can receive the initialization period signal INIT_SW, invert the initialization period signal INIT_SW, and output an inverted initialization period signal INIT_SW_N.

[0054] The first selection code generation circuit 111 can receive the initialization period signal INIT_SW, the inverted initialization period signal INIT_SW_N, and the first input selection code ISL1, and output the first selection code SL1. The first input selection code ISL1 can be a signal used to control the output of the first output voltage OV1 at a predetermined target level.

[0055] When the initialization period signal INIT_SW is activated, that is, during the initialization period, the first selection code generation circuit 111 can output a predetermined initial code as the first selection code SL1, regardless of the first input selection code ISL1. As described later, the initial code of the first selection code SL1 can be determined based on the type of level shifters LS10 to LS15 included in the first selection code generation circuit 111. The voltage corresponding to the logic high level of the first selection code SL1 can be the source voltage VE.

[0056] When the inverted initialization period signal INIT_SW_N is activated, i.e. after the initialization period, the first selection code generation circuit 111 can output a first selection code SL1 where the logic high level is the source voltage VE by level shifting the first input selection code ISL1 where the logic high level is a predetermined voltage. The first selection code SL1 can be generated according to the pattern of the first input selection code ISL1. The pattern of the first input selection code ISL1 can be predetermined according to the target level of the first output voltage OV1.

[0057] The first selection code generation circuit 111 may include level shifters LS10 to LS15. The number of level shifters LS10 to LS15 may be the same as the number of bits constituting the first input selection code ISL1. When the initialization period signal INIT_SW is activated, each of the level shifters LS10 to LS15 may output the initial value of the initial code constituting the first selection code SL1. When the inverted initialization period signal INIT_SW_N is activated, each of the level shifters LS10 to LS15 may output the bit constituting the first selection code SL1 by level shifting the corresponding bit constituting the first input selection code ISL1.

[0058] For example, the level shifter LS10 can receive the initialization period signal INIT_SW, the inverted initialization period signal INIT_SW_N, and the first bit of the first input selection code ISL1. <0> And output the first digit of the first choice code SL1. <0> When the initialization period signal INIT_SW is activated, level shifter LS10 can output the first bit of the first selection code SL1 with a predetermined initial value corresponding to the type of level shifter LS10. <0> When the inverted initialization period signal INIT_SW_N is activated, the level shifter LS10 can select the first bit of the first input selection code ISL1. <0> Perform level shifting to output the first bit of the first selection code SL1. <0> Other level shifters LS11 through LS15 can operate similarly to level shifter LS10.

[0059] According to embodiments of this disclosure, Figure 4A This is a circuit diagram showing the first type of level shifter LS_T1, and Figure 4B This is a circuit diagram illustrating a second type of level shifter, LS_T2. Each of the input values ​​to the input nodes IN1 and IN2 of level shifters LS_T1 and LS_T2 can be a corresponding bit of the corresponding input selection code, and each of the output values ​​from the output nodes OUT1 and OUT2 of level shifters LS_T1 and LS_T2 can be a corresponding bit of the corresponding selection code.

[0060] Reference Figure 4A The first type of level shifter LS_T1 may include PMOS transistors P11 and P12 and NMOS transistors N11 to N14.

[0061] PMOS transistor P11 may include a source connected to the source voltage VE, a drain connected to the output node OUT1, and a gate connected to the inverting output node OUTB1. PMOS transistor P12 may include a source connected to the source voltage VE, a drain connected to the inverting output node OUTB1, and a gate connected to the output node OUT1. NMOS transistor N11 may include a drain connected to the inverting output node OUTB1, a source connected to the sink node SN1, and a gate connected to the input node IN1. NMOS transistor N12 may include a drain connected to the output node OUT1, a source connected to the sink node SN1, and a gate connected to the inverting input node INB1. NMOS transistor N13 may include a drain connected to the sink node SN1, a source connected to ground, and a gate that receives the inverted initialization period signal INIT_SW_N. NMOS transistor N14 may include a drain connected to the output node OUT1, a source connected to ground, and a gate that receives the initialization period signal INIT_SW.

[0062] When the initialization period signal INIT_SW is activated, that is, during the initialization period, the output value of output node OUT1 can be logic low (or 0) because NMOS transistor N14 is turned on, regardless of the input value of input node IN1. When the initialization period signal INIT_SW is activated, the first type level shifter LS_T1 can output logic low (or 0) as the initial value.

[0063] The input value to input node IN1 and the inverted input value to inverting input node INB1 can be out of phase. Therefore, when the inverting initialization period signal INIT_SW_N is activated, that is, after the initialization period, the output value of output node OUT1 of the first type level shifter LS_T1 can be the same logic value as the input value of input node IN1. As mentioned above, the input value of input node IN1 can be a predetermined voltage at a logic high level, and the output value of output node OUT1 can be the source voltage VE at a logic high level.

[0064] Reference Figure 4B The second type of level shifter LS_T2 may include PMOS transistors P21 and P22 and NMOS transistors N21 to N24. The PMOS transistors P21 and P22 and the NMOS transistors N21 to N23 may be similar to... Figure 4A The configuration includes PMOS transistors P11 and P12 and NMOS transistors N11 to N13. NMOS transistor N24 may include a drain connected to the inverting output node OUTB2, a source connected to the ground node, and a gate for receiving the initialization period signal INIT_SW.

[0065] When the initialization period signal INIT_SW is activated, i.e., during the initialization period, the voltage level of the inverting output node OUTB2 can decrease due to the conduction of NMOS transistor N24. Therefore, due to the conduction of PMOS transistor P21, the output value of output node OUT2 can be logic high (or 1), regardless of the input value of input node IN2. When the initialization period signal INIT_SW is activated, the second-type level shifter LS_T2 can output logic high (or 1) as the initial value.

[0066] The input value to input node IN2 and the inverted input value to inverting input node INB2 can be out of phase. Therefore, when the inverting initialization period signal INIT_SW_N is activated, that is, after the initialization period, the output value of output node OUT2 of the second type level shifter LS_T2 can be the same logic value as the input value of input node IN2. As mentioned above, the input value of input node IN2 can be a predetermined voltage at a logic high level, and the output value of output node OUT2 can be the source voltage VE at a logic high level.

[0067] Refer again Figure 3 The level shifters LS10 to LS15 included in the first selection code generation circuit 111 can be selected from a first type and a second type, respectively. The type of level shifters LS10 to LS15 can be determined based on which initial code the first selection code SL1 should output during the initialization period, regardless of the first input selection code ISL1. The type of level shifters LS10 to LS15 can be determined based on which initial level the first output voltage OV1 should stabilize at during the initialization period. For example, during the initialization period, when the first output voltage OV1 is output from the first minimum voltage node in the first node ND1, the initial code of the first selection code SL1 can be output as "000000". In this case, each of the level shifters LS10 to LS15 can be configured as a first type level shifter LS_T1, with an output of 0 as the initial value.

[0068] The second selection code generation circuit 112 can receive the initialization period signal INIT_SW, the inverted initialization period signal INIT_SW_N, and the second input selection code ISL2, and output the second selection code SL2. The second input selection code ISL2 can be a signal used to control the output of the second output voltage OV2 at a predetermined target level.

[0069] When the initialization period signal INIT_SW is activated, that is, during the initialization period, the second selection code generation circuit 112 can output a predetermined initial code as the second selection code SL2, regardless of the second input selection code ISL2. The initial code of the second selection code SL2 can be determined according to the type of level shifters LS20 to LS25 included in the second selection code generation circuit 112. The logic high level of the second selection code SL2 can be the source voltage VE.

[0070] When the inverted initialization period signal INIT_SW_N is activated, i.e. after the initialization period, the second selection code generation circuit 112 can output a second selection code SL2 where the logic high level is the source voltage VE by level shifting the second input selection code ISL2 where the logic high level is a predetermined voltage. The second selection code SL2 can be generated according to the pattern of the second input selection code ISL2. The pattern of the second input selection code ISL2 can be predetermined according to the target level of the second output voltage OV2.

[0071] The second selection code generation circuit 112 may include level shifters LS20 to LS25. The number of level shifters LS20 to LS25 may be the same as the number of bits constituting the second input selection code ISL2. When the initialization period signal INIT_SW is activated, each of the level shifters LS20 to LS25 may output the initial value of the initial code constituting the second selection code SL2. When the inverted initialization period signal INIT_SW_N is activated, each of the level shifters LS20 to LS25 may output the bit constituting the second selection code SL2 by level shifting the corresponding bit constituting the second input selection code ISL2.

[0072] The types of level shifters LS20 through LS25 can be selected from a first type and a second type, respectively. The type of level shifters LS20 through LS25 can be determined based on which initial code the second selection code SL2 should output during the initialization period, regardless of the second input selection code ISL2. The type of level shifters LS20 through LS25 can be determined based on which initial level the second output voltage OV2 should stabilize at during the initialization period. For example, when the initial code for the second output voltage OV2 needs to be "111110", level shifter LS20 can be configured as a first-type level shifter LS_T1 with an output of 0 as the initial code, and each of level shifters LS21 through LS25 can be configured as a second-type level shifter LS_T2 with an output of 1 as the initial value.

[0073] Figure 5This is a signal timing diagram illustrating the operation of a voltage regulator 100 according to an embodiment of the present disclosure.

[0074] Reference Figure 5 At time point T1, the enable signal EN, the switch control signal SW, and the initialization signal INIT can be activated. The initialization period can be the time interval between time point T1 and time point T5 when at least one of the switch control signal SW and the initialization signal INIT is activated.

[0075] Between time points T1 and T2, a comparison signal CP can be output from comparator circuit 120 in response to the enable signal EN. Specifically, because the voltage level of the reference voltage REF is higher than the voltage level of the feedback node FN, the voltage level of the comparison signal CP can be increased. Due to the increased voltage level of the comparison signal CP, the current output from the current supply circuit 130 to the source node MN can be increased. Therefore, the voltage levels of the source node MN and the multiple nodes of the voltage divider circuit 140, including the feedback node FN, can be increased.

[0076] According to the above embodiment, the initial code of the first selection code SL1 can be "000000", and the initial code of the second selection code SL2 can be "111110". In response to the first selection code SL1 "000000", the first output circuit 150 can output the voltage of the first minimum voltage node in the first node ND1 as the first output voltage OV1. Furthermore, in response to the second selection code SL2 "111110", the second output circuit 160 can output the voltage of the node in the second node ND2 corresponding to the second selection code SL2 "111110" as the second output voltage OV2. The node corresponding to the second selection code SL2 "111110" can be the node in the second node ND2 between the switching node SN and the feedback node FN.

[0077] Between time points T2 and T3, the voltage level of feedback node FN can become higher than the voltage level of reference voltage REF, causing the voltage level of comparison signal CP to decrease. Because the voltage level of comparison signal CP decreases, the current output from current supply circuit 130 to source node MN can decrease. Therefore, the voltage level of source node MN can decrease. Although the voltage level of source node MN decreases, due to the RC delay between source node MN and feedback node FN, the voltage level of feedback node FN can increase more slowly than before time point T2, and then decrease. When the voltage level of source node MN decreases, due to the RC delay, the voltage levels of first output voltage OV1 and second output voltage OV2 can increase more slowly than before time point T2.

[0078] Between time points T3 and T4, the level of the reference voltage REF can become higher than the voltage level of the feedback node FN, causing the voltage level of the comparison signal CP to increase. Due to the increased voltage level of the comparison signal CP, the current output from the current supply circuit 130 to the source node MN can increase. Therefore, the voltage level of the source node MN can increase. Although the voltage level of the source node MN increases, the voltage level of the feedback node FN can continue to decrease due to the RC delay between the source node MN and the feedback node FN. Due to the additional RC delay of the first filter circuit 152 and the second filter circuit 162, the voltage levels of the first output voltage OV1 and the second output voltage OV2 can continue to increase slowly.

[0079] Between time points T4 and T5, the voltage level of the comparator signal CP stabilizes because the voltage level of the feedback node FN becomes equal to the voltage level of the reference voltage REF. In response to the comparator signal CP, the voltage level of the source node MN also stabilizes. Although the voltage levels of the comparator signal CP and the source node MN stabilize, due to the RC delay between the source node MN and the feedback node FN, the voltage levels of the feedback node FN, the first output voltage OV1, and the second output voltage OV2 can fully stabilize after a delay time TD1. The delay time TD1 can be the time from when the comparator signal CP stabilizes to when each output voltage stabilizes.

[0080] At time point T5, the switch control signal SW and the initialization signal INIT can be deactivated.

[0081] After time point T5, when the switching circuit SU disconnects in response to the switching control signal SW, the resistance and capacitance between the source node MN and the switching node SN can increase. Therefore, the voltage level at the source node MN can increase slightly and then stabilize. When the switching circuit SU is disconnected, the capacitance between the feedback node FN and the ground node remains constant, so the voltage level at the feedback node FN can fluctuate temporarily or remain constant as shown.

[0082] After time point T5, since the initialization period has ended, a first selection code SL1 can be generated in response to the first input selection code ISL1. In response to the first selection code SL1, the first output circuit 150 can output the voltage of the node in the first node ND1 corresponding to the first selection code SL1 as the first output voltage OV1. After time point T5, the target level of the first output voltage OV1 can be higher than its initial level. Therefore, immediately following time point T5, the first output voltage OV1 can increase slightly and then stabilize at the target level.

[0083] Similarly, a second selection code SL2 can be generated in response to the second input selection code ISL2. For example, after time point T5, the pattern of the second input selection code ISL2 can be the same as the initial code "111110" of the second selection code SL2. The target level of the second output voltage OV2 can be the same as the initial level of the second output voltage OV2. Therefore, immediately after time point T5, the voltage level of the second output voltage OV2 can continue to stabilize.

[0084] In summary, if the resistance and capacitance between the feedback node FN and the comparison node CN, which outputs the comparison signal CP during the initialization period, are large, overshoot may occur at nodes higher than the feedback node FN due to RC delay. Overshoot at the source node MN may reduce the voltage level difference between the drain and source of each of the PMOS transistors P3 and P4, thereby reducing the driving force of PMOS transistors P3 and P4. Therefore, the stabilization of the first output voltage OV1 and the second output voltage OV2 may be delayed. However, according to embodiments of this disclosure, the resistance and capacitance between the source node MN and the switching node SN can be reduced by turning on the switching circuit SU during the initialization period, thereby reducing the RC delay. Therefore, overshoot during the initialization period can be suppressed, and the first output voltage OV1 and the second output voltage OV2 can stabilize more quickly.

[0085] Furthermore, even if the first output voltage OV1 is set to be output from the node between the source node MN and the switch node SN in the first node ND1 after the initialization period, the first output voltage OV1 during the initialization period can also be output from the first minimum voltage node, whose RC delay is reduced by the conduction of the switch circuit SU. Therefore, the first output voltage OV1 can stabilize to the initial level more quickly and then be adjusted to the target level.

[0086] Furthermore, even if the initial level needs to be equal to the target level, such as the second output voltage OV2, the second output voltage OV2 can be set to be output from the node between the switching node SN and the ground node in the second node ND2. Therefore, the second output voltage OV2 can be output from the node where the RC delay is reduced due to the conduction of the switching circuit SU, and thus can stabilize to the initial level more quickly.

[0087] In this embodiment, the switch control signal SW and the initialization signal INIT can be activated and deactivated in different timing sequences.

[0088] Figure 6 This is a signal timing diagram illustrating the operation of a voltage regulator 100 according to an embodiment of the present disclosure.

[0089] Reference Figure 6After time point T11, when the enable signal EN is activated, the switch control signal SW and the initialization signal INIT can be deactivated. When the switching circuit SU is disconnected in response to the switch control signal SW, the resistance and capacitance between the feedback node FN and the comparison node CN of the output comparison signal CP may be large. Therefore, due to the RC delay, overshoot may occur at nodes higher than the feedback node FN. In this case, the overshoot 601 generated at the source node MN may reduce the voltage level difference between the drain and source of each of the PMOS transistors P3 and P4, thereby reducing the driving force of the PMOS transistors P3 and P4. Therefore, the increase in the voltage level of the source node MN can be suppressed (see "602"), and thus, the stabilization of the first output voltage OV1 and the second output voltage OV2 can be delayed. Furthermore, because the RC delay is large, the time from when the comparison signal CP stabilizes to when the first output voltage OV1 and the second output voltage OV2 stabilize, i.e., the delay time TD2, can be longer than the delay time TD1.

[0090] According to embodiments of this technology, the voltage regulator can reduce RC delay, enabling the output voltage to quickly stabilize to the initial level.

[0091] Those skilled in the art to which this disclosure pertains will understand that this disclosure can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of this disclosure is defined by the described claims rather than the specific embodiments, and it should be understood that the scope of this disclosure includes the meaning and scope of the claims and all changes or modifications derived from equivalent concepts of the claims. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A voltage regulator, comprising: A voltage divider circuit divides the voltage of the source node to generate multiple voltages through multiple nodes; A switching circuit, in response to a switching control signal, connects the source node to the switching node among the plurality of nodes; as well as The control circuit activates the switch control signal during at least a portion of the initialization period.

2. The voltage regulator according to claim 1, further comprising: The comparison circuit compares the voltage level of the feedback node among the plurality of nodes with the level of the reference voltage to output a comparison signal.

3. The voltage regulator according to claim 2, wherein, The voltage level of the switching node is higher than the voltage level of the feedback node.

4. The voltage regulator according to claim 2, further comprising: A current supply circuit, in response to the comparison signal, supplies current to the source node to generate a voltage at the source node.

5. The voltage regulator according to claim 1, further comprising: The output circuit is connected to the first node among the plurality of nodes and outputs the voltage of the node among the first nodes corresponding to the selection code as the output voltage.

6. The voltage regulator according to claim 5, wherein, The control circuit includes a selection code generation circuit, wherein the selection code generation circuit: During the initialization period, in response to the initialization period signal, an initial code is output as the selection code, regardless of the input selection code; and After the initialization period, in response to the inverted initialization period signal, the mode of the input selection code is output as the selection code.

7. The voltage regulator according to claim 6, wherein, The voltage level of the node in the first node corresponding to the initial code is lower than the voltage level of the switch node.

8. The voltage regulator according to claim 6, wherein, Among the first nodes, the node corresponding to the initial code has the lowest voltage level.

9. The voltage regulator according to claim 6, wherein, The selection code generation circuit includes a level shifter that responds to the initialization period signal and outputs initial values ​​constituting the initial code, each of which is determined by the type of the corresponding level shifter.

10. The voltage regulator according to claim 9, wherein, The level shifter responds to the inverted initialization period signal by shifting the level of the bits constituting the input selection code.

11. A voltage regulator, comprising: A voltage divider circuit divides the voltage of the source node to generate multiple voltages through multiple nodes; as well as An output circuit is connected to the first node of the plurality of nodes and outputs the voltage of the node among the first nodes that corresponds to the selection code. During the initialization period, among the first nodes, the node corresponding to the selection code has the lowest voltage level.

12. The voltage regulator of claim 11, further comprising: A switching circuit, in response to a switching control signal, connects the source node to the switching node among the plurality of nodes.

13. The voltage regulator according to claim 12, wherein, The switch control signal is activated during at least a portion of the initialization period.

14. The voltage regulator of claim 12, further comprising: The comparison circuit compares the voltage level of the feedback node among the plurality of nodes with the level of the reference voltage to output a comparison signal.

15. The voltage regulator according to claim 14, wherein, The voltage level of the switching node is higher than the voltage level of the feedback node.

16. The voltage regulator of claim 11, further comprising: Select code generation circuit: During the initialization period, an initial code is output as the selection code, regardless of the input selection code; and After the initialization period, the pattern of the input selection code is output as the selection code.

17. A voltage regulator, comprising: A voltage divider circuit divides the voltage of the source node to generate multiple voltages through multiple nodes; An output circuit is connected to the first node of the plurality of nodes and outputs the voltage of the node of the first node corresponding to the selection code; as well as The selection code generation circuit, in response to the initialization period signal, outputs an initial code as the selection code, regardless of the input selection code, and in response to the inverted initialization period signal, outputs the pattern of the input selection code as the selection code.

18. The voltage regulator of claim 17, further comprising: A switching circuit, in response to a switching control signal, connects the source node to the switching node among the plurality of nodes.

19. The voltage regulator of claim 18, further comprising: The signal combination circuit activates the initialization period signal when at least one of the switch control signal and the initialization signal is activated.

20. The voltage regulator of claim 18, further comprising: The comparison circuit compares the voltage level of the feedback node among the plurality of nodes with the level of the reference voltage to output a comparison signal.

21. The voltage regulator according to claim 20, wherein, The voltage level of the switching node is higher than the voltage level of the feedback node.

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