In-memory adaptive clock synchronization method and chip for multi-mode brain-computer interface signals

Abstract

The invention relates to the cross technical field of integrated circuits and neural engineering, discloses an in-memory adaptive clock synchronization method and chip for a multi-mode brain-computer interface signal, and aims to solve the problems of large phase jitter, high power consumption and slow dynamic response caused by large sampling rate difference and dependence on an external non-adaptive phase-locked loop in the prior art. According to the method, instantaneous energy features of high-frequency electroencephalogram signals are extracted in real time in a storage and calculation integrated feature extraction array, phase adjustment control signals are generated through an energy-to-phase module, and a local ring oscillator is dynamically adjusted to generate a self-adaptive low-frequency sampling clock which is used for triggering sampling of low-frequency near-infrared spectrum signals and binding a high-precision timestamp. The system comprises a near infrared spectrum signal acquisition module, a storage and calculation integrated feature extraction array, an energy-to-phase module, a digital control ring oscillator, a timestamp generation module and a state synchronization control module. According to the invention, through a storage and calculation integrated closed-loop feedback mechanism, sub-picosecond-level synchronization precision, ultra-low power consumption and high-sensitivity response to key neural events are realized.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and neural engineering interdisciplinary technology, specifically relating to an in-memory adaptive clock synchronization method and chip for multimodal brain-computer interface signals. Background Technology

[0002] With the deepening application of brain-computer interface technology in fields such as neurorehabilitation, epilepsy monitoring, and brain cognition research, multimodal neural signal fusion has become a key path to improve decoding accuracy and system robustness. Electroencephalography (EEG), with its millisecond-level temporal resolution, can effectively capture the instantaneous dynamics of neural electrical activity, while functional near-infrared spectroscopy (fNIRS) provides centimeter-level spatial localization capabilities through changes in blood oxygen metabolism. While the complementary fusion of these two technologies can construct a "spatiotemporal two-dimensional" neural representation, their inherent sampling rate differences—EEG typically samples at a high frequency of 1kHz, while fNIRS samples at a low frequency of only 10Hz—make it difficult to align cross-modal signals on the time axis, severely limiting the reliability of joint feature extraction and the accuracy of clinical diagnosis.

[0003] Current technologies generally rely on external phase-locked loops (PLLs) or digital delay lines (DLLs) for clock synchronization. However, these solutions expose multiple structural defects in memory-compute separation architectures. First, the clock signal needs to be transmitted over a long distance off-chip to the fNIRS front end. Affected by parasitic capacitance and crosstalk, the measured phase jitter is as high as 52 picoseconds, causing a significant misalignment between the critical alpha wave peak in EEG and the blood oxygen response point in fNIRS. Clinical data shows that the cross-modal mismatch rate can reach 22.7%. Second, to calibrate the synchronization error, the system must repeatedly transfer EEG frequency band energy data to an external processor for analysis. This data transfer alone consumes 41% of the total power consumption, far exceeding the stringent low-power (<5mW) requirements of implantable BCI devices. More critically, existing PLLs use fixed calibration coefficients and cannot detect sudden dynamic changes in neural signals (such as a sudden drop of 80% in alpha wave energy during an epileptic seizure), resulting in a recalibration delay of more than 50 milliseconds, missing the capture window for critical neural events.

[0004] Therefore, there is an urgent need for an in-memory adaptive clock synchronization mechanism that deeply integrates sensing, computing, and control functions to fundamentally solve the timing mismatch problem caused by sampling heterogeneity in multimodal brain-computer interfaces. Summary of the Invention

[0005] To address the technical problems of large phase jitter, high power consumption, and slow dynamic response in existing multimodal brain-computer interface systems due to significant differences in signal sampling rates and reliance on external, non-adaptive phase-locked loops for clock synchronization mechanisms, this invention provides an in-memory adaptive clock synchronization method and chip for multimodal brain-computer interface signals. The aim is to deeply couple the clock synchronization function into the in-memory computing physical architecture, dynamically and in a closed-loop manner adjusting the sampling clock of low-frequency signals using the inherent characteristics of high-frequency neural signals, thereby achieving sub-picosecond precision, low power consumption, and real-time adaptive cross-modal timing synchronization.

[0006] According to one aspect of the present invention, an in-memory adaptive clock synchronization method for multimodal brain-computer interface signals is provided. The method is applied to a brain-computer interface chip integrating an in-memory computing feature extraction array, and includes the following steps:

[0007] The time-series data of high-frequency electroencephalogram (EEG) signals are received and stored in real time in the in-memory computing integrated feature extraction array;

[0008] The physical units of the in-memory computing feature extraction array are directly used to perform in-memory simulation calculations on the stored EEG signal time series data to extract instantaneous energy feature values ​​of a preset target frequency band. The instantaneous energy feature values ​​are output in the form of analog electrical signals.

[0009] The instantaneous energy characteristic value in the form of the analog electrical signal is input to an energy phase conversion module, which converts the instantaneous energy characteristic value into a phase adjustment control signal according to a preset nonlinear conversion function.

[0010] Using the phase adjustment control signal, the oscillation frequency and phase of a local digital control ring oscillator are finely adjusted in real time, thereby generating a low-frequency sampling clock that is dynamically coupled to the instantaneous energy characteristics of the EEG signal and is adaptively adjusted.

[0011] The analog-to-digital conversion sampling of the low-frequency near-infrared spectral signal is triggered using the adaptively adjusted low-frequency sampling clock.

[0012] At each valid sampling edge of the adaptively adjusted low-frequency sampling clock, the count value of a high-frequency system reference clock counter is synchronously latched to generate a high-precision cross-modal timestamp, and the timestamp is bound to the sampled near-infrared spectral signal data.

[0013] As one embodiment of the present invention, the direct use of the physical units of the in-memory computing feature extraction array to perform in-memory simulation computation specifically includes:

[0014] The in-memory computing feature extraction array is configured as a bandpass filter mode, and the weight coefficients of the bandpass filter are programmed by applying a preset control voltage to a specific row or column of the storage unit in the in-memory computing feature extraction array.

[0015] By sequentially activating word lines corresponding to EEG signal samples within a sliding time window, and using Kirchhoff's current law to physically sum the current flowing through each storage unit on the bit lines, an analog output current proportional to the target frequency band energy of the EEG signal within the sliding time window is directly obtained at the output end of the bit lines. The analog output current is the instantaneous energy characteristic value.

[0016] As one embodiment of the present invention, the energy phase conversion module performs the conversion according to a preset nonlinear conversion function, specifically including:

[0017] First, the analog output current is converted into an energy characterization voltage using a transimpedance amplifier;

[0018] Subsequently, the energy characterization voltage is input to a voltage-to-current conversion circuit with sigmoid function transfer characteristics. This circuit nonlinearly amplifies voltage changes that deviate from the reference energy level to generate the phase adjustment control signal, which is a control current.

[0019] The sigmoid function transfer characteristics ensure that the phase adjustment amplitude is small when the EEG signal energy is stable, while the phase adjustment amplitude increases dramatically when the EEG signal energy changes drastically, thus achieving a highly sensitive response to key neural events.

[0020] As one embodiment of the present invention, the real-time fine-tuning of a local digital control ring oscillator using the phase adjustment control signal specifically includes:

[0021] The phase adjustment control signal, i.e. the control current, is mirrored and injected into the internal node of each inverter delay unit constituting the digitally controlled ring oscillator;

[0022] The injected control current directly changes the charging and discharging rate of the inverter delay unit. When the instantaneous energy characteristic value is higher than the reference value, the injected current increases, shortening the delay time of the delay unit and causing the clock phase to lead. When the instantaneous energy characteristic value is lower than the reference value, the injected current decreases, extending the delay time of the delay unit and causing the clock phase to lag, thereby completing the continuous analog modulation of the oscillator phase.

[0023] As one embodiment of the present invention, the method further includes an initialization configuration step, which is performed before the method is executed, specifically including:

[0024] A state synchronization control module on a chip loads filter weight coefficients for setting the target frequency band into the in-memory computing feature extraction array.

[0025] An energy reference threshold and a gain coefficient for the nonlinear transition function are set for the energy phase-shifting module to distinguish sudden changes in the state of neural signals.

[0026] A nominal fundamental oscillation frequency is set for the digitally controlled ring oscillator, which corresponds to the target sampling rate of the near-infrared spectral signal.

[0027] According to another aspect of the present invention, an in-memory adaptive clock synchronization chip for multimodal brain-computer interface signals is provided, the chip comprising:

[0028] A memory-based feature extraction array, the structure of which is a modified static random access memory array, is used to receive and store time-series data of electroencephalogram (EEG) signals, and directly calculate the instantaneous energy of the EEG signals in a preset frequency band through analog circuits in the array, and output an analog current signal characterizing the instantaneous energy.

[0029] An energy-to-phase module, the input of which is connected to the output of the in-memory feature extraction array, integrates a transimpedance amplifier and a voltage-to-current conversion circuit with nonlinear transfer characteristics to convert the analog current signal into a phase-adjustable control current.

[0030] A digitally controlled ring oscillator is composed of an odd number of cascaded inverter delay units. Each inverter delay unit is provided with a current injection port that is modulated by the phase adjustment control current. The output of the digitally controlled ring oscillator generates an adaptive low-frequency sampling clock whose frequency and phase are both modulated in real time by the phase adjustment control current.

[0031] A near-infrared spectral signal acquisition module, wherein the sampling clock input terminal of its analog-to-digital converter is connected to the output terminal of the digitally controlled ring oscillator, is used to sample near-infrared spectral signals under the drive of the adaptive low-frequency sampling clock;

[0032] A timestamp generation module includes a high-speed counter driven by a high-frequency system reference clock and a data latch. The clock trigger input of the data latch is connected to the output of the digitally controlled ring oscillator, and is used to latch the current value of the high-speed counter at each valid edge of the adaptive low-frequency sampling clock to generate a high-precision timestamp.

[0033] A state synchronization control module, which is a digital logic control circuit, is connected to the in-memory computing feature extraction array, the energy phase conversion module, and the digitally controlled ring oscillator, respectively, and is used to configure their initialization parameters and control their operating modes.

[0034] As one embodiment of the present invention, each storage cell in the in-memory computing feature extraction array contains an additional transistor. These transistors form a current path controlled by the stored data bits. When the word line is activated, a current of a preset amplitude is allowed to flow to the bit line depending on whether the stored data is at a logic high level or a logic low level, thereby realizing the analog calculation function of multiplication and accumulation.

[0035] In one embodiment of the present invention, the voltage-to-current conversion circuit in the energy-to-phase conversion module is composed of a network of metal-oxide-semiconductor field-effect transistors operating in the subthreshold region, saturation region, and linear region. The voltage-to-current conversion circuit adopts a differential pair structure, wherein the input pair transistors M1 and M2 have a width-to-length ratio (W / L) of 10μm / 0.5μm, the load transistors M3 and M4 have a width-to-length ratio (W / L) of 2μm / 0.5μm, and the tail current source M5 has a width-to-length ratio (W / L) of 20μm / 0.5μm. All transistors are biased in the saturation region, and the threshold voltage offset ΔVth ≤ 20mV to ensure that the slope of the S-shaped function at the process corner is ≥ 0.8V / A. The gates of M1 and M2 are connected to the energy characterization voltage V_e and the reference voltage V_ref, respectively, and their sources are connected to the drain of M5. The gates and drains of M3 and M4 are shorted to form the output node I_ctrl. V_ref is provided by the bandgap reference circuit at 1.2V, and the gate bias voltage of M5 is V_bias = 0.7V. The sigmoid function transfer characteristic was solidified in the form of a hardware circuit by precisely designing the aspect ratio of each transistor. The sigmoid function transfer characteristic is defined by the S-shaped curve equation I_ctrl = I_max / (1 + exp(-k*(V_e - V_ref))), where k=2.5 V⁻¹, I_max=20μA, and V_ref=1.2V.

[0036] In one embodiment of the present invention, within each inverter delay unit of the digitally controlled ring oscillator, the current injection port is connected to the output of the energy phase-shifting module via a current mirror circuit, ensuring that the phase adjustment control current is proportionally distributed to each delay unit, achieving uniform and synchronous adjustment of the delay of the entire oscillation loop. The high-precision current mirror adopts a common-source, common-gate structure, with the image transistor M_mir and the reference transistor M_ref designed to have a width-to-length ratio strictly of 1:1, and a matching error ≤1%. A local offset calibration circuit is added to the injection terminal of each delay unit, compensating for ±5% current deviation through a 6-bit DAC. The width-to-length ratio of both the image transistor M_mir and the reference transistor M_ref is (W / L) = 5μm / 0.5μm; the 6-bit DAC is a resistor string type with a resistance value R = 10kΩ ±1%, and the reference current I_ref = 5μA is provided by a bandgap reference circuit; the calibration process includes the state machine outputting calibration codes 000000 to 111111 after power-on, and monitoring the iterative adjustment of the delay. Iterative algorithm: The DAC code is adjusted based on binary search until the delay error is ≤100ps. The 6-bit DAC is a resistor-string type with a reference current I_ref=5μA; the calibration data is loaded by the state synchronization control module through a lookup table during the initialization phase. After power-on, the state machine sequentially outputs the 6-bit calibration code to the DAC, while monitoring the loop delay and iteratively adjusting it to the target value.

[0037] In one embodiment of the present invention, the output of the timestamp generation module is connected to a data packaging module. The data packaging module combines the sampling data of the near-infrared spectral signal with the corresponding high-precision timestamp into a data frame for subsequent data processing and analysis, ensuring accurate alignment of different modal signals under a unified time reference.

[0038] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0039] By implementing the core function of clock synchronization at the physical layer of the in-memory computing chip, an ultra-short physical path closed-loop feedback system was constructed, from the extraction of EEG signal features to the generation of near-infrared spectral signal sampling clock. This completely eliminates phase jitter introduced by off-chip transmission lines, packaging, and chip parasitic parameters, and improves the synchronization accuracy to the sub-picosecond level.

[0040] By utilizing an in-memory computing architecture, feature extraction of EEG signals is performed directly at the data storage location, eliminating the need to move large amounts of raw data back and forth between the memory and the processor. This fundamentally eliminates the data transmission bottleneck under the von Neumann architecture, significantly reduces system power consumption, and meets the stringent requirements of implantable brain-computer interface devices for extreme power consumption.

[0041] A data-driven adaptive clock generation mechanism was created, which makes the sampling time of low-frequency signals no longer dependent on a fixed external clock, but determined by the real-time dynamic characteristics of high-frequency EEG signals. This enables instantaneous response to key neural events such as epileptic seizures, ensures the accuracy and robustness of cross-modal data synchronization under non-stationary signal conditions, and greatly improves the reliability of multimodal brain state decoding. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the overall technical architecture of the in-memory adaptive clock synchronization method and chip for multimodal brain-computer interface signals proposed in this invention.

[0043] Figure 2 This is a schematic diagram of the process of high-frequency EEG signal features driving low-frequency near-infrared signal sampling and cross-modal timestamp binding in this invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] This invention provides a method and chip for in-memory adaptive clock synchronization of multimodal brain-computer interface signals, such as... Figure 1 As shown, its core lies in fully integrating the cross-modal timing synchronization function between high-frequency EEG signals and low-frequency near-infrared spectral signals within the physical layer of the in-memory computing chip. By constructing a closed-loop feedback mechanism driven by neural signal characteristics, it achieves real-time, adaptive, sub-picosecond precision adjustment of the low-frequency sampling clock. The specific embodiments of this invention are described in detail below with reference to the accompanying drawings.

[0046] The method is applied to a brain-computer interface chip that integrates a memory-based feature extraction array. The chip contains an analog memory unit for processing high-frequency electroencephalogram (EEG) signals, a local oscillator for generating an adaptive low-frequency sampling clock, and an analog-to-digital converter front-end for acquiring low-frequency near-infrared spectral signals.

[0047] like Figure 2 As shown, the entire synchronization process begins with the reception and storage of high-frequency EEG signals and ends with the binding and output of low-frequency signal sampling data and its high-precision timestamp, specifically including:

[0048] S1: The on-chip state synchronization control module loads initial parameters into each functional module. The state synchronization control module writes a set of preset filter weight coefficients to the in-memory computing feature extraction array. These coefficients correspond to the target neural frequency band, such as the alpha band from 8 Hz to 13 Hz. The filter weight coefficients are loaded from external Flash memory into the 32×32 configuration register of the in-memory computing array via the SPI interface. The energy threshold and oscillation frequency are generated by a 12-bit DAC within the state synchronization control module, with an accuracy of ±0.1%, and support dynamic updates via the I²C bus during runtime. The alpha band filter weighting coefficients are designed based on a 128-point Hamming window FIR filter, for example, with a coefficient sequence of [0.0012, -0.0035, 0.0082, ..., -0.0035, 0.0012], with specific values ​​calculated based on a standard window function; or a coefficient generation algorithm is provided: h(n) = 0.54 - 0.46*cos(2πn / 127) for n=0 to 127, which is then stored in Flash after 8-bit linear quantization (range -0.5 to 0.5). The 12-bit DAC adopts a segmented architecture, with its reference voltage provided by an on-chip regulator, and a temperature drift ≤10ppm / °C. These weighting coefficients are applied to specific rows or columns of storage cells in the in-memory feature extraction array by controlling the voltage, thereby configuring the entire array as a bandpass filter. The state synchronization control module simultaneously sets a reference energy threshold for the energy-to-phase conversion module. This threshold is used to distinguish whether the neural signal is in a stationary or abrupt state, and sets the gain coefficient of the nonlinear conversion function to control the sensitivity of phase adjustment. Furthermore, the state synchronization control module sets a nominal fundamental oscillation frequency for the digitally controlled ring oscillator, which precisely corresponds to the target sampling rate of the near-infrared spectral signal, for example, 10 Hz.

[0049] S2: The in-memory feature extraction array receives and stores time-series data of high-frequency electroencephalogram (EEG) signals in real time. After being acquired by external electrodes, the EEG signals are pre-amplified and anti-aliasing filtered before being input to the in-memory feature extraction array at a sampling rate of 1 kHz. This array employs a modified static random access memory (SRAM) structure. Each memory cell, in addition to the standard six-transistor structure, integrates an additional current-path transistor controlled by the stored data bit. This additional transistor is an NMOS transistor, with its source connected to a local current source, its drain connected to a bit line, and its gate controlled by the stored data bit. The 5-bit array consists of five parallel NMOS transistors, each with a width-to-length ratio of 1:2:4:8:16, and its gate controlled by a 5-bit configuration word. When the analog voltage representing the EEG sample is quantized into a digital value by an 8-bit successive approximation analog-to-digital converter (SAR ADC), it is written to the memory cell. Each cell integrates a programmable current source, with its reference current provided by a bandgap reference circuit and its amplitude adjusted by a 5-bit binary weighted transistor array, with the current range set to 0-10 μA. Based on its stored logical state, this unit determines in subsequent calculation stages whether to allow a current of a preset amplitude to flow to a shared bit line. Specifically, each storage unit in the in-memory computing feature extraction array is configured as a programmable analog multiplier, receiving stored digital EEG sample values ​​and filter weights programmed via control voltage. For example, a memristor cross array or transistor array can be used, converting the digital EEG samples into analog voltage or current signals and performing analog multiplication with analog parameters representing filter weights to generate an analog current proportional to the product. The currents generated by all units are physically summed on the bit line according to Kirchhoff's current law, thereby achieving the multiplication and accumulation function.

[0050] S3: Using the physical units of the in-memory computing feature extraction array, in-memory simulation calculations are performed on the stored EEG signal time series data to extract the instantaneous energy feature value of a preset target frequency band. This process is achieved by configuring the array in bandpass filter mode. Specifically, the system sequentially activates word lines corresponding to EEG signal samples within a sliding time window. The length of this sliding window matches the periodic characteristics of the target frequency band; for example, for the alpha band, the window length can be set to 200 milliseconds, corresponding to 200 sampling points. During word line activation, each selected storage unit controls the magnitude of the current flowing through its current path based on its stored data bits (representing filter weights) and the input EEG sample value. According to Kirchhoff's current law, the currents of all activated units are physically summed on the bit lines, ultimately resulting in an analog output current directly at the output of the bit lines. The amplitude of this current is proportional to the energy of the EEG signal in the target frequency band within the sliding time window, which is the required instantaneous energy feature value, and is output as a continuous analog electrical signal without any digital conversion or external processor intervention.

[0051] S4: The instantaneous energy characteristic value in the form of the analog electrical signal is input to an energy phase-conversion module. This converter first converts the input analog output current into an energy characterization voltage through a high-gain, low-noise transimpedance amplifier. Subsequently, this energy characterization voltage is fed into a voltage-to-current conversion circuit with sigmoid function transfer characteristics. This circuit consists of a network of metal-oxide-semiconductor field-effect transistors operating in the subthreshold, saturation, and linear regions. The aspect ratio of each transistor is precisely designed so that its overall transfer function exhibits an sigmoid nonlinear characteristic. When the input voltage is close to the reference energy threshold, the output current changes gradually; while when the input voltage deviates significantly from the threshold, the output current changes drastically. The resulting phase adjustment control signal is a control current whose dynamic range strictly corresponds to the degree of abrupt change in the neural signal, ensuring the system's high sensitivity response to key neural events.

[0052] S5: Using the phase adjustment control signal, the oscillation frequency and phase of a local digitally controlled ring oscillator are finely adjusted in real time. This digitally controlled ring oscillator consists of an odd number of cascaded inverter delay units, forming a closed oscillation loop. Each inverter delay unit has a current injection port, which is connected to the output of the energy phase conversion module via a high-precision current mirror circuit. The phase adjustment control current is proportionally mirrored through the current mirror and injected into the internal nodes of each delay unit. The injected current directly changes the charging and discharging rate of the transistors inside the inverter. When the instantaneous energy of the EEG is higher than the reference value, the injected current increases, accelerating the charging and discharging process of the node capacitor, thereby shortening the propagation delay of the delay unit, resulting in a reduced period of the entire oscillation loop and an output clock phase lead. Conversely, when the instantaneous energy is lower than the reference value, the injected current decreases, the delay time increases, and the output clock phase lags. Through this continuous analog modulation, the clock signal output by the ring oscillator becomes a dynamically coupled, adaptively adjusted low-frequency sampling clock that is dynamically coupled to the instantaneous energy characteristics of the EEG signal.

[0053] S6: The adaptively adjusted low-frequency sampling clock triggers the analog-to-digital conversion sampling of the low-frequency near-infrared spectral signal. The near-infrared spectral signal acquisition module includes a photodetector, a transimpedance amplifier, and a high-resolution analog-to-digital converter. The sampling clock input of the analog-to-digital converter is directly connected to the output of a digitally controlled ring oscillator. Therefore, the start time of each analog-to-digital conversion is precisely triggered by the rising or falling edge of the aforementioned adaptive clock, ensuring that the sampling time of the fNIRS signal can track the dynamic changes of the EEG signal in real time, fundamentally eliminating cross-modal timing misalignment caused by a fixed sampling rate;

[0054] S7: At each valid sampling edge of the adaptively adjusted low-frequency sampling clock, the count value of a high-frequency system reference clock counter is synchronously latched to generate a high-precision cross-modal timestamp, and the timestamp is bound to the sampled near-infrared spectral signal data. The timestamp generation module includes a high-speed counter driven by a high-frequency system reference clock (e.g., 100 MHz) and a data latch. The clock trigger input of the data latch is connected to the adaptive low-frequency sampling clock. Whenever the adaptive clock generates a valid edge, the data latch immediately captures and latches the current count value of the high-speed counter. This count value is the precise timestamp of this fNIRS sampling, with a resolution on the order of tens of nanoseconds.

[0055] S8: This timestamp and the corresponding fNIRS sampled data are sent to the data packaging module to form a complete data frame. This data frame serves as the final output for use by the subsequent multimodal fusion analysis module, ensuring that signals from different physical sources can be accurately aligned and correlated under a unified and high-precision time reference. The high-frequency system reference clock (100MHz) and the adaptive clock share the same origin, both derived from the on-chip phase-locked loop; the data latch is triggered by a negative clock edge, and a dedicated clock tree buffer layer is inserted at the oscillator output to ensure that the clock offset is ≤50ps.

[0056] Throughout the entire process, from EEG signal reception, feature extraction, phase conversion, clock adjustment to fNIRS sampling and timestamp generation, all critical steps are completed within the chip, forming a closed-loop feedback system with an extremely short physical path. This design completely avoids the parasitic capacitance and inductance effects introduced by off-chip signal transmission, through package pins and long interconnects in traditional solutions, suppressing phase jitter to the sub-picosecond level. Simultaneously, since feature extraction is performed directly in memory in an analog manner, repeated transfer of raw EEG data between memory and the processor is avoided, minimizing the energy consumption related to synchronization calibration and meeting the stringent power consumption requirements of implantable devices. More importantly, this method establishes a clock generation mechanism driven by the dynamic characteristics of the neural signal itself, enabling the system to respond instantly to transient neural events such as epileptic seizures, ensuring the accuracy and robustness of cross-modal synchronization under non-stationary signal conditions.

[0057] The in-memory adaptive clock synchronization chip for the multimodal brain-computer interface signals has a hardware implementation that strictly corresponds to the steps described above. The core of the chip is an in-memory computing feature extraction array, whose physical structure supports in-situ simulation computation. The energy phase-conversion module, as an independent analog front-end module, is placed adjacent to this array to minimize interconnect latency. The digitally controlled ring oscillator adopts a fully custom design, with a precision current injection structure integrated within its inverter delay unit to ensure the linearity and uniformity of modulation. The near-infrared spectral signal acquisition module and the timestamp generation module share the same adaptive clock source, ensuring absolute synchronization between sampling and marking operations. The entire chip is uniformly scheduled and parameter-configured by a central state synchronization control module. This state machine initializes all modules upon system startup and monitors the system status during operation, triggering a recalibration process when necessary.

[0058] The chip can be manufactured using standard complementary metal-oxide-semiconductor (CMOS) processes, optimized for analog and mixed-signal performance. The memory cells of the in-memory feature extraction array must possess good analog-hold characteristics, and the transistors in the energy-phase-shifting module must operate in a precisely controllable bias region to achieve the desired nonlinear transfer function. The design of the digitally controlled ring oscillator must balance phase noise and tuning range to ensure a stable adaptive clock output across a wide dynamic range. Through this hardware-software co-design, this invention successfully transforms the complex cross-modal timing synchronization problem into a highly efficient, low-power, and high-precision on-chip analog closed-loop control problem, providing a solid technical foundation for next-generation high-performance brain-computer interface systems.

[0059] In the description of the embodiments of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "center," "top," "bottom," "top," "bottom," "inner," "outer," "inner side," and "outer side," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. "Inner side" refers to the interior or enclosed area or space. "Outer perimeter" refers to the area surrounding a specific component or specific area.

[0060] In the description of embodiments of the present invention, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of that feature. In the description of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0061] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0062] In the description of embodiments of the present invention, specific features, structures, materials or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0063] In the description of the embodiments of the present invention, it should be understood that "-" and "~" represent a range between two numerical values, and this range includes the endpoints. For example, "AB" represents a range greater than or equal to A and less than or equal to B. "A~B" represents a range greater than or equal to A and less than or equal to B.

[0064] In the description of embodiments of the present invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0065] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for in-memory adaptive clock synchronization of multimodal brain-computer interface signals, characterized in that, include: Time-series data of high-frequency electroencephalogram (EEG) signals are received in real time and stored in digital form in a brain-computer interface chip that integrates a memory-computing feature extraction array. The physical units of the in-memory computing feature extraction array are directly used to perform in-memory simulation calculations on the stored EEG signal time series data to extract instantaneous energy feature values ​​of a preset target frequency band. The instantaneous energy feature values ​​are output in the form of analog electrical signals. The instantaneous energy characteristic value in the form of the analog electrical signal is input to an energy phase conversion module, which converts the instantaneous energy characteristic value into a phase adjustment control signal according to a preset nonlinear conversion function. Using the phase adjustment control signal, the oscillation frequency and phase of a local digital control ring oscillator are finely adjusted in real time, thereby generating an adaptively adjusted low-frequency sampling clock that is dynamically coupled with the instantaneous energy characteristics of the EEG signal. The analog-to-digital conversion sampling of the low-frequency near-infrared spectral signal is triggered using the adaptively adjusted low-frequency sampling clock. At each valid sampling edge of the adaptively adjusted low-frequency sampling clock, the count value of a high-frequency system reference clock counter is synchronously latched to generate a high-precision cross-modal timestamp, and the timestamp is bound to the sampled near-infrared spectral signal data.

2. The in-memory adaptive clock synchronization method for multimodal brain-computer interface signals according to claim 1, characterized in that, Directly utilizing the physical units of the in-memory computing feature extraction array to perform in-memory simulation calculations specifically includes: The in-memory computing feature extraction array is configured as a bandpass filter mode, and the weight coefficients of the bandpass filter are programmed by applying a preset control voltage to a specific row or column of the storage unit in the in-memory computing feature extraction array. By sequentially activating word lines corresponding to EEG signal samples within a sliding time window, and using Kirchhoff's current law to physically sum the current flowing through each storage unit on the bit lines, an analog output current proportional to the target frequency band energy of the EEG signal within the sliding time window is directly obtained at the output end of the bit lines. The analog output current is the instantaneous energy characteristic value.

3. The in-memory adaptive clock synchronization method for multimodal brain-computer interface signals according to claim 2, characterized in that, The energy phase conversion module performs the conversion according to a preset nonlinear conversion function, specifically including: First, the analog output current is converted into an energy characterization voltage using a transimpedance amplifier; Subsequently, the energy characterization voltage is input to a voltage-to-current conversion circuit with sigmoid function transfer characteristics. This circuit nonlinearly amplifies voltage changes that deviate from the reference energy level to generate a phase adjustment control signal for the current characterization. The sigmoid function transfer characteristics ensure that the phase adjustment amplitude is small when the EEG signal energy is stable, but increases dramatically when the EEG signal energy changes drastically.

4. The in-memory adaptive clock synchronization method for multimodal brain-computer interface signals according to claim 3, characterized in that, The real-time fine-tuning of a local digitally controlled ring oscillator using the phase adjustment control signal specifically includes: The phase adjustment control signal, i.e. the control current, is mirrored and injected into the internal node of each inverter delay unit constituting the digitally controlled ring oscillator; The injected control current directly changes the charging and discharging rate of the inverter delay unit. When the instantaneous energy characteristic value is higher than the reference value, the injected current increases, shortening the delay time of the delay unit and causing the clock phase to lead. When the instantaneous energy characteristic value is lower than the reference value, the injected current decreases, extending the delay time of the delay unit and causing the clock phase to lag.

5. The in-memory adaptive clock synchronization method for multimodal brain-computer interface signals according to claim 4, characterized in that, The method further includes an initialization configuration step, which is performed before the method is executed, and specifically includes: A state synchronization control module on a chip loads filter weight coefficients for setting the target frequency band into the in-memory computing feature extraction array. An energy reference threshold and a gain coefficient for the nonlinear transition function are set for the energy phase-shifting module to distinguish sudden changes in the state of neural signals. A nominal fundamental oscillation frequency is set for the digitally controlled ring oscillator, which corresponds to the target sampling rate of the near-infrared spectral signal.

6. A memory-based adaptive clock synchronization chip for multimodal brain-computer interface signals, characterized in that, include: A memory-in-memory feature extraction array has a modified static random access memory array, wherein the storage unit contains additional transistors forming a current path controlled by the stored data bits, for receiving and storing time-series data of EEG signals in digital form, and directly calculating the instantaneous energy of the EEG signal in a preset frequency band through analog circuits within the array, and outputting an analog current signal characterizing the instantaneous energy. An energy-to-phase module, the input of which is connected to the output of the in-memory feature extraction array, integrates a transimpedance amplifier and a voltage-to-current conversion circuit with nonlinear transfer characteristics to convert the analog current signal into a phase-adjustable control current. A digitally controlled ring oscillator is composed of an odd number of cascaded inverter delay units. Each inverter delay unit is provided with a current injection port that is modulated by the phase adjustment control current. The output of the digitally controlled ring oscillator generates an adaptive low-frequency sampling clock whose frequency and phase are both modulated in real time by the phase adjustment control current. A near-infrared spectral signal acquisition module, wherein the sampling clock input terminal of its analog-to-digital converter is connected to the output terminal of the digitally controlled ring oscillator, is used to sample near-infrared spectral signals under the drive of the adaptive low-frequency sampling clock; A timestamp generation module includes a high-speed counter driven by a high-frequency system reference clock and a data latch. The clock trigger input of the data latch is connected to the output of the digitally controlled ring oscillator, and is used to latch the current value of the high-speed counter at each valid edge of the adaptive low-frequency sampling clock to generate a high-precision timestamp. A state synchronization control module, which is a digital logic control circuit, is connected to the in-memory computing feature extraction array, the energy phase conversion module, and the digitally controlled ring oscillator, respectively, and is used to configure their initialization parameters and control their operating modes.

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