Write command synchronous updating method and system applied to CSR register array
By sending write commands and generating synchronization selection signals on the control bus, the synchronous update of the CSR register array is achieved, solving the problems of high latency and timing inconsistency in CSR register synchronous update, and realizing low-latency and high-efficiency CSR register synchronous operation.
Patent Information
- Application Number
- CN202511771726.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-03-03
AI Technical Summary
In modern System-on-Chip (SoC) or Microcontroller (MCU), the synchronous update of the CSR register suffers from high latency, timing inconsistencies, and large software overhead, leading to abnormal system behavior and degraded control performance.
By sending a write command on the control bus, the master module's master CSR register reads the write data and generates a synchronization selection signal. The synchronization selection module instructs the slave module set to perform synchronous updates. The master module's synchronization unit propagates the write data to the slave modules within the first bus cycle, thus realizing the synchronous write operation of the CSR register.
The CSR register of the multi-function module is updated synchronously within the same bus cycle, meeting the requirements of low latency, high real-time performance and low system overhead, and has flexible adaptability and good scalability.
Smart Images
Figure CN121597285A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology, and in particular relates to a method and system for synchronously updating write commands applied to a CSR register array. Background Technology
[0002] In modern complex Systems-on-Chip (SoC) or Microcontrollers (MCUs), multiple functional modules are often included, each equipped with an independent Control Registry (CSR) register for configuring the module's operating mode, status feedback, etc. Under current technology, the CSR registers of each functional module are accessed independently by the system control bus, and update operations are isolated from each other. This leads to several problems, such as high synchronization latency. If multiple functional modules' CSR registers need to be updated simultaneously (e.g., starting multi-channel PWM, synchronous ADC sampling), they must be written one by one by software, resulting in delays of multiple bus cycles. Furthermore, timing inconsistencies can cause abnormal system behavior due to time differences in CSR register updates between different functional modules, especially in real-time control applications (e.g., motor drives, power management), affecting control performance and even causing malfunctions. Finally, high software overhead, relying on CPU polling or interrupts to coordinate multiple functional modules, consumes significant processing resources and reduces system efficiency.
[0003] While existing technologies have attempted to synchronize actions between functional modules through methods such as "global synchronization signals" or "event triggering chains," these methods typically operate at the module's functional behavior layer (such as PWM counter reset or ADC triggering) rather than directly at the register configuration layer, and therefore cannot solve the synchronization problem of the CSR register configuration itself.
[0004] Therefore, there is an urgent need for a hardware mechanism that can synchronously update the CSR register in the multi-functional module within the bus write cycle to meet the control requirements of high performance, low latency, and strong consistency. Summary of the Invention
[0005] This invention provides a method and system for synchronously updating write commands for CSR register arrays, in order to solve the technical problem that it is difficult to efficiently achieve synchronous updates for multiple sets of CSR registers in the prior art.
[0006] To solve the above problems, the technical solution of the present invention is: a method for synchronously updating write commands applied to a CSR register array, comprising the following steps: S1: Send a write command to the main module based on the control bus. The write command contains the write address and write data. S2: Based on the write address, if the main module is the target of the write command recorded in the write address, then the main CSR register deployed in the main module reads the write data in the first bus cycle; Furthermore, the synchronization selection module simultaneously parses the write command and generates a synchronization selection signal based on the write address pointing to the target slave module. The synchronization selection signal is used to indicate the set of slave modules that need to be updated synchronously. S3: During the first bus cycle, the synchronization unit of the master module is configured to send the write data and the synchronization selection signal to all the slave modules. The slave CSR registers deployed in the slave modules select to read the write data based on the indication of the synchronization selection signal. S4: During the first bus cycle, the master CSR register and several selected slave CSR registers synchronously complete the write operation of the same data content.
[0007] Preferably, the synchronization selection signal is configured with a number of programmable control bits equal to the number of slave modules, and the arrangement order of the control bits matches the numbering order of the slave modules. Control position 0 indicates that the slave module matched with the current control bit does not need to be updated synchronously in the current bus cycle, while control position 1 indicates that the slave module matched with the current control bit needs to be updated synchronously in the current bus cycle.
[0008] Preferably, in S3, the slave CSR registers deployed in the slave modules select to read the write data based on the indication of the synchronization selection signal, including the following steps: S31: The synchronization units corresponding to the several slave modules respectively perform a logical AND operation on the control bits of the corresponding bits in the write data and the synchronization selection signal. When the result of the logical AND operation is 0, the slave CSR register corresponding to the slave module is enabled not to read the write data; when the result of the logical AND operation is 1, the slave CSR register corresponding to the slave module is enabled to read the write data.
[0009] Preferably, the synchronization unit of the master module and the synchronization units of the slave modules are connected in a cascaded structure to establish a hardware synchronization link. The master module is connected to the slave module in the first order, and the slave modules are connected sequentially according to their numbering order. Within the same bus cycle, the write data and the synchronization selection signal are propagated step by step from the master module to any of the slave modules.
[0010] Preferably, a hardware synchronization link is established between the synchronization unit of the master module and the synchronization units of the slave modules using a broadcast structure. The master module is connected to all the slave modules respectively. Within the same bus cycle, the write data and the synchronization selection signal are broadcast and propagated between the master module and any of the slave modules.
[0011] Preferably, the synchronization unit of the master module and the synchronization units of the slave modules simultaneously establish hardware synchronization links using a cascaded structure and a broadcast structure. The master module is connected to several primary slave modules respectively. Each primary slave module is sequentially connected to several secondary slave modules under its name based on the numbering order. Within the same bus cycle, the write data and the synchronization selection signal are broadcast by the master module to the primary slave module, and then propagated step by step by the primary slave module to the secondary slave module.
[0012] Preferably, the master CSR register and the slave CSR register include, but are not limited to, PWM control registers, ADC configuration registers, DMA control registers, or communication interface registers.
[0013] Preferably, a method for synchronously updating write commands applied to a CSR register array further includes the following steps: S5: After the main CSR register and several selected subordinate CSR registers synchronously complete the write operation of the same data content, the write operation of the main CSR register and the subordinate CSR register is determined based on the status registers deployed in the main module and the subordinate module respectively, and a synchronization confirmation signal is generated and fed back.
[0014] Based on the same concept, the present invention also provides a write command synchronization update system for a CSR register array, used to execute the write command synchronization update method for a CSR register array as described in any one of the above, including: The main module includes a main CSR register and a synchronization unit. The main module is used to receive write commands output from the control bus independently. At least one set of slave modules, each of which is provided with a slave CSR register and a synchronization unit; A synchronization selection module is used to generate a synchronization selection signal according to the write command; The synchronization unit of the master module and the synchronization unit of any of the slave modules form a hardware synchronization link. The synchronization unit of the master module and the synchronization unit of the slave module are used to parse write data and synchronization selection signals.
[0015] Preferably, a write command synchronization update system for a CSR register array further includes: The master module and any of the slave modules are also provided with a status register. The status register is used to determine whether the write operation of the master CSR register and the slave CSR register is successful, generate a synchronization confirmation signal and send it back.
[0016] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art: This invention provides a method and system for synchronously updating write commands in a CSR register array. First, a write command, containing a write address and write data, is sent to the master module via the control bus. Then, the master CSR register deployed in the master module reads the write data within the first bus cycle. Simultaneously, a synchronization selection module parses the write command and generates a synchronization selection signal based on the write address pointing to the target slave module. This signal indicates the set of slave modules requiring synchronous updates. Next, within the first bus cycle, the synchronization unit of the master module sends the write data and the synchronization selection signal to all slave modules. The corresponding slave CSR registers deployed in several slave modules select which data to read based on the synchronization selection signal. Finally, within the first bus cycle, the master CSR register and the selected slave CSR registers synchronously complete the write operation for the same data content. This invention, based on a hardware mechanism, can complete the update of all target functional modules within the same bus cycle, satisfying low latency and high real-time performance. It has high hardware utilization efficiency and low system overhead, and offers flexible adaptability and good scalability for different application scenarios. Attached Figure Description
[0017] Figure 1 The present invention provides a flowchart of a write command synchronous update method applied to a CSR register array; Figure 2 A first schematic diagram of the hardware synchronization link provided by the present invention; Figure 3 A second schematic diagram of the hardware synchronization link provided by the present invention; Figure 4 The third schematic diagram of the hardware synchronization link provided by this invention. Detailed Implementation
[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method and system for synchronously updating write commands applied to a CSR register array, as proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims.
[0019] First Embodiment See Figure 1 This embodiment provides a method for synchronously updating write commands for a CSR register array, which is used to achieve synchronous update of write commands for all CSR registers within the same bus cycle. Specifically, it includes the following steps: S1: Send a write command to the main module based on the control bus. The write command contains the write address and write data.
[0020] In this embodiment, the CSR register array formed by several CSR registers is distributed in the master module and several slave modules. The control bus and the master module form a unique connection. That is, in the initial stage of synchronous update of write command, only the master module can receive the write command output by the control bus. The write address is used to record the master module and slave module pointed to by the current write command, and the write data is used to record the actual value or configuration information that needs to be written to the target CSR register.
[0021] S2: Based on the write address, if the write command recorded in the write address of the master module points to the target, the master CSR register deployed in the master module reads the write data in the first bus cycle; and the synchronization selection module parses the write command at the same time and generates a synchronization selection signal based on the write address pointing to the target slave module. The synchronization selection signal is used to indicate the set of slave modules that need to be updated synchronously.
[0022] In this embodiment, the master module first determines whether it needs to perform a CSR register write command update based on the write command target recorded in the write address. During this process, a synchronization selection module is also provided. This synchronization selection module is uniquely connected to the master module. Based on the write command target recorded in the write address, the synchronization selection module generates a synchronization selection signal. This signal is used to mark which slave modules need to perform CSR register write command updates in subsequent steps.
[0023] S3: During the first bus cycle, the synchronization unit of the master module sends the write data and synchronization selection signal to all slave modules. The slave CSR registers deployed in several slave modules select to read the write data based on the indication of the synchronization selection signal.
[0024] In this embodiment, the master module and each slave module are equipped with a separate synchronization unit. The master module and each slave module communicate with each other through their respective synchronization units. The synchronization unit further parses the write data and synchronization selection signal to determine whether the slave CSR register in the slave module to which the synchronization unit belongs needs to read the write data, and then executes the write command to update.
[0025] S4: Based on the hardware deployment mechanism, during the first bus cycle, write data and synchronization selection signals are propagated among all functional modules, enabling the master CSR register and several selected slave CSR registers to synchronously complete the write operation of the same data content.
[0026] The following will provide a more detailed explanation of the specific steps and implementation functions of the write command synchronization update method for the CSR register array provided in this embodiment: Preferably, in one embodiment, the synchronization selection module adopts a one-hot encoding method, and the synchronization selection signal it generates is configured with a number of programmable control bits equal to the number of slave modules. Furthermore, the arrangement order of the control bits matches the numbering order of the slave modules, thus establishing a unique mapping association between the control bits and the slave modules.
[0027] In the synchronization selection signal, a control bit of 0 indicates that the slave module matching the current control bit does not need to be updated synchronously in the current bus cycle, while a control bit of 1 indicates that the slave module matching the current control bit needs to be updated synchronously in the current bus cycle. The control bit of 0 or 1 is determined by the target of the write command recorded in the write address.
[0028] For example, there are three slave modules, namely the first slave module, the second slave module, and the third slave module, arranged in sequential order. The write address of the write command records that the first slave module and the second slave module need to execute the CSR register write command to update within the current bus cycle, while the third slave module needs to maintain its original configuration. The synchronization selection signal generated by the synchronization selection module is recorded as: syncsel[1:1:0].
[0029] Furthermore, in S3, the slave CSR registers deployed in several slave modules select to read or write data based on the indication of the synchronization selection signal, including the following steps: S31: The synchronization units corresponding to several slave modules perform a logical AND operation on the control bits of the corresponding bits in the write data and synchronization selection signal. When the result of the logical AND operation is 0, the slave CSR register of the corresponding slave module is enabled without reading the write data; when the result of the logical AND operation is 1, the slave CSR register of the corresponding slave module is enabled to read the write data.
[0030] For example, there are three slave modules arranged sequentially: a first slave module, a second slave module, and a third slave module. The write address of the write command records that the first and second slave modules need to execute the CSR register write command update within the current bus cycle, while the third slave module needs to maintain its original configuration. The synchronization selection signal generated by the synchronization selection module is recorded as syncsel[1:1:0]. During the execution of the logical AND operation, the write data is set to 1 by default. Therefore, for the first slave module, [write data] & syncsel[1] results in 1; for the second slave module, [write data] & syncsel[1] results in 1; and for the third slave module, [write data] & syncsel[0] results in 0. This realizes the function of determining whether the slave module needs to execute the CSR register write command update.
[0031] In this embodiment, the synchronization unit is based on AND gate logic circuits. Its output depends only on the current input, has no memory function, and the signal changes are propagated instantaneously. This satisfies the requirement of data updates within the same bus cycle. At the same time, the hardware overhead of AND gate logic circuits is minimal. Thus, a signal path with the shortest delay, the most direct and the most certain signal path from software configuration to hardware action is constructed.
[0032] Preferred options, see Figure 2 In one embodiment, the synchronization unit of the master module and the synchronization units of several slave modules are connected in a cascaded structure to establish a hardware synchronization link. The master module is connected to the first-order slave module, and the slave modules are connected sequentially according to their numbering order. Within the same bus cycle, write data and synchronization selection signals propagate step by step from the master module to any slave module.
[0033] Preferred options, see Figure 3 In another embodiment, a hardware synchronization link is established between the synchronization unit of the master module and the synchronization units of several slave modules using a broadcast structure. The master module is connected to all slave modules respectively. Within the same bus cycle, write data and synchronization selection signals are broadcast and propagated between the master module and any slave module.
[0034] Preferred options, see Figure 4 In another embodiment, the synchronization unit of the master module and the synchronization units of several slave modules simultaneously establish hardware synchronization links using a cascaded structure and a broadcast structure. The master module is connected to several primary slave modules respectively. Each primary slave module is connected to several secondary slave modules under its name in sequence based on the numbering order. Within the same bus cycle, write data and synchronization selection signals are broadcast from the master module to the primary slave modules, and then propagated from the primary slave modules to the secondary slave modules level by level.
[0035] In this embodiment, some functional modules among several subordinate modules are selected as primary subordinate modules, and the remaining functional modules are secondary subordinate modules. For example, if there are subordinate modules numbered 1-12, then functional modules numbered 1, 5, and 9 are designated as primary subordinate modules, and the remaining functional modules are all secondary subordinate modules. During the establishment of the hardware synchronization link, the master module establishes a broadcast structure connection with primary subordinate modules 1, 5, and 9 respectively. At the same time, primary subordinate module 1 establishes a cascade structure connection with its subordinate secondary subordinate modules 2-4 based on the numbering order, primary subordinate module 5 establishes a cascade structure connection with its subordinate secondary subordinate modules 6-8 based on the numbering order, and primary subordinate module 9 establishes a cascade structure connection with its subordinate secondary subordinate modules 10-12 based on the numbering order.
[0036] In summary, in this embodiment, the connection method between the main module and each subordinate module can be selected according to actual needs. For example, in application scenarios with a large number of functional modules and less stringent requirements for the "absolute simultaneity" of data transmission synchronization, but requiring "sequentiality," a cascaded hardware synchronization link can be selected. In application scenarios with a small number of functional modules and extremely stringent requirements for synchronization latency, a broadcast hardware synchronization link can be selected. In addition, a cascaded structure and a broadcast structure can be used to establish a hardware synchronization link, improving the flexibility and adaptability of establishing the hardware synchronization link.
[0037] Preferably, in one embodiment, the master CSR register and slave CSR register include, but are not limited to, PWM control register, ADC configuration register, DMA control register or communication interface register, but this embodiment is not limited thereto.
[0038] Preferably, in one embodiment, the method for synchronously updating write commands applied to the CSR register array further includes the following steps: S5: After the master CSR register and several selected slave CSR registers synchronously complete the write operation of the same data content, the system determines whether the write operation of the master CSR register and the slave CSR register is successful based on the status registers deployed in the master module and slave module respectively, generates a synchronization confirmation signal and feeds it back, and then monitors the success or failure status of the synchronous write operation of the CSR register for backend query or triggering interrupt handling. If the failure handling mechanism is triggered, the system needs to start the retry process.
[0039] Second Embodiment Based on the same concept, the present invention also provides a write command synchronization update system for a CSR register array, used to execute the write command synchronization update method for a CSR register array as described in any one of the first embodiments, including: The main module contains a main CSR register and a synchronization unit. The main module is used to receive write commands output from the control bus independently.
[0040] At least one set of slave modules, each of which has a slave CSR register and a synchronization unit.
[0041] The synchronization selection module is connected to the synchronization unit of the main module. The synchronization selection module is used to generate a synchronization selection signal according to the write command.
[0042] A hardware synchronization link is formed between the synchronization unit of the master module and the synchronization unit of any slave module. The synchronization units of the master module and the slave module are used to parse write data and synchronization selection signals.
[0043] The functional implementation of each component in the above-described write command synchronization update system for CSR register array corresponds to each step in the above-described write command synchronization update method embodiment for CSR register array. Their functions and implementation processes will not be described in detail here.
[0044] This embodiment also provides an electronic device, including a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor. The processor executes the machine-executable instructions to implement the above-described method for synchronously updating write commands applied to the CSR register array.
[0045] This embodiment also provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by the processor, the computer-executable instructions cause the processor to implement the above-described method for synchronously updating write commands applied to the CSR register array.
[0046] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.
Claims
1. A method for synchronously updating write commands applied to a CSR register array, characterized in that, Includes the following steps: S1: Send a write command to the main module based on the control bus. The write command contains the write address and write data. S2: Based on the write address, if the main module is the target of the write command recorded in the write address, then the main CSR register deployed in the main module reads the write data in the first bus cycle; Furthermore, the synchronization selection module simultaneously parses the write command and generates a synchronization selection signal based on the write address pointing to the target slave module. The synchronization selection signal is used to indicate the set of slave modules that need to be updated synchronously. S3: During the first bus cycle, the synchronization unit of the master module is configured to send the write data and the synchronization selection signal to all the slave modules. The slave CSR registers deployed in the slave modules select to read the write data based on the indication of the synchronization selection signal. S4: During the first bus cycle, the master CSR register and several selected slave CSR registers synchronously complete the write operation of the same data content.
2. The write command synchronization update method applied to a CSR register array as described in claim 1, characterized in that, The synchronization selection signal is configured with a number of programmable control bits equal to the number of slave modules, and the arrangement order of the control bits matches the numbering order of the slave modules. Control position 0 indicates that the slave module matched with the current control bit does not need to be updated synchronously in the current bus cycle, while control position 1 indicates that the slave module matched with the current control bit needs to be updated synchronously in the current bus cycle.
3. The write command synchronization update method applied to a CSR register array as described in claim 2, characterized in that, In S3, the slave CSR registers deployed in several slave modules select to read the write data based on the indication of the synchronization selection signal, including the following steps: S31: The synchronization units corresponding to the several slave modules respectively perform a logical AND operation on the control bits of the corresponding bits in the write data and the synchronization selection signal. When the result of the logical AND operation is 0, the slave CSR register corresponding to the slave module is enabled not to read the write data; when the result of the logical AND operation is 1, the slave CSR register corresponding to the slave module is enabled to read the write data.
4. The write command synchronization update method applied to a CSR register array as described in claim 1, characterized in that, The synchronization unit of the master module and the synchronization units of several slave modules are connected in a cascaded structure to establish a hardware synchronization link. The master module is connected to the slave module in the first order, and the slave modules are connected sequentially according to their numbering order. Within the same bus cycle, the write data and the synchronization selection signal are propagated step by step from the master module to any of the slave modules.
5. The write command synchronous update method applied to a CSR register array as described in claim 1, characterized in that, The synchronization unit of the master module and the synchronization units of the slave modules establish a hardware synchronization link using a broadcast structure. The master module is connected to all the slave modules respectively. Within the same bus cycle, the write data and the synchronization selection signal are broadcast and propagated between the master module and any of the slave modules.
6. The write command synchronization update method applied to a CSR register array as described in claim 1, characterized in that, The synchronization unit of the main module and the synchronization units of several subordinate modules simultaneously establish hardware synchronization links using a cascaded structure and a broadcast structure. The main module is connected to several primary subordinate modules respectively. Each primary subordinate module is connected to several secondary subordinate modules under its name in sequence based on the numbering order. Within the same bus cycle, the write data and the synchronization selection signal are broadcast by the main module to the primary subordinate module, and then propagated step by step by the primary subordinate module to the secondary subordinate modules.
7. The write command synchronization update method applied to a CSR register array as described in claim 1, characterized in that, The master CSR register and the slave CSR register include, but are not limited to, PWM control registers, ADC configuration registers, DMA control registers, or communication interface registers.
8. The write command synchronization update method applied to a CSR register array as described in claim 1, characterized in that, It also includes the following steps: S5: After the main CSR register and several selected subordinate CSR registers synchronously complete the write operation of the same data content, the write operation of the main CSR register and the subordinate CSR register is determined based on the status registers deployed in the main module and the subordinate module respectively, and a synchronization confirmation signal is generated and fed back.
9. A write command synchronization update system applied to a CSR register array, characterized in that, A method for synchronously updating write commands applied to a CSR register array as described in any one of claims 1-8, comprising: The main module includes a main CSR register and a synchronization unit. The main module is used to receive write commands output from the control bus independently. At least one set of slave modules, each of which is provided with a slave CSR register and a synchronization unit; A synchronization selection module is used to generate a synchronization selection signal according to the write command; The synchronization unit of the master module and the synchronization unit of any of the slave modules form a hardware synchronization link. The synchronization unit of the master module and the synchronization unit of the slave module are used to parse write data and synchronization selection signals.
10. The write command synchronization update system for a CSR register array as described in claim 9, characterized in that, Also includes: The master module and any of the slave modules are also provided with a status register. The status register is used to determine whether the write operation of the master CSR register and the slave CSR register is successful, generate a synchronization confirmation signal and send it back.