ECC (Error Correction Code) memory verification processing method and device for power distribution network monitoring chip

Abstract

The invention provides an ECC (Error Correction Code) memory verification processing method and device for a power distribution network monitoring chip, and the method comprises the steps: building a binding mapping relation between a task and a physical memory segment through traversing a task scheduling table, collecting the access frequency of each physical memory segment, and forming an access frequency set; based on the binding mapping relation and the access frequency set, in combination with historical single-bit error correction times and task level weights recorded by a storage controller, performing comprehensive risk scoring on each physical memory segment, and correspondingly distributing different ECC protection strategy levels; finding out an error physical memory segment for an uncorrectable error through an error address, and then determining all tasks using the memory segment according to the binding mapping relation to form an error task set; for each error task, calculating an error influence factor; and judging according to a quantile threshold value of the disposal score set, dividing the task into reservation reconstruction or pruning offline, and executing corresponding operation.

Description

Technical Field

[0001] This invention belongs to the field of data processing, and in particular relates to an ECC memory verification processing method and apparatus for power distribution network monitoring chips. Background Technology

[0002] With the advancement of new power system construction, distribution network terminals are continuously evolving towards high-concurrency data acquisition, diversified protocols, and forward-looking edge decision-making. Monitoring chips operate under complex conditions such as frequent electromagnetic interference, lightning surges, heavy load switching, and drastic temperature gradient changes for extended periods. Soft errors, especially bit flips in memory cells, have become the primary hidden danger affecting business continuity. Current practices typically configure error correction coding (ECC) modules on-chip or off-chip memory channels to achieve single-bit correction and multi-bit detection. However, these often employ static and uniform protection levels, ignoring the significant differences in access patterns of distribution business tasks and the ever-changing noise levels in the environment. This results in insufficient protection for memory segments where high-activity or critical tasks reside, while low-activity areas are over-protected, making it difficult to balance overall energy efficiency and reliability. When uncorrectable errors occur, traditional systems often respond with global resets or coarse-grained shutdowns, which both expand the impact of the fault and prolong recovery time. Furthermore, they fail to establish a calculable link between the error and the specific task, specific memory segment, and its current operating state, making it difficult to form a closed-loop "monitoring-assessment-location-handling" chain. Meanwhile, the common multi-core heterogeneous and lockstep structures, shared buffers and preemptive scheduling of power distribution monitoring chips make it common for multiple tasks to share the same physical memory segment. A single address-module affiliation is no longer sufficient to support fine-grained judgment. In addition, the non-stationarity of field interference causes fixed thresholds and experience-based classifications to frequently fail during periods of strong disturbance, resulting in misjudgment, over-processing or under-processing. Summary of the Invention

[0003] The purpose of this invention is to design an ECC memory verification processing method and device for distribution network monitoring chips. When an error is triggered, it can combine the policy level, historical risk and current scheduling activity to make a quantifiable impact judgment. It can also complete rapid handling and memory segment limit upgrades without sacrificing critical business by task-level reconstruction or pruning and taking offline, forming an end-to-end closed loop to improve long-term stability and field maintainability.

[0004] To achieve the above objectives, a first aspect of the present invention provides an ECC memory verification processing method for distribution network monitoring chips, the method comprising: During the system startup phase, the binding mapping relationship between tasks and physical memory segments is established by traversing the task scheduling table, and the access frequency of each physical memory segment is collected to form an access frequency set. Based on the binding mapping relationship and access frequency set, combined with the historical single-bit error correction count and task level weight recorded by the storage controller, a comprehensive risk score is performed on each physical memory segment. The comprehensive risk score includes access frequency, error correction history, and task level weight related items. According to the risk score set of all memory segments, a quantile method is used to adaptively set low and high thresholds, dividing the risk scores into three levels: low, medium, and high, and assigning different ECC protection strategy levels accordingly. When the ECC verification module detects an uncorrectable error, it locates the faulty physical memory segment through the error address, and then determines all tasks using that memory segment based on the binding mapping relationship, forming a set of faulty tasks. For each faulty task, it calculates an error impact factor, which includes the risk score of the faulty memory segment, the current ECC protection policy level, and the current scheduling activity of the task. Based on the set of error impact factors, a handling score is calculated for each error task. The handling score is obtained through robust normalization of the set of error impact factors. Based on the quantile threshold of the handling score set, the task is divided into retention and reconstruction or pruning and offline, and the corresponding operation is performed. At the same time, write restrictions and protection strategies are upgraded for the faulty memory segment.

[0005] Furthermore, the steps for establishing the binding mapping relationship include: extracting the memory usage range of all tasks by traversing the task scheduling table, dividing the physical memory into non-overlapping address segments, and establishing a mapping relationship between tasks and physical memory segments.

[0006] Furthermore, the access frequency acquisition step includes: using the access statistics register or performance monitoring unit integrated in the chip to count the read and write operations of each physical memory segment, and setting a fixed statistical period to calculate the access frequency.

[0007] Furthermore, the calculation steps of the comprehensive risk score include: calculating the risk score through the access frequency weighting factor, the error correction history factor, and the task fault tolerance weighting constraint, wherein the task fault tolerance weighting constraint is calculated by summing the reciprocal of the task level weights of all tasks bound to the memory segment.

[0008] Furthermore, the step of allocating ECC protection strategy levels includes: configuring an enhanced error correction mechanism for high-risk scoring segments, wherein the enhanced error correction mechanism is single error correction, double error detection, and periodic refresh; configuring a standard single error correction and double error detection mechanism for medium-risk scoring segments; and configuring a basic error correction mechanism for low-risk scoring segments, wherein the basic error correction mechanism is parity check or mirror comparison.

[0009] Furthermore, the step of calculating the error impact factor includes: weighted summation of the risk score of the faulty memory segment, the numerical mapping of the current ECC protection policy level, and the current scheduling activity of the task.

[0010] Furthermore, the calculation steps for the disposal score include: robust normalization using the median and interquartile range of the error impact factor set.

[0011] Furthermore, the steps for preserving and rebuilding include: reading the task execution context from the lockstep execution kernel or loading the task redundancy image from the read-only region, reinitializing the task context, and adding it to the scheduling queue.

[0012] Furthermore, the pruning and offline operation steps include: removing the task from the scheduling system and releasing the memory resources it occupies, while preserving the task's read-only constant area.

[0013] A second aspect of the invention provides an ECC memory verification processing apparatus for distribution network monitoring chips, the apparatus comprising: The initial module is used during the system startup phase to establish a binding mapping relationship between tasks and physical memory segments by traversing the task scheduling table, and to collect the access frequency of each physical memory segment to form an access frequency set. The risk assessment module is used to perform a comprehensive risk score on each physical memory segment based on the binding mapping relationship and access frequency set, combined with the historical single-bit error correction count and task level weight recorded by the storage controller. The comprehensive risk score includes access frequency, error correction history, and task level weight related items. According to the risk score set of all memory segments, a quantile method is used to adaptively set low and high thresholds, divide the risk scores into three levels: low, medium, and high, and assign different ECC protection strategy levels accordingly. The error handling module is used to locate the faulty physical memory segment by the error address when the ECC verification module detects an uncorrectable error, and then determine all tasks using the memory segment according to the binding mapping relationship to form a set of faulty tasks; for each faulty task, the error impact factor is calculated, which includes the risk score of the faulty memory segment, the current ECC protection policy level and the current scheduling activity of the task. The processing execution module is used to calculate the handling score of each error task based on the error impact factor set, the handling score being obtained through robust normalization of the error impact factor set; and to determine whether the task is to be retained for reconstruction or pruned and taken offline based on the quantile threshold of the handling score set, and to perform the corresponding operations, while simultaneously imposing write restrictions and upgrading the protection strategy for the faulty memory segment.

[0014] The beneficial technical effects of the present invention are at least as follows: To address the aforementioned problems, this invention provides an ECC memory verification processing method and apparatus for distribution network monitoring chips. It constructs a joint risk assessment based on operational access frequency and error correction history, and introduces an inverted weighting term tied to task importance. This allows memory segments associated with high-level tasks to obtain higher risk scores under the same access and historical conditions, achieving on-demand allocation and hierarchical configuration of protection resources from the source. The hierarchical strategy does not use fixed thresholds but adaptively determines low, medium, and high protection levels based on the quantile of the score distribution, automatically converging to a suitable boundary with field disturbances. During the error triggering phase, it does not... This solution not only performs precise reverse lookup from the erroneous address to the task, but also proposes error impact factors based on fusion segment risk, current protection level, and current scheduling activity to measure the immediate impact of errors on critical business operations. In terms of decision-making, it uses a robust normalized score of the error impact factor and a quantile threshold to generate a binary decision of retaining / reconstructing or pruning / taking offline, avoiding mismatch of fixed thresholds under strong disturbances. It also collaborates with lockstep context or read-only mirroring to rapidly reconstruct critical tasks, while imposing write restrictions on the erroneous memory segment and increasing its protection level, achieving closed-loop control of "location—decision—execution—policy upgrade." This solution organically integrates task-oriented behavior awareness, adaptive hierarchical protection, error context impact quantification, and task-level handling mechanisms within the chip runtime, overcoming the limitations of traditional static ECC and coarse-grained fault handling. It can maintain critical business continuity and data reliability with lower energy consumption and shorter recovery paths in power distribution scenarios with strong interference, high real-time requirements, and multiple concurrent tasks, thus achieving closed-loop control of "location—decision—execution—policy upgrade." Attached Figure Description

[0015] The present invention will be further described with reference to the accompanying drawings, but the embodiments in the drawings do not constitute any limitation on the present invention. For those skilled in the art, other drawings can be obtained based on the following drawings without creative effort.

[0016] Figure 1 This is a flowchart of the ECC memory verification processing method for power distribution network monitoring chips according to the present invention.

[0017] Figure 2 This is a framework diagram of the ECC memory verification processing device for power distribution network monitoring chips according to the present invention. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] In one or more embodiments, such as Figure 1As shown, an ECC memory verification processing method for power distribution network monitoring chips is disclosed, the method comprising the following: S1: During the system startup phase, the binding mapping relationship between tasks and physical memory segments is established by traversing the task scheduling table, and the access frequency of each physical memory segment is collected to form an access frequency set. Specifically, the goal of this step is to establish the binding relationship between tasks and memory segments during the system startup phase and to configure a runtime behavior monitoring mechanism. Considering that multiple business tasks in the power distribution network monitoring chip need to run concurrently in a bare-metal or real-time operating system environment, and that each task has strong differences in memory access, and that the memory error rate is highly correlated with access activity, the following two key operations need to be completed during the system initialization phase: (1) establish a clear mapping structure between tasks and the memory segments they use; (2) configure an access behavior monitoring module to continuously collect the access frequency of each segment during chip operation, providing data support for subsequent error risk modeling and error correction strategy selection.

[0020] During chip power-on initialization, the system sequentially loads various service tasks, including typical tasks such as remote signaling and telemetry acquisition, protection setting judgment, communication protocol processing, and human-machine interaction. The task scheduling system allocates the required stack space, data buffer, and parameter constant segment for each task. All memory address spaces are divided into non-overlapping physical memory segments during allocation by the memory management unit or on-chip address controller; these memory segments are numbered as follows: Each task's description structure contains pointers to its stack start address, data segment start address, and other information. The system extracts the memory usage range of all tasks by traversing the scheduling table and establishes a task-memory segment mapping relationship. Its definition is as follows: ; in, Indicates the first One task, Indicates the first One physical memory segment, This represents the binding mapping between tasks and physical memory segments. This mapping is stored in the scheduling system table as an array of structures, used in subsequent steps to trace task ownership back from memory errors.

[0021] After completing the mapping structure, the system configures access behavior monitoring for each memory segment. The access statistics register or performance monitoring unit integrated into the chip can count read and write operations within a specific address range. For example, under the AXI bus protocol, the address decoder categorizes access requests into different address segments, which are then counted separately by an on-chip counter. The segment memory access count counter is denoted as The system is set to a fixed statistical period. Calculate access frequency per cycle : ; in, Indicates the first The access frequency of each physical memory segment within the current statistical period, dimensionless. Indicates period The number of accesses read from the internal database. The acquisition method depends on whether the chip has an access monitoring hardware module. If a performance monitoring register exists, the system can read it directly; if there is no hardware support, instrumentation statistics can be performed at the task scheduling point. The system will collect all... Combined to form a set of access frequencies: ; gather This indicates the access activity status of all memory segments within the current period and serves as the foundational variable for memory segment risk assessment and verification level allocation in subsequent steps.

[0022] To illustrate the meaning of the variables, consider the following example: Assume a communication task. The memory segment occupied is and Because this task requires continuous parsing of IEC 61850 protocol frames, its access frequency is generally high. The statistical period was set to 1 second, and monitoring revealed... , Then there is , This type of data will be used in subsequent policy allocation to ensure that high-frequency access segments receive a higher level of fault tolerance protection.

[0023] S2: Based on the binding mapping relationship and access frequency set, combined with the historical single-bit error correction count and task level weight recorded by the storage controller, a comprehensive risk score is performed on each physical memory segment. The comprehensive risk score includes access frequency, error correction history, and task level weight related items. According to the risk score set of all memory segments, a quantile method is used to adaptively set low and high thresholds, dividing the risk scores into three levels: low, medium, and high, and assigning different ECC protection strategy levels accordingly. Specifically, this step is based on the task-memory segment mapping relationship established in the previous step. and access frequency set Combined with the error counting mechanism embedded in the storage controller, for each physical memory segment Risk scoring is performed, and differentiated ECC error correction strategies are configured accordingly. For the distribution network monitoring chip scenario in this solution, the following factors need special consideration: distribution tasks are characterized by periodicity and long-term memory residency; although some memory segments are accessed infrequently, the cumulative risk of bit errors is high; if the measurement data involved in the task is corrupted, it will lead to relay protection errors. Therefore, access frequency cannot be used as the sole criterion for determining the protection level; instead, a weighted adjustment based on the task's security level is necessary.

[0024] The input is a set of variables and ,in Represents each task in the system The set of physical memory segments used This indicates that each physical memory segment is within the statistical period. Access frequency within, The acquisition of this information has been accomplished via the access count register, so there is no need to repeat the design. New variables include: the historical single-bit error correction count recorded by the storage controller. , indicating a segment Number of errors corrected since startup; task level weight Defined by the system during the task registration phase, it reflects the strength of the task's fault tolerance requirements within the system; for example, telemetry tasks are classified as low-level. Protection tasks are of high level ( ).

[0025] Based on the traditional scoring model, a task level correlation term is introduced as a regularization constraint, and the memory risk scoring formula is designed as follows: ; in, Represents memory segment The first item of the comprehensive risk score. The second item is a weighting factor based on access frequency, reflecting the activity level of the segment. To correct historical factors and reflect the risk of historical reversal, the third item is a task fault tolerance weighting constraint, used to strengthen the protection priority of high-level task-bound segments. This constraint, by taking the reciprocal of the task level, ensures that memory segments bound to critical tasks receive higher risk scores, thus reflecting the guiding control role of task security levels on memory segment protection configuration during the scoring process. This penalty item design based on task association levels is not reported in existing error correction level configuration methods based on access behavior, and is particularly suitable for scenarios in power chips where multiple task levels coexist and task importance is extremely uneven.

[0026] In actual execution, all tasks are completed in each cycle. After calculation, the system uniformly constructs a risk score set. According to the rating set The distribution is adaptively set with two thresholds. and They are divided into three levels: low, medium, and high. The default method uses quantiles for determination. , Recommended quantile level is and Adjustment within the interval. When the overall on-site disturbance increases, When shifting the overall threshold to the right, increase the quantile level of both thresholds; when the system enters a low-load or interference-reduced phase, decrease the quantile level accordingly. ; Output variables This indicates the ECC protection policy level used for each memory segment. Level III indicates the use of SEC-DED with periodic refresh; Level II indicates the use of standard SEC-DED; and Level I is a lightweight error correction policy, such as parity checking or mirroring. This output mapping will be used as a dynamic parameter for the controller and written to the register or control table in the next cycle to complete the reconstruction of the physical memory segment error correction policy.

[0027] For example: If a certain segment The access frequency is Total number of errors This section is associated with two tasks, namely... and Corresponding task level weight , Set coefficients , , The score for this segment is calculated as follows: ; If set , If the access frequency of a segment is not extreme, it is classified as high-risk and configured with a Level III strategy. By introducing task-level weighting, even if the access frequency of a segment is not extreme, it can still receive enhanced protection due to its association with high-level tasks, demonstrating the solution's precise adaptability to task scenarios.

[0028] S3: When the ECC verification module detects an uncorrectable error, it locates the faulty physical memory segment through the error address, and then determines all tasks using the memory segment based on the binding mapping relationship, forming a set of faulty tasks; for each faulty task, it calculates the error impact factor, which includes the risk score of the faulty memory segment, the current ECC protection policy level, and the current scheduling activity of the task; Specifically, this step addresses situations where the ECC verification module triggers uncorrectable errors during system operation, taking into account the memory segment risk score set calculated in the previous stage. Mapping table with verification strategy This step enables the comprehensive classification of the task attribution for erroneous addresses and their system impact. Positioned as the connecting hub between error perception and task-level response, it is a crucial link in closing the causal chain between "memory error – task behavior – system fault tolerance" in the power distribution network monitoring chip scenario. In particular, tasks in power distribution chips exhibit significant differences in reliability sensitivity; for example, even a brief interruption of the current jump detection task can cause malfunctions. Therefore, it is necessary to classify errors in a quantifiable and comparable manner, rather than simply terminating upon an error.

[0029] The input includes the risk score set output from the previous step. Mapping table with verification strategy Each memory segment in the previous step The corresponding score and error correction strategy level have been obtained. ; and the task-memory segment mapping relationship output in the first step. This is used to perform the mapping operation from the error address to the task. Furthermore, during chip operation, if the ECC controller detects an uncorrectable memory error, it will submit an error event via the interrupt controller. This event contains the physical address of the erroneous data, denoted as... .

[0030] First, the system needs to address the error. This is mapped to a specific physical memory segment. Since all memory has been segmented during system initialization, the system can find a unique memory segment that meets the address range criteria. ,Right now: ; in, and Represent memory segments respectively The start and end addresses are set and stored in a lookup table during memory management unit initialization. This lookup table is a static array of structures that does not rely on external tools and completes matching directly through linear scanning or hash indexing.

[0031] When the error segment Once confirmed, the system uses the task mapping relationship. For all tasks Determine whether it contains that segment, i.e., whether it satisfies the condition. If the conditions are met, then mark the task. For the affected tasks. If this segment is shared by multiple tasks, then all tasks that meet the criteria together form the set of erroneous tasks. This multi-task matching mechanism is very common in power embedded chips, such as event buffers and message buffers, which are shared by multiple threads. Therefore, the system needs to support a parallel matching structure rather than a one-to-one mapping.

[0032] To achieve differentiated task-level processing, this step introduces an "error impact factor" calculation mechanism based on the previous scoring model. Its core idea is to use multi-dimensional fusion modeling to ensure that error impact assessment relies not only on the scoring of the erroneous segment. With strategy level Furthermore, it considers the task's operating mode and current access density to establish an evaluation metric that reflects "the actual impact of the error on critical business within the current scheduling window."

[0033] Defining the impact factor incorrectly (Corresponding task) )as follows: ; in, Indicates an error in the task. Influence factors; For memory segment The risk score has been calculated in step two; The current ECC policy level for this segment is determined by a mapping function. They are uniformly converted into numerical forms, such as levels III, II, and I being mapped to 3, 2, and 1 respectively; Indicates tasks within the current scheduling period The activity level is the frequency at which tasks are scheduled for execution or the expected number of wake-ups in the current scheduling cycle, which can be obtained through the scheduler periodic table or time slice allocation structure.

[0034] In the above formula, , , These are weighting parameters used to balance the relative impacts of historical risk, current protection strength, and task scheduling activity. The default value is... , , It is recommended to adjust within a limited range, among which , , When "frequent errors occur in high-strategy-level segments" in recent cycles, increase... When scheduling activity increases significantly and the false alarm rate rises, appropriately increase... Or converge to In all other cases, the default value remains. (Third item) This is a regular expression used in this step to reflect the dynamic factor of whether the current fault segment is frequently used by active tasks, in order to avoid over-responding to inactive tasks.

[0035] In engineering implementation, the scheduler maintains a time slice allocation table for each task and a wake-up counter for the current cycle, which can be obtained through periodic sampling. Value. For example: if a certain task If a task is woken up 4 times within the current scheduling cycle, and the total number of tasks is 20, then we can approximate it as follows: .

[0036] Influence factors of all affected tasks After the calculation is completed, the system will set up the erroneous task set. Together with their corresponding impact factors, they constitute the structured output: Error Task Collection : Contains the task numbers of all tasks mapped to the error segment; Error Influence Factor Set : Quantify the impact of the error on each task.

[0037] This mechanism achieves a complete closed-loop path from error address to memory segment to task mapping to impact factor assessment, providing quantifiable and orderable criteria for determining whether to perform task pruning, interrupt rescheduling, or redundancy recovery. Especially in scenarios involving multi-core parallel processing in power distribution chips, with fine-grained scheduling and significant differences in service levels, this mechanism offers a refined error classification path that considers both static structure and dynamic behavior, effectively enhancing the selectivity of subsequent fault-tolerant paths and the reliability of system response.

[0038] S4: Based on the set of error impact factors, calculate the handling score for each error task. The handling score is obtained through robust normalization of the set of error impact factors. Based on the quantile threshold of the handling score set, determine whether the task is to be retained for reconstruction or pruned and taken offline, and perform the corresponding operations. At the same time, write restrictions and protection strategies are upgraded for the faulty memory segment.

[0039] Specifically, this step involves the set of error tasks obtained in the previous stage. With the set of error impact factors Based on this, task-level handling is implemented for distribution network monitoring chips: for each erroneous task, a decision is made to either prune and restore or force it offline, and specific recovery, migration, and isolation operations are executed according to the decision. This step does not introduce any new external inputs; all decision variables are explicitly derived from the output of the previous stage. and The threshold for judgment is determined by... The adaptively calculated statistics avoid reliance on additional data sources, ensuring a closed-loop process that can be implemented in real time.

[0040] This step first involves the set Perform robust statistics, calculate the median and quantile differences, to construct a system that depends only on... The adaptive decision quantity; then for each Generate disposal scores and compare them with those from The derived threshold comparison yields a binary decision of "preserve and rebuild" or "prune and take offline"; finally, the task is restored or taken offline according to the decision, and memory segment isolation and scheduling queue update are completed.

[0041] To improve the stability of judgment in scenarios with strong interference, a set-based approach is adopted. Robust normalized score definition and handling score And the threshold is determined by the set quantile. : ; In the above formula, For set The median, obtained from this step... Read directly after sorting; For set The interquartile difference is equal to the difference between the upper and lower quartiles, and is also determined by... Calculated; To avoid extremely small positive numbers with a denominator of zero, the minimum value is taken by default. It is recommended to select within the minimum range and adjust accordingly. Enabled in very minor, extreme cases. Based on normalized values. Construct a threshold using set quantiles: ; In the formula, This represents the quantile operation, which takes the quantile value of the input set. The quantile level is set to a slightly higher-than-average level by default (e.g., within the middle range), to prioritize tasks with significantly higher disposal scores than the overall level when multiple errors occur simultaneously. Through the above two equations, the disposal decision depends only on the output set of the previous stage. No additional quantity needs to be introduced, and it is robust in volatile environments; if The distribution is relatively concentrated. Very small, then Ensuring the denominator is not zero is equivalent to having a pair. and Thresholding is applied to the difference.

[0042] Based on the judgment value, perform the following operation procedure. When , will the task The task is determined to be "preserve and rebuild". During execution, the most recent valid execution context (including program counter, general-purpose register set, and stack pointer) of the task is read from the lockstep execution kernel. A new task control block is created in the scheduling system and written into the aforementioned context. If the lockstep context is unavailable, a redundant image of the task is loaded from the read-only region, and the stack and data segments are initialized. The task is then added to the ready queue in a "recovery marked" state, awaiting the scheduler's selection for execution. After completing the recovery process, the memory segment containing the error address is marked as "write restricted". The verification policy mapping table generated in the previous stage is called to upgrade the verification policy level for this segment, or the controller is triggered to perform a fast refresh of this segment. In this case, the task The task was determined to be "pruned and taken offline." During execution, the task was removed from the scheduling system, and its stack and data segment usage were released, while its read-only constant area was preserved for subsequent remote updates. Simultaneously, the task number and the faulty memory segment number were recorded in the error log for maintenance purposes. Stricter access restrictions were set for the associated memory segment until subsequent version replacements or offline troubleshooting were completed. To avoid cascading effects on shared segments, when... Contains multiple tasks and When there is a clear hierarchy, only tasks in the lower hierarchy are taken offline, while tasks in the higher hierarchy are rebuilt to maintain the continuity of critical business operations.

[0043] This step outputs two result variables, which are used in the controller and scheduler: the set of pruning tasks. This represents the set of task IDs that were forcibly taken offline; the set of tasks that were restored. , representing the set of task numbers that have been rebuilt and rescheduled. The above two sets are directly constructed by this step based on the handling score and threshold. At the same time as generating the sets, the corresponding recovery or offline operation is completed, and access restrictions and policy upgrades are applied to the relevant memory segments. This allows this step to both provide a decision result and complete the actual handling action, which can be directly used for system operation and status auditing in the next cycle.

[0044] In one or more embodiments, such as Figure 2 As shown, an ECC memory verification processing device for distribution network monitoring chips is disclosed, the device comprising: The initial module is used during the system startup phase to establish a binding mapping relationship between tasks and physical memory segments by traversing the task scheduling table, and to collect the access frequency of each physical memory segment to form an access frequency set. The risk assessment module is used to perform a comprehensive risk score on each physical memory segment based on the binding mapping relationship and access frequency set, combined with the historical single-bit error correction count and task level weight recorded by the storage controller. The comprehensive risk score includes access frequency, error correction history, and task level weight related items. According to the risk score set of all memory segments, a quantile method is used to adaptively set low and high thresholds, divide the risk scores into three levels: low, medium, and high, and assign different ECC protection strategy levels accordingly. The error handling module is used to locate the faulty physical memory segment by the error address when the ECC verification module detects an uncorrectable error, and then determine all tasks using the memory segment according to the binding mapping relationship to form a set of faulty tasks; for each faulty task, the error impact factor is calculated, which includes the risk score of the faulty memory segment, the current ECC protection policy level and the current scheduling activity of the task. The processing execution module is used to calculate the handling score of each error task based on the error impact factor set, the handling score being obtained through robust normalization of the error impact factor set; and to determine whether the task is to be retained for reconstruction or pruned and taken offline based on the quantile threshold of the handling score set, and to perform the corresponding operations, while simultaneously imposing write restrictions and upgrading the protection strategy for the faulty memory segment.

[0045] It is worth noting that the specific workflow of the ECC memory verification processing device for distribution network monitoring chips provided in this embodiment of the invention is the same as that of the ECC memory verification processing method for distribution network monitoring chips described in the above embodiments, and will not be repeated here.

[0046] This invention also provides an ECC memory verification processing device for distribution network monitoring chips, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the steps described in the above embodiments of the ECC memory verification processing method for distribution network monitoring chips, for example... Figure 1 The steps S1 to S4 described above; or, when the processor executes the computer program, it implements the functions of each module in the above-described device embodiments.

[0047] For example, the computer program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the ECC memory verification processing device for power distribution network monitoring chips.

[0048] The ECC memory verification processing device for the distribution network monitoring chip can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the ECC memory verification processing device for the distribution network monitoring chip may also include input / output devices, network access devices, buses, etc.

[0049] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASACs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. This processor is the control center of the ECC memory verification processing device for the power distribution network monitoring chip, connecting all parts of the device via various interfaces and lines.

[0050] The memory can be used to store the computer program and / or modules. The processor implements various functions of the ECC memory verification processing device for the power distribution network monitoring chip by running or executing the computer program and / or modules stored in the memory and calling the data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating device, the application program required for at least one function, etc.; the data storage area may store data created according to the operation of the air conditioner controller, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0051] The ECC memory verification processing device integrated with the power distribution network monitoring chip, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0052] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0053] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An ECC memory verification processing method for distribution network monitoring chips, characterized in that, The method includes: During the system startup phase, the binding mapping relationship between tasks and physical memory segments is established by traversing the task scheduling table, and the access frequency of each physical memory segment is collected to form an access frequency set. Based on the binding mapping relationship and access frequency set, combined with the historical single-bit error correction count and task level weight recorded by the storage controller, a comprehensive risk score is performed on each physical memory segment. The comprehensive risk score includes access frequency, error correction history, and task level weight related items. According to the risk score set of all memory segments, a quantile method is used to adaptively set low and high thresholds, dividing the risk scores into three levels: low, medium, and high, and assigning different ECC protection strategy levels accordingly. When the ECC verification module detects an uncorrectable error, it locates the faulty physical memory segment through the error address, and then determines all tasks using that memory segment based on the binding mapping relationship, forming a set of faulty tasks. For each faulty task, it calculates an error impact factor, which includes the risk score of the faulty memory segment, the current ECC protection policy level, and the current scheduling activity of the task. Based on the set of error impact factors, a handling score is calculated for each error task. The handling score is obtained through robust normalization of the set of error impact factors. Based on the quantile threshold of the handling score set, the task is divided into retention and reconstruction or pruning and offline, and the corresponding operation is performed. At the same time, write restrictions and protection strategies are upgraded for the faulty memory segment.

2. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The steps for establishing the binding mapping relationship include: extracting the memory usage range of all tasks by traversing the task scheduling table, dividing the physical memory into non-overlapping address segments, and establishing a mapping relationship between tasks and physical memory segments.

3. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The steps for collecting the access frequency include: using the access statistics register or performance monitoring unit integrated in the chip to count the read and write operations of each physical memory segment, and calculating the access frequency by setting a fixed statistical period.

4. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The calculation steps of the comprehensive risk score include: calculating the risk score through access frequency weighting factor, error correction history factor and task fault tolerance inversion weight constraint term, wherein the task fault tolerance inversion weight constraint term is calculated by summing the reciprocal of the task level weight of all tasks bound to the memory segment.

5. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The steps for allocating ECC protection strategy levels include: configuring an enhanced error correction mechanism for high-risk scoring segments, wherein the enhanced error correction mechanism is single error correction, double error detection, and periodic refresh; configuring a standard single error correction and double error detection mechanism for medium-risk scoring segments; and configuring a basic error correction mechanism for low-risk scoring segments, wherein the basic error correction mechanism is parity check or mirror comparison.

6. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The steps for calculating the error impact factor include: weighted summation of the risk score of the faulty memory segment, the numerical mapping of the current ECC protection policy level, and the current scheduling activity of the task.

7. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The calculation steps for the disposal score include: robust normalization using the median and interquartile range of the error impact factor set.

8. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The steps for preserving and rebuilding include: reading the task execution context from the lockstep execution kernel or loading the task redundancy image from the read-only region, reinitializing the task context, and adding it to the scheduling queue.

9. The ECC memory verification processing method for distribution network monitoring chips according to claim 1, characterized in that, The pruning and offline operation steps include: removing the task from the scheduling system and releasing the memory resources it occupies, while preserving the read-only constant area of ​​the task.

10. An ECC memory verification processing device for distribution network monitoring chips, characterized in that, The device includes: The initial module is used during the system startup phase to establish a binding mapping relationship between tasks and physical memory segments by traversing the task scheduling table, and to collect the access frequency of each physical memory segment to form an access frequency set. The risk assessment module is used to perform a comprehensive risk score on each physical memory segment based on the binding mapping relationship and access frequency set, combined with the historical single-bit error correction count and task level weight recorded by the storage controller. The comprehensive risk score includes access frequency, error correction history, and task level weight related items. According to the risk score set of all memory segments, a quantile method is used to adaptively set low and high thresholds, divide the risk scores into three levels: low, medium, and high, and assign different ECC protection strategy levels accordingly. The error handling module is used to locate the faulty physical memory segment by the error address when the ECC verification module detects an uncorrectable error, and then determine all tasks using the memory segment according to the binding mapping relationship to form a set of faulty tasks; for each faulty task, the error impact factor is calculated, which includes the risk score of the faulty memory segment, the current ECC protection policy level and the current scheduling activity of the task. The processing execution module is used to calculate the handling score of each error task based on the error impact factor set, the handling score being obtained through robust normalization of the error impact factor set; and to determine whether the task is to be retained for reconstruction or pruned and taken offline based on the quantile threshold of the handling score set, and to perform the corresponding operations, while simultaneously imposing write restrictions and upgrading the protection strategy for the faulty memory segment.

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