System based on network-on-chip transmission, transmission method and electronic equipment
By splitting large packet write data and requests into multiple target data and requests using the splitting module of the on-chip network, the problem of low bandwidth utilization is solved, achieving more efficient data transmission and a smaller network area.
Patent Information
- Application Number
- CN202511850819.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-03
AI Technical Summary
In data transmission systems based on on-chip networks, existing technologies suffer from low bandwidth utilization when transmitting large packets of data, leading to increased on-chip network area overhead and high transmission capacity requirements.
By splitting large packet write data into multiple target write data and large packet write requests into target write requests through the splitting module, the number of transmissions and requests is reduced. These operations are performed using the second end of the on-chip network, thereby improving bandwidth utilization and reducing power consumption.
This improves the bandwidth utilization of the on-chip network, reduces transmission power consumption, and reduces the area overhead of the on-chip network.
Smart Images
Figure CN121597631A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of on-chip network technology, and more specifically, to a system based on on-chip network transmission, a method for transmitting large packet write data, and an electronic device. Background Technology
[0002] Currently, in systems that use Network on Chip (NOC) for data transmission, the data source module typically performs data write operations to the storage device via NOC.
[0003] According to the on-chip network transmission protocol, each transmission of on-chip network is based on the size of the largest cache line in the system. However, with the continuous development of computer systems, a large number of different modules and processors have been introduced to form heterogeneous systems. Furthermore, with the increase in data bandwidth requirements, there is an increasing need for the transmission of large packets of write data and corresponding large packet write requests within the system.
[0004] When transmitting large packet write data and large packet write requests, the existing method first splits the large packet write data into multiple smaller write data according to the maximum cache line size, and splits the large packet write request into write requests corresponding to each small write data, and then transmits these multiple write requests and small write data through the on-chip network.
[0005] In this approach, the on-chip network needs to transmit multiple cache line-sized write data and multiple write requests. However, only the bandwidth used for writing data transmission is effective; the bandwidth occupied by write requests is additional bandwidth usage, resulting in low bandwidth utilization of the on-chip network. Furthermore, the larger the amount of information to be transmitted, the higher the requirements for the on-chip network's transmission capacity. This leads to a larger area overhead required when designing the on-chip network, thus hindering the reduction of on-chip network area overhead using existing transmission methods. Summary of the Invention
[0006] The purpose of this application is to provide a system, a method for transmitting large-packet write data, and an electronic device based on on-chip network transmission, so as to improve the bandwidth utilization of on-chip network in large-packet write data scenarios.
[0007] This application provides a system based on on-chip network transmission, including: a data source module, an on-chip network, and a splitting module; the data source module is used to output large packet write data and large packet write requests for the large packet write data to the splitting module through the on-chip network; the splitting module is used to: split the received large packet write data into multiple target write data according to a preset size, and split the received large packet write requests into target write requests corresponding to each of the target write data, and send each of the target write data and the target write requests to a storage device; the preset size is equal to the size of the maximum cache line in the system; and is used to: when each of the target write data is written to the storage device, feed back a large packet write response to the data source module through the on-chip network.
[0008] In the above implementation scheme, when transmitting large packet write data, the operations of splitting the large packet write data into multiple smaller target write data according to the maximum cache line size, and splitting the large packet write request into target write requests corresponding to each target write data, are performed by the splitting module connected to the second end of the on-chip network. This allows the on-chip network to transmit only the large packet write data and one large packet write request, which reduces the number of write requests to be transmitted in terms of total transmission volume and the number of transmissions, thereby improving the bandwidth utilization of the on-chip network and reducing power consumption. At the same time, since the amount of information to be transmitted is smaller than that of the traditional method, the requirements for the transmission capacity of the on-chip network are also smaller. When designing the on-chip network, the area overhead required by the on-chip network can also be smaller, which helps to reduce the area overhead of the on-chip network.
[0009] For example, assuming the maximum cache line size is 64 bytes, and the current large packet write data being transmitted is 256 bytes, then according to the traditional approach, the on-chip network (NIC) would need to transmit four 64-byte write data packets and four write requests, requiring a total of eight transmissions. However, using the approach proposed in this application, assuming the NIC's transmission bit width is 256 bytes, the NIC only needs to transmit one write request while transmitting the 256-byte large packet write data. This increases bandwidth utilization from 1 / 2 to 4 / 5, effectively improving the NIC's bandwidth utilization. Simultaneously, the number of transmissions is reduced from eight to two, thus lowering the NIC's transmission power consumption. Furthermore, due to the increased bandwidth utilization and decreased transmission power consumption, the NIC can be designed to be smaller.
[0010] Optionally, the system further includes a proxy module for the data source module; the information output end of the data source module is connected to the first end of the on-chip network through the proxy module; the proxy module is used to split the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network when the size of the large packet write data is greater than the transmission bit width of the on-chip network; the splitting module is specifically used to: split the intermediate write data into multiple target write data according to the preset size when the size of the intermediate write data is greater than the preset size; and use the intermediate write data as the target write data when the size of the intermediate write data is equal to the preset size.
[0011] In the above implementation, when the size of the large packet write data exceeds the transmission bit width of the on-chip network, the proxy module of the data source module splits the large packet write data into multiple intermediate write data for transmission according to the transmission bit width of the on-chip network. This allows the transmission of the large packet write data to meet the transmission bit width requirements of the on-chip network, thereby reducing the risk of packet loss during transmission and improving the reliability of write data transmission.
[0012] Optionally, the proxy module includes: a first control circuit, a first request queue, a first data cache, and a response queue; the first control circuit is configured to receive the large packet write data and the large packet write request, and place the large packet write request into the first request queue; the first control circuit is further configured to: store the large packet write data into the first data cache when the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network; and, when the size of the large packet write data is greater than the transmission bit width of the on-chip network, split the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network, and store each intermediate write data into the first data cache; the first control circuit is further configured to receive the large packet write response and place the large packet write response into the response queue; the first control circuit is further configured to: control the first request queue to sequentially transmit the stored large packet write requests to the on-chip network, and control the first data cache to sequentially transmit the stored large packet write data or the intermediate write data to the on-chip network; and control the response queue to sequentially transmit the stored large packet write responses to the data source module.
[0013] In the above implementation, the first control circuit determines the size of the received large packet write data and splits it, thereby placing the write data and large packet write request into the first data buffer and the first request queue respectively, and sending them in order. Similarly, the first control circuit places the received large packet write response into the response queue and sends it in order. This achieves ordered storage and transmission of write data, write requests, and write responses at the circuit level. Furthermore, the existence of the first request queue, the first data buffer, and the response queue reduces the risk of write data and write request loss due to transmission circuit congestion, as well as the risk of large packet write response loss when the data source module is busy.
[0014] Optionally, the first request queue and the response queue reuse the same queue entity.
[0015] In the above implementation, since the large packet write response is received only after the large packet write request is sent, the large packet write request and the large packet write response will not be stored in the queue entity at the same time. Therefore, by reusing the same queue entity to implement the first request queue and the response queue, the system implementation cost can be reduced while ensuring that the information in the queues is not confused.
[0016] Optionally, the splitting module includes: a second control circuit, a second request queue, and a second data cache; the second control circuit is used to receive the large packet write data and the large packet write request, and split the large packet write data into multiple target write data according to a preset size, and split the large packet write request into target write requests corresponding to each of the target write data, and store each of the target write data into the second data cache, and put each of the target write requests into the second request queue; the second control circuit is further used to: control the second request queue to sequentially transmit the stored target write requests to the storage device, and control the second data cache to sequentially transmit the stored target write data to the storage device.
[0017] In the above implementation, the received large packet write data is split into target write data according to a preset size by the second control circuit, and the large packet write request is split into multiple target write requests. The target write data and target write requests are then placed into the second data buffer and the second request queue, respectively, and sent out in sequence. This allows for the splitting of write data and write requests, as well as their ordered storage and transmission, at the circuit level. Furthermore, the existence of the second request queue and the second data buffer reduces the risk of data and request loss due to storage device congestion.
[0018] Optionally, the splitting module further includes: a completion queue; the second control circuit is further configured to place the write response into the completion queue upon receiving a write response from the storage device; and to generate the large packet write response upon receiving write responses corresponding to all the target write requests from the storage device.
[0019] In the above implementation, a completion queue is set up to temporarily store the write responses fed back by the storage device. By counting the number of write responses corresponding to the target write requests stored in the completion queue, it is possible to confirm whether all target write data has been successfully written, thereby generating large packet write responses for feedback more accurately.
[0020] Optionally, the second request queue and the completion queue reuse the same queue entity.
[0021] In the above implementation, since the write response from the storage device is received only after the target write request is sent, the target write request and the write response from the storage device are usually not stored in the queue entity at the same time. Therefore, by reusing the same queue entity to implement the second request queue and the completion queue, the system implementation cost can be reduced while ensuring that the information in the queues is not confused.
[0022] Optionally, the splitting module includes: a consistency maintenance master node or a non-consistency maintenance master node.
[0023] Optionally, when the splitting module includes a consistency maintenance master node, the consistency maintenance master node includes a counter; the count value of the counter is equal to the number of target write data segments split from the large packet write data; the consistency maintenance module is used to perform a consistency maintenance operation when writing one target write data segment to the storage device; and when all the target write data segments are written to the storage device and the counter has performed a consistency maintenance operation, generate the large packet write response and feed it back to the data source module through the on-chip network.
[0024] In the above implementation, by setting a counter in the consistency master node that serves as the splitting module, and generating a large packet write response after all target write data has been written to the storage device and the counter value has been maintained for consistency, and feeding back the large packet write response to the data source module through the on-chip network, consistency maintenance can be achieved while implementing write response feedback.
[0025] Optionally, the system based on on-chip network transmission is a system-on-a-chip.
[0026] This application embodiment also provides a method for transmitting large packet write data, applied to a splitting module in any of the above-described systems; the method includes: receiving large packet write data and large packet write requests transmitted through the on-chip network; splitting the large packet write data into multiple target write data according to a preset size; the preset size is equal to the size of the maximum cache line in the system; splitting the received large packet write requests into target write requests corresponding to each of the target write data; sending each of the target write data and the target write request to the storage device; and, when each of the target write data is written to the storage device, feeding back a large packet write response to the data source module through the on-chip network.
[0027] In the above implementation, the splitting module connected to the second end of the on-chip network performs the operations of splitting large packet write data into multiple smaller target write data according to the maximum cache line size, and splitting large packet write requests into target write requests corresponding to each target write data. This allows the on-chip network to transmit only one large packet write data and one large packet write request during transmission. This reduces the number of write requests to be transmitted in terms of total transmission volume and the number of transmissions, thereby improving the bandwidth utilization of the on-chip network and reducing transmission power consumption. At the same time, since the amount of information to be transmitted is smaller than that of the traditional method, the requirements for the transmission capacity of the on-chip network are also smaller. When designing the on-chip network, the area overhead required by the on-chip network can also be smaller, which helps to reduce the area overhead of the on-chip network.
[0028] Optionally, the storage device is a first type of storage device that will send back a write response after the target write data is successfully written; when each of the target write data is written to the storage device, sending back a large packet write response to the data source module through the on-chip network includes: generating the large packet write response after receiving all write responses from the storage device for each of the target write data, and sending back the large packet write response to the data source module through the on-chip network.
[0029] Optionally, the storage device is a second type of storage device that does not send back a write response after the target write data is successfully written; when each of the target write data is written to the storage device, a large packet write response is sent back to the data source module through the on-chip network, including: when all the target write data is sent to the storage device, generating the large packet write response, and sending the large packet write response back to the data source module through the on-chip network.
[0030] Optionally, the splitting module includes a consistency maintenance master node; the method further includes: performing a consistency maintenance operation when writing one of the target write data to the storage device; before feeding back a large packet write response to the data source module through the on-chip network, it further includes: determining that the consistency maintenance operation has been completed a preset number of times; the preset number of times is equal to the number of target write data split from the large packet write data.
[0031] This application embodiment also provides a method for transmitting large packet write data, applied to a proxy module in any of the above-described systems; the method includes: receiving large packet write data and a large packet write request transmitted by the data source module; if the size of the large packet write data is greater than the transmission bit width of the on-chip network, splitting the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network, and outputting each intermediate write data and the large packet write request to the splitting module through the on-chip network; if the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network, outputting the large packet write data and the large packet write request to the splitting module through the on-chip network; receiving a large packet write response from the splitting module and transmitting it to the data source module.
[0032] In the above implementation, when the size of the large packet write data exceeds the transmission bit width of the on-chip network, the proxy module of the data source module splits the large packet write data into multiple intermediate write data for transmission according to the transmission bit width of the on-chip network. This allows the transmission of the large packet write data to meet the transmission bit width requirements of the on-chip network, thereby reducing the risk of packet loss during transmission and improving the reliability of write data transmission.
[0033] This application also provides an electronic device, including any of the above-described on-chip network transmission-based systems. Attached Figure Description
[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 A schematic diagram of the basic structure of a system based on on-chip network transmission provided in this application embodiment; Figure 2 A schematic diagram of a system architecture with a proxy module is provided for an embodiment of this application; Figure 3This is a schematic diagram of the structure of a proxy module provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a first control circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of a split module provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a second control circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of another modular structure provided in an embodiment of this application; Figure 8 A more specific structural diagram of the split module is provided for an embodiment of this application; Figure 9 A more specific structural diagram of a proxy module is provided for an embodiment of this application; Figure 10 A flowchart illustrating a method for transmitting large packet write data in a splitting module, as provided in an embodiment of this application; Figure 11 A flowchart illustrating a method for transmitting large packet write data in a proxy module, provided in an embodiment of this application; Figure 12 A specific system structure diagram is provided for an embodiment of this application; Figure 13 This is an interactive diagram illustrating the data transmission process using a traditional approach. Figure 14 This is an interactive schematic diagram illustrating the data transmission process when using the solution of this application, as provided in an embodiment of this application. Detailed Implementation
[0036] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0037] To facilitate understanding of the solutions and advantages of the embodiments of this application, some relevant technical terms that may be used will be explained below: On-chip network: A network-based communication subsystem in an integrated circuit chip, used to transmit data, requests, and other information between circuit modules.
[0038] The Home Node / Home Agent is the core component for maintaining cache consistency across multi-core processors. It manages data ownership, coordinates inter-core communication, and resolves cache conflicts. It receives read and write requests from all cores, handles cache line permission allocation (such as exclusive, shared, and invalid states), and prevents data conflicts caused by multi-core concurrency. It implements consistency protocols (such as directory protocols and listening protocols) and maintains the global cache state through message broadcasting or directory tables.
[0039] Non-consistent master node: In contrast to the concept of a consistent master node, a non-consistent master node does not maintain cache consistency.
[0040] Data source module: In this embodiment of the application, it refers to the circuit module in the integrated circuit chip that outputs write data and write requests to the on-chip network.
[0041] Large data write: Data writes that are larger than the maximum cache line size in the system.
[0042] Large packet write request: The request corresponding to writing large packet data.
[0043] Large packet write response: The write response for the large packet of data when it is successfully written.
[0044] Currently, when transmitting large packet write data and large packet write requests, the large packet write data is first split into multiple smaller write data packets according to the maximum cache line size, and the large packet write request is split into write requests corresponding to each smaller write data packet. These multiple write requests and smaller write data packets are then transmitted through the on-chip network. This requires the on-chip network to transmit multiple cache line-sized write data packets and multiple write requests, but only the bandwidth used for transmitting write data is effective; the bandwidth used for write requests is additional bandwidth consumption. This results in low bandwidth utilization of the on-chip network. Furthermore, the larger the amount of information to be transmitted, the higher the requirements for the on-chip network's transmission capacity. This leads to a larger area overhead required when designing the on-chip network, thus hindering the reduction of on-chip network area overhead using the current transmission method.
[0045] To address the aforementioned issues to some extent, this application provides a system based on on-chip network transmission and a method for transmitting large-packet write data based on this system.
[0046] See also Figure 1 As shown, Figure 1 This is a schematic diagram of the basic structure of the system based on on-chip network transmission provided in the embodiments of this application, including a data source module, an on-chip network, and a splitting module.
[0047] Specifically: the information output end of the data source module is connected to the first end of the on-chip network; the information receiving end of the split module is connected to the second end of the on-chip network; the split module is also configured to communicate with the storage device.
[0048] In the embodiments of this application, the data source module may be, but is not limited to, at least one of the following: processor cluster (including but not limited to CPU (Central Processing Unit), GPU (Graphics Processing Unit), GPGPU (General-purpose computing on graphics processing), DCU (Deep Computing Unit), etc.), deep learning accelerator, DMA (Direct Memory Access), I / O (Input / Output) device, etc.
[0049] In this embodiment, the data source module is used to output large packet write data and large packet write requests for large packet write data to the splitting module through the on-chip network.
[0050] The splitting module is used to: split the received large packet write data into multiple target write data according to a preset size, split the received large packet write request into target write requests corresponding to each target write data, and send each target write data and the target write request to the storage device. The preset size is equal to the size of the maximum cache line in the system.
[0051] The splitting module is also used to: send a large packet write response back to the data source module via the on-chip network when writing the target write data to the storage device.
[0052] In this embodiment of the application, the splitting module can split the large packet write request into individual target write requests in the format required by the protocol of the large packet request.
[0053] In this way, when transmitting large packet write data, the operations of splitting the large packet write data into multiple smaller target write data according to the maximum cache line size, and splitting the large packet write request into target write requests corresponding to each target write data, are performed by the splitting module connected to the second end of the on-chip network. This allows the on-chip network to transmit only the large packet write data and one large packet write request during transmission, which reduces the number of write requests to be transmitted in terms of total transmission and the number of transmissions, thereby improving the bandwidth utilization of the on-chip network and reducing power consumption. At the same time, since the amount of information to be transmitted is smaller than that of the traditional method, the requirements for the transmission capacity of the on-chip network are also smaller. When designing the on-chip network, the area overhead required by the on-chip network can also be smaller, which helps to reduce the area overhead of the on-chip network.
[0054] In the embodiments of this application, the storage device may be, but is not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), flash memory, RAM, etc.
[0055] In this application embodiment, considering the limitation of transmission bit width in on-chip networks, in order to ensure transmission effect, some optional implementations of this application embodiment can refer to... Figure 2 As shown, the system may also include a proxy module for the data source module. The information output end of the data source module is connected to the first end of the on-chip network through the proxy module.
[0056] In this optional implementation, the proxy module can be used to split the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network when the size of the large packet write data is greater than the transmission bit width of the on-chip network, and transmit these intermediate write data to the splitting module through the on-chip network. This ensures that the transmission of the large packet write data meets the transmission bit width requirements of the on-chip network, thereby reducing the risk of packet loss during transmission and improving the reliability of write data transmission.
[0057] For example, assuming the size of the large packet write data is 256 bytes and the transmission bit width of the on-chip network is 128 bytes, after the proxy module receives the large packet write data from the data source module, it splits the large packet write data into two intermediate write data of 128 bytes each and transmits them to the splitting module through the transmission network.
[0058] At this point, the splitting module will be used specifically to: split the intermediate write data into multiple target write data according to the preset size when the size of the intermediate write data is greater than the preset size; and use the intermediate write data as the target write data when the size of the intermediate write data is equal to the preset size.
[0059] For example, continuing with the previous example, assuming the preset size is 64 bytes, after receiving two intermediate write data, the splitting module will further split each of the two intermediate write data into two target write data, thus obtaining four target write data. On the other hand, it will split the received large packet write request into the target write requests corresponding to these four target write data respectively.
[0060] For example, continuing with the previous example, assuming the preset size is 128 bytes, the size of the intermediate write data is exactly equal to the preset size. At this time, the two intermediate write data are directly used as the target write data, and the received large packet write request is split into the target write requests corresponding to these two target write data respectively.
[0061] It is understood that in this optional implementation, when the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network, the proxy module will not split the data, and will directly transmit the large packet write data to the splitting module through the transmission network.
[0062] For example, assuming the size of the large packet write data is 256 bytes and the transmission bit width of the on-chip network is also 256 bytes, the proxy module, after receiving the large packet write data from the data source module, will directly transmit the 256 bytes of large packet write data to the splitting module through the transmission network.
[0063] In one feasible embodiment of the above optional implementation, see Figure 3 As shown, the proxy module may include: a first control circuit, a first request queue, a first data buffer, and a response queue. Wherein: The first control circuit is used to receive large packet write data and large packet write requests, and put the large packet write requests into the first request queue.
[0064] The first control circuit is further configured to: store the large packet write data in a first data buffer when the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network; and, when the size of the large packet write data is greater than the transmission bit width of the on-chip network, split the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network, and store each of the intermediate write data in the first data buffer.
[0065] The first control circuit is also used to receive large packet write responses and put them into the response queue.
[0066] The first control circuit is also used to: control the first request queue to sequentially transmit the stored large packet write requests to the on-chip network, and control the first data buffer to sequentially transmit the stored large packet write data or intermediate write data to the on-chip network; and control the response queue to sequentially transmit the stored large packet write responses to the data source module.
[0067] In one optional exemplary implementation of the above feasible embodiments, such as Figure 4 As shown, the first control circuit may include a type judgment circuit, a size comparison circuit, a data splitting circuit, and an output selection circuit (such as a multiplexer).
[0068] The type detection circuit is used to determine the type of received information, thereby determining whether it is written data, a write request, or a write response.
[0069] The output of the type determination circuit is connected to the first request queue, the response queue, the size comparison circuit, and the output selection circuit, respectively, and is used to: output the write request to the first request queue when the received information is identified as a write request; output the write response to the response queue when the received information is identified as a write response; and output the write data to the size comparison circuit and the output selection circuit when the received information is identified as write data.
[0070] The size comparator circuit is used to determine whether the size of the large packet of data written is greater than the transmission bit width of the on-chip network. The output of the size comparator circuit can be connected to the selection control terminal of the output selection circuit, thereby controlling the signal output path of the output selection circuit.
[0071] One signal output terminal of the output selection circuit is connected to the first data buffer, and the other signal output terminal is connected to the data splitting circuit. The output selection circuit is used to output the large packet write data to the first data buffer when the size comparison circuit determines that the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network; and to output the large packet write data to the data splitting circuit when the size comparison circuit determines that the size of the large packet write data is greater than the transmission bit width of the on-chip network.
[0072] The output of the data splitting circuit is connected to the first data buffer and is used to split the input large packet write data into multiple intermediate write data according to the preset transmission bit width of the on-chip network, and output them to the first data buffer.
[0073] It is understood that, in the embodiments of this application, the first control circuit may further include a monitoring circuit for monitoring the idle status of the on-chip network and the idle status of the signal receiving port of the data source module, thereby controlling the first request queue to output large packet write requests in sequence when the on-chip network is idle, and controlling the first data buffer to output large packet write data or intermediate write data in sequence, and controlling the response queue to output large packet write responses in sequence when the signal receiving port of the data source module is idle.
[0074] It is understandable that the first control circuit can also be implemented using other circuit forms, such as ASIC (Application Specific Integrated Circuit).
[0075] In the embodiments of this application, the queue entities of the first request queue and the response queue may be, but are not limited to, FIFO (First-In First-Out) buffers, ring buffers, etc.
[0076] Since the large packet write response is received only after the large packet write request is sent, the large packet write request and the large packet write response will not be stored in the queue entity at the same time. Therefore, in some optional embodiments of this application, the first request queue and the response queue can reuse the same queue entity, thereby reducing the system implementation cost while ensuring that the information in the queue is not confused.
[0077] In some optional embodiments of this application, such as Figure 5 As shown, the split module may include a second control circuit, a second request queue, and a second data cache. Wherein: The second control circuit is used to receive large packet write data or intermediate write data, and to receive large packet write requests. If the size of the large packet write data or intermediate write data exceeds a preset size, it splits the large packet write data or intermediate write data into multiple target write data according to the preset size, and splits the large packet write request into target write requests corresponding to each target write data. Each target write data is stored in a second data buffer, and each target write request is placed in a second request queue. If the size of the intermediate write data is less than or equal to the preset size, the intermediate write data is directly used as the target write data, and the large packet write request is split into target write requests corresponding to each target write data. Each target write data is stored in a second data buffer, and each target write request is placed in a second request queue.
[0078] The second control circuit is also used to: control the second request queue to sequentially transmit the target write requests to the storage device, and control the second data buffer to sequentially transmit the target write data to the storage device.
[0079] In one optional exemplary embodiment of the above optional implementation, such as Figure 6 As shown, the second control circuit may include a type judgment circuit, a size comparison circuit, a data splitting circuit, a request splitting circuit, a counter, and an output selection circuit (such as a multiplexer).
[0080] The type detection circuit is used to determine the type of received information, thereby determining whether it is write data or a write request. Objective The output of the type determination circuit is connected to the request splitting circuit, the size comparison circuit, and the output selection circuit, respectively, and is used to: output the write request to the request splitting circuit when the received information is identified as a write request; and output the write data to the size comparison circuit and the output selection circuit when the received information is identified as write data.
[0081] The size comparison circuit is used to determine whether the size of the received write data is greater than a preset size. The output of the size comparison circuit can be connected to the selection control terminal of the output selection circuit, thereby controlling the signal output path of the output selection circuit.
[0082] One signal output terminal of the output selection circuit is connected to the first data buffer, and the other signal output terminal is connected to the data splitting circuit. The output selection circuit is used to output the write data to the second data buffer when the size comparison circuit determines that the size of the write data is less than or equal to a preset size; and to output the write data to the data splitting circuit when the size comparison circuit determines that the size of the write data is greater than the preset size.
[0083] The output of the data splitting circuit is connected to the second data buffer and is used to split the input write data into multiple target write data according to a preset size and output them to the second data buffer.
[0084] A counter, connected to the data receiving end of the type determination circuit, the data splitting circuit, and the request splitting circuit, is used to record the number of write data received by the type determination circuit when the data splitting circuit is not started, and to record the number of target write data split by the data splitting circuit when the data splitting circuit is started.
[0085] The request splitting circuit is used to split the received large packet write request into target write requests according to the counter value, and output them to the second request queue in sequence.
[0086] In the embodiments of this application, there are two types of storage devices: one is a first type of storage device that will send a write response after the target write data is successfully written, and the other is a second type of storage device that will not send a write response after the target write data is successfully written.
[0087] If the storage device is a first-class storage device, then for the splitting module, upon receiving all write responses from the storage device for each target write data, it can be considered that the target write data has been written to the storage device, thereby generating a large packet write response, and feeding back the large packet write response to the data source module through the on-chip network.
[0088] At this point, in order to temporarily store the write responses from the storage device, such as Figure 7As shown, the splitting module may also include a completion queue. The second control circuit is further configured to place the write response into the completion queue when a write response is received from the storage device, and to generate a large packet write response and transmit it to the data source module via the on-chip network when write responses corresponding to all target write requests are received from the storage device.
[0089] If the storage device is a type II storage device, then for the splitting module, sending all target write data to the storage device is considered equivalent to writing all target write data to the storage device, thereby generating a large packet write response and feeding it back to the data source module via the on-chip network. In this case, a completion queue may not be required in the splitting module.
[0090] Optionally, the queue entities of the second request queue and the completion queue can be, but are not limited to, FIFO (First-In-First-Out) buffers, ring buffers, etc.
[0091] Furthermore, since the write response from the storage device is only received after the target write request is sent, the target write request and the write response from the storage device will not be stored in the queue entity at the same time. Therefore, in some optional embodiments of this application, the second request queue and the completion queue can reuse the same queue entity, thereby reducing system implementation costs while ensuring that the information in the queue is not confused.
[0092] It is understood that, in the embodiments of this application, the second control circuit may further include a monitoring circuit for monitoring the information receiving port of the storage device and the idle status of the on-chip network, thereby controlling the second request queue to output target write requests in sequence when the information receiving port of the storage device is idle, and controlling the second data buffer to output target write data in sequence, and outputting large packet write response when the on-chip network is idle.
[0093] It is understandable that the second control circuit can also be implemented using other circuit forms, such as ASIC.
[0094] In this embodiment, the splitting module may include a consistency maintenance master node or a non-consistency maintenance master node. The related circuitry of the splitting module can be integrated into the consistency maintenance master node or the non-consistency maintenance master node, or it can be set up separately outside of the consistency maintenance master node or the non-consistency maintenance master node.
[0095] In this embodiment, when the splitting module includes a consistency maintenance master node, consistency maintenance is required. In this case, the consistency maintenance master node may include a counter; the counter's value is equal to the number of target write data segments split from the large packet write data. For example, this counter may be the one described above. Figure 6 The counter shown in the embodiment is not intended to be limiting.
[0096] At this point, the consistency maintenance master node is used to perform a consistency maintenance operation when a target write data is written to the storage device. Specifically, the splitting module is used to generate a large packet write response after all target write data has been written to the storage device and a counter-value consistency maintenance operation has been performed, and then feeds back the large packet write response to the data source module via the on-chip network.
[0097] It is understood that, in the embodiments of this application, when the splitting module includes a consistency maintenance master node, the system may also include modules such as a directory listening filter, which are used to implement listening and other operations designed in the consistency maintenance process.
[0098] Correspondingly, such as Figure 8 As shown, the splitting module may also include a listening queue. The consistency maintenance master node can store the listening information generated or transmitted during the listening process into the listening queue, and generate listening response information when the listening is completed.
[0099] Correspondingly, such as Figure 9 As shown, the proxy module can also have a listen queue and a listen response queue. The proxy module can receive listen information from the data source module and temporarily store it in the listen queue. It then controls the listen queue to transmit the listen information sequentially to the consistency maintenance master node through the on-chip network for the master node to listen to. The proxy module can also receive listen response information from the consistency maintenance master node and temporarily store it in the listen response queue. It then controls the listen response queue to feed back the listen response information sequentially to the data source module.
[0100] Optionally, after the consistency maintenance is completed, the consistency maintenance result, which includes the listening response information, can be packaged together with the large packet write response generated after the large packet write data is completed and returned to the data source module in the format required by the protocol of the large packet response.
[0101] In this embodiment, the system based on on-chip network transmission can be a System-on-a-Chip (SoC) or other systems that achieve data transmission via an on-chip network, such as a multi-chip system, or a module with multiple chips deployed. When the on-chip network transmission system is an SoC, the storage device can be integrated within the SoC or disposed independently outside the SoC.
[0102] Based on the same inventive concept, see [link to relevant documentation] Figure 10 The method for transmitting large packet write data shown is applied to the splitting module in the aforementioned system and includes: S101: Receive large packet write data and large packet write requests transmitted through the on-chip network.
[0103] S102: Split large packet write data into multiple target write data according to the preset size.
[0104] S103: Split the received large packet write request into target write requests corresponding to each target write data.
[0105] There is no timing constraint between S102 and S103.
[0106] S104: Send the target write data and target write request to the storage device.
[0107] S105: When writing the target write data to the storage device, the large packet write response is fed back to the data source module through the on-chip network.
[0108] Optionally, if the storage device is a first type of storage device that will send back a write response after the target write data is successfully written, step S105 may include: generating a large packet write response after receiving all write responses from the storage device for each target write data, and sending the large packet write response back to the data source module through the on-chip network.
[0109] Optionally, if the storage device is a second type of storage device that does not send a write response after the target write data is successfully written, step S105 may include: generating a large packet write response and sending the large packet write response back to the data source module via the on-chip network after all the target write data has been sent to the storage device.
[0110] Optionally, when the splitting module includes a consistency maintenance master node, the method provided in this embodiment may further include: performing a consistency maintenance operation when writing a target write data to the storage device; and determining that the consistency maintenance operation has been completed a preset number of times before sending a large packet write response back to the data source module via the on-chip network. The preset number of times is equal to the number of target write data segments split from the large packet write data.
[0111] See also Figure 11 The method for transmitting large packet write data shown is applied to the proxy module in the aforementioned system and includes: S111: Receives large packet write data and large packet write requests transmitted by the data source module.
[0112] S112: When the size of the large packet write data is greater than the transmission bit width of the on-chip network, the large packet write data is split into multiple intermediate write data according to the transmission bit width of the on-chip network, and each intermediate write data and the large packet write request are output to the splitting module through the on-chip network. When the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network, the large packet write data and the large packet write request are output to the splitting module through the on-chip network.
[0113] S113: Receive the large packet write response from the splitting module and transmit it to the data source module.
[0114] It should be understood that, for the sake of brevity, some of the content described in the system embodiments will not be repeated in the above two method embodiments.
[0115] To facilitate understanding of the solutions in the embodiments of this application, the following example uses a specific scenario where the split module is the consistency master node to illustrate the solutions in the embodiments of this application.
[0116] See Figure 12 As shown, Figure 12 A specific system architecture is illustrated, including multiple data source modules: processor clusters, deep computing accelerators, DMA, I / O devices, and proxy modules for each data source module, distributed as processor proxy modules, accelerator proxy modules, DMA proxy modules, and I / O proxy modules. The system also includes an on-chip network, a consistency master node, and memory. The following example, using DMA to write large packets of data to memory, provides a comparative illustration of the traditional and proposed solutions. In this process, it is assumed that the on-chip network's transmission bit width is 128 bytes, the system's maximum cache line size is 64 bytes, and the large packet of data to be written is 256 bytes.
[0117] See also Figure 13 As shown, Figure 13 This illustrates the process of writing large packets of data to memory using DMA in a traditional approach, including: First, the DMA device outputs large packet write data and large packet write requests to the DMA agent module.
[0118] Next, the DMA proxy module splits the large packet write data into four 64-byte target write data 0, target write data 1, target write data 2, and target write data 3, and splits the large packet write request into four target write request 0, target write request 1, target write request 2, and target write request 3, respectively, corresponding to target write data 0, target write data 1, target write data 2, and target write data 3.
[0119] Next, the DMA agent module sends the target write data 0 and target write request 0, target write data 1 and target write request 1, target write data 2 and target write request 2, and target write data 3 and target write request 3 to the consistency master node in sequence through the on-chip network.
[0120] Next, the consistency master node sequentially sends target write data 0 and target write request 0, target write data 1 and target write request 1, target write data 2 and target write request 2, target write data 3 and target write request 3 to memory, and performs four consistency maintenance operations in sequence.
[0121] Next, the consistency master node waits for the memory to return the write responses to each target write request (write response 0, write response 1, write response 2, write response 3), and waits for the consistency maintenance to complete.
[0122] The consistency master node checks whether the number of currently received write responses and the number of completed consistency maintenance operations are both 4.
[0123] Next, with the number of write responses received and the number of consistency maintenance operations completed both being 4, the consistency master node generates write responses (write response 00, write response 11, write response 22, and write response 33) for the four target write requests respectively, and returns the four write responses to the DMA proxy module through the on-chip network.
[0124] Finally, the DMA agent module merges the four write responses into a single large write response according to the protocol requirements of the large packet response and sends it back to the DMA.
[0125] And see Figure 14 As shown, Figure 14 The process of writing large packets of data to memory using DMA in the scheme of this application is illustrated, including: First, the DMA device outputs large packet write data and large packet write requests to the DMA agent module.
[0126] Next, the DMA agent module splits the large packet write data into two 128-byte intermediate write data 0 and intermediate write data 1, and transmits intermediate write data 0, intermediate write data 1 and the large packet write request to the consistency master node through the on-chip network.
[0127] Next, the consistency master node splits the intermediate write data 0 into two 64-byte target write data 0 and target write data 1, splits the two 64-byte intermediate write data 1 into target write data 2 and target write data 3, and splits the large packet write request into four target write requests 0, 1, 2 and 3, respectively, corresponding to target write data 0, 1, 2 and 3.
[0128] Next, the consistency master node sequentially sends target write data 0 and target write request 0, target write data 1 and target write request 1, target write data 2 and target write request 2, target write data 3 and target write request 3 to memory, and performs four consistency maintenance operations in sequence.
[0129] Next, the consistency master node waits for the memory to return the write responses to each target write request (write response 0, write response 1, write response 2, write response 3), and waits for the consistency maintenance to complete.
[0130] The consistency master node checks whether the number of currently received write responses and the number of completed consistency maintenance operations are both 4.
[0131] When the number of write responses received and the number of consistency maintenance operations completed are both 4, the consistency master node generates a large packet write response and returns it to the DMA proxy module through the on-chip network, and then forwards it to the DMA.
[0132] contrast Figure 13 and Figure 14 As can be seen, compared with the traditional solution, the on-chip network of this application only transmits two write data, one write request and one write response, while the on-chip network of the traditional solution transmits four write data, four write requests and four write responses. The bandwidth utilization of the on-chip network in this application is significantly higher and the number of transmissions is significantly less. Therefore, the transmission power consumption of this application can be lower and the on-chip network can be designed to be smaller.
[0133] Based on the same inventive concept, this embodiment provides an electronic device, including the system based on on-chip network transmission provided in the embodiments of this application.
[0134] In this application embodiment, the electronic device can be a device capable of independently providing services to users, such as a smartphone, computer, smart wearable device, server, drone, car, gateway, etc. Furthermore, the electronic device can also be a device that, while capable of independent production and sale, still requires cooperation with other electronic devices to provide services to users, such as a motherboard with a System-on-a-Chip (SoC), graphics card, circuit board, control module, etc.
[0135] It is understandable that electronic devices may have even more components. For example, they may have communication interfaces, such as USB (Universal Serial Bus) interfaces or CAN (Controller Area Network) bus interfaces; and they may also have information display components such as displays, but this is not a limitation.
[0136] In the embodiments provided in this application, it should be understood that the disclosed products and methods can be implemented in other ways. The product embodiments described above are merely illustrative. Furthermore, the interconnections shown or discussed may be via communication interfaces and may be electrical, mechanical, or other forms.
[0137] Additionally, the modules described as separate components may or may not be physically separate.
[0138] Furthermore, the modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0139] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.
[0140] In this article, "multiple" refers to two or more.
[0141] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A system based on on-chip network transmission, characterized in that, include: Data source module, on-chip network, split module; The data source module is used to output large packet write data and large packet write requests for the large packet write data to the splitting module through the on-chip network; The splitting module is used to: split the received large packet write data into multiple target write data according to a preset size, and split the received large packet write request into target write requests corresponding to each of the target write data, and send each of the target write data and the target write request to the storage device; the preset size is equal to the size of the maximum cache line in the system; and is used to: when each of the target write data is written to the storage device, feed back a large packet write response to the data source module through the on-chip network.
2. The system based on on-chip network transmission as described in claim 1, characterized in that, The system also includes a proxy module for the data source module; the information output end of the data source module is connected to the first end of the on-chip network through the proxy module. The proxy module is used to split the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network when the size of the large packet write data is greater than the transmission bit width of the on-chip network. The splitting module is specifically used to: split the intermediate write data into multiple target write data according to the preset size when the size of the intermediate write data is greater than the preset size; and use the intermediate write data as the target write data when the size of the intermediate write data is equal to the preset size.
3. The system based on on-chip network transmission as described in claim 2, characterized in that, The proxy module includes: a first control circuit, a first request queue, a first data cache, and a response queue; The first control circuit is used to receive the large packet write data and the large packet write request, and put the large packet write request into the first request queue; The first control circuit is further configured to: store the large packet write data in the first data buffer when the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network; and split the large packet write data into multiple intermediate write data according to the transmission bit width of the on-chip network when the size of the large packet write data is greater than the transmission bit width of the on-chip network, and store each of the intermediate write data in the first data buffer. The first control circuit is also used to receive the large packet write response and put the large packet write response into the response queue; The first control circuit is further configured to: control the first request queue to sequentially transmit the stored large packet write requests to the on-chip network, and control the first data cache to sequentially transmit the stored large packet write data or the intermediate write data to the on-chip network; and control the response queue to sequentially transmit the stored large packet write responses to the data source module.
4. The system based on on-chip network transmission as described in claim 3, characterized in that, The first request queue and the response queue reuse the same queue entity.
5. The system based on on-chip network transmission as described in claim 1, characterized in that, The splitting module includes: a second control circuit, a second request queue, and a second data cache; The second control circuit is used to receive the large packet write data and the large packet write request, and split the large packet write data into multiple target write data according to a preset size, and split the large packet write request into target write requests corresponding to each of the target write data, and store each of the target write data into the second data cache, and put each of the target write requests into the second request queue. The second control circuit is further configured to: control the second request queue to sequentially transmit the stored target write requests to the storage device, and control the second data cache to sequentially transmit the stored target write data to the storage device.
6. The system based on on-chip network transmission as described in claim 5, characterized in that, The splitting module also includes: a completion queue; The second control circuit is further configured to place the write response into the completion queue upon receiving a write response from the storage device; and to generate the large packet write response upon receiving write responses corresponding to all the target write requests from the storage device.
7. The system based on on-chip network transmission as described in claim 6, characterized in that, The second request queue and the completion queue reuse the same queue entity.
8. The system based on on-chip network transmission as described in any one of claims 1-7, characterized in that, The splitting module includes either a consistency-maintaining master node or a non-consistency-maintaining master node.
9. The system based on on-chip network transmission as described in claim 8, characterized in that, In the case where the splitting module includes a consistency maintenance master node, the consistency maintenance master node includes a counter; the count value of the counter is equal to the number of target write data segments split from the large packet write data. The consistency maintenance module is used to perform a consistency maintenance operation when writing target write data to the storage device. The splitting module is used to generate the large packet write response when all the target write data has been written to the storage device and the counter value has been maintained for consistency, and to feed back the large packet write response to the data source module through the on-chip network.
10. The system based on on-chip network transmission as described in any one of claims 1-7, characterized in that, The system based on on-chip network transmission is a system-on-a-chip.
11. A method for transmitting large-packet write data, characterized in that, Applied to a split module in the system as described in any one of claims 1-10; the method includes: Receive large packet write data and large packet write requests transmitted through the on-chip network; The large packet of write data is split into multiple target write data according to a preset size; the preset size is equal to the size of the maximum cache line in the system. The received large packet write request is split into target write requests corresponding to each of the target write data; Send each of the target write data and the target write request to the storage device; When writing the target write data to the storage device, a large packet write response is sent back to the data source module via the on-chip network.
12. The method for transmitting large packet write data as described in claim 11, characterized in that, The storage device is a first type of storage device that will send back a write response after the target write data is successfully written; When writing the target write data to the storage device, a large packet write response is sent back to the data source module via the on-chip network, including: Upon receiving all write responses from the storage device for each of the target write data, the large packet write response is generated and fed back to the data source module via the on-chip network.
13. The method for transmitting large packet write data as described in claim 11, characterized in that, The storage device is a second type of storage device that does not send a write response after the target write data is successfully written; When writing the target write data to the storage device, a large packet write response is sent back to the data source module via the on-chip network, including: When all the target write data is sent to the storage device, the large packet write response is generated and fed back to the data source module through the on-chip network.
14. The method for transmitting large packet write data as described in any one of claims 11-13, characterized in that, The splitting module includes a consistency maintenance master node; the method further includes: When writing the target write data to the storage device, a consistency maintenance operation is performed. Before sending a large packet write response back to the data source module via the on-chip network, the process also includes: The consistency maintenance operation has been completed a preset number of times; the preset number of times is equal to the number of target write data segments split from the large packet write data.
15. A method for transmitting large-packet write data, characterized in that, Applied to a proxy module in the system as described in any one of claims 2-4; the method includes: Receive large packet write data and large packet write requests transmitted by the data source module; If the size of the large packet write data is greater than the transmission bit width of the on-chip network, the large packet write data is split into multiple intermediate write data according to the transmission bit width of the on-chip network, and each intermediate write data and the large packet write request are output to the splitting module through the on-chip network. When the size of the large packet write data is less than or equal to the transmission bit width of the on-chip network, the large packet write data and the large packet write request are output to the splitting module through the on-chip network; Receive the large packet write response from the splitting module and transmit it to the data source module.
16. An electronic device, characterized in that, Including the system based on on-chip network transmission as described in any one of claims 1-10.