A quantum circuit compiling method based on circuit merging and a related device

Abstract

The application discloses a quantum circuit compiling method based on line merging and a related device, and belongs to the technical field of quantum computing. The method comprises the following steps: obtaining a plurality of quantum circuits to be compiled, and determining whether the plurality of quantum circuits to be compiled can perform a line merging operation process; in response to the plurality of quantum circuits to be compiled being capable of performing the line merging operation, merging the plurality of quantum circuits to be compiled to generate a new quantum circuit; and performing a quantum operation process based on the new quantum circuit obtained after the merging process to obtain a quantum circuit that can be executed on a quantum processor. The application introduces a merging mechanism of shared sub-lines in the quantum circuit, aims to reduce the utilization rate of quantum bits and quantum logic gates, improve the service throughput of the quantum computing platform, realizes effective management of quantum computing resources through the merging process of the quantum circuit, and thus improves the overall quantum computing processing efficiency.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a quantum circuit compilation method and related apparatus based on circuit merging. Background Technology

[0002] Quantum computing has gradually matured from its initial theoretical computing model. For specific quantum problems, its performance has surpassed that of traditional computers. Now, many companies are launching access services for quantum hardware. Whether the access is free or paid, most of these services rely on quantum computing cloud platforms. With the rapid growth in demand for quantum computing, the scarcity of quantum computing resources has gradually become apparent. When users try to access computing resources, they often face long queues. Their computing tasks can only be executed after all the preceding computing tasks have been completed. This inefficient allocation of computing resources not only affects the user's computing efficiency but also greatly reduces the user experience.

[0003] Therefore, the urgent technical problem to be solved is to provide a new method for compiling quantum circuits, which aims to reduce the utilization of qubits and quantum logic gates, thereby increasing the service throughput of quantum computing platforms and thus improving the efficiency of quantum computing processing. Summary of the Invention

[0004] The purpose of this invention is to provide a quantum circuit compilation method and related apparatus based on circuit merging, which aims to reduce the utilization of qubits and quantum logic gates, thereby increasing the service throughput of the quantum computing platform and thus improving the efficiency of quantum computing processing.

[0005] One embodiment of the present invention provides a quantum circuit compilation method based on circuit merging, the method comprising:

[0006] Obtain multiple quantum circuits to be compiled, and determine whether the multiple quantum circuits to be compiled can be processed by circuit merging.

[0007] In response to the plurality of quantum circuits to be compiled, a quantum circuit merging operation can be performed to merge the plurality of quantum circuits to be compiled to generate a new quantum circuit;

[0008] Based on the merged new quantum circuit, quantum operations are performed to obtain a quantum circuit that can be executed by a quantum processor.

[0009] Optionally, the process of determining whether the plurality of quantum circuits to be compiled can perform a circuit merging operation includes:

[0010] The determination of whether the multiple quantum circuits to be compiled can be processed by circuit merging is based on the shared sub-circuit; the shared sub-circuit is the sub-circuit with the same topology among the multiple quantum circuits to be compiled; the sub-circuit is all or part of the quantum circuits to be compiled.

[0011] Optionally, in response to the plurality of quantum circuits to be compiled, a quantum circuit merging operation can be performed to merge the plurality of quantum circuits to be compiled to generate a new quantum circuit, including:

[0012] If there is a shared sub-circuit among the multiple quantum circuits, the multiple quantum circuits are merged according to the largest shared sub-circuit to generate a new quantum circuit; the largest shared sub-circuit is the shared sub-circuit that occupies the most qubits.

[0013] Optionally, when there is a shared sub-circuit among the plurality of quantum circuits, merging the plurality of quantum circuits to generate a new quantum circuit based on the largest shared sub-circuit includes:

[0014] Obtain the plurality of quantum circuits to be merged, and determine the largest shared sub-circuit of the plurality of quantum circuits;

[0015] Construct a new quantum circuit and establish a mapping relationship between the qubits of the new quantum circuit and the qubits of the multiple quantum circuits to be merged; the new quantum circuit is a quantum circuit framework in which the number of qubits has been determined and the qubits are set to a quantum state, but no quantum logic gate operations are inserted.

[0016] Based on the mapping relationship of the qubits, the quantum logic gates of the largest shared sub-circuit are inserted into the new quantum circuit, and the quantum logic gates of the non-shared sub-circuit are inserted into the new quantum circuit according to the execution order of the multiple original quantum circuits.

[0017] Optionally, the quantum manipulation process includes one or a combination of the following:

[0018] Quantum circuit optimization processing and quantum circuit mapping processing.

[0019] Optionally, the plurality of quantum circuits to be compiled are applied to a reactive service, which is a quantum computing operation executed by the server in response to a user's request in real time;

[0020] The quantum operation processing based on the new quantum circuit after merging includes:

[0021] In response to a client request, the merged new quantum circuit will be subjected to quantum operations.

[0022] Optionally, the method further includes:

[0023] The multiple quantum circuits to be compiled are applied to non-responsive services, which are quantum computing operations preset by the quantum computing platform.

[0024] The quantum operation processing based on the new quantum circuit after merging includes:

[0025] In response to the quantum computing operation preset by the quantum computing platform, the merged new quantum circuit will be subjected to quantum operation processing.

[0026] Another embodiment of the present invention provides a quantum circuit compilation device based on circuit merging, the device comprising:

[0027] The acquisition unit is used to acquire multiple quantum circuits to be compiled and to determine whether the multiple quantum circuits to be compiled can be processed by circuit merging.

[0028] A response unit is configured to perform a quantum circuit merging operation in response to the plurality of quantum circuits to be compiled, thereby merging the plurality of quantum circuits to be compiled to generate a new quantum circuit.

[0029] An execution unit is used to perform quantum operation processing based on the merged new quantum circuit to obtain a quantum circuit that can be executed by a quantum processor.

[0030] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0031] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0032] Another embodiment of the present invention provides a quantum computer operating system, which implements quantum circuit compilation based on circuit merging according to the method described in any of the above embodiments.

[0033] Compared with the prior art, the present invention first obtains multiple quantum circuits to be compiled and determines whether the multiple quantum circuits to be compiled can be processed by circuit merging; then, in response to the multiple quantum circuits to be compiled being able to be processed by quantum circuit merging, the multiple quantum circuits to be compiled are merged to generate a new quantum circuit; finally, quantum operation processing is performed on the new quantum circuit after merging to obtain a quantum circuit that can be executed by a quantum processor.

[0034] This invention first obtains multiple quantum circuits to be compiled and determines whether these multiple quantum circuits can undergo a circuit merging operation. The purpose of this step is to determine whether multiple quantum circuits can be merged, providing a prerequisite and foundation for subsequent merging operations. Then, in response to the fact that the multiple quantum circuits to be compiled can undergo a quantum circuit merging operation, the multiple quantum circuits to be compiled are merged to generate a new quantum circuit. If multiple quantum circuits can be merged, then by performing this step, a more efficient new quantum circuit can be created, and the merging operation can reduce the number of quantum lines. Redundant operations in the circuit reduce the complexity of the quantum circuit, which may reduce the number and depth of quantum gates required to execute the quantum algorithm, thereby improving the execution efficiency of the quantum circuit. Finally, quantum operation processing is performed on the merged new quantum circuit to obtain a quantum circuit that can be executed by a quantum processor. This step involves further processing the merged new quantum circuit to adapt it to the quantum processor. This process may include quantum logic gate optimization and quantum circuit mapping, so that the final result can be the generation of a quantum circuit that can be executed on actual quantum hardware, so that the quantum algorithm can run on a practical quantum processor, thereby improving the practicality and executability of the quantum algorithm. Attached Figure Description

[0035] Figure 1 This is a network block diagram of a quantum circuit compilation system based on circuit merging, provided for an embodiment of the present invention.

[0036] Figure 2 A flowchart of a quantum circuit compilation method based on circuit merging is provided for an embodiment of the present invention.

[0037] Figure 3 is a schematic diagram of a shared sub-line provided in an embodiment of the present invention.

[0038] Figure 4 is a schematic diagram of a line merging operation provided by an embodiment of the present invention.

[0039] Figure 5 is a schematic diagram of another line merging operation provided by an embodiment of the present invention.

[0040] Figure 6This is a flowchart of a novel quantum circuit acquisition method provided in an embodiment of the present invention.

[0041] Figure 7 This is a structural diagram of a quantum circuit compilation device based on circuit merging, provided as an embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0043] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] Figure 1 This is a network block diagram of a quantum circuit compilation system based on circuit merging provided in an embodiment of the present invention. The quantum circuit compilation system based on circuit merging may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices (not shown).

[0045] Network 110 is a medium used to provide communication links between various devices and computers connected together within a circuit-merging-based quantum circuit compilation system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof, and the connection method can be wired, wireless communication links, or fiber optic cables.

[0046] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0047] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by a quantum circuit compilation method based on circuit merging provided in an embodiment of the present invention.

[0048] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0049] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0050] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0051] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0052] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0053] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0054] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0055] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0056] Quantum computing has gradually matured from its initial theoretical computing model. For specific quantum problems, its performance has surpassed that of traditional computers. Now, many companies are launching access services for quantum hardware. Whether the access is free or paid, most of these services rely on quantum computing cloud platforms. With the rapid growth in demand for quantum computing, the scarcity of quantum computing resources has gradually become apparent. When users try to access computing resources, they often face long queues. Their computing tasks can only be executed after all the preceding computing tasks have been completed. This inefficient allocation of computing resources not only affects the user's computing efficiency but also greatly reduces the user experience.

[0057] Therefore, the urgent technical problem to be solved is to provide a new method for compiling quantum circuits, which aims to reduce the utilization of qubits and quantum logic gates, thereby increasing the service throughput of quantum computing platforms and thus improving the efficiency of quantum computing processing.

[0058] See Figure 2 , Figure 2 A quantum circuit compilation method based on circuit merging, provided for embodiments of the present invention, includes the following steps:

[0059] Step S201: Obtain multiple quantum circuits to be compiled, and determine whether the multiple quantum circuits to be compiled can be processed by circuit merging.

[0060] Specifically, multiple quantum circuits to be compiled will be obtained, and it will be determined whether the multiple quantum circuits to be compiled can be processed by circuit merging.

[0061] Step S202: In response to the plurality of quantum circuits to be compiled, a quantum circuit merging operation can be performed to merge the plurality of quantum circuits to be compiled to generate a new quantum circuit.

[0062] Specifically, if multiple quantum circuits to be compiled can be merged, the multiple quantum circuits to be compiled are merged to generate a new quantum circuit.

[0063] Step S203: Perform quantum operation processing based on the new quantum circuit after merging to obtain a quantum circuit that can be executed by a quantum processor.

[0064] Specifically, quantum operations will be performed on new quantum circuits that can be processed by merging them to obtain quantum circuits that can be executed on a quantum processor.

[0065] In summary, this invention first acquires multiple quantum circuits to be compiled and determines whether these multiple quantum circuits can undergo a circuit merging operation. The purpose of this step is to determine whether multiple quantum circuits can be merged, providing a prerequisite and foundation for subsequent merging operations. Then, in response to the fact that the multiple quantum circuits to be compiled can undergo a quantum circuit merging operation, the multiple quantum circuits to be compiled are merged to generate a new quantum circuit. If multiple quantum circuits can be merged, then by performing this step, a more efficient new quantum circuit can be created, and the merging operation can reduce... Redundant operations in quantum circuits reduce their complexity, potentially reducing the number and depth of quantum gates required to execute quantum algorithms, thus improving execution efficiency. Finally, quantum operations are performed on the merged new quantum circuit to obtain a quantum circuit executable by a quantum processor. This step involves further processing the merged new quantum circuit to adapt it to the quantum processor. This process may include quantum logic gate optimization and quantum circuit mapping, ultimately generating a quantum circuit executable on practical quantum hardware. This allows quantum algorithms to run on actual quantum processors, improving their practicality and executability.

[0066] In one embodiment of the present invention, the process of determining whether the plurality of quantum circuits to be compiled can perform a circuit merging operation includes:

[0067] The determination of whether the multiple quantum circuits to be compiled can be processed by circuit merging is based on the shared sub-circuit; the shared sub-circuit is the sub-circuit with the same topology among the multiple quantum circuits to be compiled; the sub-circuit is all or part of the quantum circuits to be compiled.

[0068] Among them, a shared sub-circuit is a sub-circuit with the same topology in the quantum circuit to be compiled; a sub-circuit is the entire content of the quantum circuit to be compiled or part of the content of the quantum circuit to be compiled.

[0069] Specifically, the process determines whether multiple quantum circuits to be compiled can be processed by merging based on the shared sub-circuit.

[0070] For example, referring to Figure 3, which is a schematic diagram of a shared sub-circuit provided by an embodiment of the present invention, in Figure 3(a), the evolution path of qubit q0 of quantum circuit C1 includes quantum logic gate Y, and in Figure 3(b), the evolution path of qubit q0' of quantum circuit C2 includes quantum logic gate Y. The topological structure of the evolution path of qubit q0 and the topological structure of the evolution path of q0' are the same. Therefore, there is a shared sub-circuit in quantum circuit C1 and quantum circuit C2, and quantum circuit C1 and quantum circuit C2 can perform a merging operation.

[0071] In summary, by identifying shared sub-circuits (i.e., sub-circuits with the same topology) among multiple quantum circuits to be compiled, it is possible to more accurately determine which quantum circuits can be merged. This merging strategy based on shared sub-circuits improves the overall efficiency of quantum circuit compilation optimization. The existence of shared sub-circuits means that these sub-circuits appear repeatedly in multiple quantum circuits. By merging these quantum circuits, this repetition can be eliminated, thereby reducing the resources required by the quantum processor when performing quantum operations (such as the number of qubits, the number of quantum gates, etc.).

[0072] In one embodiment of the present invention, the step of performing a quantum circuit merging operation in response to the plurality of quantum circuits to be compiled, merging the plurality of quantum circuits to be compiled to generate a new quantum circuit, includes:

[0073] If there is a shared sub-circuit among the multiple quantum circuits, the multiple quantum circuits are merged according to the largest shared sub-circuit to generate a new quantum circuit; the largest shared sub-circuit is the shared sub-circuit that occupies the most qubits.

[0074] Among them, the largest shared sub-circuit is the shared sub-circuit that occupies the most qubits.

[0075] Specifically, when multiple quantum circuits share a sub-circuit, the multiple quantum circuits are merged based on the largest shared sub-circuit to generate a new quantum circuit.

[0076] For example, referring to Figure 4, which is a schematic diagram of performing a line merging operation according to an embodiment of the present invention, in Figure 4(a), the evolution path of qubit q0 of quantum circuit C1 includes quantum logic gate Y, and the evolution path of qubit q1 includes quantum logic gate X; in Figure 4(b), the evolution path of qubit q0' of quantum circuit C2 includes quantum logic gate Y, and the evolution path of qubit q1' includes quantum logic gate X. Therefore, the topological structure of the evolution path of qubit q0 and the topological structure of the evolution path of q0' are the same, and the quantum ratio... If the topological structure of the evolution path of qubit q1 is the same as that of the evolution path of qubit q1', then there is a shared sub-circuit in quantum circuits C1 and C2. Therefore, quantum circuits C1 and C2 can perform a merging operation. Furthermore, the topological structure of the evolution paths of qubit q0 and qubit q0' is the same as that of the evolution paths of qubit q1 and qubit q1', which is the maximum shared sub-circuit. Therefore, according to the maximum shared sub-circuit, quantum circuits C1 and C2 are merged to generate a new quantum circuit as shown in Figure 4(c).

[0077] Referring to Figure 5, which is a schematic diagram of another circuit merging operation provided by an embodiment of the present invention, in Figure 5(a), the evolution path of qubit q0 of quantum circuit C1 includes quantum logic gates Y and S, and the evolution path of qubit q1 includes quantum logic gates X and T; in Figure 5(b), the evolution path of qubit q0' of quantum circuit C2 includes quantum logic gates Y and S, and the evolution path of qubit q1' includes quantum logic gates X and T. The topological structure of the evolution path of qubit q0 and the evolution path of qubit q0'... If the topology is the same, and the topology of the evolution path of qubit q1 is the same as that of the evolution path of qubit q1', then there is a shared sub-circuit in quantum circuits C1 and C2. Therefore, quantum circuits C1 and C2 can perform a merging operation. Furthermore, the topology of the evolution paths of qubit q0 and qubit q0' is the same as that of the evolution paths of qubit q1 and qubit q1', which is the maximum shared sub-circuit. Therefore, according to the maximum shared sub-circuit, quantum circuits C1 and C2 are merged to generate a new quantum circuit as shown in Figure 5(c).

[0078] In summary, when multiple shared sub-circuits exist, selecting the shared sub-circuit with the largest number of qubits as the basis for merging maximizes the utilization of quantum resources. This is because the sub-circuit with the largest number of qubits often has a greater impact on the overall circuit performance and resource consumption. By merging these sub-circuits, the redundant use of qubits and quantum logic gates can be significantly reduced, thereby improving the overall efficiency of the quantum circuit. The merging strategy based on the largest shared sub-circuit helps optimize the structure of the quantum circuit. By identifying and merging the largest shared sub-circuit, the repetitive parts in the quantum circuit can be reduced, making the circuit structure more compact and efficient. The merged quantum circuit, due to the reduction of redundancy and repetition, typically has fewer quantum logic gates and shorter execution paths. This means that the probability of error accumulation in the quantum computing process is reduced, thereby improving the accuracy and reliability of quantum computing.

[0079] See Figure 6 , Figure 6 A flowchart of a novel quantum circuit acquisition method provided by an embodiment of the present invention includes the following steps:

[0080] Step S601: Obtain the plurality of quantum circuits to be merged and determine the largest shared sub-circuit of the plurality of quantum circuits.

[0081] Specifically, it acquires multiple quantum circuits to be merged and determines the largest shared sub-circuit among the multiple quantum circuits.

[0082] Step S602: Construct a new quantum circuit and establish a mapping relationship between the qubits of the new quantum circuit and the qubits of the multiple quantum circuits to be merged. The new quantum circuit is a quantum circuit framework in which the number of qubits has been determined and the qubits are set to a quantum state, but no quantum logic gate operations are inserted.

[0083] Specifically, a new quantum circuit is constructed, and a mapping relationship is established between the qubits in the new quantum circuit and the qubits of multiple quantum circuits to be merged. The qubits of the new quantum circuit are associated with the qubits of multiple quantum circuits to be merged. It should be emphasized that the new quantum circuit here is a quantum circuit framework with a determined number of qubits and each qubit of the quantum circuit is set to a quantum state, but no quantum logic gate operations are inserted.

[0084] For example, suppose there are two quantum circuits, circuit A and circuit B, both of which need to be executed on a quantum computer. Each quantum circuit has its own qubits: circuit A has qubits qA0 and qA1, and circuit B has qubits qB0 and qB1. Now, we want to optimize these two circuits by merging them so that they can be executed more efficiently on the quantum processor. First, we create a new quantum circuit, called quantum circuit C. Based on maximum sharing, the number of qubits in quantum circuit C is already determined. It will contain all the qubits of circuit A and circuit B, namely qC0 / qC0', qC1, and qC2. Then, we establish mapping relationships between these qubits qC0 / qC0', qC1, and qC2 and the qubits of circuit A and circuit B, respectively. At this point, no quantum logic gate operations are inserted into quantum circuit C, making it a quantum circuit framework that does not execute any quantum logic gates.

[0085] Step S603: Based on the mapping relationship of the qubits, insert the quantum logic gate of the largest shared sub-circuit into the new quantum circuit, and insert the quantum logic gate of the non-shared sub-circuit into the new quantum circuit according to the execution order of the multiple original quantum circuits.

[0086] Specifically, based on the mapping relationship of qubits established in step S602 above, the quantum logic gates of the largest shared sub-circuit are inserted into the new quantum circuit framework, and the quantum logic gates of the non-shared sub-circuit are sequentially inserted into the new quantum circuit framework according to the execution order of the original quantum circuit.

[0087] For example, referring to Figure 5, it is first determined that quantum circuit C1 and quantum circuit C2 share a sub-circuit. The largest shared sub-circuit is then identified, and a quantum circuit C3 is constructed. It is confirmed that the number of qubits required for quantum circuit C3 is 4. Based on the largest shared sub-circuit, qubits q0 and q0' of quantum circuit C1 are mapped to the first qubit of quantum circuit C3. This process is repeated until qubit q2 of quantum circuit C1 is mapped to the third qubit of quantum circuit C3, and qubit q2' of quantum circuit C1 is mapped to the fourth qubit of quantum circuit C3. Then, the quantum logic gates Y and S, as well as X and T of the largest shared sub-circuit, are inserted into quantum circuit C3. Then, the non-shared sub-circuits, such as the two-qubit quantum logic gate CZ in quantum circuit C1 and the two-qubit quantum logic gate CP in quantum circuit C2, are inserted into quantum circuit C3 in the execution order of the original quantum circuits to generate quantum circuit C3.

[0088] In summary, by acquiring the quantum circuits to be merged and identifying the largest shared sub-circuit, we can clearly understand which parts are repetitive or can be merged, providing a clear direction for subsequent steps. Identifying the largest shared sub-circuit helps maximize the utilization of quantum resources because this part of the sub-circuit appears repeatedly in multiple original circuits, and merging reduces redundancy. The new quantum circuit, as the result of merging, needs to establish a clear mapping relationship with the original circuits to ensure that the merged circuit can correctly reflect the logic and function of the original circuits. The new quantum circuit, as a blank framework, provides a basis for subsequent insertion of quantum logic gates. Since no quantum logic gate operations are inserted into the new circuit at the beginning, errors introduced by improper initial operations can be avoided. By inserting quantum logic gates according to the mapping relationship and the execution order of the original circuits, it can be ensured that the merged quantum circuit can correctly execute the logic and function of the original circuits. The merged circuit, due to the removal of repetitive parts, usually has a simpler structure, which helps reduce the consumption of quantum resources and improve the efficiency of quantum computing.

[0089] In one embodiment of the present invention, the quantum manipulation process includes one or a combination of the following:

[0090] Quantum circuit optimization processing and quantum circuit mapping processing.

[0091] Quantum circuit optimization refers to the process of making a series of improvements and adjustments to the circuit before execution, in order to improve efficiency, reduce resource consumption (such as the number of qubits and quantum gates), improve fidelity, or simplify the circuit structure; quantum circuit mapping refers to the process of converting logical quantum circuits into mapped circuits, which are quantum circuits that can be executed on quantum hardware resources.

[0092] In one embodiment of the present invention, the plurality of quantum circuits to be compiled are applied to a responsive service, wherein the responsive service is a quantum computing operation performed by the server in response to a user's request in real time;

[0093] The quantum operation processing based on the new quantum circuit after merging includes:

[0094] In response to a client request, the merged new quantum circuit will be subjected to quantum operations.

[0095] Specifically, if multiple quantum circuits to be compiled are applied to a reactive service, that is, in response to a client request, the multiple quantum circuits to be compiled are merged to generate a new quantum circuit, and the new quantum circuit is used to perform quantum operations on the server.

[0096] In one embodiment of the present invention, the method further includes:

[0097] The multiple quantum circuits to be compiled are applied to non-responsive services, which are quantum computing operations preset by the quantum computing platform.

[0098] The quantum operation processing based on the new quantum circuit after merging includes:

[0099] In response to the quantum computing operation preset by the quantum computing platform, the merged new quantum circuit will be subjected to quantum operation processing.

[0100] Specifically, if multiple quantum circuits to be compiled are applied to non-responsive services, the compilation requirements of the quantum circuits may be automatically generated by the internal programs or algorithms preset by the quantum computing platform. These requirements may be based on specific computing tasks, algorithm optimizations, or experimental purposes. The compilation process is carried out proactively without external requests. Similar to the server side, quantum circuits in non-server environments also need to be analyzed in depth. That is, multiple quantum circuits to be compiled are merged to generate new quantum circuits. Driven by the internal programs or algorithms preset by the quantum computing platform, the new quantum circuits are subjected to quantum operations.

[0101] See Figure 7 , Figure 7 A quantum circuit compilation device based on circuit merging is provided in an embodiment of the present invention. The device includes: an acquisition unit 701, a response unit 702, and an execution unit 703.

[0102] The acquisition unit 701 is used to acquire multiple quantum circuits to be compiled and to determine whether the multiple quantum circuits to be compiled can be processed by circuit merging.

[0103] Specifically, the process of determining whether the plurality of quantum circuits to be compiled can perform a circuit merging operation includes:

[0104] The determination of whether the multiple quantum circuits to be compiled can be processed by circuit merging is based on the shared sub-circuit; the shared sub-circuit is the sub-circuit with the same topology among the multiple quantum circuits to be compiled; the sub-circuit is all or part of the quantum circuits to be compiled.

[0105] The response unit 702 is configured to perform a quantum circuit merging operation in response to the plurality of quantum circuits to be compiled, thereby merging the plurality of quantum circuits to be compiled to generate a new quantum circuit.

[0106] Specifically, the step of performing a quantum circuit merging operation in response to the plurality of quantum circuits to be compiled, merging the plurality of quantum circuits to be compiled to generate a new quantum circuit, includes:

[0107] If there is a shared sub-circuit among the multiple quantum circuits, the multiple quantum circuits are merged according to the largest shared sub-circuit to generate a new quantum circuit; the largest shared sub-circuit is the shared sub-circuit that occupies the most qubits.

[0108] Specifically, when there are shared sub-circuits among the plurality of quantum circuits, the plurality of quantum circuits are merged to generate a new quantum circuit based on the largest shared sub-circuit, including:

[0109] Obtain the plurality of quantum circuits to be merged, and determine the largest shared sub-circuit of the plurality of quantum circuits;

[0110] Construct a new quantum circuit and establish a mapping relationship between the qubits of the new quantum circuit and the qubits of the multiple quantum circuits to be merged; the new quantum circuit is a quantum circuit framework in which the number of qubits has been determined and the qubits are set to a quantum state, but no quantum logic gate operations are inserted.

[0111] Based on the mapping relationship of the qubits, the quantum logic gates of the largest shared sub-circuit are inserted into the new quantum circuit, and the quantum logic gates of the non-shared sub-circuit are inserted into the new quantum circuit according to the execution order of the multiple original quantum circuits.

[0112] Execution unit 703 is used to perform quantum operation processing based on the merged new quantum circuit to obtain a quantum circuit that can be executed by a quantum processor.

[0113] Specifically, the quantum manipulation process includes one or a combination of the following:

[0114] Quantum circuit optimization processing and quantum circuit mapping processing.

[0115] Specifically, the multiple quantum circuits to be compiled are applied to a reactive service, which is a quantum computing operation executed by the server in response to a user's request in real time.

[0116] The quantum operation processing based on the new quantum circuit after merging includes:

[0117] In response to a client request, the merged new quantum circuit will be subjected to quantum operations.

[0118] Specifically, the method further includes:

[0119] The multiple quantum circuits to be compiled are applied to non-responsive services, which are quantum computing operations preset by the quantum computing platform.

[0120] The quantum operation processing based on the new quantum circuit after merging includes:

[0121] In response to the quantum computing operation preset by the quantum computing platform, the merged new quantum circuit will be subjected to quantum operation processing.

[0122] The specific functions and effects of the aforementioned quantum circuit compilation device based on circuit merging can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the quantum circuit compilation device based on circuit merging can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0123] Please see Figure 8 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit compilation method based on circuit merging as described in any of the above embodiments. Please refer to [link to documentation]. Figure 8 The electronic device can be a classical computer or a quantum computer.

[0124] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit compilation method based on circuit merging in any of the above embodiments.

[0125] This invention also provides a quantum computer operating system, which implements quantum circuit compilation based on circuit merging according to any of the above-described method embodiments provided in this invention.

[0126] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0127] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0128] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0129] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0130] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0131] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0132] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0133] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0134] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0135] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0136] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0137] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0138] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum circuit compiling method based on circuit merging, characterized in that, The method includes: Obtain multiple quantum circuits to be compiled, and determine whether the multiple quantum circuits to be compiled can be processed by circuit merging. In response to the plurality of quantum circuits to be compiled, a quantum circuit merging operation can be performed to obtain the plurality of quantum circuits to be merged, and to determine the largest shared sub-circuit of the plurality of quantum circuits, wherein the largest shared sub-circuit is the shared sub-circuit that occupies the most qubits, and the shared sub-circuit is the sub-circuit with the same topology among the plurality of quantum circuits to be compiled; the sub-circuit is all of the quantum circuits to be compiled or a portion of the quantum circuits to be compiled; Construct a new quantum circuit and establish a mapping relationship between the qubits of the new quantum circuit and the qubits of the multiple quantum circuits to be merged; the new quantum circuit is a quantum circuit framework in which the number of qubits has been determined and the qubits are set to a quantum state, but no quantum logic gate operations are inserted. Based on the mapping relationship of the qubits, the quantum logic gates of the largest shared sub-circuit are inserted into the new quantum circuit, and the quantum logic gates of the non-shared sub-circuit are inserted into the new quantum circuit according to the execution order of the multiple original quantum circuits, to obtain the new quantum circuit after merging. Based on the merged new quantum circuit, quantum operations are performed to obtain a quantum circuit that can be executed by a quantum processor.

2. The method according to claim 1, characterized in that, The process of determining whether the multiple quantum circuits to be compiled can perform a circuit merging operation includes: Based on the shared sub-circuit, it is determined whether the multiple quantum circuits to be compiled can be processed by circuit merging.

3. The method according to claim 1, characterized in that, The quantum manipulation process includes one or a combination of the following: Quantum circuit optimization processing and quantum circuit mapping processing.

4. The method according to claim 1, characterized in that, The multiple quantum circuits to be compiled are applied to a reactive service, which is a quantum computing operation executed by the server in response to a user's request in real time. The quantum operation processing based on the new quantum circuit after merging includes: In response to a client request, the merged new quantum circuit will be subjected to quantum operations.

5. The method according to claim 4, characterized in that, The method further includes: The multiple quantum circuits to be compiled are applied to non-responsive services, which are quantum computing operations preset by the quantum computing platform. The quantum operation processing based on the new quantum circuit after merging includes: In response to the quantum computing operation preset by the quantum computing platform, the merged new quantum circuit will be subjected to quantum operation processing.

6. A quantum circuit compilation device based on circuit merging, characterized in that, The device includes: The acquisition unit is used to acquire multiple quantum circuits to be compiled and to determine whether the multiple quantum circuits to be compiled can be processed by circuit merging. A response unit is configured to, in response to the plurality of quantum circuits to be compiled being able to perform a quantum circuit merging operation, acquire the plurality of quantum circuits to be merged, and determine the largest shared sub-circuit among the plurality of quantum circuits, wherein the largest shared sub-circuit is the shared sub-circuit occupying the most qubits, and the shared sub-circuit is a sub-circuit with the same topology among the plurality of quantum circuits to be compiled; the sub-circuit may be all or part of the quantum circuits to be compiled. Construct a new quantum circuit and establish a mapping relationship between the qubits of the new quantum circuit and the qubits of the multiple quantum circuits to be merged; the new quantum circuit is a quantum circuit framework in which the number of qubits has been determined and the qubits are set to a quantum state, but no quantum logic gate operations are inserted. Based on the mapping relationship of the qubits, the quantum logic gates of the largest shared sub-circuit are inserted into the new quantum circuit, and the quantum logic gates of the non-shared sub-circuit are inserted into the new quantum circuit according to the execution order of the multiple original quantum circuits, to obtain the new quantum circuit after merging. An execution unit is used to perform quantum operation processing based on the merged new quantum circuit to obtain a quantum circuit that can be executed by a quantum processor.

7. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-5.

9. A quantum computer operating system, characterized in that, The quantum computer operating system implements quantum circuit compilation based on circuit merging according to any one of claims 1-5.

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