Read-only memory array structure, read-only memory, read method of read-only memory and electronic equipment

Abstract

The invention relates to a read-only memory array structure, a read-only memory, a reading method of the read-only memory and electronic equipment. The read-only memory array structure comprises N * M memory units, wherein N and M are integers greater than or equal to 2; wherein the grid electrode of the NMOS transistor of at least one auxiliary storage unit in the N * M storage units is connected to the gating word line of the target storage unit in the N * M storage units, and the drain electrode of the NMOS transistor of at least one auxiliary storage unit is connected to the target word line of the target storage unit; wherein the auxiliary storage unit is a storage unit for storing data 1, and the target storage unit is a storage unit for storing data 0. According to the read-only memory array structure, design optimization is carried out on the read-only memory array structure, when the target memory unit is read, the NMOS transistor of the at least one auxiliary memory unit is started, the NMOS transistor of the at least one auxiliary memory unit and the NMOS transistor of the target memory unit form a parallel pull-down path, discharging is carried out on the target bit line together, and therefore the pull-down capacity is enhanced.

Description

Technical Field

[0001] This application belongs to the field of semiconductor memory technology, specifically relating to a read-only memory array structure, a read-only memory and its reading method, and an electronic device. Background Technology

[0002] Read-Only Memory (ROM), as a non-volatile memory, is widely used in critical storage scenarios such as embedded systems, device firmware, and boot code because its data is not lost after power failure. Traditional ROM permanently stores data 0 or 1 through the physical structure of the storage cells, and cannot be modified after manufacturing. Its basic storage cell typically contains an NMOS (N-channel Metal-Oxide-Semiconductor) transistor. The core read principle is as follows: the word line (WL) is connected to the gate of the NMOS transistor to select a specific storage cell; the bit line (BL) is pre-charged to a logic high level (such as the power supply voltage VDD, representing 1) before the read operation. When the word line is activated, if the drain of the NMOS transistor is connected to the bit line, the bit line discharges to ground through the conducting NMOS transistor, thereby pulling the level down to a logic low level (representing 0); if the drain is not connected to the bit line, the bit line remains high, thus reading 1.

[0003] As integrated circuit manufacturing processes continue to evolve towards smaller sizes (such as nanometer-level nodes), traditional ROM structures face challenges in read reliability, resulting in poor read reliability. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a read-only memory array structure, a read-only memory and its reading method, and an electronic device to improve the problem of insufficient pull-down capability of existing read-only memories, thereby enhancing the read reliability of read-only memories.

[0005] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a read-only memory array structure, comprising: N×M memory cells, where N and M are both integers greater than or equal to 2; wherein, the gate of the NMOS transistor of at least one auxiliary memory cell among the N×M memory cells is connected to the gating word line of the target memory cell among the N×M memory cells, and the drain of the NMOS transistor of the at least one auxiliary memory cell is connected to the target word line of the target memory cell; wherein, the auxiliary memory cell is a memory cell storing data 1, and the target memory cell is a memory cell storing data 0.

[0006] This application optimizes the design of the read-only memory array structure by utilizing idle memory cells (i.e., auxiliary memory cells) to enhance the pull-down capability of the target memory cell to the bit line. For example, an NMOS transistor (the cell storing data 1) that is not used to directly pull down the BL is connected to the target memory cell (the cell storing data 0) that needs to be pulled down in the vicinity via WL gating, forming a parallel pull-down path. This allows at least one NMOS transistor of the auxiliary memory cell to be enabled when reading the target memory cell, forming a parallel pull-down path with the NMOS transistor of the target memory cell, and jointly discharging the target bit line, thereby enhancing the pull-down capability.

[0007] In one possible implementation of the first aspect embodiment, at least one of the auxiliary storage units is located in the same row as the target storage unit.

[0008] In the above-described scheme of this application, the pull-down capability of the target memory cell to the bit line is enhanced by prioritizing the use of idle memory cells located in the same row as the target memory cell. Compared with cross-row optimization, this simplifies the design. Since memory cells in the same row are usually connected to the same word line, prioritizing the use of idle memory cells on the same word line only requires connecting the drain of the NMOS transistor of the idle memory cell to the target bit line, which is simpler and more efficient in circuit design and layout than cross-word line optimization.

[0009] In one possible implementation of the first aspect embodiment, at least one of the auxiliary storage units is located in the same column as the target storage unit.

[0010] In the above-mentioned solution of this application, the pull-down capability of the target storage cell to the bit line is enhanced by utilizing the idle storage cell located in the same column as the target storage cell. Compared with optimization that spans both rows and columns, this approach simplifies the design and provides more optimization options for enhancing the pull-down capability.

[0011] In one possible implementation of the first aspect embodiment, the at least one auxiliary storage unit includes a first auxiliary storage unit and a second auxiliary storage unit; the first auxiliary storage unit is located in the same row as the target storage unit; and the second auxiliary storage unit is located in the same column as the target storage unit.

[0012] In the above-mentioned scheme of this application, two optimization methods are combined (using left and right auxiliary methods and using WL up and down auxiliary methods) to form more drop-down paths, thereby further improving the drop-down capability of the alignment line.

[0013] In one possible implementation of the first aspect embodiment, the first auxiliary storage unit and / or the second auxiliary storage unit are adjacent units physically distributed around the target storage unit.

[0014] In the above-mentioned scheme of this application, the idle storage cell that is physically adjacent to the target storage cell is selected first to enhance the pull-down capability, which helps to simplify the design difficulty.

[0015] Secondly, embodiments of this application also provide a read-only memory, comprising: N×M memory cells, N word lines, and M bit lines, where N and M are both integers greater than or equal to 2; each of the N word lines is used to select a row of the memory cells; each of the M bit lines is used to read data from a column of the memory cells; wherein, the gate of the NMOS transistor of at least one auxiliary memory cell among the N×M memory cells is connected to the select word line of the target memory cell among the N×M memory cells, and the drain of the NMOS transistor of the at least one auxiliary memory cell is connected to the target word line of the target memory cell; wherein, the auxiliary memory cell is a memory cell storing data 1, and the target memory cell is a memory cell storing data 0.

[0016] In one possible implementation of the second aspect embodiment, at least one of the auxiliary storage units is located in the same row as the target storage unit.

[0017] In one possible implementation of the second aspect embodiment, at least one of the auxiliary storage units is located in the same column as the target storage unit.

[0018] In one possible implementation of the second aspect embodiment, the at least one auxiliary storage unit includes a first auxiliary storage unit and a second auxiliary storage unit; the first auxiliary storage unit is located in the same row as the target storage unit; and the second auxiliary storage unit is located in the same column as the target storage unit.

[0019] In one possible implementation of the second aspect embodiment, the first auxiliary storage unit and / or the second auxiliary storage unit are adjacent units physically distributed around the target storage unit.

[0020] Thirdly, embodiments of this application also provide an electronic device, including a read-only memory provided as in the second aspect embodiments and / or any possible implementation in conjunction with the second aspect embodiments.

[0021] Fourthly, embodiments of this application also provide a method for reading a read-only memory, comprising: activating a strobe word line to select a target memory cell; enabling an NMOS transistor of at least one auxiliary memory cell; wherein the auxiliary memory cell is a memory cell storing data 1, and the target memory cell is a memory cell storing data 0; and pulling down a target bit line of the target memory cell through a parallel path formed by the NMOS transistor of the target memory cell and the NMOS transistor of the at least one auxiliary memory cell to read the data stored in the target memory cell.

[0022] The technical effects of any of the implementation methods in the second to fourth aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0023] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0025] Figure 1 A schematic diagram of a primitive storage cell array structure provided in an embodiment of this application is shown.

[0026] Figure 2 To Figure 1 The diagram shows a modified version of the memory cell array structure.

[0027] Figure 3 To Figure 1 The diagram shows another structure of the memory cell array after circuit improvement.

[0028] Figure 4 This illustration shows a schematic diagram of another original storage cell array structure provided in an embodiment of this application.

[0029] Figure 5 To Figure 4 The diagram shows a modified version of the memory cell array structure.

[0030] Figure 6 To Figure 4The diagram shows another structure of the memory cell array after circuit improvement.

[0031] Figure 7 The diagram shows a flowchart of a read-only memory reading method provided in an embodiment of this application.

[0032] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0034] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0035] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0036] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0037] The inventors of this application have discovered that the core reason for the read reliability challenge of traditional ROM structures lies in the fact that, as the process size shrinks, the pull-down capability of NMOS transistors to bit lines is limited by process fluctuations such as channel resistance (the shrinking of transistor channel size leads to an increase in channel resistance) and contact resistance (the shrinking of interconnect contact hole size increases the contact resistance connecting the transistor and the metal interconnect). In addition, under deep submicron processes, the power supply voltage decreases, further weakening the driving capability of NMOS transistors, which may lead to insufficient pull-down speed or level recognition errors, affecting read reliability.

[0038] Given the problems existing in current read-only memory (ROM), such as the following: 1. Insufficient pull-down capability (i.e., pull-down current capability) of the NMOS transistors in the memory cell for the bit lines. Insufficient pull-down capability of the NMOS transistors for the bit lines may lead to insufficient pull-down speed or level recognition errors. Insufficient pull-down speed means that, under limited pull-down current, the time required for the bit line voltage to discharge from the pre-charge high level to below the logic "0" recognition threshold is prolonged. Within a fixed read timing window, the voltage may not drop to a valid low level in time, causing read timing violations or even failures. Level recognition errors mean that insufficient pull-down capability may cause the bit line voltage to be pulled only to an intermediate level or metastable level between logic "0" and logic "1," making it impossible to make a clear judgment on this ambiguous level, thus resulting in data read errors.

[0039] 2. Low utilization of memory cells. For example, memory cells not used for the pull-down bit line BL (i.e., memory cells storing "1") are simply idle structures and do not play an additional role. The NMOS transistors in these idle memory cells are not fully utilized, resulting in low chip area utilization.

[0040] 3. Poor process compatibility. For example, to enhance the pull-down capability of NMOS transistors to bit lines, existing technologies may require additional transistor size or adjustment of process parameters, but this will sacrifice circuit area or cost.

[0041] To address the aforementioned technical problems, this application proposes an innovative read-only memory array structure, a read-only memory and its reading method, and an electronic device. This application enhances the pull-down capability of the target memory cell to the bit line by utilizing idle memory cells (i.e., auxiliary memory cells). For example, an NMOS transistor (the cell storing data 1) not used for direct pull-down of the bit line (BL) is connected to a surrounding memory cell (the cell storing data 0) that needs to be pulled down via a WL gate, forming a parallel pull-down path, thereby significantly improving the pull-down drive capability. Through circuit design optimization, no process modifications are required, avoiding the impact of process fluctuations and improving read reliability.

[0042] The read-only memory array structure provided in this application includes N×M memory cells, where N and M are both integers greater than or equal to 2. In some possible implementations, N can be equal to M.

[0043] The gate of the NMOS transistor in at least one auxiliary memory cell among N×M memory cells is connected to the gate word line of the target memory cell among N×M memory cells, and the drain of the NMOS transistor in at least one auxiliary memory cell is connected to the target word line of the target memory cell. The auxiliary memory cell is a memory cell storing data 1, and the target memory cell is a memory cell storing data 0.

[0044] This application optimizes the design of the read-only memory array structure. When reading the target memory cell, at least one auxiliary memory cell's NMOS transistor is activated, forming a parallel pull-down path with the target memory cell's NMOS transistor to discharge the target bit line, thereby enhancing the pull-down capability. When the memory cell storing data 0 (with its NMOS transistor drain connected to BL) is selected by WL, it not only pulls down BL through its own NMOS transistor but also through the parallel pull-down of the adjacent idle memory cell (the cell storing data 1), forming a multi-path current drive. Using parallel pull-down paths reduces the overall conduction circuit, accelerates BL discharge, and ensures accurate "0" level recognition. Simultaneously, the idle memory cell is reused as a pull-down auxiliary cell, requiring no additional area overhead and providing a "double insurance," making the read-only memory less susceptible to process interference and improving yield.

[0045] The auxiliary storage unit can be one or more. Using multiple auxiliary storage units to form multiple pull-down paths in parallel with the target storage unit and jointly discharge the target bit line can further enhance the pull-down capability.

[0046] In one possible implementation, at least one auxiliary memory cell is located in the same row as the target memory cell. By prioritizing the use of idle memory cells in the same row as the target memory cell, the pull-down capability of the target memory cell to the bit line is enhanced. This simplifies the design compared to cross-row optimization. Since memory cells in the same row are usually connected to the same word line, prioritizing the use of idle memory cells on the same word line is simpler and more efficient in circuit design and layout than cross-word line optimization.

[0047] In one possible implementation, at least one auxiliary storage cell is located in the same column as the target storage cell. By utilizing an idle storage cell in the same column as the target storage cell, the pull-down capability of the target storage cell to the bit line is enhanced. Compared to optimization that spans both rows and columns, this simplifies the design and provides more optimization options for enhancing the pull-down capability.

[0048] In one possible implementation, the two optimizations for enhancing pull-down capabilities described above can be sampled simultaneously. For example, at least one auxiliary storage unit includes a first auxiliary storage unit and a second auxiliary storage unit, with the first auxiliary storage unit located in the same row as the target storage unit and the second auxiliary storage unit located in the same column as the target storage unit. In some possible ways, the number of first auxiliary storage units and / or first auxiliary storage units can be greater than one.

[0049] In some possible implementations, the first auxiliary storage unit and / or the second auxiliary storage unit are physically adjacent units distributed around the target storage unit. Preferentially selecting idle storage units physically adjacent to the target storage unit to enhance pull-down capability helps simplify the design.

[0050] To facilitate understanding, the following will be combined with... Figure 1 , Figure 2 , Figure 3 Please provide an explanation.

[0051] Figure 1 This is the original storage cell array structure. Figure 1 The thick black line in the diagram represents the programmable portion of the design, determining whether the drain of the NMOS transistor is connected to the bit line BL. Figure 1 The storage cell array structure shown in Table 1 stores the data.

[0052] Table 1

[0053] In the traditional structure, WL is fixedly connected to the gate of the NMOS transistor; however, in this application, whether WL is connected to the gate can be a programmable option during the design. If a memory cell storing data 1 (does not directly pull down BL) has its NMOS transistor gate programmed to be connected to the WL of other memory cells to assist in pulling down BL.

[0054] like Figure 2 As shown, Figure 2 The thick black line connecting the gate is the programmable part. It uses a WL (Write-Lock-Down) auxiliary method, utilizing the parallel pull-down of NMOS transistors in adjacent idle memory cells to enhance the pull-down capability of the target memory cell to the bit line. For example, for... Figure 1The WL[3]&BL[0] nodes in the optimized WL[2]&BL[0] nodes have their drains connected to BL[0] and their gates connected to WL[3]. When WL[3] is turned on, the pull-down capability of BL[0] is enhanced. That is, the pull-down of the WL[3]&BL[0] nodes uses the assistance of the WL[2]&BL[0] nodes. Similarly, the pull-down of the WL[2]&BL[1] nodes uses the assistance of the WL[3]&BL[1] nodes; the pull-down of the WL[1]&BL[2] nodes uses the assistance of the WL[2]&BL[2] nodes; and the pull-down of the WL[0]&BL[3] nodes uses the assistance of the WL[1]&BL[3] nodes.

[0055] Understandable, Figure 2 The structure shown is only an example. When using idle storage units (i.e., auxiliary storage units) to enhance the pull-down capability of the target storage unit to the bit line, there are other ways. For example, for the WL2]&BL[1] node, in addition to using the WL[3]&BL[1] node to assist, the WL[1]&BL[1] node can also be used to assist. Similarly, for the WL[1]&BL[2] node, in addition to using the WL[2]&BL[2] node to assist, the WL[0]&BL[2] node can also be used to assist. Therefore, it is not possible to use the WL[0]&BL[2] node to assist. Figure 2 The examples shown are to be understood as limitations of this application.

[0056] Besides using the WL up-down assist method, you can also use the left-right assist method, such as... Figure 3 As shown. For Figure 1 The WL[3]&BL[0] nodes shown are optimized so that the drain of their NMOS transistors is connected to BL[0]; similarly, for Figure 1 The WL[2]&BL[1] nodes shown are optimized so that the drain of their NMOS transistors is connected to BL[1]; similarly, for Figure 1 The WL[1] & BL[2] nodes shown are optimized so that the drain of their NMOS transistors is connected to BL[2]; similarly, for Figure 1 The WL[0]&BL[3] nodes shown are optimized so that the drain of the NMOS transistor is connected to BL[3] by optimizing the connection of the WL[0]&BL[2] nodes.

[0057] Understandable, Figure 3 The structure shown is only one example. There are other ways to enhance the pull-down capability of the target memory cell to the bit line by utilizing idle memory cells (i.e., auxiliary memory cells).

[0058] Understandably, not all cells storing data 0 (cell A) can have "parallel assistance," because this is related to the surrounding cells that actually store data 0 or 1. If all the surrounding cells of cell A store data 0, it means there are no available idle cells around cell A. Therefore, idle cells cannot be used to enhance the pull-down capability of cell A to the bit line. The pull-down capability of the target cell to the bit line can be enhanced by optimizing the connection method of the drain (or gate and drain) of the idle cells. When selecting idle cells, the optimal choice needs to be made based on the actual layout.

[0059] For example, such as Figure 4 As shown in Table 2, assuming the original storage cell array structure, the data stored therein is as shown in Table 2.

[0060] Table 2

[0061] exist Figure 4 In the memory cell array structure shown, there are no available idle memory cells around the memory cell connected to WL[3]. Therefore, idle memory cells cannot be used to enhance the pull-down capability of the memory cell connected to WL[3] to the bit line. As for the memory cell connected to WL[2], the idle memory cell connected to WL[1] can be used to assist it. The schematic diagram is as follows. Figure 5 As shown, for example, for Figure 4 The WL[2]&BL[0] nodes shown are optimized by connecting the WL[1]&BL[0] nodes so that the drain of the NMOS transistor is connected to BL[0] and the gate is connected to WL[2], so that when WL[2] is turned on, BL[0] is pulled down. The auxiliary principle of the other nodes is similar and will not be introduced again.

[0062] In some possible implementations, for Figure 4 The storage cell array structure shown can be modified by using some decoding order adjustment techniques to adjust the order of WL[2] and WL[1], thus achieving the following: Figure 6 The effect shown is that for the memory cell connected to WL[3], the idle memory cell connected to WL[1] can be used to assist it, and for the memory cell connected to WL[2], the idle memory cell connected to WL[0] can be used to assist it, thereby enhancing the pull-down capability of the bit line.

[0063] Based on the same inventive concept, this application also provides a read-only memory, including: N×M storage cells, N word lines, and M bit lines, where N and M are both integers greater than or equal to 2. Each word line is used to select a row of storage cells, and each bit line is used to read data from a column of storage cells.

[0064] The gate of the NMOS transistor of at least one auxiliary memory cell in the N×M memory cells is connected to the gate word line of the target memory cell in the N×M memory cells, and the drain of the NMOS transistor of at least one auxiliary memory cell is connected to the target word line of the target memory cell.

[0065] In this embodiment, at least one auxiliary storage unit is located in the same row as the target storage unit, or at least one auxiliary storage unit is located in the same column as the target storage unit. In some implementations, at least one auxiliary storage unit includes a first auxiliary storage unit and a second auxiliary storage unit; the first auxiliary storage unit is located in the same row as the target storage unit, and the second auxiliary storage unit is located in the same column as the target storage unit.

[0066] The N×M storage cells provided in the read-only memory embodiment have the same implementation principle and technical effects as those in the aforementioned read-only memory array structure embodiment. For the sake of brevity, any parts not mentioned in the read-only memory embodiment can be referred to the corresponding content in the aforementioned read-only memory array structure embodiment.

[0067] This application also provides a method for reading a read-only memory, which is described below in conjunction with... Figure 7 Explain it.

[0068] S1: Activate a strobe word line to select a target memory cell and enable the NMOS transistor of at least one auxiliary memory cell.

[0069] By optimizing the circuit structure of at least one auxiliary memory cell, the gate of the NMOS transistor in at least one auxiliary memory cell is connected to the gating word line of the target memory cell, and the drain of the NMOS transistor in at least one auxiliary memory cell is connected to the target word line of the target memory cell. When a gating word line is activated to select a target memory cell, the NMOS transistor in at least one auxiliary memory cell is simultaneously enabled.

[0070] S2: Pull down the target bit line of the target memory cell through the parallel path formed by the NMOS transistor of the target memory cell and the NMOS transistor of at least one auxiliary memory cell to read the data stored in the target memory cell.

[0071] By optimizing the circuit structure of at least one auxiliary memory cell to form a parallel pull-down path with the NMOS transistor of the target memory cell, when it is necessary to read the data stored in the target memory cell, the target bit line of the target memory cell can be pulled down through the parallel path formed by the NMOS transistor of the target memory cell and the NMOS transistor of at least one auxiliary memory cell to read the data stored in the target memory cell.

[0072] The method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned read-only memory embodiment. For the sake of brevity, any part not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned read-only memory embodiment.

[0073] This application also provides an electronic device, which includes the read-only memory described above. The electronic device provided in this application may include, but is not limited to, devices equipped with parallel processors such as mobile phones, tablets, personal computers (PCs), netbooks, personal digital assistants (PDAs), wearable electronic devices, and virtual reality devices.

[0074] In some possible implementations, in addition to read-only memory, the electronic device may also include read-write random access memory (RAM), and furthermore, such as Figure 8 As shown, electronic devices may also include transceivers, communication buses, and processors. The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, which include at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor executes the software functional modules or computer programs stored in the memory.

[0075] The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc., or the memory may include both read-only memory and read-write memory.

[0076] A processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit (ACCU), a Multimedia Application Processor (MAP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any conventional processor.

[0077] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0078] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A read-only memory array structure, characterized in that, include: There are N×M storage units, where N and M are both integers greater than or equal to 2; Wherein, the gate of the NMOS transistor of at least one auxiliary memory cell among the N×M memory cells is connected to the gating word line of the target memory cell among the N×M memory cells, and the drain of the NMOS transistor of the at least one auxiliary memory cell is connected to the target word line of the target memory cell. The auxiliary storage unit is a storage unit for storing data 1, and the target storage unit is a storage unit for storing data 0.

2. The read-only memory array structure according to claim 1, characterized in that, At least one of the auxiliary storage units is located in the same row as the target storage unit.

3. The read-only memory array structure according to claim 1, characterized in that, At least one of the auxiliary storage units is located in the same column as the target storage unit.

4. The read-only memory array structure according to claim 1, characterized in that, The at least one auxiliary storage unit includes a first auxiliary storage unit and a second auxiliary storage unit; The first auxiliary storage unit and the target storage unit are located in the same row; The second auxiliary storage unit is located in the same column as the target storage unit.

5. The read-only memory array structure according to claim 4, characterized in that, The first auxiliary storage unit and / or the second auxiliary storage unit are adjacent units physically distributed around the target storage unit.

6. A read-only memory, characterized in that, include: There are N×M storage units, where N and M are both integers greater than or equal to 2; N word lines, each word line is used to select a row of the memory cells; M bit lines, each bit line is used to read data from one column of the memory cells; Wherein, the gate of the NMOS transistor of at least one auxiliary memory cell among the N×M memory cells is connected to the gating word line of the target memory cell among the N×M memory cells, and the drain of the NMOS transistor of the at least one auxiliary memory cell is connected to the target word line of the target memory cell. The auxiliary storage unit is a storage unit for storing data 1, and the target storage unit is a storage unit for storing data 0.

7. The read-only memory according to claim 6, characterized in that, At least one of the auxiliary storage units is located in the same row as the target storage unit.

8. The read-only memory according to claim 6, characterized in that, At least one of the auxiliary storage units is located in the same column as the target storage unit.

9. The read-only memory according to claim 6, characterized in that, The at least one auxiliary storage unit includes a first auxiliary storage unit and a second auxiliary storage unit; the first auxiliary storage unit is located in the same row as the target storage unit; the second auxiliary storage unit is located in the same column as the target storage unit.

10. The read-only memory according to claim 9, characterized in that, The first auxiliary storage unit and / or the second auxiliary storage unit are adjacent units physically distributed around the target storage unit.

11. An electronic device, characterized in that, Includes the read-only memory as described in any one of claims 6-10.

12. A method for reading a read-only memory, characterized in that, include: Activate a strobe word line to select a target memory cell and enable the NMOS transistor of at least one auxiliary memory cell; The auxiliary storage unit is a storage unit for storing data 1, and the target storage unit is a storage unit for storing data 0; The target bit line of the target memory cell is pulled down through a parallel path formed by the NMOS transistor of the target memory cell and the NMOS transistor of at least one auxiliary memory cell, so as to read the data stored in the target memory cell.

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