Semiconductor memory device

Abstract

A semiconductor memory device includes a bit line, a memory cell array, a plate electrode structure, a bit line shielding structure, and a conductive path. The memory cell array includes memory cells connected to bit lines. The plurality of memory cells are arranged in a first direction and a second direction parallel to a surface of the semiconductor substrate. Each memory cell includes a cell transistor and a cell capacitor arranged in a third direction perpendicular to the surface of the semiconductor substrate. The plate electrode structure forms a common electrode including a cell capacitor in the plurality of memory cells. The bit line shielding structure is disposed between the plurality of bit lines to block electrical interference between the plurality of bit lines. The conductive path electrically connects the plate electrode structure and the bit line shield structure.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0109813, filed on August 16, 2024, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor memory devices. Background Technology

[0003] The electronics market has recently seen a rapid increase in demand for portable devices, leading to the miniaturization and weight reduction of electronic components, such as semiconductor memory devices installed in portable devices. To achieve miniaturization and lighter weight of semiconductor memory devices, the individual dimensions of the mounting components are reduced, but electrical characteristics can degrade during the manufacturing process. Summary of the Invention

[0004] In a first aspect, a semiconductor memory device includes multiple bit lines, a memory cell array, a plate electrode structure, a bit line shielding structure, and a capacitive connection conductive path. The multiple bit lines are arranged in a first direction parallel to the surface of a semiconductor substrate and extend in a second direction parallel to the surface of the semiconductor substrate and perpendicular to the first direction. The memory cell array includes a plurality of memory cells connected to the multiple bit lines. The plurality of memory cells are arranged in the first and second directions. Each memory cell includes a cell transistor and a cell capacitor arranged in a third direction perpendicular to the surface of the semiconductor substrate. The plate electrode structure forms a common electrode for the cell capacitors included in the plurality of memory cells. The bit line shielding structure is disposed between the multiple bit lines to block electrical interference between the multiple bit lines. The capacitive connection conductive path connects the plate electrode structure and the bit line shielding structure.

[0005] In a second general aspect, a semiconductor memory device includes: a plurality of bit lines; a memory cell array including a plurality of memory cells connected to the plurality of bit lines, each memory cell including a cell transistor and a cell capacitor; a plate electrode structure configured to provide a plate voltage to the plurality of memory cells; a bit line shielding structure disposed between the plurality of bit lines to block electrical interference between the plurality of bit lines; and a capacitive connection conductive path connecting the plate electrode structure and the bit line shielding structure.

[0006] In a third aspect, a semiconductor memory device includes: a plurality of bit lines arranged in a first direction parallel to the surface of a semiconductor substrate and extending in a second direction parallel to the surface of the semiconductor substrate and perpendicular to the first direction; a memory cell array including a plurality of memory cells connected to the plurality of bit lines, the plurality of memory cells being arranged in the first and second directions, each memory cell including a vertical channel transistor with a channel extending in a third direction and a cell capacitor disposed above the vertical channel transistor in a third direction; a plate electrode structure forming a common electrode of the cell capacitors included in the plurality of memory cells; a bit line shielding structure disposed between the plurality of bit lines to block electrical interference between the plurality of bit lines; and a capacitive connection conductive path connecting the plate electrode structure and the bit line shielding structure. The semiconductor memory device is divided into a memory core region having the memory cell array formed and a peripheral circuit region disposed adjacent to the memory core region in the first or second direction. The capacitive connection conductive path includes a peripheral connection conductive path formed in the peripheral circuit region and a core connection conductive path formed in the core circuit region.

[0007] In some embodiments, semiconductor memory devices and electronic devices including semiconductor memory devices may have enhanced electrical characteristics compared to conventional semiconductor memories and electronic devices. For example, the electrical performance of a semiconductor memory device can be improved by using capacitive connection conductive paths to connect the plate electrode structure and the bit line shielding structure, thereby increasing the capacitance of the plate electrode structure and stabilizing the voltage of the capacitor electrodes.

[0008] Furthermore, semiconductor memory devices can further improve their electrical performance by using capacitive connection conductive path connecting plate electrode structures and bit line shielding structures to reduce electrical interference between bit lines. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating an example of a semiconductor memory device.

[0010] Figure 2 , Figure 3 , Figure 4A and Figure 4B This is a diagram illustrating an example of a conductive path connected by a capacitor in a semiconductor memory device.

[0011] Figure 5 This is a block diagram illustrating an example of a semiconductor memory device.

[0012] Figure 6 This is a diagram illustrating an example of a memory bank array included in a semiconductor memory device.

[0013] Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a diagram illustrating an example of a semiconductor memory device including a vertical channel transistor.

[0014] Figure 11 and Figure 12 This is a diagram illustrating an example of a bit line shielding structure included in a semiconductor memory device.

[0015] Figure 13 and Figure 14 This is a diagram illustrating another example of a bit line shielding structure included in a semiconductor memory device.

[0016] Figure 15 This is a perspective view of an example of the memory core circuitry included in a semiconductor memory device.

[0017] Figure 16 It is shown that it includes Figure 15 A diagram illustrating an example layout of the sub-peripheral circuitry within the core circuitry of a memory.

[0018] Figure 17 It is shown that it includes Figure 15 A diagram illustrating an example of the arrangement of bit lines in the core circuitry of a memory.

[0019] Figure 18 This is a diagram illustrating an example of a conductive path connected by a capacitor in a semiconductor memory device.

[0020] Figure 19 This is a diagram illustrating an example of a stacked memory device.

[0021] Figure 20 This is a diagram illustrating an example structure of a semiconductor package including a semiconductor memory device.

[0022] Figure 21 This is a block diagram illustrating an example of a mobile system including a semiconductor memory device.

[0023] In the accompanying drawings, the same reference numerals always denote the same elements. Repeated descriptions may be omitted. Detailed Implementation

[0024] In the following text, two directions parallel to and intersecting each other on the top surface of the semiconductor substrate are defined as the first direction D1 and the second direction D2, respectively, and a direction substantially perpendicular to the top surface of the semiconductor substrate is defined as the third direction D3. For example, the first direction D1 and the second direction D2 may intersect each other substantially perpendicularly. The first direction D1 may be referred to as the row direction or the first horizontal direction, the second direction D2 may be referred to as the column direction or the second horizontal direction, and the third direction D3 may be referred to as the vertical direction. In the accompanying drawings, the direction indicated by the arrow and its opposite direction are described as the same direction (same direction). The aforementioned definitions of directions are the same in all subsequent drawings.

[0025] Figure 1 This is a diagram illustrating an example of a semiconductor memory device.

[0026] Reference Figure 1 The semiconductor memory device 1000 includes multiple bit lines, a memory cell array (MCA), a plate electrode structure (PEST), a bit line shielding structure (BSST), and a capacitor connection conductive path (PH). Figure 1 The components shown are for illustrative purposes, and for clarity, components such as bit lines have been omitted. See below for reference. Figures 5 to 10 A more detailed description of the construction of a semiconductor memory device.

[0027] As will be described below, multiple bit lines may be arranged in a first direction D1 parallel to the surface of the semiconductor substrate and extend in a second direction D2 parallel to the surface of the semiconductor substrate and perpendicular to the first direction D1.

[0028] As described below, a memory cell array (MCA) may include multiple memory cells. The memory cells may be connected to multiple bit lines and arranged in a first direction D1 and a second direction D2. In this disclosure, unless otherwise indicated, the phrase "connection" is understood to mean "electrical connection." (Referencing...) Figure 6 Further described, each memory cell can be a dynamic random access memory (DRAM) cell including a cell transistor and a cell capacitor. In the example, see below. Figures 7 to 10 As described, the unit transistor can be a vertical channel transistor (VCT) having a channel extending on the third direction D3, and the unit capacitor can be disposed on the third direction D3 above the vertical channel transistor.

[0029] The plate electrode structure PEST can form a common electrode for cell capacitors included in multiple memory cells. The plate electrode structure PEST can correspond to a reference. Figures 7 to 10 The second capacitor electrode described, or may be publicly connected to the second capacitor electrode.

[0030] Bit line shielding structures (BSSTs) can be installed between multiple bit lines to block electrical interference. See below for reference. Figures 11 to 14 A further example of the bit-line shielded structure BSST is described.

[0031] The capacitive connection conductive path PH can connect the plate electrode structure PEST and the bit line shielding structure BSST. The capacitive connection conductive path PH may include conductive elements (such as pads, vertical contacts, etc.). In other words, the plate electrode structure PEST and the bit line shielding structure BSST can be electrically connected via the capacitive connection conductive path PH.

[0032] As the number of memory cells included in a semiconductor memory device increases, the fluctuation of charge stored in the cell capacitors increases during sensing operations. This increases the voltage fluctuation across the plate electrode structure PEST, across which the plate voltage VP is applied. This voltage fluctuation affects the voltage generated on the bit lines during sensing operations and can potentially increase sensing errors. See below for a comparison with conventional structures. Figures 7 to 10 In the described VCT structure, capacitors are formed above the memory cells, and bit lines are formed below the memory cells, thus eliminating the capacitance facing the plate electrode structure (PEST) and the bit lines. As a result, the capacitance of the PEST becomes smaller, which degrades the electrical characteristics of the memory cells. Furthermore, as the density of semiconductor memory devices increases, the spacing between bit lines decreases, which increases electrical interference between bit lines and degrades the electrical characteristics of the semiconductor memory device.

[0033] In the semiconductor memory device 1000, by using a capacitively connected conductive path PH to connect the plate electrode structure PEST and the bit line shielding structure BSST, the capacitance of the plate electrode structure PEST can be efficiently increased, and the voltage of the capacitor electrodes can be stabilized, thereby improving the electrical performance of the semiconductor memory device 1000. Therefore, the conductive path is called a "capacitively connected conductive path".

[0034] Furthermore, the semiconductor memory device 1000 can efficiently reduce electrical interference between bit lines by using the capacitively connected conductive path PH connection plate electrode structure PEST and the bit line shielding structure BSST, thereby further improving the electrical performance of the semiconductor memory device 1000.

[0035] In the example, such as Figure 1As shown, the semiconductor memory device 1000 may have a peripheral upper cell (CoP) structure in which a core semiconductor die CSD and a peripheral semiconductor die PSD are stacked on a third-direction D3 by a bonding method. A pad PD2 formed on the bottom surface of the core semiconductor die CSD and a pad PD3 formed on the top surface of the peripheral semiconductor die PSD are bonded to each other, allowing the core semiconductor die CSD and the peripheral semiconductor die PSD to be interconnected. The bottom surface of the core semiconductor die CSD and the top surface of the peripheral semiconductor die PSD correspond to the bonding surface SBN.

[0036] Test pad PD1 can be formed on the top surface STP of the core semiconductor die CSD. Test pad PD1 can be used during the test process of semiconductor memory device 1000 and can be disabled after semiconductor memory device 1000 leaves the factory.

[0037] I / O pads PD4 can be formed on the bottom surface SBT of the peripheral semiconductor die PSD. I / O pads PD4 can be used for communication with external devices, such as memory controllers.

[0038] Furthermore, the semiconductor memory device 1000 may be divided into a memory core region MCR and a peripheral circuit region PCR adjacent to the memory core region MCR in a first direction D1 or a second direction D2.

[0039] Within the memory core region (MCR) of the core semiconductor die (CSD), a memory cell array (MCA), a plate electrode structure (PEST), and a bit line shielding structure (BSST) can be formed. Furthermore, within the memory core region (MCR) of the peripheral semiconductor die (PSD), a core control circuit (CCC) can be formed. The plate electrode structure (PEST) and the bit line shielding structure (BSST) can be considered as included within the memory cell array (MCA). The memory cell array (MCA) and the core control circuit (CCC) can be referred to as the memory core circuit. (Refer to...) Figures 15 to 18 Further description of the memory core circuitry.

[0040] In the peripheral circuit region PCR of the peripheral semiconductor die PSD, a device peripheral circuit (such as a voltage generator VG) may be formed. The voltage generator VG can generate a plate voltage VP applied to the plate electrode structure PEST based on the external voltage EVDD received via the input-output pad PD4.

[0041] In some examples, the capacitive connection conductive path PH may include the peripheral connection conductive path PPH formed in the peripheral circuit region PCR. See below for reference. Figures 2 to 4B Examples of peripheral connection conductive paths PPH are described below. In some examples, the capacitive connection conductive path PH may include the core connection conductive path CPH formed in the memory core region MCR. See below for reference. Figure 18 Example describing the core connection conductive path CPH. In some examples, the capacitive connection conductive path PH may include both the peripheral connection conductive path PPH and the core connection conductive path CPH.

[0042] Figure 2 , Figure 3 , Figure 4A and Figure 4B This is a diagram illustrating an example of a conductive path for a capacitor connection included in a semiconductor memory device. Because... Figure 2 , Figure 3 , Figure 4A and Figure 4B The semiconductor memory devices 1001, 1002, 1003, and 1004 are similar to Figure 1 The semiconductor memory device 1000 is described below, therefore the capacitor connection conductive path PH will be described below, and redundant descriptions will be omitted.

[0043] Reference Figure 2 The peripheral connection conductive path PPH1 of the semiconductor memory device 1001 may include a first voltage-applying conductive line LD1, a second voltage-applying conductive line LD2, and a vertical contact VC1. In this specification, the voltage-applying conductive line is a conductive line electrically connected to a voltage source (e.g., a voltage generator VG).

[0044] The first voltage-applying conductive line LD1 can be connected to the bit line shielding structure BSST and can extend in either the first direction D1 or the second direction D2. The second voltage-applying conductive line LD2 can be connected to the plate electrode structure PEST and can extend in either the first direction D1 or the second direction D2.

[0045] Vertical contact VC1 can extend on third-direction D3 to connect the first voltage-applied conductive line LD1 and the second voltage-applied conductive line LD2. The plate electrode structure PEST and the bit-line shielding structure BSST can be connected via the peripheral connection conductive path PPH1.

[0046] The plate voltage VP generated by the voltage generator VG can be applied to the peripheral connection conductive path PPH1 via the peripheral pad PD31, the core pad PD21 and the vertical contact VC2. As a result, the common plate voltage VP is applied to the plate electrode structure PEST and the bit line shield structure BSST.

[0047] Reference Figure 3 The peripheral connection conductive path PPH2 of the semiconductor memory device 1002 may include a first voltage application conductive line LD1, a second voltage application conductive line LD2, a first test pad PD11, a second test pad PD12, a first vertical contact VC1, a second vertical contact VC2, and a pad connection conductive line PCP1.

[0048] A first voltage-applying conductive line LD1 can be connected to a bit-line shielding structure BSST and can extend in either a first direction D1 or a second direction D2. A second voltage-applying conductive line LD2 can be connected to a plate electrode structure PEST and can extend in either a first direction D1 or a second direction D2. A first test pad PD11 and a second test pad PD12 can be formed on the top surface STP of the core semiconductor die CSD.

[0049] A first vertical contact VC1 may extend in the third direction D3 to connect a first voltage-applying conductive line LD1 and a first test pad PD11. A second vertical contact VC2 may extend in the third direction D3 to connect a second voltage-applying conductive line LD2 and a second test pad PD12. A pad-connecting conductive line PCP1 may be formed on the top surface of the core semiconductor die CSD and may connect the first test pad PD11 and the second test pad PD12.

[0050] The plate voltage VP generated by the voltage generator VG can be applied to the peripheral connection conductive path PPH2 via the peripheral pad PD31, the core pad PD21, and the vertical contact VC3. As a result, the plate voltage VP can be commonly applied to the plate electrode structure PEST and the bit line shield structure BSST.

[0051] Reference Figure 4A The peripheral connection conductive path PPH3 of the semiconductor memory device 1003 may include a first voltage-applied conductive line LD1, a second voltage-applied conductive line LD2, a first core pad PD21, a second core pad PD22, a first vertical contact VC1, a second vertical contact VC2, a first peripheral pad PD31, a second peripheral pad PD32, a horizontal conductive line CCP, a third vertical contact VC3, and a fourth vertical contact VC4.

[0052] The first voltage-applied conductive line LD1 can be connected to the bit line shielding structure BSST and can extend in either the first direction D1 or the second direction D2. The second voltage-applied conductive line LD2 can be connected to the plate electrode structure PEST and can extend in either the first direction D1 or the second direction D2. The first core pad PD21 and the second core pad PD22 can be formed on the bottom surface of the core semiconductor die CSD (i.e., formed on the bonding surface SBN).

[0053] A first vertical contact VC1 may extend in the third direction D3 to connect a first voltage-applying conductive line LD1 and a first core pad PD21. A second vertical contact VC2 may extend in the third direction D3 to connect a second voltage-applying conductive line LD2 and a second core pad PD22.

[0054] The first peripheral pad PD31 and the second peripheral pad PD32 can be formed on the top surface (i.e., the bonding surface SBN) of the peripheral semiconductor die PSD, which is bonded to the lower surface of the core semiconductor die CSD, and can be bonded to the first core pad PD21 and the second core pad PD22, respectively. A horizontal conductive line CCP can be formed on the peripheral semiconductor die PSD and can extend in a first direction D1 or a second direction D2.

[0055] The third vertical contact VC3 may extend on the third direction D3 to connect the first peripheral pad PD31 and the horizontal conductive line CCP. The fourth vertical contact VC4 may extend on the third direction D3 to connect the second peripheral pad PD32 and the horizontal conductive line CCP.

[0056] The plate voltage VP generated by the voltage generator VG can be applied to the horizontal conductive line CCP, which is formed on the peripheral semiconductor die PSD and forms part of the peripheral interconnect conductive path PPH3. As a result, the common plate voltage VP can be applied to the plate electrode structure PEST and the bit line shielding structure BSST.

[0057] Reference Figure 4B The peripheral connection conductive path PPH4 of the semiconductor memory device 1004 may include a first voltage application conductive line LD1, a second voltage application conductive line LD2, a first core pad PD21, a second core pad PD22, a first vertical contact VC1, a second vertical contact VC2, and a pad connection conductive line PCP2.

[0058] A first voltage-applied conductive line LD1 may be connected to a bit-line shielding structure BSST and may extend in a first direction D1 or a second direction D2. A second voltage-applied conductive line LD2 may be connected to a plate electrode structure PEST and may extend in a first direction D1 or a second direction D2. A first core pad PD21 and a second core pad PD22 may be formed on the bottom surface of the core semiconductor die CSD (e.g., formed on the bonding surface SBN).

[0059] A first vertical contact VC1 may extend in the third direction D3 to connect a first voltage-applying conductive line LD1 and a first core pad PD21. A second vertical contact VC2 may extend in the third direction D3 to connect a second voltage-applying conductive line LD2 and a second core pad PD22.

[0060] The pad connection conductor PCP3 can be formed on the bottom surface of the core semiconductor die CSD and can connect the first core pad PD21 and the second core pad PD22. In the example, the first core pad PD21, the second core pad PD22 and the pad connection conductor PCP2 can be integrally formed into a single pad.

[0061] The plate voltage VP generated by the voltage generator VG can be applied to the peripheral connection conductive path PPH4 via peripheral pads PD31 and PD32 formed on the peripheral semiconductor die PSD. As a result, the common plate voltage VP can be applied to the plate electrode structure PEST and the bit line shielding structure BSST.

[0062] Figure 5 This is a block diagram illustrating an example of a semiconductor memory device.

[0063] Reference Figure 5 The memory device 1400 includes control logic 1410, address register 1420, memory bank control logic 1430, row address multiplexer (RA MUX) 1440, column address latch (CA latch) 1450, row decoder 1460, column decoder 1470, memory cell array (MCA) 1480, core control circuit (CCC) 1485, input-output (I / O) gating circuit (I / O gate) 1490, data input-output (I / O) buffer 1495, and refresh counter 1445. Components other than the memory cell array 1480 and the core control circuit 1485 may be referred to as "device peripheral circuitry".

[0064] The memory cell array 1480 may include multiple memory bank arrays 1480a to 1480h. The row decoder 1460 may include multiple memory bank row decoders 1460a to 1460h respectively incorporated into the memory bank arrays 1480a to 1480h. The column decoder 1470 may include multiple memory bank column decoders 1470a to 1470h respectively incorporated into the memory bank arrays 1480a to 1480h, and the core control circuitry 1485 may include multiple memory bank core control circuits 1485a to 1485h respectively incorporated into the memory bank arrays 1480a to 1480h. The multiple memory bank arrays 1480a to 1480h and the multiple memory bank core control circuits 1485a to 1485h may be stacked vertically to form a CoP structure.

[0065] Address register 1420 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the memory controller. Address register 1420 can provide the received bank address BANK_ADDR to the bank control logic 1430, and can provide the received row address ROW_ADDR to the row address multiplexer 1440. In addition, address register 1420 can provide the received column address COL_ADDR to the column address latch 1450.

[0066] The memory bank control logic 1430 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. The memory bank control signal may include a memory bank enable signal BEN, which is used to activate the selected memory bank corresponding to the memory bank address BANK_ADDR. The memory bank row decoders 1460a to 1460h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and the memory bank column decoders 1470a to 1470h corresponding to the memory bank address BANK_ADDR can also be activated in response to the memory bank control signal.

[0067] The row address multiplexer 1440 can receive the row address ROW_ADDR from the address register 1420 and the refresh row address REF_ADDR from the refresh counter 1445. The row address multiplexer 1440 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 1440 can be applied to the memory bank row decoders 1460a to 1460h.

[0068] The activated bank row decoder in bank decoders 1460a to 1460h can decode the row address RA output from the row address multiplexer 1440 and can activate the word line corresponding to the row address RA. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address RA.

[0069] Column address latch 1450 can receive column address COL_ADDR from address register 1420 and can temporarily store the received column address COL_ADDR. In some examples, in burst mode, column address latch 1450 can generate a column address incremented from the received column address COL_ADDR. Column address latch 1450 can apply the temporarily stored or generated column address to memory bank column decoders 1470a to 1470h.

[0070] The active memory column decoder in memory column decoders 1470a to 1470h can decode the column address COL_ADDR output from the column address latch 1450 and can control the input-output (I / O) gate circuit 1490 to output data corresponding to the column address COL_ADDR.

[0071] I / O gating circuit 1490 may include circuitry for gating input-output data. I / O gating circuit 1490 may also include a read data latch and a write driver. The read data latch is used to store data output from memory arrays 1480a to 1480h, and the write driver is used to write data to memory arrays 1480a to 1480h.

[0072] Data to be read from one of the memory arrays 1480a to 1480h can be sensed by a CCC 1485 associated with the memory array from which data is to be read, and can be stored in a read data latch. The data stored in the read data latch can be provided to the memory controller via a data I / O buffer 1495. Data DQ to be written to one of the memory arrays 1480a to 1480h can be provided from the memory controller to the data I / O buffer 1495. A write driver can write data DQ to one of the memory arrays 1480a to 1480h.

[0073] Control logic 1410 controls the operation of memory device 1400. For example, control logic 1410 generates control signals for memory device 1400 to perform write or read operations. Control logic 1410 may include command decoder 1411 and mode register set (or mode register) 1412. The command decoder decodes commands (CMD) received from the memory controller, and mode register set 1412 sets the operating mode of memory device 1400.

[0074] For example, the command decoder 1411 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc.

[0075] Figure 6 This is a diagram illustrating an example of a memory bank array included in a semiconductor memory device.

[0076] Reference Figure 6 The memory bank array includes multiple word lines WL1 to WL2m (where m is a binary integer), multiple bit lines BL1 to BL2n (where n is a binary integer), and multiple memory cells MC located at the intersection points between the word lines WL1 to WL2m and the bit lines BL1 to BL2n. For example... Figure 6As shown, each memory cell MC may have a DRAM cell structure. The memory cell MC may include a cell capacitor connected to the board voltage VP and a cell transistor connected between each bit line and the cell capacitor, with the gate electrode of the cell transistor connected to each word line. The word lines to which the memory cell MC is connected may be defined as rows of the memory bank array, and the bit lines to which the memory cell MC is connected may be defined as columns of the memory bank array.

[0077] Semiconductor memory devices can be as referenced Figure 5 and Figure 6 The DRAM device described is not limited to any particular type of memory.

[0078] Figures 7 to 10 This is a diagram illustrating an example of a semiconductor memory device including vertical-channel transistors. For example, Figure 7 It is a perspective view. Figure 8 It is a floor plan, and Figure 9 and Figure 10 It is a sectional view. Figure 9 Including along respectively Figure 8 A sectional view taken from lines A-A', B-B', and C-C'. Figure 10 Including along respectively Figure 8 A sectional view taken along lines D-D' and E-E'. For simplicity, Figure 7 Some components are not shown.

[0079] Reference Figures 7 to 10 The semiconductor device includes a bit line structure, a first shielding pattern 400, a semiconductor pattern 137, a first gate electrode 215 and a second gate electrode 305, a first gate insulating pattern 207 and a second gate insulating pattern 297, a contact plug structure, and a capacitor 700 disposed on a second substrate 500.

[0080] The semiconductor device may also include a first adhesive layer 520 and a second adhesive layer 510, a third spacer 395, a first insulating intermediate layer pattern 185, a second insulating intermediate layer 310 and a third insulating intermediate layer 560, a third insulating layer 270, fourth to seventh insulating patterns 330, 410, 540 and 545, a first etch stop layer 550 and a second etch stop layer 620, a capping layer 570, and a first support layer 640 and a second support layer 660.

[0081] The second substrate 500 may include, for example, a semiconductor material, an insulating material, or a conductive material.

[0082] The second adhesive layer 510 and the first adhesive layer 520 may be stacked on the third-direction D3 and may include an insulating material (e.g., silicon carbonitride).

[0083] The bit line structure may include a second conductive pattern 360, a blocking pattern 350, and a first conductive pattern 340 sequentially stacked on a third-direction D3.

[0084] In the example, the first conductive pattern 340 may include polysilicon doped with n-type or p-type impurities, the blocking pattern 350 may include metal nitrides (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), and the second conductive pattern 360 may include metals (e.g., tungsten, titanium, tantalum, etc.).

[0085] In some embodiments, a plurality of bit line structures may be spaced apart from each other in a first direction D1, and each of the plurality of bit line structures may extend along a second direction D2 and contact the upper surface of the first adhesive layer 520. However, the examples of this disclosure are not limited thereto. In some examples, an eighth insulating pattern 370 may be further provided between the bit line structure (e.g., the second conductive pattern 360) and the first adhesive layer 520.

[0086] The first shielding pattern 400 may extend along the second direction D2 between adjacent bit line structures in the first direction D1 of the bit line structure. In some embodiments, the upper surface and sidewalls of the first shielding pattern 400 may be covered by a third spacer 395 extending in the second direction D2, and the lower surface of the first shielding pattern 400 may be covered by a fifth insulating pattern 410 extending in the second direction D2. Because the first shielding pattern 400 is formed, interference and parasitic capacitance between bit line structures can be reduced, and therefore, resistive-capacitive (RC) delay can be reduced, which can increase the operating speed of the semiconductor device.

[0087] The sidewalls of the fifth insulating pattern 410 may be covered by the third spacer 395. The lower surfaces of the third spacer 395 and the fifth insulating pattern 410 may contact the upper surface of the first adhesive layer 520.

[0088] In some embodiments, the third spacer 395 may contact the sidewall of the bit line structure. The upper and lower surfaces of the third spacer 395 may be substantially coplanar with the upper and lower surfaces of the bit line structure, respectively.

[0089] The first shielding pattern 400 may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and the third spacer 395 and the fifth insulating pattern 410 may include oxides (e.g., silicon oxide).

[0090] In some embodiments, a plurality of semiconductor patterns 137 may be spaced apart from each other along a second direction D2 in each of the bit line structures, and each of the plurality of semiconductor patterns 137 may contact a first conductive pattern 340 included in each of the bit line structures. Since the bit line structures are spaced apart from each other in a first direction D1, the plurality of semiconductor patterns 137 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0091] In the example, semiconductor pattern 137 may comprise a single-crystal semiconductor material (e.g., single-crystal silicon, single-crystal germanium, etc.) or a polycrystalline semiconductor material (e.g., polycrystalline silicon, polycrystalline germanium, etc.) and may serve as a channel for a semiconductor device. However, unlike the central portion of semiconductor pattern 137 that serves as a channel, the upper and lower portions of semiconductor pattern 137 may be doped with n-type or p-type impurities and may serve as source / drain regions for a semiconductor device. Therefore, current can flow in the vertical direction (i.e., in semiconductor pattern 137 along the third direction D3), and thus, the semiconductor device may comprise a vertical channel transistor (VCT) with a vertical channel.

[0092] Optionally, the semiconductor pattern 137 may comprise a single-crystal semiconductor material or a polycrystalline semiconductor material doped with n-type or p-type impurities. In this case, the impurity concentration in the central portion of the semiconductor pattern 137 used as a channel may be lower than the impurity concentration in the upper and lower portions of the semiconductor pattern 137 used as source / drain regions, respectively.

[0093] In the example, p-type impurities can be doped into the center of semiconductor pattern 137 at a relatively low concentration, and n-type impurities can be doped into the upper and lower parts of semiconductor pattern 137 at relatively high concentrations, respectively.

[0094] The first insulating interlayer pattern 185 may be formed between adjacent semiconductor patterns in the first direction D1 of the semiconductor pattern 137. Therefore, the semiconductor pattern 137 and the first insulating interlayer pattern 185 may be alternately and repeatedly arranged in the first direction D1.

[0095] The lower surface of the first insulating interlayer pattern 185 may contact the upper surface of the third spacer 395. In some embodiments, the width of the first insulating interlayer pattern 185 in the second direction D2 may be greater than the width of the semiconductor pattern 137 in the second direction D2. The first insulating interlayer pattern 185 may include an oxide (e.g., silicon oxide).

[0096] In some embodiments, a slit 181 or a gap may be formed in the center of the first insulating intermediate layer pattern 185 in the first direction D1.

[0097] The second gate electrode 305 may extend along the first direction D1 on one side of the semiconductor pattern 137 and the first insulating intermediate layer pattern 185 in the second direction D2, and the first gate electrode 215 may extend along the first direction D1 on the other side of the semiconductor pattern 137 and the first insulating intermediate layer pattern 185 in the second direction D2.

[0098] For example, each of the semiconductor patterns 137 may include a first sidewall and a second sidewall disposed opposite to each other in the second direction D2, each of the first insulating intermediate layer patterns 185 may include a third sidewall and a fourth sidewall disposed opposite to each other in the second direction D2, the second gate electrode 305 may be disposed adjacent to the first sidewall of the semiconductor pattern 137 and the third sidewall of the first insulating intermediate layer pattern 185, and the first gate electrode 215 may be disposed adjacent to the second sidewall of the semiconductor pattern 137 and the fourth sidewall of the first insulating intermediate layer pattern 185.

[0099] The first gate electrode 215 and the second gate electrode 305 may include metals (e.g., molybdenum, ruthenium, tungsten, etc.), metal nitrides (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.) or metal silicides.

[0100] In some embodiments, the second gate electrode 305 may be a front gate electrode relative to each of the semiconductor patterns 137 and may be used as a word line in a semiconductor device. The first gate electrode 215 may be a back gate electrode relative to each of the semiconductor patterns 137.

[0101] In some embodiments, the semiconductor pattern 137 may include a first semiconductor pattern disposed in a first direction D1 and a second semiconductor pattern disposed in the first direction D1 and spaced apart from the first semiconductor pattern in a second direction D2.

[0102] In some embodiments, the word lines may include a first word line extending along a first direction D1 adjacent to a first sidewall of a first semiconductor pattern and a second word line extending along the first direction D1 adjacent to a first sidewall of a second semiconductor pattern, and the second sidewalls of the first semiconductor pattern and the second sidewalls of the second semiconductor pattern may face each other in a second direction D2. A back gate electrode 215 may be formed between the second sidewalls of the first semiconductor pattern and the second sidewalls of the second semiconductor pattern.

[0103] For example, the first word line, the first sidewall and the second sidewall of each of the first semiconductor patterns, the back gate electrode 215, the second sidewall and the first sidewall of each of the second semiconductor patterns, and the second word line may be arranged in this order in the second direction D2.

[0104] In some embodiments, a first word line and a second word line at opposite sides of the back gate electrode 215 in the second direction D2 may form word line pairs, and multiple word line pairs may be disposed in the second direction D2. A second insulating interlayer 310 may be formed between adjacent word line pairs in the second direction D2 and may include oxides (e.g., silicon oxide).

[0105] In some embodiments, the width of each adjacent portion of the first gate electrode 215 in the first insulating interlayer pattern 185 in the second direction D2 may be greater than the width of each adjacent portion of the first gate electrode 215 in the semiconductor pattern 137 in the second direction D2. Therefore, the width of the first gate electrode 215 in the second direction D2 may vary periodically in the first direction D1.

[0106] In some embodiments, the width of the second gate electrode 305 in the second direction D2 may be constant in the first direction D1. The second gate electrode 305 may extend in the first direction D1 and may include recesses and protrusions alternately and repeatedly disposed in the first direction D1 in the second direction D2.

[0107] In some embodiments, the upper and lower surfaces of the first gate electrode 215 may be substantially coplanar with the upper and lower surfaces of the second gate electrode 305, respectively. However, the examples in this disclosure are not limited thereto.

[0108] In some embodiments, the lower surface of the first gate electrode 215 may be covered by a third insulating layer 270, and the upper surface of the first gate electrode 215 may be covered by a sixth insulating pattern 540. Furthermore, the lower surface of the second gate electrode 305 may be covered by a fourth insulating pattern 330, and the upper surface of the second gate electrode 305 may be covered by a seventh insulating pattern 545.

[0109] In some embodiments, the lower surfaces of the third insulating layer 270 and the fourth insulating pattern 330 may be substantially coplanar with each other and may contact the upper surfaces of the bit line structure and the third spacer 395. Furthermore, the upper surfaces of the sixth insulating pattern 540 and the seventh insulating pattern 545 may be substantially coplanar with each other.

[0110] The third insulating layer 270, as well as the fourth insulating pattern 330, the sixth insulating pattern 540, and the seventh insulating pattern 545, may include oxides (e.g., silicon oxide).

[0111] The second gate insulating pattern 297 may extend along the first direction D1 on the first sidewall of the semiconductor pattern 137 and the third sidewall of the first insulating intermediate layer pattern 185, and contact the first sidewall of the semiconductor pattern 137 and the third sidewall of the first insulating intermediate layer pattern 185. Similarly, the first gate insulating pattern 207 may extend along the first direction D1 on the second sidewall of the semiconductor pattern 137 and the fourth sidewall of the first insulating intermediate layer pattern 185, and contact the second sidewall of the semiconductor pattern 137 and the fourth sidewall of the first insulating intermediate layer pattern 185. Therefore, the second gate insulating pattern 297 may be formed between each of the semiconductor pattern 137 and the second gate electrode 305, and the first gate insulating pattern 207 may be formed between each of the semiconductor pattern 137 and the first gate electrode 215.

[0112] The first gate insulating pattern 207 can cover not only the sidewall of the first gate electrode 215, but also the sidewalls of the sixth insulating pattern 540 and the third insulating layer 270, which are respectively above and below the first gate electrode 215. The second gate insulating pattern 297 can cover not only the sidewall of the second gate electrode 305, but also the sidewalls of the seventh insulating pattern 545 and the fourth insulating pattern 330, which are respectively above and below the second gate electrode 305.

[0113] Each of the first gate insulating pattern 207 and the second gate insulating pattern 297 may include an oxide (e.g., silicon oxide). Optionally, each of the first gate insulating pattern 207 and the second gate insulating pattern 297 may have a multilayer structure, the multilayer structure including a first layer containing silicon oxide and contacting the semiconductor pattern 137 and a second layer containing a metal oxide (e.g., hafnium oxide, zirconium oxide, etc.) and contacting the sidewalls of the first layer and the sidewalls of the first insulating intermediate layer pattern 185.

[0114] In some embodiments, the width of the portion of each of the first gate insulating pattern 207 and the second gate insulating pattern 297 adjacent to the sidewall of each of the semiconductor pattern 137 in the second direction D2 may be greater than the width of the portion of each of the first gate insulating pattern 207 and the second gate insulating pattern 297 adjacent to the sidewall of each of the first insulating intermediate layer pattern 185 in the second direction D2. Therefore, the width of each of the first gate insulating pattern 207 and the second gate insulating pattern 297 in the second direction D2 may periodically change in the first direction D1.

[0115] As described above, if each of the first gate insulating pattern 207 and the second gate insulating pattern 297 has a multilayer structure including a first layer and a second layer, then the portion of each of the first gate insulating pattern 207 and the second gate insulating pattern 297 that contacts each of the semiconductor pattern 137 may include both the first layer and the second layer, while the portion of each of the first gate insulating pattern 207 and the second gate insulating pattern 297 that contacts each of the first insulating intermediate layer pattern 185 may include only the second layer.

[0116] The first etch stop layer 550, the third insulating intermediate layer 560, and the capping layer 570 may be sequentially stacked on the semiconductor pattern 137, the first insulating intermediate layer pattern 185, the second insulating intermediate layer 310, the first gate insulating pattern 207, the second gate insulating pattern 297, the sixth insulating pattern 540, and the seventh insulating pattern 545, and the contact plug structure may extend through the first etch stop layer 550, the third insulating intermediate layer 560, and the capping layer 570 to contact the upper surface of the semiconductor pattern 137.

[0117] The first etch stop layer 550 and the capping layer 570 may include an insulating nitride (e.g., silicon nitride), and the third insulating intermediate layer 560 may include an oxide (e.g., silicon oxide).

[0118] Since the multiple semiconductor patterns 137 are spaced apart from each other in the first direction D1 and the second direction D2, the multiple contact plug structures can also be spaced apart from each other in the first direction D1 and the second direction D2. In the example, the contact plug structures can be arranged in a grid pattern in a planar view. Alternatively, the contact plug structures can be arranged in a honeycomb pattern in a planar view.

[0119] The contact plug structure can contact not only the upper surface of each of the semiconductor patterns 137, but also the upper surfaces of the first gate insulating pattern 207 and the second gate insulating pattern 297, as well as the sixth insulating pattern 540 and the seventh insulating pattern 545 adjacent to each of the semiconductor patterns 137.

[0120] The contact plug structure may include a lower contact plug 590, an ohmic contact pattern 600, and an upper contact plug 610 sequentially stacked on a third direction D3.

[0121] The lower contact plug 590 may include polycrystalline silicon doped with n-type or p-type impurities, the ohmic contact pattern 600 may include metal silicides (e.g., cobalt silicide, nickel silicide, titanium silicide, etc.), and the upper contact plug 610 may include conductive materials (e.g., metals, metal nitrides, metal silicides, etc.).

[0122] The second etch stop layer 620 may be formed on the third insulating intermediate layer 560 and the contact plug structure, and the first capacitor electrode 670 may extend through the second etch stop layer 620 in the third direction D3.

[0123] Since the multiple contact plug structures are spaced apart from each other in the first direction D1 and the second direction D2, the multiple first capacitor electrodes 670 can also be spaced apart from each other in the first direction D1 and the second direction D2.

[0124] In some embodiments, the first capacitor electrode 670 may have a shape in a planar view, such as a circle, an ellipse, a polygon, or a polygon with rounded corners. In an example, the first capacitor electrode 670 may be arranged in a grid pattern in a planar view. Alternatively, the first capacitor electrode 670 may be arranged in a honeycomb pattern in a planar view.

[0125] The first support layer 640 and the second support layer 660 can respectively contact the center and the top of each of the first capacitor electrodes 670, which can prevent the first capacitor electrode 670 from collapsing.

[0126] A dielectric layer 680 may be formed on the surfaces of the first capacitor electrode 670, the first support layer 640, and the second support layer 660, and a second capacitor electrode 690 may be formed on the dielectric layer 680. The first capacitor electrode 670, the second capacitor electrode 690, and the dielectric layer 680 may together form a capacitor 700.

[0127] The second etch stop layer 620 may include an insulating nitride (e.g., silicon boron nitride, silicon carbonitride, etc.), and the first support layer 640 and the second support layer 660 may include insulating nitrides (e.g., silicon nitride). The first capacitor electrode 670 may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.) or a metal (e.g., titanium, tantalum, tungsten). The dielectric layer 680 may include a metal oxide having a high dielectric constant (e.g., hafnium oxide, zirconium oxide, etc.), and the second capacitor electrode 690 may include, for example, silicon germanium doped with impurities.

[0128] In some examples, another type of data storage structure, replacing the capacitor 700, may be formed on each of the contact plug structures, and the data storage structure may include a variable resistance pattern containing, for example, a phase change material, a transition metal oxide, a magnetic material, etc.

[0129] Figures 7 to 10 Only the cell area of ​​the semiconductor device is shown. However, Figures 7 to 10 Some of the components shown can also be formed on the peripheral circuit area of ​​the semiconductor device.

[0130] For example, Figure 8The second gate electrode 305, used as a word line, extends in the first direction D1. However, each of the first and second word lines forming a word line pair may include an extension extending in the peripheral circuit region along the second direction D2, and the first and second word lines may have a loop shape in the cell region and the peripheral circuit region in a planar view. In some examples, a dividing layer may be formed between the first and second word lines in the peripheral circuit region or the cell region, such that the first and second word lines are electrically insulated from each other.

[0131] Furthermore, the first shielding pattern 400 extending along the second direction D2 between adjacent bit line structures may include an extension extending along the first direction D1 in the peripheral circuit region, and the first shielding patterns 400 spaced apart from each other along the first direction D1 in the cell region may be connected to each other in the peripheral circuit region. Contact plugs and wiring may be further formed in the peripheral circuit region to connect to the bit line structure and the first shielding pattern 400.

[0132] In some embodiments, the semiconductor device may include a vertical channel transistor (VCT), which may include a semiconductor pattern 137 serving as a channel, a second gate electrode 305 serving as a front gate electrode, and a first gate electrode 215 serving as a back gate electrode. The back gate electrode 215 may increase the threshold voltage of the VCT. As a result, even if the VCT has a small size, the leakage current characteristics may not deteriorate.

[0133] Furthermore, a back gate electrode 215 may be disposed between the two second gate electrodes 305 to apply a voltage to the common ground of the channels in the semiconductor patterns 137 located on opposite sides. As a result, the integration density of the semiconductor device can be increased compared to a VCT having two gate electrodes located on opposite sides of the channel.

[0134] In some implementations, the semiconductor pattern 137 of the VCT includes a single-crystal semiconductor material. As a result, leakage current characteristics can be further enhanced.

[0135] Figure 11 and Figure 12 This is a diagram illustrating an example of a bit line shielding structure included in a semiconductor memory device.

[0136] Reference Figure 11 and Figure 12 The bit-line shielding structure BSST1 includes multiple vertical shielding patterns VSD1 to VSD4 and a horizontal shielding plate HSP. The multiple vertical shielding patterns VSD1 to VSD4 can correspond to... Figures 7 to 10 The shielding pattern is 400.

[0137] For reference Figures 7 to 10As described, a plurality of vertical shielding patterns VSD1 to VSD4 may be arranged in a first direction D1 and extended in a second direction D2, and each of the plurality of vertical shielding patterns VSD1 to VSD4 may be disposed between adjacent bit lines in a plurality of bit lines.

[0138] The horizontal shielding plate HSP can be connected to the lower surface of multiple vertical shielding patterns VSD1 to VSD4 to shield the lower space between the multiple vertical shielding patterns VSD1 to VSD4.

[0139] like Figure 12 As shown, one or more voltage-applying conductive lines LD11 to LD14 may be connected to the ends of the horizontal shield plate HSP in the first direction D1 or the second direction D2, and extend in the first direction D1 or the second direction D2 to connect with the capacitor connection conductive path.

[0140] Figure 13 and Figure 14 This is a diagram illustrating another example of a bit line shielding structure included in a semiconductor memory device.

[0141] Reference Figure 13 and Figure 14 The bit line shielding structure BSST2 may include a plurality of vertical shielding patterns VSD1 to VSD4 arranged in a first direction D1 and extending in a second direction D2. The bit line shielding structure BSST2 may also include one or two horizontal conductive lines CNL1 and CNL2 connected to the ends of the plurality of vertical shielding patterns VSD1 to VSD4 in the second direction D2 and extending in the first direction D1.

[0142] like Figure 14 As shown, one or two voltage-applied conductive lines LD11 and LD12 can be connected to horizontal conductive lines CNL1 and CNL2 and extend in the second direction D2 to connect with the capacitor connection conductive path.

[0143] Figure 15 This is a perspective view of an example of the memory core circuitry included in a semiconductor memory device, and Figure 16 It is shown that it includes Figure 15 A diagram illustrating an example layout of the sub-peripheral circuitry within the core circuitry of a memory.

[0144] Reference Figure 15 The memory core circuit MCC includes the memory cell array MCA and the core control circuit CCC. The memory core circuit MCC may have a peripheral upper cell (CoP) structure in which the core control circuit CCC is located below the memory cell array MCA.

[0145] The memory cell array (MCA) may include multiple sub-cell arrays (SCA) arranged in a matrix of multiple array rows AR1 to AR4 and multiple array columns AC1 to AC8.

[0146] The core control circuit (CCC) may include multiple sub-peripheral circuits (SPCs) arranged below multiple sub-cell arrays (SCAs). Each SPC can individually control the operation of one of the multiple sub-cell arrays (SCAs).

[0147] Each subcell array (SCA) includes multiple memory cells, each memory cell being connected to multiple word lines extending in a first direction D1 and arranged in a second direction D2, and multiple bit lines extending in the second direction D2 and arranged in the first direction D1. Each memory cell may include a vertical channel transistor (VCT) and a cell capacitor disposed above the vertical channel transistor.

[0148] As described below, each sub-peripheral circuit (SPC) may include a sense amplifier region and other regions. The sense amplifier region includes multiple bit line sense amplifiers, each of which senses the voltage of multiple bit lines. The other regions include the remaining circuitry in addition to the multiple bit line sense amplifiers.

[0149] For ease of explanation and description, Figure 15 The example shows a thirty-two sub-cell array SCA and thirty-two corresponding sub-peripheral circuits SPC arranged in four array rows AR1 to AR4 and eight array columns AC1 to AC8, but the example is not limited to a specific number of array rows and array columns.

[0150] Figure 16 The layout of a sub-peripheral circuit (SPC) is shown. Includes... Figure 15 Each of the multiple sub-peripheral circuits (SPCs) in the core control circuit (CCC) can have Figure 16 The structure shown is shown.

[0151] Reference Figure 16 The sub-peripheral circuitry (SPC) may include a sense amplifier region (RSA) and a separate RETC region. The sense amplifier region (RSA) may include multiple bit line sense amplifiers, each sensing the voltage of multiple bit lines. The other RETC region may include circuitry in addition to the multiple bit line sense amplifiers.

[0152] like Figure 16As shown, the other areas of RETC may include a word line driver area RWD, a decoder area RRD, and a power and control area RPC. The word line driver area RWD includes multiple sub-word line drivers that drive each of the multiple word lines. The decoder area RRD includes line decoding circuitry that controls the multiple sub-word line drivers to select at least one of the multiple word lines. The power and control area RPC includes power circuitry that supplies power to each of the sub-peripheral circuits SPC and control circuitry that controls the operation of each of the sub-peripheral circuits SPC.

[0153] The word line driver area RWD, sense amplifier area RSA, decoder area RRD, and power and control area RPC can be set on the first direction D1.

[0154] In some implementations, such as Figure 16 As shown, the word line driver region RWD and the sense amplifier region RSA can be located at both ends of each sub-peripheral circuit SPC in the first direction D1.

[0155] The decoder region RRD can be located adjacent to the word line driver region RWD in the first direction D1, between the word line driver region RWD and the sense amplifier region RSA.

[0156] The power and control area RPC can be positioned adjacent to the sense amplifier area RSA in the first direction D1, between the word line driver area RWD and the sense amplifier area RSA.

[0157] like Figure 16 As shown, the length SZT of each sub-peripheral circuit SPC in the first direction D1 corresponds to the sum of the length SZ1 of the sense amplifier region RSA in the first direction D1 and the length SZ2 of the other regions RETC in the first direction D1. In some embodiments, the length SZ1 of the sense amplifier region RSA in the first direction D1 may be greater than half the length SZT of each sub-peripheral circuit SPC in the first direction D1 for efficient placement of the bit line sense amplifier. In other words, the length SZ1 of the sense amplifier region RSA in the first direction D1 may be greater than or equal to the length SZ2 of the other regions RETC in the first direction D1.

[0158] Figure 17 It is shown that it includes Figure 15 A diagram illustrating an example of the arrangement of bit lines in the core circuitry of a memory.

[0159] Figure 17 Shown in an array column (e.g., Figure 15The first sub-peripheral circuit SPC11, the second sub-peripheral circuit SPC12, and the third sub-peripheral circuit SPC13 are arranged adjacent to each other and sequentially in the second direction D2 in the first array column AC1).

[0160] Reference Figure 17 Multiple bit lines BL are arranged above each of the sub-peripheral circuits of the first sub-peripheral circuit SPC11, the second sub-peripheral circuit SPC12, and the third sub-peripheral circuit SPC13.

[0161] like Figure 17 As shown, the bit line BL may be cut (e.g., discontinuous) at the boundary region BNC between the sub-peripheral circuits SPC11, SPC12, and SPC13. Such a cut enables an open bit line structure.

[0162] Figure 18 This is a diagram illustrating an example of a conductive path connected by a capacitor in a semiconductor memory device.

[0163] Figure 18 This illustrates a CoP structure where the unit capacitor CP is positioned on top of the third-direction D3 and the bit line BL is positioned on the bottom of the third-direction D3. (See reference...) Figures 7 to 10 As described, word lines can be disposed between unit capacitor CP and bit lines BL. Bit lines BLa and BLb can be connected to bit line sense amplifier BLSA included in sense amplifier region RSA via conductive pattern PT formed on conductive layers BP and LM and vertical contact VC.

[0164] In such Figure 18 In the example shown, the bit line BLb of the sub-peripheral circuit SPC12 can be connected to the bit line sense amplifier BLSA included in the sense amplifier region RSA of the adjacent sub-peripheral circuit SPC11 via a horizontal conductive path CCP formed in the boundary region BNC between adjacent sub-peripheral circuits SPC11 and SPC12 in the second direction D2. The horizontal conductive path CCP can be connected to the bit line BLb via a vertical path VPH.

[0165] In this way, the horizontal conductive path CCP can extend across the boundary region BNC in the second direction D2 to connect the bit line BLb and the bit line sensing amplifier BLSA.

[0166] like Figure 18 As shown, each bit line sense amplifier BLSA can be simultaneously coupled to a bit line BLb and a complementary bit line BLa. For example, a bit line BLb can correspond to a bit line of sub-peripheral circuit SPC12, and the complementary bit line BLa can correspond to a bit line of adjacent sub-peripheral circuit SPC11.

[0167] Thus, the memory core circuit can have an open bit line structure, in which each bit line sense amplifier BLSA is connected to a bit line BLb disposed on the upper side of each sub-peripheral circuit SPC12 and a complementary bit line BLa disposed on the upper side of the adjacent sub-peripheral circuit SPC11. In this case, a bit line BLb connected to the corresponding bit line sense amplifier BLSA and a complementary bit line BLa can be disposed at the same location in the first direction D1.

[0168] like Figure 17 and Figure 18 As shown, multiple bit lines are cut at the boundary region BNC of the sub-peripheral circuits SCP11, SPC12 and SPC13 arranged along the second direction D2.

[0169] Reference Figure 18 The aforementioned bit line shielding structure BSST may include sub-bit line shielding structures BSST11 and BSST12 corresponding to sub-peripheral circuits SCP11 and SPC12 respectively, and a first horizontal conductive line CCP1 formed in the boundary region BNC to connect the sub-bit line shielding structures BSST11 and BSST12. Furthermore, the aforementioned plate electrode structure PEST may include sub-plate electrode structures PEST11 and PEST12 corresponding to sub-peripheral circuits SCP11 and SPC12 respectively, and a second horizontal conductive line CCP2 formed in the boundary region BNC to connect the sub-plate electrode structures PEST11 and PEST12.

[0170] Reference Figure 1 The core conductive path CPH described can be formed in the boundary region BNC. For example... Figure 18 As shown, the core connection conductive path CPH may include a vertical contact VC1 extending from the boundary region BNC in the third direction D3. The vertical contact VC1 may connect a first horizontal conductive line CCP1 and a second horizontal conductive line CCP2. The first horizontal conductive line CCP1 is formed in the boundary region BNC and corresponds to a portion of the bit line shielding structure BSST, and the second horizontal conductive line CCP2 is formed in the boundary region BNC and corresponds to a portion of the plate electrode structure PEST. In this way, the bit line shielding structure BSST and the plate electrode structure PEST can be efficiently connected by arranging the core connection conductive path CPH in the boundary region BNC.

[0171] Figure 19 This is a diagram illustrating an example of a stacked memory device.

[0172] Figure 19 An example of a high-bandwidth memory structure is shown. (See reference...) Figure 19The high-bandwidth memory (HBM) 1100 may include a structure in which multiple DRAM semiconductor dies 1120, 1130, 1140 and 1150 are stacked. The multiple DRAM semiconductor dies 1120, 1130, 1140 and 1150 correspond to the aforementioned core semiconductor die.

[0173] High-bandwidth memories can be optimized for high-bandwidth operation on stacked structures through multiple independent interfaces called channels. According to the HBM standard, each DRAM stack can support multiple channels.

[0174] although Figure 19 The example shown is of four stacked DRAM semiconductor dies, but the example is not limited to this. Each semiconductor die can provide additional capacity and additional channels to the stacked structure. Each channel provides independent access to a separate group of DRAM memory. A request from one channel does not access data attached to another channel. Channels are independently clocked and do not need to be synchronized with each other. Figure 19 An example is shown where the memory bank MB of each DRAM semiconductor die is grouped into eight independent channels CH0 to CH7, but the example is not limited to this.

[0175] The high-bandwidth memory 1100 may include a buffer die or interface die 1110 located at the bottom of the stacked structure and providing signal redistribution and other functions. Functions typically implemented in DRAM semiconductor dies 1120, 1130, 1140 and 1150 may be implemented in the interface die 1110.

[0176] Figure 20 This is a diagram illustrating an example structure of a semiconductor package including a semiconductor memory device.

[0177] Reference Figure 20 The semiconductor package 1700 includes one or more stacked memory devices 1710 and a graphics processing unit (GPU) 1720. The stacked memory devices 1710 and GPU 1720 may be mounted on an interposer 1730, and the interposer 1730 on which the stacked memory devices 1710 and GPU 1720 are mounted may be mounted on a package substrate 1740. The GPU 1720 may perform substantially the same functions as the aforementioned memory controller, or may include the memory controller. The GPU 1720 may store data generated or used in graphics processing in one or more stacked memory devices 1710.

[0178] The stacked memory device 1710 can be implemented in various forms, and can be a memory device in the form of high-bandwidth memory (HBM) with multiple layers stacked. Therefore, the stacked memory device 1710 may include buffer semiconductor dies and multiple core semiconductor dies. In some examples, connection terminals 1750 for connecting or communicating with external devices may be disposed below the package substrate 1740 (e.g., on the lower surface of the package substrate 1740).

[0179] Figure 21 This is a block diagram illustrating an example of a mobile system including a semiconductor memory device.

[0180] Reference Figure 21 The mobile system 2000 includes an application processor (AP) 2100, a connectivity unit 2200, a semiconductor memory device (or volatile semiconductor memory device, VM) 2300, a non-volatile semiconductor memory device (NVM) 2400, a user interface 2500, and a power supply 2600. In some embodiments, the mobile system 2000 can be any mobile system (such as a mobile phone, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation system, etc.). The application processor 2100 can execute applications that provide internet browsers, games, videos, etc. The connectivity unit 2200 can perform wireless or wired communication with external devices. The semiconductor memory device 2300 can store data processed by the application processor 2100 or can operate as working memory.

[0181] The non-volatile semiconductor memory device 2400 can store user data and a boot image for starting the mobile system 2000. The user interface 2500 may include one or more input devices (such as a keyboard, a touch screen) and / or one or more output devices (such as a speaker, a display device). The power supply 2600 can supply the operating voltage for the mobile system 1200.

[0182] In some embodiments, the semiconductor memory device 2300 may include a plate electrode structure PEST, a bit line shielding structure BSST, and a capacitive connection conductive path PH connecting the plate electrode structure PEST and the bit line shielding structure BSST.

[0183] The aspects of this disclosure can be applied to any electronic device and system. For example, the inventive concept can be applied to systems such as: memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash memory (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive driving systems, etc.

[0184] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual implementations in this disclosure may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in a specific combination, in some cases one or more features from that combination may be removed, and the combination may involve sub-combinations or variations thereof.

[0185] The foregoing is illustrative and should not be construed as limiting. Although some examples have been described, those skilled in the art will readily understand that many modifications are possible in the examples without substantially departing from the inventive concept.

Claims

1. A semiconductor memory device, comprising: Multiple bit lines are arranged in a first direction parallel to the surface of the semiconductor substrate and extend in a second direction parallel to the surface of the semiconductor substrate and perpendicular to the first direction. A memory cell array includes a plurality of memory cells connected to the plurality of bit lines, wherein the plurality of memory cells are arranged in a first direction and a second direction, and each memory cell includes a cell transistor and a cell capacitor arranged in a third direction perpendicular to the surface of a semiconductor substrate. A plate electrode structure provides a common electrode for the cell capacitors included in the plurality of memory cells; Bit line shielding structure, between the plurality of bit lines; and Conductive path, connecting plate electrode structure and bit line shielding structure.

2. The semiconductor memory device according to claim 1, wherein, The semiconductor memory device includes a memory core region on which an array of memory cells is arranged, and also includes a peripheral circuit region disposed adjacent to the memory core region in a first direction or a second direction.

3. The semiconductor memory device according to claim 2, wherein, Conductive paths include peripheral connection conductive paths arranged in the peripheral circuit region.

4. The semiconductor memory device according to claim 3, wherein, The external connection conductive path includes: A first conductive line is connected to the bit line shielding structure and extends in a first direction or a second direction; A second conductive line is connected to the plate electrode structure and extends in a first or second direction; and A vertical contact extends upwards from a third party and connects the first conductive wire and the second conductive wire. The first and second conductive lines are configured to be connected to a voltage source.

5. The semiconductor memory device according to claim 3, wherein, The external connection conductive path includes: A first conductive line is connected to the bit line shielding structure and extends in a first direction or a second direction; The second conductive line is connected to the plate electrode structure and extends in a first direction or a second direction; The first test pad and the second test pad are on the top surface of the core semiconductor die on which the memory cell array is arranged; A first vertical contact extends upward in a third direction and connects a first conductive wire and a first test pad; A second vertical contact extends upward from a third party and connects to a second conductive wire and a second test pad; and The third conductive line is on the top surface of the core semiconductor die and connects the first and second test pads. The first and second conductive lines are configured to be connected to a voltage source.

6. The semiconductor memory device according to claim 3, wherein, The external connection conductive path includes: A first conductive line is connected to the bit line shielding structure and extends in a first direction or a second direction; The second conductive line is connected to the plate electrode structure and extends in a first direction or a second direction; The first core pad and the second core pad are on the bottom surface of the core semiconductor die on which the memory cell array is arranged; The first vertical contact extends upward in a third direction and connects the first conductive line and the first core pad; The second vertical contact extends upward on the third side and connects the second conductive line and the second core pad; The first peripheral pad and the second peripheral pad are on the top surface of the peripheral semiconductor die bonded to the bottom surface of the core semiconductor die, wherein the first peripheral pad and the second peripheral pad are bonded to the first core pad and the second core pad, respectively. A horizontal conductive line extends in a peripheral semiconductor die in a first or second direction; A third vertical contact extends upward from the third and connects to the first peripheral pad and the horizontal conductive line; and The fourth vertical contact extends upward from the third and connects to the second peripheral pad and the horizontal conductive line. The first and second conductive lines are configured to be connected to a voltage source.

7. The semiconductor memory device according to claim 3, wherein, The external connection conductive path includes: A first conductive line is connected to the bit line shielding structure and extends in a first direction or a second direction; The second conductive line is connected to the plate electrode structure and extends in a first direction or a second direction; The first core pad and the second core pad are on the bottom surface of the core semiconductor die on which the memory cell array is arranged; The first vertical contact extends upward in a third direction and connects the first conductive line and the first core pad; A second vertical contact extends upward in a third direction and connects to the second conductive line and the second core pad; and The third conductive line is on the bottom surface of the core semiconductor die and connects the first core pad and the second core pad. The first and second conductive lines are configured to be connected to a voltage source.

8. The semiconductor memory device according to claim 2, wherein, Conductive paths include core connection conductive paths in the memory core region.

9. The semiconductor memory device according to claim 1, wherein, Bit line shielding structure includes: Multiple vertical shielding patterns are arranged in a first direction and extend in a second direction, wherein each of the multiple vertical shielding patterns is arranged between adjacent bit lines in the multiple bit lines; and A horizontal shielding plate is connected to the bottom surface of the plurality of vertical shielding patterns to block the lower space between the plurality of vertical shielding patterns.

10. The semiconductor memory device of claim 9, further comprising: Conductive wires are connected to the ends of a horizontal shielding plate and extend in a first or second direction to connect with a conductive path.

11. The semiconductor memory device according to claim 1, wherein, Bit line shielding structure includes: Multiple vertical shielding patterns are arranged in a first direction and extend in a second direction, wherein each of the multiple vertical shielding patterns is arranged between adjacent bit lines in the multiple bit lines.

12. The semiconductor memory device according to claim 11, wherein, The bit line shielding structure also includes: A horizontal conductive line is connected to the end of the plurality of vertical shielding patterns and extends in a first direction.

13. The semiconductor memory device according to claim 12, wherein, The horizontal conductive line is the first conductive line, and the semiconductor memory device further includes: The second conductive wire is connected to the horizontal conductive wire and extends in the second direction to connect with the conductive path.

14. The semiconductor memory device of claim 1, further comprising: The core control circuit is located below the memory cell array and is configured to control the operation of the memory cell array.

15. The semiconductor memory device according to claim 14, wherein, The memory cell array comprises multiple sub-cell arrays arranged in a matrix, wherein the matrix includes multiple array rows and multiple array columns, and The core control circuit includes multiple sub-peripheral circuits, which are respectively arranged below the multiple sub-unit arrays and configured to control the operation of the multiple sub-unit arrays respectively.

16. The semiconductor memory device according to claim 15, wherein, The multiple bit lines are discontinuous at the boundary region of the sub-peripheral circuit, wherein the sub-peripheral circuit is arranged in the second direction, and The conductive path includes the core connecting conductive path formed in the boundary region.

17. The semiconductor memory device of claim 14, wherein, The memory cell array is arranged in the core semiconductor die, the core control circuit is arranged in the peripheral semiconductor die, and the semiconductor memory device includes a peripheral upper cell structure in which the core semiconductor die and the peripheral semiconductor die are stacked in the third direction.

18. The semiconductor memory device according to claim 1, wherein, A unit transistor is a vertical channel transistor with its channel extending upward in the third direction, and a unit capacitor is disposed above the vertical channel transistor in the third direction.

19. A semiconductor memory device, comprising: Multiple bit lines; The memory cell array includes multiple memory cells connected to the multiple bit lines, each memory cell including a cell transistor and a cell capacitor; The plate electrode structure is configured to provide a common plate voltage to the plurality of memory cells; Bit line shielding structures are provided between adjacent bit lines among the plurality of bit lines; and Conductive path, connecting plate electrode structure and bit line shielding structure.

20. A semiconductor memory device, comprising: Multiple bit lines are arranged in a first direction parallel to the surface of the semiconductor substrate and extend in a second direction parallel to the surface of the semiconductor substrate and perpendicular to the first direction. A memory cell array includes a plurality of memory cells connected to the plurality of bit lines, the plurality of memory cells being arranged in a first direction and a second direction, each memory cell including a vertical channel transistor with a channel extending upward in a third direction and a cell capacitor above the vertical channel transistor in a third direction. A plate electrode structure provides a common electrode for the cell capacitors included in the plurality of memory cells; Bit line shielding structure between the multiple bit lines; as well as Conductive path, connecting plate electrode structure and bit line shielding structure The semiconductor memory device includes a memory core region on which an array of memory cells is formed, and a peripheral circuit region adjacent to the memory core region in a first direction or a second direction. The conductive paths include peripheral connection conductive paths formed in the peripheral circuit region and core connection conductive paths formed in the memory core region.

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