Memory device and operating method thereof

Abstract

The invention relates to a memory device and an operating method thereof. A memory device may include: a memory cell array including a plurality of memory cells; a power-off temperature determination circuit configured to generate a power-off temperature code based on a level of a threshold voltage of at least one memory cell included in a specific region of the memory cell array; a control circuit configured to generate a voltage control signal based on the power-off temperature code; and a read voltage generation circuit configured to provide a read voltage to the memory cell array based on the voltage control signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0113730, filed with the Korean Intellectual Property Office on August 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments relate to an integrated circuit technology and a storage device and a method of operating the same. Background Technology

[0004] Recently, with the reduction in size, power consumption, performance improvement, and diversification of electronic devices, various electronic devices (such as computers and portable communication devices) require storage devices capable of storing information.

[0005] Because storage devices are sensitive to temperature, research is underway on storage devices that select an operating method suitable for the current temperature by checking the temperature when driven. In particular, storage devices in a power-off state are highly likely to malfunction when switching back to a power-on state, since the temperature experienced by the storage device is unknown. Summary of the Invention

[0006] In one embodiment, a storage device may include: a storage cell array including a plurality of storage cells; a power-off temperature determination circuit configured to generate a power-off temperature code based on the level of a threshold voltage of at least one storage cell included in a specific region of the storage cell array; a control circuit configured to generate a voltage control signal based on the power-off temperature code; and a read voltage generation circuit configured to provide a read voltage to the storage cell array based on the voltage control signal.

[0007] In one embodiment, an operation method of a storage device may include: turning the power supply of the storage device off; and writing to a specific cell in a predetermined state when the power supply of the storage device is turned off. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the construction of a storage device according to embodiments of the present disclosure.

[0009] Figure 2 and Figure 3 This is a diagram illustrating the storage cells of a storage device according to embodiments of the present disclosure.

[0010] Figure 4 This is a diagram illustrating the construction of a power-off temperature determination circuit according to an embodiment of the present disclosure.

[0011] Figure 5This is a diagram illustrating the operation of a power-off temperature determination circuit according to an embodiment of the present disclosure.

[0012] Figure 6 This is a diagram used to illustrate the operation of a storage device according to embodiments of the present disclosure.

[0013] Figure 7 This is a flowchart describing the operation of a storage device according to embodiments of the present disclosure. Detailed Implementation

[0014] In the following description, some embodiments of the present disclosure are illustrated with reference to the accompanying drawings.

[0015] Embodiments of this disclosure provide a storage device and its operation method capable of storing temperature changes even in the event of a power outage.

[0016] It can still operate normally even when the temperature changes during a power outage.

[0017] Figure 1 This is a diagram illustrating the construction of a storage device 1 according to an embodiment of the present disclosure.

[0018] Reference Figure 1 The storage device 1 may include a control circuit 100, a read voltage generation circuit 200, a storage cell array 300, a data output circuit 400, a temperature sensor 500, and a power-off temperature determination circuit 600.

[0019] Control circuit 100 can control the internal circuitry of the storage device in response to requests from an external device (e.g., a controller). For example, control circuit 100 can control the internal circuitry in response to requests from an external device to store data in the storage cell array 300 or to output data stored in the storage element array 300 to an external device. Furthermore, when control circuit 100 controls the storage cell array 300, which includes temperature-sensitive storage cells, control circuit 100 can change the method of controlling the storage cell array 300 according to temperature. For example, after a read operation begins, control circuit 100 can control read voltage generation circuit 200 such that the level of the read voltage Vread supplied to the storage cell array 300 changes according to temperature variations. In one embodiment, control circuit 100 can generate a voltage control signal V_c for controlling read voltage generation circuit 200 based on an on-temperature code (on_code) received from temperature sensor 500 and a off-temperature code (off_code) received from off-temperature determination circuit 600. In this case, the read operation can be an operation that outputs data stored in the storage cell array 300 to an external device.

[0020] The read voltage generation circuit 200 can generate a read voltage Vread to be provided to the memory cell array 300 based on a voltage control signal V_c received from the control circuit 100. For example, the read voltage generation circuit 200 can change the level of the read voltage Vread based on the voltage control signal V_c.

[0021] The memory cell array 300 may include multiple memory cells (not shown). In this case, the memory cell may be a component for storing data. The memory cell may be made of a chalcogenide series material. The threshold voltage level of the memory cell may change based on the direction of the current flowing through the memory cell. For example, when the direction of the current flowing through the memory cell is a first direction, the memory cell may switch to a first state. When the direction of the current flowing through the memory cell is a second direction, the memory cell may switch to a second state. In this case, the threshold voltage of the memory cell in the first state may be different from the threshold voltage of the memory cell in the second state. Furthermore, the first direction and the second direction of the current flowing through the memory cell may be different directions.

[0022] Furthermore, the storage cell array 300 may include a specific region 310, which includes at least one storage cell not used for storing data received from an external device. In other words, the specific region 310 may be a region in the storage cell array 300 other than one or more regions in the storage cell array 300 designated for storing data received from an external device. According to one embodiment of this disclosure, the storage cell array 300 included in the storage device may include a specific region 310, which includes at least one storage cell configured such that when the power to the storage device is turned off, at least one storage cell switches to a first state (e.g., a set state).

[0023] After a read operation begins, the data output circuit 400 can detect and determine the state of each memory cell in the memory cell array 300 and output this state as data DATA. For example, when the state of the memory cell is detected and determined to be a first state (or a set state), the data output circuit 400 can output data DATA at a first level. Furthermore, when the state of the memory cell is detected and determined to be a second state (or a reset state), the data output circuit 400 can output data DATA at a second level. In this case, the first level and the second level can be different levels.

[0024] Temperature sensor 500 can sense the current temperature and generate an on-temperature code (on_code) with a code value based on the sensed temperature. In one embodiment, temperature sensor 500 can sense... Figure 1The current temperature of storage device 1. For example, temperature sensor 500 can sense the current temperature of one or more memory cells in memory array 300. Temperature sensor 500 can provide an on-temperature code (on_code) to control circuit 100.

[0025] The power-off temperature determination circuit 600 can generate a power-off temperature code off_code by detecting the threshold voltage V_mth of at least one memory cell included in the specific region 310. The power-off temperature determination circuit 600 can provide the power-off temperature code off_code to the control circuit 100. For example, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code having a code value corresponding to the level of the threshold voltage V_mth of the memory cell included in the specific region 310, and can provide the power-off temperature code off_code to the control circuit 100.

[0026] In this scenario, after power is supplied to the storage device in a power-off state, i.e., after the storage device switches to a power-on state, the control circuit 100 can change the level of the read voltage Vread based on the power-off temperature code off_code within a given time interval (e.g., a set time interval or a preset time interval). For example, the preset time interval can be determined based on the period during which the temperature sensor 500 is stabilized to output the precise temperature of one or more storage cells in the storage cell array 300, thereby ensuring reliable read operations on the storage cells. Furthermore, after the set time interval has elapsed, the control circuit 100 can change the level of the read voltage Vread based on the power-on temperature code on_code. In one embodiment of this disclosure, a configuration of a storage device that changes the level of the read voltage Vread based on the power-off temperature code off_code and the power-on temperature code on_code is described. However, it should be noted that the power-off temperature code off_code and the power-on temperature code on_code can also be applied to various operations of storage devices that require control based on temperature changes.

[0027] Figure 2 and Figure 3 This is a diagram illustrating the storage cells of a storage device according to embodiments of the present disclosure.

[0028] Figure 2 This is a diagram used to describe how a write operation changes the threshold voltage of a memory cell. In this case, the write operation can be the operation of switching the memory cell to either the first state SET or the second state RST.

[0029] Reference Figure 2Each of the plurality of memory cells included in the memory cell array 300 can be switched to a first state SET or a second state RST. In one embodiment, the memory cell array 300 may include a plurality of memory cells electrically connected between bit lines and word lines. In this case, when current flows through the memory cell from the bit line to the word line, the memory cell can switch to the first state (e.g., set state SET). When current flows through the memory cell from the word line to the bit line, the memory cell can switch to the second state (e.g., reset state RST). The threshold voltage of the memory cell in the second state RST may have a higher level than the threshold voltage of the memory cell in the first state SET. Furthermore, the memory cell array 300 may be configured such that after a read operation begins, current flows through the memory cell from the word line to the bit line. In this case, when current flows through the memory cell from the bit line to the word line, the direction of the current through the memory cell can be defined as a first direction. Furthermore, when current flows through the memory cell from the word line to the bit line, the direction of the current through the memory cell can be defined as a second direction.

[0030] Figure 3 It is a diagram used to describe how the level of its threshold voltage changes with temperature for a memory cell.

[0031] Reference Figure 3 In the memory cell array 300, the threshold voltage level of the memory cell in the first state SET can change according to the temperature. For example, the threshold voltage Vth level of the memory cell in the first state SET can be higher at high temperature than at low temperature, that is, it increases as the temperature increases.

[0032] The read voltage Vread provided after the read operation begins can be a voltage level between the threshold voltage level of the memory cell in the first state SET and the threshold voltage level of the memory cell in the second state RST. For example, the read voltage Vread can be a voltage at the midpoint between the threshold voltage of the memory cell in the first state SET and the threshold voltage of the memory cell in the second state RST, that is, the average level of the threshold voltage of the first state SET and the threshold voltage of the second state RST.

[0033] Therefore, when the threshold voltage level of the memory cell in the first state SET changes according to the temperature, the level of the read voltage Vread also needs to be changed.

[0034] In a storage device according to an embodiment of the present disclosure, the state of each storage cell in a storage cell array 300 can be switched due to a write operation. The threshold voltage level of the storage cell in the first state can change according to temperature. Furthermore, since the storage cell can have non-volatile storage characteristics, the state of the storage cell can be maintained even when the power applied to the storage device is turned off, after the storage cell is switched due to a write operation.

[0035] Figure 4 This is a diagram illustrating the construction of a power-off temperature determination circuit 600 according to an embodiment of the present disclosure. In this case, when power is supplied to the storage device in a power-off state, the read voltage generation circuit 200 can provide a read voltage Vread at a given level (e.g., a set level) to the storage cells (MCs) 310-1 included in a specific region 310 of the storage cell array 300. When the read voltage Vread at the set level is provided to the storage cells 310-1 of the specific region 310, a voltage corresponding to the threshold voltage V_mth of the storage cell 310-1 can be provided to the power-off temperature determination circuit 600. Figure 3 As shown, the voltage corresponding to the threshold voltage V_mth of the storage cell 310-1 provided to the power-off temperature determination circuit 600 can have different levels depending on the temperature.

[0036] Furthermore, according to an embodiment of this disclosure, the power-off temperature determination circuit can be configured to determine the level of change in the threshold voltage V_mth of the memory cell 310-1 based on intervals implemented by multiple comparison circuits receiving reference voltages at different levels. The power-off temperature determination circuit can also be implemented to generate a power-off temperature code off_code corresponding to the determined level of change in the threshold voltage V_mth. Although Figure 4 The power-off temperature determination circuit 600 shown includes first to fourth comparison circuits 610, 620, 630, and 640 as an example, but the number of comparison circuits can vary depending on the embodiments of this disclosure. If desired, the power-off temperature determination circuit 600 can be constructed by increasing or decreasing the number of comparison circuits.

[0037] Reference Figure 4The power-off temperature determination circuit 600 can generate a power-off temperature code off_code based on the level of the threshold voltage V_mth of at least one memory cell 310-1 included in the specific region 310. In this case, when the power applied to the storage device becomes off, at least one memory cell 310-1 included in the specific region 310 can switch to a predetermined state, namely the first state SET. That is, when the power applied to the storage device becomes off, a write operation to switch the memory cell to the first state SET can be performed on at least one memory cell 310-1 included in the specific region 310. Thereafter, when power is applied to the storage device, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code by detecting the level of the threshold voltage V_mth of at least one memory cell 310-1 included in the specific region 310. The power-off temperature code off_code generated by the power-off temperature determination circuit 600 can be provided to the control circuit 100.

[0038] In one embodiment, the power-off temperature determination circuit 600 may include first to fourth comparison circuits 610, 620, 630 and 640 and a code generation circuit 650.

[0039] The first comparison circuit 610 generates a first comparison signal Com1 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 with the level of the first reference voltage Vref0. For example, the first comparison circuit 610 can change the level of the first comparison signal Com1 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 with the level of the first reference voltage Vref0. In one embodiment, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is lower than the level of the first reference voltage Vref0, the first comparison circuit 610 can generate a first comparison signal Com1 with a first value (e.g., low level). When the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is higher than the level of the first reference voltage Vref0, the first comparison circuit 610 can generate a first comparison signal Com1 with a second value (e.g., high level).

[0040] The second comparison circuit 620 generates a second comparison signal Com2 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 with the level of a second reference voltage Vref1. For example, the second comparison circuit 620 can change the level of the second comparison signal Com2 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 with the level of the second reference voltage Vref1. In one embodiment, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is lower than the level of the second reference voltage Vref1, the second comparison circuit 620 can generate a second comparison signal Com2 with a first value (e.g., low level). Conversely, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is higher than the level of the second reference voltage Vref1, the second comparison circuit 620 can generate a second comparison signal Com2 with a second value (e.g., high level).

[0041] The third comparison circuit 630 generates a third comparison signal Com3 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 with the level of the third reference voltage Vref2. For example, the third comparison circuit 630 can change the level of the third comparison signal Com3 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 with the level of the third reference voltage Vref2. In one embodiment, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is lower than the level of the third reference voltage Vref2, the third comparison circuit 630 can generate a third comparison signal Com3 with a first value (e.g., low level). Conversely, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is higher than the level of the third reference voltage Vref2, the third comparison circuit 630 can generate a third comparison signal Com3 with a second value (e.g., high level).

[0042] The fourth comparison circuit 640 generates a fourth comparison signal Com4 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 with the level of the fourth reference voltage Vref3. For example, the fourth comparison circuit 640 can change the level of the fourth comparison signal Com4 by comparing the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 with the level of the fourth reference voltage Vref3. In one embodiment, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is lower than the level of the fourth reference voltage Vref3, the fourth comparison circuit 640 can generate a fourth comparison signal Com4 with a first value (e.g., low level). Conversely, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 is higher than the level of the fourth reference voltage Vref3, the fourth comparison circuit 640 can generate a fourth comparison signal Com4 with a second value (e.g., high level). In this case, the levels of the first to fourth reference voltages Vref0, Vref1, Vref2, and Vref3 can be different. Furthermore, the voltage levels can be increased in the order of the first reference voltage Vref0, the second reference voltage Vref1, the third reference voltage Vref2, and the fourth reference voltage Vref3.

[0043] The code generation circuit 650 can generate an off-temperature code (off_code) based on the first to fourth comparison signals Com1, Com2, Com3, and Com4. The first to fourth comparison signals Com1, Com2, Com3, and Com4 represent the comparison results output from the first to fourth comparison circuits 610 to 640, respectively.

[0044] For example, when the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 is lower than the level of the first reference voltage Vref0, the levels of the first to fourth comparison signals Com1, Com2, Com3 and Com4 can all be low.

[0045] When the first to fourth comparison signals Com1, Com2, Com3 and Com4 are all at a low level, that is, when the level of the voltage corresponding to the threshold voltage V_mth is lower than the level of the first reference voltage Vref0, the code generation circuit 650 can generate a power-off temperature code off_code with the lowest code value.

[0046] When the voltage level corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 is between the level of the first reference voltage Vref0 and the level of the second reference voltage Vref1, only the level of the first comparison signal Com1 can be high, while the levels of the second to fourth comparison signals Com2, Com3 and Com4 can be low.

[0047] When the level of the first comparison signal Com1 among the first to fourth comparison signals Com1, Com2, Com3 and Com4 is high, that is, when the level of the voltage corresponding to the threshold voltage V_mth is between the level of the first reference voltage Vref0 and the level of the second reference voltage Vref1, the code generation circuit 650 can generate a power-off temperature code off_code with a second minimum code value.

[0048] When the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 is between the level of the second reference voltage Vref1 and the level of the third reference voltage Vref2, among the first to fourth comparison signals Com1, Com2, Com3 and Com4, only the levels of the first comparison signal Com1 and the second comparison signal Com2 can be high, while the levels of the third comparison signal Com3 and the fourth comparison signal Com4 can be low.

[0049] When only the first comparison signal Com1 and the second comparison signal Com2 among the first to fourth comparison signals Com1, Com2, Com3 and Com4 are at a high level, that is, when the level of the voltage corresponding to the threshold voltage V_mth is between the level of the second reference voltage Vref1 and the level of the third reference voltage Vref2, the code generation circuit 650 can generate a power-off temperature code off_code with a third minimum code value.

[0050] When the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 is between the level of the third reference voltage Vref2 and the level of the fourth reference voltage Vref3, the levels of the first to third comparison signals Com1, Com2 and Com3 among the first to fourth comparison signals Com1, Com2 and Com3 and Com4 can be high, while the level of the fourth comparison voltage Com4 can be low.

[0051] When only the first to third comparison signals Com3, Com2, and Com3 among the first to fourth comparison signals Com1, Com2, Com3, and Com4 are at a high level, that is, when the level of the voltage corresponding to the threshold voltage V_mth is between the level of the third reference voltage Vref2 and the level of the fourth reference voltage Vref3, the code generation circuit 650 can generate a power-off temperature code off_code with a fourth minimum code value.

[0052] When the level of the voltage corresponding to the threshold voltage V_mth of the memory cell 310-1 included in the specific region 310 is higher than the level of the fourth reference voltage Vref3, the levels of the first to fourth comparison signals Com1, Com2, Com3 and Com4 can all be high.

[0053] When the levels of the first to fourth comparison signals Com1, Com2, Com3 and Com4 are all high, that is, when the level of the voltage corresponding to the threshold voltage V_mth of the storage cell is higher than the level of the fourth reference voltage Vref3, the code generation circuit 650 can generate the power-off temperature code off_code with the highest code value.

[0054] As mentioned above, Figure 4 The first to fourth comparison circuits 610, 620, 630, and 640 shown can all be configured to determine the level of the threshold voltage V_mth of the memory cell by receiving first to fourth reference voltages Vref0, Vref1, Vref2, and Vref3, respectively. This level is included in any one of a first interval, a second interval, a third interval, a fourth interval, and a fifth interval. In the first interval, the threshold voltage V_mth level is lower than the first reference voltage Vref0 level; in the second interval, the threshold voltage V_mth level is between the first reference voltage Vref0 level and the second reference voltage Vref1 level; in the third interval, the threshold voltage V_mth level is between the second reference voltage Vref1 level and the third reference voltage Vref2 level; in the fourth interval, the threshold voltage V_mth level is between the third reference voltage Vref2 level and the fourth reference voltage Vref3 level; and in the fifth interval, the threshold voltage V_mth level is higher than the fourth reference voltage Vref3 level. Although according to... Figure 4The power-off temperature determination circuit 600 of the embodiment uses four reference voltages and four comparison circuits to determine the level of the threshold voltage V_mth of the memory cell 310-1 based on five intervals. However, according to embodiments of the present disclosure, the number of reference voltages and the number of comparison circuits can be varied to change the number of intervals. For example, a power-off temperature determination circuit according to one embodiment that increases the number of reference voltages at different levels and the number of comparison circuits can be modified and implemented to increase the number of intervals. In contrast, a power-off temperature determination circuit according to one embodiment that decreases the number of reference voltages at different levels and the number of comparison circuits can be modified and implemented to decrease the number of intervals.

[0055] Furthermore, if necessary, the range that can be determined by the power-off temperature determination circuit 600 can be reduced by deactivating one or more of the first to fourth comparison circuits 610, 620, 630, and 640. For example, when the first comparison circuit 610 of the first to fourth comparison circuits 610, 620, 630, and 640 is deactivated, the power-off temperature determination circuit 600 can be configured to determine the level of the threshold voltage V_mth of the memory cell, which is included in any of the following ranges: the range where the threshold voltage V_mth is lower than the level of the second reference voltage Vref1; the range where the threshold voltage V_mth is between the level of the second reference voltage Vref1 and the level of the third reference voltage Vref2; the range where the threshold voltage V_mth is between the level of the third reference voltage Vref2 and the level of the fourth reference voltage Vref3; and the range where the threshold voltage V_mth is higher than the level of the fourth reference voltage Vref3. In other words, when the first comparator circuit 610 of the first to fourth comparator circuits 610, 620, 630, and 640 is deactivated, the power-off temperature determination circuit 600 can be configured to determine one interval among four intervals, including the level of the threshold voltage V_mth. Therefore, a power-off temperature determination circuit comprising multiple comparator circuits can be configured to adjust the number of intervals in which the level of the threshold voltage V_mth is determined by deactivating one or more of the multiple comparator circuits.

[0056] Figure 5 This is for describing a power-off temperature determination circuit according to embodiments of the present disclosure (e.g., Figure 4 The diagram illustrates the operation of the power-off temperature determination circuit 600. In this case, for ease of description, the voltage corresponding to the threshold voltage V_mth of the storage cell 310-1 included in the specific region 310 is referred to as the threshold voltage V_mth of the storage cell 310-1. Furthermore, the power-off temperature code off_code is described as a code value with 3 bits, but embodiments of this disclosure are not limited thereto.

[0057] Reference Figure 5 When the threshold voltage V_mth of the storage cell 310-1 included in the specific region 310 is lower than the level of the first reference voltage Vref0, the power-off temperature determination circuit 600 according to an embodiment of the present disclosure can generate a power-off temperature code off_code with the lowest code value (i.e., code value (0, 0, 0)).

[0058] When the level of the threshold voltage V_mth of the storage cell 310-1 is between the level of the first reference voltage Vref0 and the level of the second reference voltage Vref1, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code with a code value (0, 0, 1).

[0059] When the level of the threshold voltage V_mth of the storage cell 310-1 is between the level of the second reference voltage Vref1 and the level of the third reference voltage Vref2, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code with a code value (0, 1, 0).

[0060] When the threshold voltage V_mth of the storage cell 310-1 is between the level of the third reference voltage Vref2 and the level of the fourth reference voltage Vref3, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code with a code value (0, 1, 1).

[0061] When the threshold voltage V_mth of the storage cell 310-1 is higher than the level of the fourth reference voltage Vref3, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code with the code value (1, 0, 0).

[0062] As a result, the power-off temperature determination circuit 600 can generate a power-off temperature code off_code with a code value based on the change in the threshold voltage of the storage cell 310-1 included in a specific area.

[0063] Figure 6 This is for describing storage devices (e.g., according to embodiments of the present disclosure) Figure 1 A diagram illustrating the operation of storage device 1).

[0064] When power is supplied to the storage device in a power-off state, the control circuit 100 can control the read voltage generation circuit 200 and the storage cell array 300 so that the read voltage Vread, which is at the set level, is provided to the storage cells 310-1 included in a specific region 310 of the storage cell array 300.

[0065] The power-off temperature determination circuit 600 can generate a power-off temperature code off_code, which has a code value that changes based on the level of a threshold voltage V_mth provided by a storage cell 310-1 included in a specific region 310.

[0066] When power is supplied to the storage unit 310-1 in the power-off state, the control circuit 100 can change the level of the read voltage Vread based on the code value of the power-off temperature code off_code within a set time interval.

[0067] refer to Figure 6 The threshold voltage V_mth level of the memory cell 310-1 included in the specific region 310 (i.e., the memory cell 310-1 in the first state SET) can be changed according to the temperature change under the power-off state. For example, the threshold voltage V_mth level of the memory cell 310-1 in the first state SET can be higher at a high temperature than at a low temperature.

[0068] Therefore, the power-off temperature determination circuit 600 of the storage device according to an embodiment of the present disclosure can generate a power-off temperature code (off_code) as the temperature change experienced by the storage device in a power-off state based on the threshold voltage level of the storage cells included in the specific region 310. In other words, the power-off temperature determination circuit 600 can generate a power-off temperature code (off_code) indicating the temperature change that occurs in the storage device in a power-off state based on the threshold voltage level of the storage cells included in the specific region 310.

[0069] In this scenario, the threshold voltage level of each memory cell in the first state SET of the plurality of memory cells included in the memory cell array 300 can also change according to temperature variations. Similar to memory cell 310-1 in a specific region 310, the threshold voltage level of each memory cell in the first state SET of the memory cell array 300 can be higher at high temperatures (High Temp) than at low temperatures (Low Temp). For example, a temperature change in memory cell 310-1 in a specific region 310 of the memory cell array 300 can represent a temperature change in one or more memory cells in another region of the memory cell array 300 designated for storing data received from an external device.

[0070] When a storage device in a power-off state is powered on, the storage device can change the level of the read voltage Vread based on the power-off temperature code off_code. In this case, based on the power-off temperature code off_code, the storage device can provide the storage cell array 300 with a read voltage Vread that is higher when the storage device in a power-off state experiences a high temperature (High Temp) than when the storage device in a power-off state experiences a low temperature (Low Temp). Figure 6 The read voltage Vread when the storage device is in a power-off state and experiences a low temperature is shown as Vread_lt, and the read voltage Vread when the storage device is in a power-off state and experiences a high temperature is shown as Vread_ht.

[0071] Therefore, when a storage device in a power-off state according to an embodiment of the present disclosure is powered on, the storage device can generate a read voltage Vread based on the power-off temperature code off_code within a set time interval (e.g., a preset time interval), and provide the read voltage Vread to the storage cell array 300 after the read operation begins, thereby improving the reliability of data storage in the storage device.

[0072] In other words, when a storage device in a power-off state according to an embodiment of the present disclosure is powered on, the storage device can change the level of the read voltage based on the change of the threshold voltage of the storage cells included in a specific region within a set time interval, and can provide the read voltage to the storage cell array 300 after the read operation begins.

[0073] Figure 7 This is for describing storage devices (e.g., according to embodiments of the present disclosure) Figure 1 A flowchart of the operation of the storage device 1).

[0074] Reference Figure 7 The operation method of the storage device according to the embodiments of the present disclosure may include a power-off process S1, a specific cell initialization process S2, a power-on process S3, a time elapsed determination process S4, a first read voltage provision process S5, and a second read voltage provision process S6.

[0075] The power outage process S1 may include cutting off the power applied to the storage device. For example, the power applied to the storage device may be intentionally or accidentally cut off.

[0076] The specific cell initialization process S2 may include writing to at least one memory cell (e.g., memory cell 310-1 included in a specific region 310 of the memory cell array 300) in a predetermined state (e.g., first state SET) during the power failure process S1. For example, in the specific cell initialization process S2, when the power applied to the memory device is cut off, the memory device may perform a write operation on the memory cell 310-1 included in the specific region 310 to give the memory cell 310-1 a predetermined state (e.g., first state SET).

[0077] The power-on process S3 may include supplying power to the storage device. In one embodiment, the power-on process S3 may include providing a set voltage to a storage cell 310-1 in a first state SET included in a specific region 310, and generating a power-off temperature code off_code based on the level of a threshold voltage of the storage cell 310-1 in the first state SET.

[0078] The time elapsed determination process S4 may include determining whether a preset time interval has elapsed since the power-on process S3. For example, the time elapsed determination process S4 may include determining whether a preset time interval has elapsed since power was supplied to switch the storage device from a power-off state to a power-on state.

[0079] For example, if it is determined in the time elapsed determination process S4 that a preset time interval has not elapsed since the power-on process S3 (no), the first read voltage supply process S5 can be executed.

[0080] When it is determined in the time elapsed determination process S4 that a preset time interval has elapsed since the power-on process S3 (yes), the second reading voltage provision process S6 can be executed.

[0081] The first read voltage execution process S5 may include providing a read voltage Vread to the memory cell array 300 based on the power-off temperature code off_code after the start of the read operation. After the first read voltage execution process S5 is completed, the time elapsed determination process S4 may be executed again. Therefore, if a preset time interval has not elapsed after the power-on process S3, the first read voltage execution process S5 may be a process executed whenever a read operation is performed.

[0082] The second read voltage execution process S6 may include a process of providing a read voltage Vread to the memory cell array 300 based on the current temperature. In this case, the second read voltage execution process S6 may include a process in which the control circuit 100 controls the read voltage generation circuit 200 based on the power-on temperature code on_code provided by the temperature sensor 500. As a result, whenever a read operation is performed, the read voltage generation circuit 200 generates a read voltage Vread to be provided to the memory cell array 300.

[0083] In one embodiment, a method of operating a storage device including a storage cell array includes: generating a power-off temperature code based on characteristics of at least one storage cell in a specific region of the storage cell array, the power-off temperature code indicating a temperature change occurring in the storage device during a power-off state; and generating a read voltage based on the power-off temperature code to provide the read voltage to the storage cell array. For example, the characteristic of the at least one storage cell may be its threshold voltage.

[0084] In one embodiment, the method further includes writing to at least one memory cell to have a predetermined state when the power to the storage device is cut off.

[0085] In one embodiment, the method further includes applying power to the storage device. After applying power to the storage device, a read voltage is generated based on the level of a threshold voltage of at least one storage cell.

[0086] In one embodiment, at least one storage cell is in a set state.

[0087] In one embodiment, applying power includes supplying a read voltage of a given level to at least one memory cell in a set state. A power-off temperature code is generated based on the level of a threshold voltage of the at least one memory cell.

[0088] In one embodiment, generating the read voltage includes providing a read voltage to the memory cell array based on a power-off temperature code within a preset time interval after power is applied to the memory device.

[0089] In one embodiment, generating the read voltage further includes providing the read voltage to the memory cell array based on the power-on temperature code of a temperature sensor after a preset time interval has elapsed.

[0090] In one embodiment, generating a power-off temperature code includes comparing the level of each of a plurality of reference voltages having different levels with the level of a threshold voltage of at least one memory cell.

[0091] Although some embodiments of this disclosure have been described above with reference to the accompanying drawings, the embodiments of this disclosure are not limited to those described above. Those skilled in the art to which this disclosure pertains can substitute, modify, and change the embodiments in various ways. Such substitutions, modifications, and changes can fall within the scope of the various embodiments of this disclosure.

Claims

1. A storage device, comprising: A storage cell array, which comprises multiple storage cells; A power-off temperature determination circuit generates a power-off temperature code based on the threshold voltage level of at least one memory cell included in a specific region of the memory cell array. The control circuit, which: generates a voltage control signal based on the power-off temperature code; and The read voltage generation circuit provides a read voltage to the memory cell array based on the voltage control signal.

2. The storage device according to claim 1, wherein, When the power applied to the storage device is cut off, the storage device performs a write operation on the at least one storage cell to have a predetermined state.

3. The storage device according to claim 2, wherein, The power-off temperature determination circuit generates the power-off temperature code with a code value based on the level of the change in the threshold voltage of the at least one storage cell.

4. The storage device according to claim 3, wherein, The control circuit generates the voltage control signal based on the power-off temperature code, such that the level of the read voltage changes based on the level of the change in the threshold voltage of the at least one storage cell.

5. The storage device according to claim 1, wherein: The plurality of storage units includes at least one storage unit included in the specific region; Each of the plurality of storage units is switched to either the first state or the second state; and The first level of the first threshold voltage of each of the plurality of memory cells in the first state is lower than the second level of the second threshold voltage of each of the plurality of memory cells in the second state.

6. The storage device according to claim 5, wherein, When the power applied to the storage device is cut off, the at least one storage cell included in the specific area switches to the first state.

7. The storage device according to claim 6, wherein, The control circuit generates the voltage control signal based on the power-off temperature code, such that the level of the read voltage increases as the level of the first threshold voltage of the at least one memory cell in the first state increases.

8. The storage device according to claim 1, further comprising a temperature sensor, the temperature sensor generating an on-state temperature code based on changes in the current temperature of the storage device.

9. The storage device according to claim 8, wherein, After power is supplied to the storage device, the control circuit generates the read voltage based on the power-off temperature code within a preset time interval, and after the preset time interval has elapsed, the control circuit generates the read voltage based on the power-on temperature code.

10. The storage device according to claim 1, wherein: The power-off temperature determination circuit includes multiple comparison circuits; and The plurality of comparison circuits respectively receive a plurality of reference voltages having a plurality of different levels, and each of the plurality of comparison circuits compares the level of the threshold voltage of the at least one memory cell with the level of the corresponding reference voltage among the plurality of reference voltages.

11. The storage device according to claim 10, wherein, The power-off temperature determination circuit further includes a code generation circuit, which generates the power-off temperature code based on the comparison results output from the plurality of comparison circuits.

12. The storage device according to claim 11, wherein, The code generation circuit generates the power-off temperature code with a code value that increases as the level of the threshold voltage of the at least one storage cell increases.

13. A method of operating a storage device including an array of storage cells, comprising: A power-off temperature code is generated based on the characteristics of at least one storage cell in a specific region of the storage cell array, the power-off temperature code indicating the temperature change that occurs in the storage device in a power-off state. and A read voltage is generated based on the power-off temperature code, and the read voltage is provided to the storage cell array.

14. The operating method according to claim 13, further comprising: When the power supply to the storage device is cut off, the at least one storage cell is written to have a predetermined state.

15. The method of operation according to claim 14, further comprising applying the power supply to the storage device. in, The read voltage is generated based on the threshold voltage level of the at least one memory cell after the power is applied to the memory device.

16. The operating method according to claim 15, wherein, The predetermined state of the at least one storage unit is a set state.

17. The operating method according to claim 16, wherein, Applying the power supply includes providing the read voltage with a given level to the at least one memory cell in the set state. The power-off temperature code is generated based on the level of the threshold voltage of the at least one storage cell.

18. The operating method according to claim 17, wherein, Generating the read voltage includes: after applying the power supply to the storage device, providing the read voltage to the storage cell array based on the power-off temperature code within a preset time interval.

19. The operating method according to claim 18, wherein, Generating the read voltage further includes: after the preset time interval has elapsed, providing the read voltage to the storage cell array based on the power-on temperature code of the temperature sensor.

20. The operating method according to claim 17, wherein, Generating the power-off temperature code includes comparing the level of each of a plurality of reference voltages with different levels with the level of the threshold voltage of the at least one memory cell.

21. The operating method according to claim 20, wherein, Generating the power-off temperature code includes generating the power-off temperature code based on the interval corresponding to the threshold voltage of the at least one memory cell among the intervals to which the plurality of reference voltages belong.

22. A method of operating a storage device, comprising: The power to the storage device was cut off; and When the power supply to the storage device is cut off, a specific cell is written to in a predetermined state.

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