Memory device, operating method thereof and memory system
By dividing the memory array into two arrays and using progressively increasing pulses with different timings during read/write and idle phases, the correlation between timing and reliability in memory devices is resolved, resulting in faster data storage speeds and higher reliability.
Patent Information
- Application Number
- CN202411199188.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-20
- Filing Date
- 2024-08-29
- Publication Date
- 2026-03-03
AI Technical Summary
Existing memory devices exhibit a correlation between progressively increasing pulse write steps and reliability, impacting the balance between storage speed and reliability.
The memory array is divided into two different arrays, and different write steps are used to gradually increase the pulse writing during the read/write phase and the idle phase. The voltage value is controlled by the array control circuit and the voltage generator, and the data is transferred from the buffer array to the background array during the idle phase.
While maintaining reliability, the speed and efficiency of data storage are improved, and the performance of the memory device is optimized by buffering temporary data and storing background data.
Smart Images
Figure CN121600979A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to storage technology for memory devices, and in particular to memory devices, methods of operation, and memory systems that use multiple sub-blocks to store / temporarily store data at different stages. Background Technology
[0002] With the development of IoT and 5G technologies, the amount of data involved in computing is becoming increasingly massive, thus requiring storage speeds for memory devices. To optimize storage speed, some approaches use incremental step pulse programming (ISPP) to design the write speed of memory devices.
[0003] However, the step size of the ISPP of a memory device affects the distribution of the output voltage of the memory array, which in turn affects the reliability of the memory device during operation. This phenomenon also requires memory devices to make trade-offs between ISPP step size and reliability. Therefore, how to reduce the correlation between ISPP step size and reliability is one of the issues in this field. Summary of the Invention
[0004] This disclosure provides a memory device including a memory array, a voltage generator, and an array control circuit. The memory array includes a first array and a second array. The voltage generator is coupled to the memory array. The array control circuit is coupled to the memory array and the voltage generator, and is configured to: during read / write phases of the memory array, control the voltage generator to generate a first control voltage to the memory array, and generate a temporary address to control the first array to store stored data and address data in a first write step according to the temporary address and the first control voltage; during idle phases of the memory array, control the voltage generator to generate a second control voltage to the memory array, control the second array to store stored data in a second write step according to the address data and the second control voltage, and control the first array to perform a clear operation. The voltage value of the first write step is greater than the voltage value of the second write step.
[0005] In some embodiments of the memory device, the memory device further includes input circuitry. The input circuitry is coupled to the memory array and array control circuitry to split input data into storage data and address data.
[0006] In some embodiments of the memory device, the memory device further includes a detection and adjustment circuit. The detection and adjustment circuit is coupled to a voltage generator and an array control circuit to adjust the voltage values of a first write step and a second write step according to at least one adjustment parameter during read / write and idle phases.
[0007] In some embodiments of the memory device, the memory array is used to generate a plurality of first output voltages based on a first control voltage, the plurality of first output voltages forming a plurality of non-overlapping first subsets in an output voltage-quantity graph. The memory array is also used to generate a plurality of second output voltages based on a second control voltage, the plurality of second output voltages forming a plurality of non-overlapping second subsets in an output voltage-quantity graph.
[0008] In some embodiments of the memory device, the spacing between adjacent pairs in a plurality of first subsets is negatively correlated with the voltage value of a first write step, and the spacing between adjacent pairs in a plurality of second subsets is negatively correlated with the voltage value of a second write step.
[0009] In some embodiments of the memory device, the memory array is divided into multiple sub-blocks according to multiple word lines, one of the multiple sub-blocks is used as at least part of a first array, and at least one of the remaining multiple sub-blocks is used as a second array.
[0010] In some embodiments of the memory device, the memory array is divided into multiple sub-blocks according to multiple word lines, with a first block of each of the multiple sub-blocks serving as a first array, and a second block of each of the multiple sub-blocks serving as a second array.
[0011] In some embodiments of the memory device, the voltage value of the first write step is between 1 volt and 3 volts.
[0012] This disclosure provides an operating method applicable to a memory device, comprising: receiving stored data and address data through a memory array of the memory device; during a read / write phase of the memory array, activating a voltage generator of the memory device through an array control circuit of the memory device to generate a first control voltage to the memory array; during the read / write phase, generating a temporary address through the array control circuit to control a first array of the memory array to store the stored data and address data in a first write step according to the temporary address and the first control voltage; during an idle phase of the memory array, activating a voltage generator through the array control circuit to generate a second control voltage to the memory array; during the idle phase, controlling a second array of the memory array to store the stored data in a second write step according to the address data and the second control voltage through the array control circuit; and during the idle phase, controlling the first array to perform a clear operation through the array control circuit. The voltage value of the first write step is greater than the voltage value of the second write step.
[0013] In some embodiments of the operating method, receiving stored data and address data via the memory array of the memory device includes: receiving input data via the input circuit of the memory device; splitting the input data into stored data and address data via the input circuit; and transmitting the stored data and address data to the memory array via the input circuit.
[0014] In some embodiments of the operating method, the operating method further includes: during the read / write phase, adjusting the voltage value of a first write step according to at least one adjustment parameter by a detection and adjustment circuit of the memory device; and during the idle phase, adjusting the voltage value of a second write step according to at least one adjustment parameter by a detection and adjustment circuit.
[0015] In some embodiments of the operating method, the operating method further includes: generating a plurality of first output voltages based on a first control voltage via a memory array, wherein the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-quantity graph; and generating a plurality of second output voltages based on a second control voltage via a memory array, wherein the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in an output voltage-quantity graph.
[0016] In some embodiments of the operation method, the spacing between adjacent pairs in a plurality of first subsets is negatively correlated with the voltage value of the first write step, and the spacing between adjacent pairs in a plurality of second subsets is negatively correlated with the voltage value of the second write step.
[0017] In some embodiments of the operating method, the operating method further includes: dividing a memory array into a plurality of sub-blocks via a plurality of word lines of the memory device; configuring at least partially one of the plurality of sub-blocks as a first array via array control circuitry; and configuring at least one of the remaining plurality of sub-blocks as a second array via array control circuitry.
[0018] In some embodiments of the operating method, the operating method further includes: dividing a memory array into a plurality of sub-blocks via a plurality of word lines of the memory device; configuring a first block of each of the plurality of sub-blocks into a first array via an array control circuit; and configuring a second block of each of the plurality of sub-blocks into a second array via the array control circuit.
[0019] In some embodiments of the operating method, the voltage value of the first write step is between 1 volt and 3 volts.
[0020] This disclosure provides a memory system comprising a plurality of memory devices. Each of the plurality of memory devices includes a memory array, a voltage generator, and array control circuitry. The voltage generator is coupled to the memory array. The array control circuitry is coupled to the memory array and the voltage generator. The memory array of at least one first memory device among the plurality of memory devices is configured as a first array, and the memory array of at least one second memory device among the plurality of memory devices is configured as a second array. During the read / write phase of the memory system, the array control circuitry of the at least one first memory device controls the voltage generator of the at least one first memory device to generate a first control voltage to the first array, and generates a temporary address to the first array, so as to control the first array to store stored data and address data in a first write step according to the temporary address and the first control voltage. During the read / write phase of the memory system, the array control circuitry of the at least one second memory device controls the voltage generator of the at least one second memory device to generate a second control voltage to the second array, and controls the second array to store stored data in a second write step according to the address data and the second control voltage, and the array control circuitry of the at least one first memory device controls the first array to perform a clear operation. The voltage value of the first write step is greater than the voltage value of the second write step.
[0021] In some embodiments of the memory system, each of the multiple memory devices further includes input circuitry. The input circuitry is coupled to the memory array and array control circuitry to split the input data into storage data and address data.
[0022] In some embodiments of the memory system, each of the multiple memory devices further includes a detection and adjustment circuit. The detection and adjustment circuit is coupled to a voltage generator and an array control circuit to adjust the voltage values of a first write step and a second write step according to at least one adjustment parameter during read / write and idle phases.
[0023] In some embodiments of the memory system, the memory array is used to generate a plurality of first output voltages based on a first control voltage, the plurality of first output voltages forming a plurality of non-overlapping first subsets in an output voltage-quantity graph. The memory array is used to generate a plurality of second output voltages based on a second control voltage, the plurality of second output voltages forming a plurality of non-overlapping second subsets in an output voltage-quantity graph. The spacing between adjacent pairs in the plurality of first subsets is negatively correlated with the voltage value of a first write step, and the spacing between adjacent pairs in the plurality of second subsets is negatively correlated with the voltage value of a second write step.
[0024] The memory device, its operation method, and memory system disclosed herein enable the memory array responsible for executing temporary and stored data to be divided and ISPP to be executed at different step sizes, thereby effectively improving the speed of data storage while maintaining reliability. Attached Figure Description
[0025] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings.
[0026] Figure 1 A functional block diagram of a memory device according to an embodiment of the present disclosure is schematically shown;
[0027] Figure 2 This schematically illustrates a diagram showing the number of output voltages for multiple subsets of the output voltages according to embodiments of the present disclosure.
[0028] Figure 3 This illustration schematically shows the relationship between adjusting parameters and gradually increasing the pulse write (ISPP) size and total runtime according to an embodiment of the present disclosure;
[0029] Figure 4 A flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure is shown schematically.
[0030] Figures 5A to 5F A schematic diagram illustrating the configuration of the first array and the second array in the memory array according to an embodiment of the present disclosure is shown.
[0031] Figure 6 A schematic diagram illustrating the configuration of a first array and a second array in a memory system according to an embodiment of the present disclosure is shown.
[0032] Explanation of reference numerals in the attached figures:
[0033] 100: Memory device
[0034] 110: Input Circuit
[0035] 120: Memory Array
[0036] 130: Voltage Generator
[0037] 140: Logic Circuits
[0038] 150: Array control circuit
[0039] 160: Detection and adjustment circuit
[0040] 400: Operating Instructions
[0041] S410, S420, S430, S440: Steps
[0042] S450, S455, S460, S470: Steps
[0043] S480, S490: Steps
[0044] 600: Memory System
[0045] ADD: Address Data
[0046] DATA: Stored data
[0047] G1~G4: Subsets
[0048] IN: Input data
[0049] P1~P4: Plane
[0050] T1: First array
[0051] T2: Second Array
[0052] V1, V2: Control voltage
[0053] Vt: Output voltage
[0054] W1, W2: Spacing. Detailed Implementation
[0055] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0056] In this disclosure, when an element is referred to as a "connection," it may mean an "electrical connection" or an "optical connection," and when an element is referred to as a "coupled connection," it may mean an "electrical coupling" or an "optical coupling." "Connection" or "coupled connection" may also be used to indicate the operation or interaction between two or more elements. Unless specifically defined herein, "a" and "the" may refer to one or more in general. It will be further understood that the terms "comprising," "including," "having," and similar words as used herein specify the features, regions, integers, steps, operations, elements, and / or components described herein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof described or additionally.
[0057] Figure 1 This is a functional block diagram of a memory device 100 illustrated according to some embodiments of this disclosure. In some embodiments, the memory device 100 includes an input circuit 110, a memory array 120, a voltage generator 130, logic circuitry 140, array control circuitry 150, and detection and adjustment circuitry 160.
[0058] Input circuit 110 is coupled to memory array 120 and array control circuit 150 to receive input data IN, split the input data IN into storage data DATA and address data ADD, and transmit the split storage data DATA and address data ADD to memory array 120. In some embodiments, when input circuit 110 receives input data IN, it sends a signal to array control circuit 150 to instruct array control circuit 150 to perform a corresponding operation (which will be described in detail in subsequent paragraphs).
[0059] The memory array 120 is coupled to the input circuit 110, the voltage generator 130 and the array control circuit 150 to receive stored data DATA and address data ADD from the input circuit 110, control voltages V1 and V2 from the voltage generator 130, and a temporary address (not shown) from the array control circuit 150. The array array 120 also temporarily stores and reads the stored data DATA according to the address data ADD, the control voltages V1 and V2 and the temporary address.
[0060] In some embodiments, the memory array 120 may be implemented as a two-dimensional memory array, a three-dimensional memory array, or a combination thereof. Furthermore, it should be noted that in some embodiments, the memory array 120 further includes word line decoders and bit line decoders. For the sake of simplicity in the diagram, these elements are... Figure 1 The middle part is omitted.
[0061] In some embodiments, the memory array 120 includes a first array T1 and a second array T2 for temporarily / storing stored data DATA in different operating phases of the memory array 120.
[0062] In detail, firstly, during the read / write phase, the memory array 120 performs incremental step pulse programming (ISPP) based on a first write step to temporarily store the stored data DATA in the first array T1, making the first array T1 a buffer. Then, when the memory array 120 enters an idle phase, it performs ISPP based on a second write step to store (i.e., transfer) the stored data DATA temporarily stored in the first array T1 to the second array T2, allowing the second array T2 to operate in the background. Furthermore, the memory array 120 also clears the stored data DATA temporarily stored in the first array T1 at this time. In some embodiments, the first write step and the second write step are each a specific voltage value.
[0063] Voltage generator 130 is coupled to memory array 120, logic circuit 140, array control circuit 150 and detection and adjustment circuit 160 to generate control voltages V1 and V2 to memory array 120 based on the control of logic circuit 140, array control circuit 150 and detection and adjustment circuit 160.
[0064] The logic circuit 140 is coupled to the voltage generator 130, the array control circuit 150 and the detection and adjustment circuit 160, and is used to control the magnitude of the voltage generated by the voltage generator 130 based on the activation of the array control circuit 150 and the adjustment of the detection and adjustment circuit 160.
[0065] Array control circuit 150 is coupled to input circuit 110, memory array 120, voltage generator 130, logic circuit 140, and detection and adjustment circuit 160. It receives signals from input circuit 110 to generate a temporary address and activates voltage generator 130 and logic circuit 140 to control voltage generator 130 to generate voltage. In some embodiments not shown, array control circuit 150 may be located within logic circuit 140.
[0066] The detection and adjustment circuit 160 is coupled to the voltage generator 130, the logic circuit 140, and the array control circuit 150 to detect adjustment parameters of the memory device 100 (e.g., temperature, pressure, number of usage cycles, interference during reads, etc.) and adjust the step size of the memory array 120 when performing incremental step pulse programming (ISPP) based on these adjustment parameters. In some embodiments, the detection and adjustment circuit 160 may be omitted.
[0067] In some embodiments, the classification of data stored in the memory array 120 can be determined by its output voltage. In other words, the voltages output by the memory array 120 can be grouped to correspond to different data. Figure 2 This is a schematic diagram illustrating the number of output voltages Vt of a subset G1 to G4 of the output voltage Vt of a memory array 120 according to some embodiments of this disclosure.
[0068] First, please see Figure 2 The upper half. In some embodiments, by statistically analyzing the types and quantities of the output voltage Vt of the memory array 120, the output voltage Vt can be divided into multiple non-overlapping subsets (e.g., subsets G1~G4), and each subset corresponds to one type of data. Therefore, Figure 2 The subsets G1 to G4 in the dataset can be used to distinguish four types of data.
[0069] However, the output voltage Vt may change its distribution due to various factors (e.g., increased device temperature, increased number of usage cycles, interference during reading, etc.). For details, please see... Figure 2 The lower half. Under the influence of the aforementioned factors, the output voltage Vt of the memory array 120 will gradually become more dispersed, that is, the width of subsets G1 to G4 will increase. As the width of each subset increases, the spacing between adjacent subsets will decrease (e.g., from spacing W1 to spacing W2). When adjacent subsets overlap, since the same output voltage Vt may correspond to two subsets, it will cause data resolution errors in the memory device 100.
[0070] To avoid overlap between adjacent subsets due to the aforementioned factors, a larger spacing is required between subsets. In some embodiments, the step size of the memory array 120 during incremental pulse write (ISPP) is negatively correlated with the spacing between multiple subsets of the output voltage Vt. In other words, the smaller the step size of ISPP, the larger the spacing between adjacent subsets, and the higher the reliability of the memory device.
[0071] Figure 3 This is a schematic diagram illustrating the relationship between adjustment parameters and progressively increasing pulse write (ISPP) size and total runtime, according to some embodiments of this disclosure. Figure 3 As shown, the step size of ISPP can be adjusted by adjusting parameters (e.g., the aforementioned device temperature, number of usage cycles, interference during reads, etc.). However, when the step size of ISPP decreases, it means that the time required to complete ISPP will increase, thereby lengthening the total runtime of the memory device.
[0072] To optimize the relationship between ISPP step size (i.e. reliability) and the execution efficiency of the memory device, the memory device 100 disclosed in this disclosure achieves improved benefits by dividing the memory array 120 into two different arrays and performing ISPP with different step sizes.
[0073] Figure 4 This is a flowchart illustrating an operation method 400 of a memory device according to some embodiments of this disclosure. In some embodiments, the operation method 400 is applicable to a memory device (e.g., Figure 1 The memory device 100 includes steps S410, S420, S430, S440, S450, S455, S460, S470, S480, and S490.
[0074] In step S410, through the input circuit (e.g., Figure 1The input circuit 110 receives input data, splits the input data into storage data and address data, and transmits them to the memory array (e.g., Figure 1 The memory array 120), and then transmits signals to the array control circuit (e.g., the memory array 120), and then transmits signals to the array control circuit (e.g., Figure 1 (Array control circuit 150). Next, step S420 is executed.
[0075] In step S420, the array control circuit receives a signal from the input circuit and generates a temporary address for the memory array. Then, step S430 is executed.
[0076] In step S430, the adjustment circuit (e.g., is detected) is adjusted. Figure 1 The detection and adjustment circuit 160 detects at least one adjustment parameter (e.g., temperature, pressure, number of usage cycles, interference during reading, etc.) and adjusts the voltage value of the first write step according to the detected adjustment parameter. Then, step S440 is executed.
[0077] In step S440, the voltage generator is activated via the array control circuit (e.g., Figure 1 The voltage generator 130 and logic circuitry are used to cause the voltage generator to generate a first control voltage (e.g., Figure 1 The control voltage V1 is supplied to the memory array. Next, step S450 is executed.
[0078] In step S450, the first array of the memory array (e.g., Figure 1 The first array T1 performs ISPP in a first write step according to the temporary address and the first control voltage to temporarily store the stored data and address data. Then, step S455 is executed. In some embodiments, the stages from steps S410 to S450 can be referred to as the read / write stages of the memory array.
[0079] In step S455, the array control circuit determines whether the memory array has completed the read / write phase (i.e., temporarily storing the stored data and address data in the first array). If the array control circuit determines that the memory array has completed the read / write phase, step S460 is executed; if the array control circuit determines that the memory array has not yet completed the read / write phase, step S455 is repeated.
[0080] In step S460, the voltage generator and logic circuit are restarted via the array control circuit to cause the voltage generator to produce a second control voltage (e.g., Figure 1 The control voltage V2 is supplied to the memory array. Next, step S470 is executed.
[0081] In step S470, the adjustment parameters are detected again by the adjustment detection circuit, and the voltage value of the second write step is adjusted according to the detected adjustment parameters. Then, step S480 is executed.
[0082] In step S480, the second array of the memory array (e.g., Figure 1 The second array (T2) performs ISPP in the second write step according to the address data and the second control voltage to store the stored data. Then, step S490 is executed.
[0083] In step S490, the array control circuit controls the first array to perform a clearing operation to clear the stored data and address data temporarily stored in the first array. In some embodiments, the stages from steps S460 to S490 can be referred to as the idle stage of the memory array.
[0084] It is worth noting that since the stored data and address data are only temporarily stored in the first array during the read / write phase and are not stored for a long time or subjected to multiple read / write operations, the stress on the first array is relatively small. Therefore, a higher voltage can be used in the first write step to improve the write speed. In some embodiments, the voltage value of the first write step is between 1 volt and 3 volts.
[0085] In contrast, since the second array is used to store data for a long time and is under greater pressure, in some embodiments the voltage value of the second write step is lower than the voltage value of the first write step (i.e., a lower voltage is used during the idle phase) to increase the reliability of the memory device.
[0086] It should be noted that the number and order of steps in the operation method 400 of this disclosure are merely examples and are not intended to limit this disclosure. The number and order of other steps are all within the scope of this disclosure. In some embodiments, steps S430 and S470 may be omitted. In some embodiments, step S456 may be included between steps S455 and S460: transmitting stored data and address data back to the array control circuit via the first array.
[0087] By dividing the memory array into two arrays and performing ISPP on the two arrays with different write steps, the memory device 100 of this disclosure can maintain stable reliability while increasing write speed. Furthermore, by using one array as a buffer to temporarily store data and the other array to store data in the background, the memory device 100 of this disclosure can also improve the efficiency of data storage.
[0088] Figures 5A to 5F This is a schematic diagram illustrating the distribution of a first array and a second array in a memory array according to some embodiments of this disclosure. Figures 5A to 5F In one embodiment, the memory array is implemented by a three-dimensional memory array, and this memory array is divided into multiple sub-blocks by multiple word lines (not shown).
[0089] exist Figures 5A to 5C In one embodiment, at least a portion of one sub-block of the memory array is configured as a first array, and the remaining portion of that sub-block and other sub-blocks are configured as a second array. For example, in Figure 5A In one embodiment, a complete sub-block is configured as a first array, and the other sub-blocks are configured as a second array; Figure 5B In one embodiment, a specific layer within a sub-block is configured as a first array, and the other layers of that sub-block and other sub-blocks are configured as a second array; Figure 5C In one embodiment, multiple memory cells sharing the same specific positioning line (not shown) in a specific layer of a sub-block are configured as a first array, and other memory cells of the sub-block and other sub-blocks are configured as a second array.
[0090] exist Figures 5D to 5F In some embodiments, at least a portion of each sub-block of the memory array is configured as a first array, and the remaining portion of these sub-blocks is configured as a second array. For example, in Figure 5D In one embodiment, multiple memory cells sharing the same specific positioning line (not shown) in each sub-block are configured as a first array, and other memory cells in the sub-block are configured as a second array; Figure 5E In one embodiment, a specific layer in each sub-block is configured as a first array, and the other layers of the sub-block are configured as a second array; Figure 5F In one embodiment, multiple memory cells sharing the same specific positioning line (not shown) in a specific layer of each sub-block are configured as a first array, and other memory cells in the sub-block are configured as a second array.
[0091] It should be noted that Figures 5A to 5F The configurations of the first and second arrays described herein are merely examples and are not intended to limit this disclosure. Other configurations of the first and second arrays are within the scope of this disclosure. In some embodiments, the first array may be configured to be located in the lower layer or to the right of the sub-block. In other embodiments, the first array may be configured to surround the second array.
[0092] Figure 6 This is a schematic diagram illustrating the distribution of a first array and a second array in a memory system 600 according to some embodiments of this disclosure. In some embodiments, the memory system 600 may be implemented by a chip comprising planes P1 to P4, wherein each of planes P1 to P4 may be comprised of a memory device (e.g., Figure 1 The memory device 100 in the middle is implemented, so the construction of planes P1 to P4 will not be repeated below.
[0093] Compared to Figures 5A to 5F At least a portion of the memory devices in the array are configured as a first array and the remainder are configured as a second array. Figure 6 In some embodiments, at least one plane (e.g., plane P2) is configured as a first array, while other planes (e.g., planes P1, P3, P4) are configured as a second array. In other words, in Figure 6 In one embodiment, the memory system 600 includes a plurality of memory devices, and the entire memory array of at least one memory device is configured as a first array, while the entire memory arrays of the other memory devices are configured as a second array. Therefore, the memory system 600, which includes a plurality of memory devices, can perform similar functions to the memory device 100 described above.
[0094] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A memory device comprising: A memory array comprising a first array and a second array; A voltage generator is coupled to the memory array; and An array control circuit, coupled to the memory array and the voltage generator, is used to: During a read / write phase of this memory array: The voltage generator is controlled to produce a first control voltage to the memory array; and A temporary address is generated to control the first array to store storage data and address data in a first write step according to the temporary address and the first control voltage. During an idle phase of the memory array: The voltage generator is controlled to produce a second control voltage to the memory array; The second array is controlled to store the stored data in a second write step according to the address data and the second control voltage; and Control the first array to perform a clearing operation. The voltage value of the first write step is greater than the voltage value of the second write step.
2. The memory device of claim 1 further includes an input circuit coupled to the memory array and the array control circuit for splitting an input data into the stored data and the address data.
3. The memory device of claim 1 further includes a detection adjustment circuit coupled to the voltage generator and the array control circuit for adjusting the voltage value of the first write step and the voltage value of the second write step according to at least one adjustment parameter during the read / write phase and the idle phase.
4. The memory device of claim 1, wherein the memory array is configured to generate a plurality of first output voltages based on the first control voltage, the plurality of first output voltages forming a plurality of non-overlapping first subsets in an output voltage-quantity graph, and The memory array is used to generate multiple second output voltages based on the second control voltage, and the multiple second output voltages form multiple non-overlapping second subsets in the output voltage-quantity diagram.
5. The memory device of claim 4, wherein the spacing between adjacent pairs in the plurality of first subsets is negatively correlated with the voltage value of the first write step, and the spacing between adjacent pairs in the plurality of second subsets is negatively correlated with the voltage value of the second write step.
6. The memory device of claim 1, wherein the memory array is divided into a plurality of sub-blocks according to a plurality of word lines, one of the plurality of sub-blocks is used to at least partially serve as the first array, and at least one of the remaining plurality of sub-blocks is used to serve as the second array.
7. The memory device of claim 1, wherein the memory array is divided into a plurality of sub-blocks according to a plurality of word lines, a first block of each of the plurality of sub-blocks is used as the first array, and a second block of each of the plurality of sub-blocks is used as the second array.
8. The memory device of claim 1, wherein the voltage value of the first write step is between 1 volt and 3 volts.
9. An operating method applicable to a memory device, comprising: The memory device receives stored data and address data through a memory array. During a read / write phase of the memory array, a voltage generator of the memory device is activated by an array control circuit of the memory device to generate a first control voltage to the memory array. During the read / write phase, a temporary address is generated by the array control circuit to control a first array of the memory array to store the stored data and the address data in a first write step according to the temporary address and the first control voltage. During an idle phase of the memory array, the voltage generator is activated by the array control circuit to generate a second control voltage to the memory array. During the idle phase, the array control circuit controls a second array of the memory array to store the stored data in a second write step according to the address data and the second control voltage; and During this idle phase, the array control circuit controls the first array to perform a clearing operation. The voltage value of the first write step is greater than the voltage value of the second write step.
10. The method of operation according to claim 9, wherein receiving the stored data and the address data via the memory array of the memory device includes: The memory device receives input data through an input circuit. The input circuit splits the input data into the stored data and the address data; and The stored data and the address data are transmitted to the memory array through the input circuit.
11. The operating method according to claim 9, further comprising: During the read / write phase, a detection and adjustment circuit of the memory device adjusts the voltage value of the first write step according to at least one adjustment parameter; and During the idle phase, the voltage value of the second write step is adjusted by the detection and adjustment circuit according to the at least one adjustment parameter.
12. The operating method according to claim 9, further comprising: The memory array generates a plurality of first output voltages based on the first control voltage, wherein the plurality of first output voltages form a plurality of non-overlapping first subsets in an output voltage-quantity graph; and The memory array generates a plurality of second output voltages based on the second control voltage, wherein the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram.
13. The method of operation according to claim 12, wherein the spacing between adjacent pairs in the plurality of first subsets is negatively correlated with the voltage value of the first write step, and the spacing between adjacent pairs in the plurality of second subsets is negatively correlated with the voltage value of the second write step.
14. The operating method according to claim 9, further comprising: The memory array is divided into multiple sub-blocks by multiple word lines of the memory device; The array control circuit configures at least partially one of the plurality of sub-blocks as the first array; and The array control circuit configures at least one of the remaining sub-blocks as the second array.
15. The operating method according to claim 9, further comprising: The memory array is divided into multiple sub-blocks by multiple word lines of the memory device; The array control circuit configures a first block of each of the plurality of sub-blocks into the first array; and The array control circuit configures a second block of each of the plurality of sub-blocks into the second array.
16. The method of operation according to claim 9, wherein the voltage value of the first write step is between 1 volt and 3 volts.
17. A memory system comprising a plurality of memory devices, wherein each of the plurality of memory devices comprises: A memory array; A voltage generator is coupled to the memory array; and An array control circuit is coupled to the memory array and the voltage generator. The memory array of at least one first memory device among the plurality of memory devices is configured as a first array, and the memory array of at least one second memory device among the plurality of memory devices is configured as a second array. In a read / write phase of the memory system, the array control circuit of the at least one first memory device controls the voltage generator of the at least one first memory device to generate a first control voltage to the first array, and generates a temporary address to the first array, so as to control the first array to store a storage data and an address data in a first write step according to the temporary address and the first control voltage. During an idle phase of the memory system, the array control circuit of the at least one second memory device controls the voltage generator of the at least one second memory device to generate a second control voltage to the second array, thereby controlling the second array to store the stored data in a second write step according to the address data and the second control voltage. The array control circuit of the at least one first memory device also controls the first array to perform a clear operation. The voltage value of the first write step is greater than the voltage value of the second write step.
18. The memory system of claim 17, wherein each of the plurality of memory devices further includes an input circuit coupled to the memory array and the array control circuit for splitting an input data into the stored data and the address data.
19. The memory system of claim 17, wherein each of the plurality of memory devices further includes a detection adjustment circuit coupled to the voltage generator and the array control circuit for adjusting the voltage value of the first write step and the voltage value of the second write step according to at least one adjustment parameter during the read / write phase and the idle phase.
20. The memory system of claim 17, wherein the memory array is configured to generate a plurality of first output voltages based on the first control voltage, the plurality of first output voltages forming a plurality of non-overlapping first subsets in an output voltage-quantity graph. The memory array is used to generate multiple second output voltages based on the second control voltage. These multiple second output voltages form multiple non-overlapping second subsets in the output voltage-quantity graph. The spacing between adjacent pairs in the plurality of first subsets is negatively correlated with the voltage value of the first write step, and the spacing between adjacent pairs in the plurality of second subsets is negatively correlated with the voltage value of the second write step.