Semiconductor device and operating method thereof

Abstract

The invention relates to a semiconductor device and an operating method thereof. A semiconductor device including one or more memory cells and a method of operating the same are disclosed. Each memory cell includes: a first transistor configured to write data; a second transistor configured to store data; and a third transistor configured to refresh data. The memory cell includes: a first transistor including a first gate connected to a write word line and one terminal connected to a memory node; a second transistor including a second gate connected to the storage node and one terminal connected to a read word line; and a third transistor including a third gate connected to the read word line and one terminal connected to the read bit line.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2024-0113384, filed on August 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to a semiconductor device and a method of operating the same, and more specifically to a semiconductor device including a memory cell and a method of operating the same. Background Technology

[0004] Among various semiconductor devices, a semiconductor device with storage functionality can include an array that serves as a means for storing information, the array comprising individual memory cells containing transistors. A semiconductor device with storage functionality can include, for example, dynamic random access memory (DRAM). Memory semiconductors can include bit lines and word lines that may intersect each other in a vertical direction. Bit lines and word lines may extend through the array comprising memory cells. Bit lines and word lines can be used to access individual memory cells.

[0005] Memory performance, cell stability and reliability, efficiency, ease of handling, and cost can vary depending on the design and placement of individual memory cells. Therefore, research is actively underway on cell array design and manufacturing processes for memory devices. Summary of the Invention

[0006] Various embodiments of this disclosure relate to a semiconductor device that can replace capacitors designed to store data in a unit memory cell with transistors.

[0007] Various embodiments of this disclosure relate to a semiconductor device including a structure in which a plurality of transistors included in a unit memory cell can be stacked.

[0008] According to one embodiment of the present disclosure, a memory cell may include: a first gate configured to contact a write word line; a second gate disposed below the first gate and above a read bit line, and configured to pass through the read word line; a third gate spaced apart from the second gate and disposed above the read bit line; a first interconnect structure configured to have a portion contacting the second gate and another portion passing through the third gate; and a second interconnect structure configured to contact each read word line and the third gate.

[0009] In some embodiments, the first gate may be configured to extend through a write bit line; the write word line and the read word line may be configured to extend along a first direction; and the write bit line and the read bit line may be configured to extend along a second direction different from the first direction.

[0010] In some embodiments, the first interconnect structure may include: a first horizontal interconnect layer configured to contact a second gate; a second horizontal interconnect layer configured to be traversed by a third gate; and a vertical interconnect layer configured to contact each of the first and second horizontal interconnect layers.

[0011] In some embodiments, a first channel layer formed to contact the side surface and bottom surface of a first gate can be configured to contact a write bit line; a second channel layer formed to contact the side surface and bottom surface of a second gate can be configured to contact a read word line; and a third channel layer formed to contact the side surface and bottom surface of a third gate can be configured to contact a second horizontal interconnect layer.

[0012] In some embodiments, each of the first to third channel layers may be configured to include an oxide semiconductor.

[0013] In some embodiments, the oxide semiconductor may be configured to include at least one of In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and In-Ga-O.

[0014] In some embodiments, each of the first to third gates may extend along a third direction perpendicular to the first direction, wherein the second gate is spaced apart from the first gate in the third direction, and the height of the second gate in the third direction is greater than the height of the third gate in the third direction.

[0015] According to another embodiment of this disclosure, a semiconductor device may include: a first transistor including a first gate connected to a write word line and having a terminal connected to a memory node; a second transistor including a second gate connected to a memory node and having a terminal connected to a read word line; and a third transistor including a third gate connected to a read word line and having a terminal connected to a read bit line.

[0016] In some embodiments, the second transistor may include another terminal connected to the read bit line; and the third transistor may include another terminal connected to the memory node.

[0017] In some embodiments, the first transistor may include another terminal connected to the write bit line.

[0018] In some embodiments, the first transistor can be turned on when the first word line signal is applied to the write word line and the first word line signal has a high level; and the first transistor can be turned off when the first word line signal has a low level.

[0019] In some embodiments, when the first word line signal is high and the first bit line signal applied to the write bit line is high, data "1" can be stored in the memory node; and when the first word line signal is high and the first bit line signal is low, data "0" can be stored in the memory node.

[0020] In some embodiments, the second transistor can be turned on when data "1" is stored in the storage node, and turned off when data "0" is stored in the storage node.

[0021] In some embodiments, when the second word line signal is applied to the read word line and the second transistor is turned on, a second bit line signal with a high level can be applied to the read bit line; while when the second word line signal is applied to the read word line and the second transistor is turned off, a second bit line signal with a low level can be applied to the read bit line.

[0022] In some embodiments, the read word line can be configured to receive a second word line signal for turning on the third transistor; and the third transistor can be configured to refresh data stored in the memory node.

[0023] According to another embodiment of this disclosure, a method for operating a semiconductor device may include: applying a first word line signal to the gate of a first transistor; storing data corresponding to the level of a first bit line signal applied to a terminal of the first transistor in a memory node connected to a second transistor; applying a second word line signal to a terminal of the second transistor; outputting a second bit line signal corresponding to the data to another terminal of the second transistor; applying the second bit line signal to a terminal of a third transistor; and refreshing the data stored in the memory node.

[0024] In some embodiments, the first transistor can be turned on when the first word line signal is high, and turned off when the first word line signal is low.

[0025] In some embodiments, when the first bit line signal is high, the data can be "1"; and when the first bit line signal is low, the data can be "0".

[0026] In some embodiments, the second transistor can be turned on when the data is "1" and turned off when the data is "0".

[0027] In some embodiments, the second bit line signal may have a high level when the data is "1" and a low level when the data is "0".

[0028] In some embodiments, when the second bit line signal is high, the data stored in the storage node can be refreshed to "1"; while when the second bit line signal is low, the data stored in the storage node can be refreshed to "0".

[0029] It should be understood that the foregoing general description of embodiments of this disclosure and the following detailed description are illustrative and intended to provide further description of the claimed invention. Attached Figure Description

[0030] The above and other features and advantages of this disclosure will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0031] Figure 1 This is a circuit diagram illustrating a portion of a semiconductor device based on some embodiments of the present disclosure.

[0032] Figure 2A and Figure 2B This illustrates some embodiments based on the present disclosure. Figure 1 The storage cell shown is used to write data "1" and retrieve data from... Figure 1 The timing diagram shown illustrates the operation of reading data "1" from the storage unit.

[0033] Figure 3A and Figure 3B This illustrates some embodiments based on the present disclosure. Figure 1 The storage cell shown is used to write data "0" and retrieve data from... Figure 1 The timing diagram shown illustrates the operation of reading data "0" from the storage unit.

[0034] Figure 4 This is a refresh illustrating some embodiments based on this disclosure. Figure 1 The flowchart shows the operation of data in the storage unit.

[0035] Figure 5 This is a plan view illustrating a portion of a memory cell array based on some embodiments of the present disclosure, in which... Figure 1 The storage unit is used as the unit storage unit.

[0036] Figure 6 This illustrates some embodiments based on this disclosure. Figure 5 A cross-sectional view of the memory cell array taken by line A-A'.

[0037] Figure 7 This illustrates some embodiments based on the present disclosure. Figure 5 The image shows a three-dimensional (3D) view of the storage cell.

[0038] Figure 8 This illustrates some embodiments based on the present disclosure. Figure 5 A three-dimensional diagram showing the arrangement of the multiple storage cells. Detailed Implementation

[0039] This disclosure provides embodiments and examples of semiconductor devices and methods of operation thereof, which can be used in configurations to substantially solve one or more technical or engineering problems and mitigate limitations or disadvantages encountered in certain semiconductor devices in the art. Some embodiments of this disclosure relate to semiconductor devices including memory cells and methods of operation thereof. Some embodiments of this disclosure relate to semiconductor devices capable of replacing capacitors designed for storing data in a unit memory cell with transistors. Some embodiments of this disclosure relate to semiconductor devices including structures in which multiple transistors included in a unit memory cell can be stacked.

[0040] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Although the present disclosure is readily adaptable to various modifications and alternatives, specific embodiments thereof are illustrated by way of example in the accompanying drawings. However, the present disclosure should not be construed as limiting itself to the embodiments described herein.

[0041] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that this disclosure is not limited to the specific embodiments, but includes various modifications, equivalents, and / or alternatives to the embodiments. The embodiments of this disclosure can provide a variety of beneficial effects that can be directly or indirectly recognized.

[0042] Figure 1 This is a circuit diagram of a portion of a semiconductor device based on some embodiments of the present disclosure.

[0043] refer to Figure 1 A semiconductor device can be a storage device capable of storing data therein. A storage device can refer to a device that temporarily or permanently stores data in electronic devices (such as computers, smartphones, etc.). Storage devices can be divided into non-volatile memory and volatile memory. Non-volatile memory is a storage device that retains stored information even without power. Examples of non-volatile memory include read-only memory (ROM), flash memory, hard disk drive (HDD), etc. Volatile memory is a storage device that requires power to retain stored information. Examples of volatile memory include dynamic random access memory (DRAM), static random access memory (SRAM), etc. In some embodiments, for ease of description, DRAM will be used as an example of a semiconductor device in the following description.

[0044] Semiconductor devices may include memory cells (MC), write word lines (WWL), write bit lines (WBL), read word lines (RWL), and read bit lines (RBL).

[0045] A memory cell (MC) may include a first transistor (TR1) and a latch (LTH). A memory cell (MC) may be a unit cell constituting an array of memory cells included in a semiconductor device. A memory cell (MC) may be the smallest unit for storing data within a semiconductor device.

[0046] The first transistor (TR1) can be used as a write transistor. The first transistor (TR1) may include a first gate terminal (G1), a first source terminal (S1), and a first drain terminal (D1). The first gate terminal (G1) can be connected to the write word line (WWL). The first source terminal (S1) can be connected to the write bit line (WBL). The first drain terminal (D1) can be connected to the memory node (SN). When the first transistor (TR1) is turned on, a first channel is formed through which charge carriers can move, allowing the first source terminal (S1) and the first drain terminal (D1) to be electrically connected to each other. When the first transistor (TR1) is turned off, the first channel may not be formed.

[0047] The write word line (WWL) transmits a first word line signal to the first gate terminal (G1) of the first transistor (TR1), enabling the WWL to control the on / off operation of the first transistor (TR1) and to control data write operations. When the first word line signal is high, the first transistor (TR1) can be turned on. A high level in the first word line signal can represent, for example, a voltage level higher than the threshold voltage of the first transistor (TR1). When the first word line signal is low, the first transistor (TR1) can be turned off. A low level in the first word line signal can represent, for example, a voltage level lower than the threshold voltage of the first transistor (TR1).

[0048] The write bit line (WBL) determines the data to be written to the memory cell (MC). The write bit line (WBL) receives the first bit line signal. When the first bit line signal is high, the logic to write to the memory cell (MC) can be a logic value "1". A high level on the first bit line signal can represent, for example, a voltage level higher than the threshold voltage of the second transistor (TR2). When the first bit line signal is low, the logic to write to the memory cell (MC) can be a logic value "0". A low level on the first bit line signal can represent, for example, a voltage level lower than the threshold voltage of the second transistor (TR2).

[0049] Data writing can be performed when the first word line signal is high and the first bit line signal is either high or low.

[0050] In the memory cell (MC) where a data write operation is performed, when the first word line signal is high and the first bit line signal is high, the first transistor (TR1) can be turned on, and the data "1" can be stored in the memory node (SN). When the first word line signal is high and the first bit line signal is low, the first transistor (TR1) can be turned on, and the data "0" can be stored in the memory node (SN).

[0051] When the first word line signal is low, the first transistor (TR1) can be turned off, and data write operations can be skipped.

[0052] The latch (LTH) may include a second transistor (TR2), a third transistor (TR3), and a memory node (SN).

[0053] The storage node (SN) can be connected to a first drain terminal (D1), a second gate terminal (G2), and a third drain terminal (D3). Data can be stored in the storage node (SN). When data "1" is stored in the storage node (SN), the voltage level of the storage node (SN) can be high, for example, higher than the threshold voltage of the second transistor (TR2).

[0054] The voltage level of the storage node (SN) storing data "1" can be the same as the high level of the first word line signal, but may vary due to variable factors such as leakage over time. When data "0" is stored in the storage node (SN), the voltage level of the storage node (SN) can be low, for example, below the threshold voltage of the second transistor (TR2).

[0055] The second transistor (TR2) can be used as a read transistor. The second transistor (TR2) may include a second gate terminal (G2), a second source terminal (S2), and a second drain terminal (D2). The second gate terminal (G2) can be connected to the memory node (SN). The second source terminal (S2) can be connected to the read word line (RWL). The second drain terminal (D2) can be connected to the read bit line (RBL). When data "1" is stored in the memory node (SN), the second transistor (TR2) can be turned on. When logic "0" is stored in the memory node (SN), the second transistor (TR2) can be turned off. When the second transistor (TR2) is turned on, a second channel is formed through which charge carriers can move, allowing the second source terminal (S2) and the second drain terminal (D2) to be electrically connected to each other. When the second transistor (TR2) is turned off, the second channel may not be formed.

[0056] The read word line (RWL) controls the data read operation by transmitting a second word line signal to the second source terminal (S2) of the second transistor (TR2). The second word line signal can be high or low. When the second word line signal is high, the data read operation can be performed. When the second word line signal is low, the data read operation may not be performed. The high level of the second word line signal can, for example, be the same voltage level as the high level of the first word line signal. The low level of the second word line signal can, for example, be the same voltage level as the low level of the first word line signal.

[0057] The read word line (RWL) can control the on / off operation of the third transistor (TR3) by transmitting the second word line signal to the third gate terminal (G3) of the third transistor (TR3), and can also control the data refresh operation.

[0058] The read bit line (RBL) can be a line that outputs data stored in the memory node (SN). The read bit line (RBL) can also be a line that outputs a second bit line signal during a data read operation. The second bit line signal varies depending on whether the data stored in the memory node (SN) is "1" or "0". The second bit line signal can be high or low. When a data read operation is not performed, the second bit line signal can be low. The low level of the second bit line signal can, for example, be the same voltage level as the low level of the second word line signal. The high level of the second bit line signal can be the same voltage level as the high level of the second word line signal. During a data read operation, when the second word line signal is high and data "1" is stored in the memory node (SN), the second transistor (TR2) can be turned on, and a high-level second bit line signal can be output from the read bit line (RBL). During a data read operation, when the second word line signal is high and data "0" is stored in the memory node (SN), the second transistor (TR2) can be turned off, and a low-level second bit line signal can be output from the read bit line (RBL).

[0059] The third transistor (TR3) can be used as a refresh transistor. The third transistor (TR3) may include a third gate terminal (G3), a third source terminal (S3), and a third drain terminal (D3). The third gate terminal (G3) can be connected to the read word line (RWL). The third source terminal (S3) can be connected to the read bit line (RBL). The third drain terminal (D3) can be connected to the memory node (SN). The third transistor (TR3) can be turned on when the second word line signal is high. When the third transistor (TR3) is turned on, charge carriers can move through the formation of a third channel, allowing the third source terminal (S3) and the third drain terminal (D3) to be electrically connected to each other. When the third transistor (TR3) is turned off, the third channel may not be formed.

[0060] When the data stored in the memory node (SN) is "1", the second transistor (TR2) is turned on, so that when the second word line signal applied to the second source terminal (S2) is high, the second bit line signal applied to the second drain terminal (D2) can also be high. When the second word line signal applied to the third gate terminal (G3) is high, the third transistor (TR3) is turned on, so that the voltage level of the memory node (SN) connected to the third drain terminal (D3) can be transmitted to the third source terminal (S3) and the second bit line signal with a high level is refreshed to a high level.

[0061] When the data stored in the memory node (SN) is "0", the second transistor (TR2) is turned off, and when the second word line signal applied to the third gate terminal (G3) is high, the third transistor (TR3) is turned on, so that the voltage level of the memory node (SN) connected to the third drain terminal (D3) can be transmitted to the third source terminal (S3) and the second bit line signal with a low level is refreshed to a low level.

[0062] In the following Figure 2A , 2B In the signal levels indicated by the vertical axes of 3A and 3B, "H" can represent a high level, "L" can represent a low level, "Y" can represent a refresh operation (REF) in progress (i.e., the refresh signal REF is activated at a high level), and "N" can represent a refresh operation (REF) not in progress (i.e., the refresh signal REF is deactivated at a low level).

[0063] Figure 2A and Figure 2B This illustrates some embodiments based on the present disclosure. Figure 1 The timing diagram shows the operation of writing data "1" to the memory cell (MC) and reading data "1" from the memory cell (MC).

[0064] When a state in a memory cell (MC) where neither data write operations nor data read operations are performed is called a hold state, Figure 2A The diagram illustrates the operation of writing data "1" to and reading data "1" from memory cell (MC) when the storage node voltage (VSN) is low in hold state. Figure 2B The timing diagram can be a timing diagram showing the operation of writing data "1" to the memory cell (MC) and reading data "1" from the memory cell (MC) when the memory node voltage (VSN) is high in the hold state.

[0065] refer to Figure 1 and Figure 2ADuring the hold period (HT) when the memory cell (MC) is in the hold state, the first bit line signal (BLV1) applied to the first source terminal (S1) via the write bit line (WBL), the first word line signal (WLV1) applied to the first gate terminal (G1) via the write word line (WWL), the second word line signal (WLV2) applied to each of the second source terminal (S2) and the third gate terminal (G3) via the read word line (RWL), and the second bit line signal (BLV2) applied to the third source terminal (S3) via the read bit line (RBL) can all be at a low level. During the hold period (HT), the refresh operation of the memory node (SN) may not occur (REF_N), and the memory node voltage (VSN) may be at a low level.

[0066] The operation of writing data "1" to a storage node (SN) in a storage cell (MC) can be configured such that, during the data write period (WT), the first bit line signal (BLV1), which is low, can go high. After the first bit line signal (BLV1) goes high, the first word line signal (WLV1), which is low, can also go high.

[0067] When the first word line signal (WLV1) goes high, the first transistor (TR1) turns on, and the data "1" can be stored in the memory node (SN) through the first bit line signal (BLV1) which is high. The state in which the data "1" is stored in the memory node (SN) can be the state in which the memory node voltage (VSN) is high.

[0068] Subsequently, when the first word line signal (WLV1) goes low, the first transistor (TR1) is turned off, and the memory node (SN) and write bit line (WBL) can be electrically decoupled while the memory node voltage (VSN) remains high. When the first bit line signal (BLV1) also goes low, the data write period (WT) can be terminated.

[0069] In the operation of reading data "1" from the memory cell (MC) and memory node (SN), the second word line signal (WLV2), which is low, can go high during the data read period (RT). Since the memory node voltage (VSN) is high, the second transistor (TR2) can be turned on. With the second transistor (TR2) on, when the second word line signal (WLV2) goes high, the second bit line signal (BLV2), which is low, can also go high. When the second bit line signal (BLV2) goes high, data "1" can be output from the read bit line (RBL).

[0070] Furthermore, when the second word line signal (WLV2) goes high, the third transistor (TR3) turns on, and the refresh operation (REF) of the memory node (SN) can be performed. When the second bit line signal (BLV2) goes high, the memory node voltage (VSN) can be refreshed to maintain a high level.

[0071] refer to Figure 2A and Figure 2B Even in Figure 2B The timing diagram (which shows the timing of data "1" being rewritten to a memory cell (MC) including a memory node (SN) that already stores data "1") shows that data write operations and data read operations can also be performed in accordance with... Figure 2A It is executed in the same way as described in [the document].

[0072] Figure 3A and Figure 3B This illustrates some embodiments based on the present disclosure. Figure 1 The timing diagram shows the operations of writing data "0" to a storage cell and reading data "0" from a storage cell.

[0073] Figure 3A The timing diagram can be a timing diagram showing the operation of writing "0" to the memory cell (MC) and reading "0" from the memory cell (MC) while the memory node voltage (VSN) is high in the hold state. Figure 3B The timing diagram can be a timing diagram showing the operation of writing data "0" and reading data "0" when the storage node voltage (VSN) is low in the hold state.

[0074] See Figure 1 and Figure 3A During the hold period (HT) when the memory cell (MC) is in the hold state, each of the first bit line signal (BLV1), the first word line signal (WLV1), the second word line signal (WLV2), and the second bit line signal (BLV2) can be at a low level. During the hold period (HT), the refresh operation of the memory node (SN) may not occur (REF_N), and the memory node voltage (VSN) can be at a high level (i.e., the state where data "1" is stored).

[0075] The operation of writing data "0" to the storage node (SN) can be configured such that, during the data write period (WT), the first bit line signal (BLV1), which is low, can be kept low. Additionally, the first word line signal (WLV1), which is low, can be high.

[0076] When the first word line signal (WLV1) goes high, the first transistor (TR1) is turned on, and the data "0" can be stored in the memory node (SN) through the first bit line signal (BLV1) which is low. The state in which the data "0" is stored in the memory node (SN) can be a state in which the memory node voltage (VSN) is low.

[0077] Subsequently, when the first word line signal (WLV1) goes low, the first transistor (TR1) is turned off, and the memory node (SN) and write bit line (WBL) can be electrically decoupled while the memory node voltage (VSN) also remains low. The data write period (WT) can terminate when the first bit line signal (BLV1) also goes low.

[0078] The operation of reading data "0" from the memory node (SN) in the memory cell (MC) can be configured such that, during the data read period (RT), the second word line signal (WLV2), which is low, can transition to a high level. Since the memory node voltage (VSN) is low, the second transistor (TR2) can remain off. Because the second transistor (TR2) remains off, the second bit line signal (BLV2) can remain low even if the second word line signal (WLV2) is high. When the second bit line signal (BLV2) remains low, the data "0" can be output from the read bit line (RBL).

[0079] When the second word line signal (WLV2) goes high, the third transistor (TR3) can be turned on, and the refresh operation (REF) of the memory node (SN) can be performed. When the second bit line signal (BLV2) remains low, the memory node voltage (VSN) can also be refreshed to remain low.

[0080] Figure 4 This illustrates some embodiments based on the present disclosure. Figure 1 The flowchart shows the operation of refreshing data in the storage unit.

[0081] refer to Figure 1 and Figure 4 Data in memory cells (MCs), especially data in memory cells (MCs) where data "1" has been written, may require a refresh operation because storage node voltage may be affected. Figure 2A and Figure 2B The leakage phenomenon where the VSN gradually decreases over time. For refresh operations, the voltage (signal level) of the read word line (RWL) can be high (S810). Since the storage node voltage (VSN) is already high when the data "1" is written to the storage node (SN), the second transistor (TR2) can be turned on.

[0082] Because the voltage on the read word line (RWL) is high, the third transistor (TR3) can also be turned on (S820). Because the second transistor (TR2) is turned on, the read bit line (RBL) electrically connected to the second drain terminal (D2) can also be high.

[0083] Since the voltage of the read line (RBL) is high, the voltage of the storage node (SN) is refreshed to high level through the conducting third transistor (TR3), and as a result, the data stored in the storage cell (MC) can be refreshed (S830).

[0084] Figure 5 This is a plan view illustrating a portion of a memory cell array (MCA) based on some embodiments of the present disclosure, in which... Figure 1 The memory cell (MC) is used as the unit of memory.

[0085] refer to Figure 1 and Figure 5 ,in Figure 1 The memory cell (MC) is used as a unit of memory. A memory cell array (MCA) can be a configuration used to store data within a semiconductor device. When a memory cell array (MCA) is modeled as a circuit diagram, Figure 1 The circuit diagram can be modeled as a repeating arrangement. Figure 5 The diagram illustrates a memory cell array (MCA) in which four memory cells (MC1 to MC4) are arranged in a (2×2) matrix structure, but the number of memory cells is not limited to this. For example, multiple memory cells can also be arranged in a first direction (X), a second direction (Y), or a third direction (Z). The memory cell array (MCA) may include the first to fourth memory cells (MC1 to MC4).

[0086] The first memory cell (MC1) may overlap with the first write bit line (WBL1), the first read bit line (RBL1), the first write word line (WWL1), and the first read bit line (RWL1). The second memory cell (MC2) may overlap with the second write bit line (WBL2), the second read bit line (RBL2), the first write word line (WWL1), and the first read bit line (RWL1). The third memory cell (MC3) may overlap with the first write bit line (WBL1), the first read bit line (RBL1), the second write word line (WWL2), and the second read bit line (RWL2). The fourth memory cell (MC4) may overlap with the second write bit line (WBL2), the second read bit line (RBL2), the second write word line (WWL2), and the second read bit line (RWB2). Each of the first to fourth memory cells (MC1 to MC4) may have substantially the same layout.

[0087] Each of the first to fourth memory cells (MC1 to MC4) may include a first gate electrode layer 110, a second gate electrode layer 210, and a third gate electrode layer 310. Figure 5 In the diagram, the cross-sections of the first to third gate electrode layers (110, 210, 310) are shown as circular, but are not limited thereto.

[0088] The first gate electrode layer 110 may be included in the first gate terminal (G1) of the first transistor (TR1). The first gate electrode layer 110 may be located at, for example, the point where the write word line (WWL) and the write bit line (WBL) intersect each other.

[0089] The second gate electrode layer 210 may be included in the second gate terminal (G2) of the second transistor (TR2). The second gate electrode layer 210 may be located, for example, at the point where the write word line (WWL) and the write bit line (WBL) intersect each other, and may overlap with the first gate electrode layer 110 when viewed in the third direction (Z). The second gate electrode layer 210 may be spaced apart from the first gate electrode layer 110 in the third direction (Z).

[0090] The third gate electrode layer 310 may be included in the third gate terminal (G3) of the third transistor (TR3). The third gate electrode layer 310 may be arranged spaced apart from the second gate electrode layer 210 in the second direction (Y). The third gate electrode layer 310 may be disposed between adjacent second gate electrode layers 210.

[0091] Figure 5 Each of the first and second reading lines (RWL1, RWL2) can be implemented Figure 1 An example of the Reading Line (RWL). Figure 5 Each of the first and second read lines (RBL1, RBL2) can be implemented Figure 1 An example of a read line (RBL). Figure 5 Each of the first and second writing lines (WWL1, WWL2) can be used to implement Figure 1 An example of a writing line (WWL). Figure 5 Each of the first and second write bit lines (WBL1, WBL2) can be implemented Figure 1 An example of a write bit line (WBL).

[0092] Each of the first and second writing lines (WWL1, WWL2) may extend in a first direction (X). Multiple writing lines including the first and second writing lines (WWL1, WWL2) may be repeated. For example, multiple writing lines including the first and second writing lines (WWL1, WWL2) may be repeated in a second direction (Y) spaced apart from each other by a predetermined distance (e.g., a first interval).

[0093] Each of the first and second reading lines (RWL1, RWL2) can extend in a first direction (X). Multiple reading lines including the first and second reading lines (RWL1, RWL2) can be repeated. For example, multiple reading lines including the first and second reading lines (RWL1, RWL2) can be repeated in a second direction (Y) spaced apart from each other by a predetermined distance (e.g., a first interval). The first reading line (RWL1) can overlap with the first writing line (WWL1) in a third direction (Z) and can be arranged below the first writing line (WWL1). The second reading line (RWL2) can overlap with the second writing line (WWL2) in a third direction (Z) and can be arranged below the second writing line (WWL2).

[0094] Each of the first and second write bit lines (WBL1, WBL2) may extend in a second direction (Y). Multiple write bit lines including the first and second write bit lines (WBL1, WBL2) may be repeatedly arranged. For example, multiple write bit lines including the first and second write bit lines (WBL1, WBL2) may be repeatedly arranged in a first direction (X) spaced apart from each other by a predetermined distance (e.g., a second interval).

[0095] Each of the first and second read bit lines (RBL1, RBL2) may extend in a second direction (Y). Multiple read bit lines including the first and second read bit lines (RBL1, RBL2) may be repeatedly arranged. For example, multiple read bit lines including the first and second read bit lines (RBL1, RBL2) may be repeatedly arranged in a first direction (X) spaced apart from each other by a predetermined distance (e.g., a second interval). The first read bit line (RBL1) may overlap with the first write bit line (WBL1) in a third direction (Z) and may be arranged below the first write bit line (WBL1). The second read bit line (RBL2) may overlap with the second write bit line (WBL2) in a third direction (Z) and may be arranged below the second write bit line (WBL2).

[0096] As the widths of the read word lines (RWL1, RWL2), write bit lines (WBL1, WBL2), read bit lines (RBL1, RBL2), and write word lines (WWL1, WWL2) are reduced, the integration density of memory cells (MCs) in a memory cell array (MCA) can be increased.

[0097] exist Figure 5 For ease of explanation, components other than the write word lines (WWL1, WWL2), read word lines (RWL1, RWL2), write bit lines (WBL1, WBL2), read bit lines (RBL1, RBL2), and gate electrode layers (110, 210, 310) will be omitted here. Figure 5More detailed configurations will be provided below. Figure 6 It is described by a cross-sectional view.

[0098] Figure 6 It is based on some embodiments shown in this disclosure. Figure 5 A cross-sectional view of the memory cell array (MCA) taken by line A-A'.

[0099] refer to Figure 1 , Figure 5 and Figure 6 , Figure 6 The cross section taken along line A-A' may include transistor region 710 and latch region 720.

[0100] The transistor region 710 may include a write word line (WWL), a first gate electrode layer 110, a first gate insulating layer 120, a first channel layer 130, a write bit line (WBL), and a first interlayer insulating layer 610.

[0101] A write word line (WWL) may be disposed on the first gate electrode layer 110. The write word line (WWL) can transmit a first word line signal to the first gate electrode layer 110. The write word line (WWL) may include a conductive material (e.g., at least one selected from polysilicon, impurity-containing polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide).

[0102] The first gate electrode layer 110 may be the gate electrode layer of a first transistor (TR1) included in the first gate terminal (G1). The first gate electrode layer 110 may contact the write word line (WWL). The first gate electrode layer 110 may be disposed below the write word line (WWL). The first gate electrode layer 110 may include a conductive material (e.g., at least one selected from polysilicon, impurity-containing polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide). The first gate electrode layer 110 may include a first vertical gate electrode layer (110V) extending in a vertical direction and a first horizontal gate electrode layer (110H) extending in a horizontal direction. The first vertical gate electrode layer (110V) may pass through the write bit line (WBL). The first horizontal gate electrode layer (110H) may be disposed above and in contact with the first vertical gate electrode layer (110V). The cross-section of the first gate electrode layer 110 may have, for example, a T-shape.

[0103] The first gate insulating layer 120 may be the gate insulating layer of the first transistor (TR1) included in the first gate terminal (G1). The first gate insulating layer 120 may be disposed below the first gate electrode layer 110. The first gate insulating layer 120 may contact the first gate electrode layer 110. The first gate insulating layer 120 may electrically insulate the first gate electrode layer 110 and the first channel layer 130.

[0104] The first gate insulating layer may include an insulating material (e.g., at least one of oxides, oxynitrides, and nitrides). The first gate insulating layer 120 may surround the bottom surface of the first horizontal gate electrode layer (110H) and the side and bottom surfaces of the first vertical gate electrode layer (110V). The first gate insulating layer 120 may also extend through the write bit line (WBL).

[0105] The first channel layer 130 can be formed when the first transistor (TR1) is turned on. Figure 1 The first channel region is described in the diagram. The first channel layer 130 may be disposed beneath the first gate insulating layer 120. The first channel layer 130 may contact the first gate insulating layer 120. The first channel layer 130 may extend through a write bit line (WBL). The first channel layer 130 may comprise an oxide semiconductor (e.g., at least one of In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and In-Ga-O). The first channel layer 130 may have a specific shape surrounding the side and bottom surfaces of the first gate insulating layer 120.

[0106] The write bit line (WBL) can extend along the second direction (Y). The write bit line (WBL) can be positioned below the write word line (WWL). The write bit line (WBL) can be connected to the first source terminal ( Figure 1 (S1). When the first word line signal is transmitted to the first gate electrode layer 110, the write bit line (WBL) can transmit the first bit line signal obtained through the channel formed in the first channel layer 130 to the second gate electrode layer 210 via the first horizontal interconnect layer 410. The write bit line (WBL) can be horizontally wrapped around the first channel layer 130. The write bit line (WBL) can include a conductive material (e.g., at least one of polysilicon, impurity-containing polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide).

[0107] The first interlayer insulating layer 610 may fill the space around the write word line (WWL), the first gate electrode layer 110, the first gate insulating layer 120, the first channel layer 130, and the write bit line (WBL). The first interlayer insulating layer 610 may provide electrical insulation between layers spaced apart from each other and comprising conductive material. The first interlayer insulating layer 610 may include an insulating material. For example, the first interlayer insulating layer 610 may include at least one of oxides, nitrides, and oxynitrides.

[0108] The latch region 720 may include a first horizontal interconnect layer 410, a second horizontal interconnect layer 420, a vertical interconnect layer 430, a second gate electrode layer 210, a second gate insulating layer 220, a second channel layer 230, a read word line (RWL), a second interconnect layer 500, a third gate electrode layer 310, a third gate insulating layer 320, a third channel layer 330, a read bit line (RBL), and a second interlayer insulating layer 620.

[0109] The second gate electrode layer 210 may be the gate electrode layer of the second transistor (TR2) included in the second gate terminal (G2). The second gate electrode layer 210 may contact the first horizontal interconnect layer 410. The second gate electrode layer 210 may be disposed below the first horizontal interconnect layer 410. The second gate electrode layer 210 may be disposed below the write bit line (WBL). The second gate electrode layer 210 may include a conductive material (e.g., at least one of polysilicon, impurity-containing polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide). A memory node voltage corresponding to the voltage level of the first word line signal transmitted to the first horizontal interconnect layer 410 may be applied to the second gate electrode layer 210. The second gate electrode layer 210 may include a second vertical gate electrode layer 210V extending in a vertical direction and a second horizontal gate electrode layer 210H extending in a horizontal direction. The second vertical gate electrode layer 210V may pass through the read word line (RWL) and the second interconnect layer 500. The cross-section of the second gate electrode layer 210 can be, for example, T-shaped. As the length of the second gate electrode layer 210 extending along the third direction (Z) increases, the portion of the second gate insulating layer 220 surrounding the second vertical gate electrode layer 210V becomes longer and its cross-section becomes larger, thereby increasing the capacitance of the storage node (SN).

[0110] The second gate insulating layer 220 may be a gate insulating layer of the second transistor (TR2) included in the second gate terminal (G2). The second gate insulating layer 220 may electrically insulate the second gate electrode layer 210 from the second channel layer 230. The second gate insulating layer 220 may contact the second gate electrode layer 210. The second gate insulating layer 220 may be disposed beneath the second gate electrode layer 210. The second gate insulating layer 220 may include an insulating material (e.g., at least one of oxides, oxynitrides, and nitrides). The second gate insulating layer 220 may realize the intrinsic capacitance of the second transistor (TR2). The second gate insulating layer 220 may be in the form of surrounding the bottom surface of the second horizontal gate electrode layer 210H and the side and bottom surfaces of the second vertical gate electrode layer 210V. The second gate insulating layer 220 may also extend through the read word line (RWL) and the second interconnect layer 500.

[0111] The second channel layer 230 can form the above reference when the second transistor (TR2) is turned on. Figure 1The region of the second channel. The second channel layer 230 may be disposed below the second gate insulating layer 220. The second channel layer 230 may contact the second gate insulating layer 220. The second channel layer 230 may be arranged to pass through read word lines (RWL). The second channel layer 230 may include an oxide semiconductor (e.g., at least one of In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and In-Ga-O). The second channel layer 230 may surround the side surface and bottom surface of the second gate insulating layer 220.

[0112] When the storage node voltage applied to the second gate electrode layer 210 is high, the second transistor (TR2) can be turned on, thereby enabling the formation of the second channel in the second channel layer 230. The second gate insulating layer 220 may be an embodiment for implementing a storage node (SN).

[0113] The read line (RWL) can be connected to the second source region ( Figure 1 S2 in the middle). The read word line (RWL) can transmit the second word line signal to the second source terminal (S2). Figure 1 The third gate electrode layer 310 is included in each of the third gate terminal (S2) and the third gate terminal (G3). A read bit line (RWL) may contact the second interconnect layer 500 which contacts the third gate electrode layer 310. The read word line (RWL) may surround the second channel layer 230. The read word line (RWL) may include a conductive material (e.g., at least one selected from polysilicon, impurity-containing polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide).

[0114] The third gate electrode layer 310 may be the gate electrode layer of a third transistor (TR3). The third gate electrode layer 310 may contact the second interconnect layer 500. The third gate electrode layer 310 may receive a second word line signal via the second interconnect layer 500 that contacts the read word line (RWL). The third gate electrode layer 310 may include a conductive material (e.g., at least one of doped polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide).

[0115] When a high-level second word line signal is applied to the third gate electrode layer 310, the third transistor (TR3) can be turned on. The third gate electrode layer 310 may include a third vertical gate electrode layer 310V extending in a vertical direction and a third horizontal gate electrode layer 310H extending in a horizontal direction. The third horizontal gate electrode layer 310H and the third vertical gate electrode layer 310V may be in contact with each other. The third vertical gate electrode layer 310V may pass through the second horizontal interconnect layer 420. The cross-section of the third gate electrode layer 310 may have, for example, a T-shape.

[0116] The third gate insulating layer 320 may be the gate insulating layer of the third transistor (TR3). The third gate insulating layer 320 may contact the third gate electrode layer 310. The third gate insulating layer 320 may be disposed below the third gate electrode layer 310. The third gate insulating layer 320 may include an insulating material. The third gate insulating layer 320 may include at least one of, for example, oxides, oxynitrides, and nitrides.

[0117] The third channel layer 330 can be formed when the third transistor (TR3) is turned on. Figure 1 The third channel region is described in the diagram. The third channel layer 330 may contact the third gate insulating layer 320. The third channel layer 330 may be disposed below the third gate insulating layer 320. The third channel layer 330 may penetrate the second horizontal interconnect layer 420. The third channel layer 330 may include an oxide semiconductor (e.g., at least one of In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-Ga-O).

[0118] The vertical height of the second gate electrode layer 210 can be higher than the vertical height of the third gate electrode layer 310.

[0119] The read bit line (RBL) may overlap with the write bit line (WBL) in a third direction (Z). The read bit line (RBL) may correspond to each of the second drain terminal (D2) and the third source terminal (S3). The read bit line (RBL) may be disposed below the second channel layer 230 and the third channel layer 330. The read bit line (RBL) may contact each of the second channel layer 230 and the third channel layer 330. The read bit line (RBL) may include a conductive material (e.g., at least one selected from polysilicon, impurity-containing polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide, and tantalum silicide).

[0120] The first interconnect structure 400 may include a first horizontal interconnect layer 410, a second horizontal interconnect layer 420, and a vertical interconnect layer 430.

[0121] The first horizontal interconnect layer 410 may extend below the first channel layer 130 along a first direction (X) and / or a second direction (Y) and may contact the vertical interconnect layer 430. The first horizontal interconnect layer 410 may correspond to the first drain terminal (D1).

[0122] The second horizontal interconnect layer 420 may surround the third channel layer 330 and may extend along the first direction (X) to contact the vertical interconnect layer 430. The second horizontal interconnect layer 420 may correspond to the third drain terminal (D3).

[0123] The vertical interconnect layer 430 may be arranged spaced apart from the second interconnect layer 500, read word line (RWL), third gate electrode layer 310, third gate insulating layer 320 and third channel layer 330.

[0124] The vertical interconnect layer 430 may be disposed between the first horizontal interconnect layer 410 and the second horizontal interconnect layer 420. The vertical interconnect layer 430 may contact the first horizontal interconnect layer 410 and the second horizontal interconnect layer 420.

[0125] The second interconnect layer 500 may contact the read word line (RWL) and the third gate electrode layer 310. The second interconnect layer 500 may extend along a second direction (Y). The second interconnect layer 500 may surround the second channel layer 230. The second interconnect layer 500 may transmit the second word line signal from the read word line (RWL) to the third gate electrode layer 310.

[0126] Each of the first interconnect structure 400 and the second interconnect layer 500 may include a conductive material (e.g., at least one of doped polysilicon, platinum, gold, molybdenum, nickel, tungsten, titanium, aluminum copper, titanium silicide, tungsten silicide and tantalum silicide).

[0127] The second interlayer insulating layer 620 may fill the space surrounding the first horizontal interconnect layer 410, the second horizontal interconnect layer 420, the vertical interconnect layer 430, the second gate electrode layer 210, the second gate insulating layer 220, the second channel layer 230, the read word line (RWL), the second interconnect layer 500, the third gate electrode layer 310, the third gate insulating layer 320, the third channel layer 330, and the read bit line (RBL) within the latch region 720. The second interlayer insulating layer 620 may provide electrical insulation between layers spaced apart from each other and comprising conductive material. The second interlayer insulating layer 620 may include an insulating material. For example, the second interlayer insulating layer 620 may include at least one of oxides, nitrides, and oxynitrides.

[0128] In Figure 7 and Figure 8 For ease of explanation, the text is not shown. Figure 6 The first interlayer insulating layer 610 and the second interlayer insulating layer 620 are shown. Figure 7 and Figure 8 In the text, we will omit as much as possible the related characters. Figure 6 The descriptions overlap.

[0129] Figure 7 This illustrates some embodiments based on the present disclosure. Figure 5 Storage cells (MCs) and through Figure 5 A three-dimensional diagram of the write word line (WWL), write bit line (WBL), read word line (RWL), and read bit line (RBL) of a memory cell (MC).

[0130] The memory cell (MC) may include a first gate electrode layer 110, a first gate insulating layer 120, a first channel layer 130, a second gate electrode layer 210, a second gate insulating layer 220, a second channel layer 230, a third gate electrode layer 310, a third gate insulating layer 320, a third channel layer 330, a first interconnect structure 400, and a second interconnect layer 500.

[0131] The writing line (WWL) can extend along the first direction (X).

[0132] Write lines (WBL) can extend along the second direction (Y). Write lines (WBL) can be spaced apart from write lines (WWL) in the third direction (Z).

[0133] The read line (RWL) can extend along the first direction (X). The read line (RWL) can be spaced apart from the write line (WBL) in the third direction (Z).

[0134] The read line (RBL) can extend along the second direction (Y). The read line (RBL) can be spaced apart from the write line (WBL) in the third direction (Z).

[0135] The first interconnect structure 400 may include a first horizontal interconnect layer 410, a second horizontal interconnect layer 420, and a vertical interconnect layer 430.

[0136] The first horizontal interconnect layer 410 may extend in a first direction (X) and a second direction (Y). The first horizontal interconnect layer 410 may contact each of the second gate electrode layer 210 and the vertical interconnect layer 430.

[0137] The second horizontal interconnect layer 420 may be arranged spaced apart from the first horizontal interconnect layer 410 in a third direction (Z). The second horizontal interconnect layer 420 may extend along a first direction (X).

[0138] The vertical interconnect layer 430 can be disposed between the first horizontal interconnect layer 410 and the second horizontal interconnect layer 420, and can extend along a third direction (Z).

[0139] The second interconnect layer 500 can contact the read word line (RWL) and the third gate electrode layer 310. The second interconnect layer 500 can extend along a second direction (Y).

[0140] A second gate terminal (G2), which can be implemented by including a second gate electrode layer 210 and a second gate insulating layer 220, can be spaced apart in a third direction (Z) from a first gate terminal (G1), which can be implemented by including a first gate electrode layer 110 and a first gate insulating layer 120.

[0141] The third gate terminal (G3), which can be implemented by including a third gate electrode layer 310 and a third gate insulating layer 320, can be spaced apart from the second gate terminal (G2) in the second direction (Y).

[0142] Figure 8 This illustrates some embodiments based on the present disclosure in which the arrangement is... Figure 5 A 3D diagram of a memory cell array (MCA) with multiple memory cells.

[0143] Figure 8 It shows that it is stacked Figure 7 A three-dimensional structure of a memory cell array (MCA).

[0144] exist Figure 8 For ease of explanation, only the first to fourth writing lines (WWL1~WWL4), the first to fourth reading lines (RWL1~RWL4), the first to fourth writing position lines (WBL1~WBL4), and the reading position lines (RBL1~RBL4) are indicated by the attached reference numerals.

[0145] refer to Figure 7 and Figure 8 , Figure 8 The storage cell stacking structure can have a stacking structure in which eight storage cells (MCs) are stacked into a (2×2×2) cube structure. Figure 8 Each of the eight storage units can be connected to Figure 7 The storage cells (MCs) are basically the same. The planar layout structure of the cubic storage cell array (MCA) viewed from the third direction (Z) can be compared with... Figure 5 The basics are the same.

[0146] In the following text, with Figure 6 and Figure 7 Overlapping descriptions will be omitted for brevity.

[0147] When the above eight storage units are classified into the first to the eighth storage units, each storage unit can be described or defined as follows.

[0148] Each row in the first row (R1) and the second row (R2) can be a line extending along the second direction (Y). Each column in the first column (C1) and the second column (C2) can be a line extending along the first direction (X). Each layer in the first layer (F1) and the second layer (F2) can be a portion extending along the first direction (X) and the second direction (Y).

[0149] The first storage cell can be arranged in the first row (R1). The first storage cell can be arranged in the first column (C1). The first storage cell can be arranged in the first level (F1).

[0150] The second storage cell can be arranged adjacent to the first storage cell in the first direction (X). The second storage cell can be arranged in the second row (R2). The second storage cell can be arranged in the first column (C1). The second storage cell can be arranged in the first layer (F1). The second storage cell can share the first write word line (WWL1) and the first read word line (RWL1) with the first storage cell.

[0151] The third storage cell can be arranged adjacent to the first storage cell in the second direction (Y). The third storage cell can be arranged in the first row (R1). The third storage cell can be arranged in the second column (C2). The third storage cell can be arranged in the first layer (F1). The third storage cell can share the first write bit line (WBL1) and the first read bit line (RBL1) with the first storage cell.

[0152] The fourth memory cell can be arranged adjacent to the second memory cell in the second direction (Y). The fourth memory cell can be arranged adjacent to the third memory cell in the first direction (X). The fourth memory cell can be arranged in the second row (R2). The fourth memory cell can be arranged in the second column (C2). The fourth memory cell can be arranged in the first layer (F1). The fourth memory cell can share the second write bit line (WBL2) and the second read bit line (RBL2) with the second memory cell. The fourth memory cell can share the second write word line (WWL2) and the second read word line (RWL2) with the third memory cell.

[0153] The fifth storage cell can be arranged adjacent to the first storage cell in the third direction (Z). The fifth storage cell can be arranged in the first row (R1). The fifth storage cell can be arranged in the first column (C1). The fifth storage cell can be arranged in the second layer (F2).

[0154] The sixth storage cell can be arranged adjacent to the second storage cell in the third direction (Z). The sixth storage cell can be arranged in the second row (R2). The sixth storage cell can be arranged in the first column (C1). The sixth storage cell can be arranged in the second layer (F2). The sixth storage cell can share the third write word line (WWL3) and the third read word line (RWL3) with the fifth storage cell.

[0155] The seventh memory cell can be arranged adjacent to the third memory cell in the third direction (Z). The seventh memory cell can be arranged in the first row (R1). The seventh memory cell can be arranged in the second column (C2). The seventh memory cell can be arranged in the second layer (F2). The seventh memory cell can share the third write bit line (WBL3) and the third read bit line (RBL3) with the fifth memory cell.

[0156] The eighth memory cell can be arranged adjacent to the sixth memory cell in the second direction (Y). The eighth memory cell can be arranged adjacent to the seventh memory cell in the first direction (X). The eighth memory cell can be arranged adjacent to the fourth memory cell in the third direction (Z). The eighth memory cell can be arranged in the second row (R2). The eighth memory cell can be arranged in the second column (C2). The eighth memory cell can be arranged in the second layer (F2). The eighth memory cell can share the fourth write bit line (WBL4) and the fourth read bit line (RBL4) with the sixth memory cell. The eighth memory cell can share the fourth write word line (WWL4) and the fourth read word line (RWL4) with the seventh memory cell.

[0157] The first write word line (WWL1) can extend along a first direction (X). The first write word line (WWL1) can provide a first write word line signal to the first memory cell and the second memory cell. The first read word line (RWL1) can extend along the first direction (X). The first read word line (RWL1) can provide a first read word line signal to the first memory cell and the second memory cell. The first write bit line (WBL1) can extend along a second direction (Y). The first write bit line (WBL1) can provide a first write bit line signal to the first memory cell and the third memory cell. The first read bit line (RBL1) can extend along a second direction (Y). The first read bit line (RBL1) can provide a first read bit line signal to the first memory cell and the third memory cell.

[0158] The second write word line (WWL2) can extend along the first direction (X). The second write word line (WWL2) can provide second write word line signals to the third and fourth memory cells. The second read word line (RWL2) can extend along the first direction (X). The second read word line (RWL2) can provide second read word line signals to the third and fourth memory cells. The second write bit line (WBL2) can extend along the second direction (Y). The second write bit line (WBL2) can provide second write bit line signals to the second and fourth memory cells. The second read bit line (RBL2) can extend along the second direction (Y). The second read bit line (RBL2) can provide second read bit line signals to the second and fourth memory cells.

[0159] Each of the first writing line (WWL1), the first reading line (RWL1), the first writing position line (WBL1), the first reading position line (RBL1), the second writing line (WWL2), the second reading line (RWL2), the second writing position line (WBL2), and the second reading position line (RBL2) can be arranged in the first layer (F1).

[0160] The third write word line (WWL3) can extend along the first direction (X). The third write word line (WWL3) can provide third write word line signals to the fifth and sixth memory cells. The third read word line (RWL3) can extend along the first direction (X). The third read word line (RWL3) can provide third read word line signals to the fifth and sixth memory cells. The third write bit line (WBL3) can extend along the second direction (Y). The third write bit line (WBL3) can provide third write bit line signals to the fifth and seventh memory cells. The third read bit line (RBL3) can extend along the second direction (Y). The third read bit line (RBL3) can provide third read bit line signals to the fifth and seventh memory cells.

[0161] The fourth write word line (WWL4) can extend along the first direction (X). The fourth write word line (WWL4) can provide the fourth write word line signal to the seventh and eighth memory cells. The fourth read word line (RWL4) can extend along the first direction (X). The fourth read word line (RWL4) can provide the fourth read word line signal to the seventh and eighth memory cells. The fourth write bit line (WBL4) can extend along the second direction (Y). The fourth write bit line (WBL4) can provide the fourth write bit line signal to the sixth and eighth memory cells. The fourth read bit line (RBL2) can extend along the second direction (Y). The fourth read bit line (RBL2) can provide the fourth read bit line signal to the sixth and eighth memory cells.

[0162] Each of the third writing line (WWL3), the third reading line (RWL3), the third writing position line (WBL3), the third reading position line (RBL3), the second writing line (WWL4), the fourth reading line (RWL4), the fourth writing position line (WBL4), and the fourth reading position line (RBL4) can be arranged in the second layer (F2).

[0163] Each of the first to fourth scribing lines (WWL1 to WWL4) can have the same... Figure 6 and Figure 7 The writing line (WWL) shown has essentially the same structure and material.

[0164] Each of the first to fourth reading lines (RWL1 to RWL4) can have the same as Figure 6 and Figure 7 The Reading Lines (RWL) shown have essentially the same structure and material.

[0165] Each of the first to fourth write lines (WBL1 to WBL4) can have the same characteristics as... Figure 6 and Figure 7 The read line (WBL) shown has essentially the same structure and material.

[0166] Each of the first to fourth reading lines (RBL1 to RBL4) can have the same as Figure 6 and Figure 7 The read line (RBL) shown has essentially the same structure and material.

[0167] The interconnects are configured such that the first interconnect structure 400 and the second interconnect layer 500, respectively, correspond to the interconnect layers of the first to eighth memory cells, which may not be shared with each other and may be spaced apart from each other.

[0168] It is evident from the above description that semiconductor devices based on some embodiments of this disclosure can use transistors instead of capacitors designed to store data in a single memory cell.

[0169] Semiconductor devices based on some embodiments of this disclosure can be designed to have a structure in which multiple transistors included in a unit memory cell can be stacked.

[0170] The embodiments disclosed herein can provide a variety of beneficial effects that can be directly or indirectly recognized.

[0171] Those skilled in the art will understand that embodiments of this disclosure can be implemented in other specific ways than those described herein. Furthermore, claims not expressly set forth in the appended claims may be offered as a combination of embodiments or included as new claims through subsequent amendments after the filing of the application.

[0172] While several illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed and other embodiments can be designed based on the description and / or illustration in this disclosure. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A storage unit, comprising: The first gate is configured to contact the write line; A second gate is disposed below the first gate and above the read bit line, and the second gate passes through the read word line; A third gate, which is spaced apart from the second gate and disposed above the read bit line; A first interconnect structure is configured to partially contact the second gate, and the first interconnect structure is penetrated by the third gate; as well as A second interconnect structure is configured to contact the word line and the third gate.

2. The storage unit according to claim 1, wherein: The first gate is configured to pass through the write bit line; The writing line and the reading line are configured to extend along a first direction; and The write bit line and the read bit line are configured to extend along a second direction different from the first direction.

3. The storage unit according to claim 1, wherein, The first interconnect structure includes: A first horizontal interconnect layer is configured to contact the second gate; A second horizontal interconnect layer, configured to be traversed by the third gate; and A vertical interconnect layer is configured to contact the first horizontal interconnect layer and the second horizontal interconnect layer.

4. The storage unit according to claim 3, wherein: The first channel layer is configured to contact the side surface and bottom surface of the first gate and to contact the write bit line; The second channel layer is configured to contact the side surface and bottom surface of the second gate and to contact the read line; as well as The third channel layer is configured to contact the side and bottom surfaces of the third gate and to contact the second horizontal interconnect layer.

5. The storage unit according to claim 4, wherein Each of the first to the third trench layers comprises an oxide semiconductor.

6. The storage unit according to claim 5, wherein The oxide semiconductor includes at least one of In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and In-Ga-O.

7. The storage unit according to claim 2, wherein: Each of the first gate to the third gate is configured to extend along a third direction perpendicular to the first direction; and The second gate is spaced apart from the first gate in the third direction, and the height of the second gate in the third direction is higher than the height of the third gate in the third direction.

8. A semiconductor device, comprising: The first transistor includes a first gate connected to a write line and a terminal connected to a memory node; The second transistor includes a second gate connected to the memory node and a terminal connected to a read word line; as well as The third transistor includes a third gate connected to the read word line and a terminal connected to the read bit line.

9. The semiconductor device according to claim 8, wherein: The second transistor includes another terminal connected to the read bit line; and The third transistor includes another terminal connected to the memory node.

10. The semiconductor device of claim 8, wherein The first transistor includes another terminal connected to the write bit line.

11. The semiconductor device according to claim 10, wherein: When the first word line signal applied to the write word line has a high level, the first transistor is turned on; as well as When the first word line signal is low, the first transistor is turned off.

12. The semiconductor device according to claim 11, wherein: When the first word line signal is high and the first bit line signal applied to the write bit line is high, the data corresponding to "1" is stored in the memory node; as well as When the first word line signal is high and the first bit line signal is low, the data corresponding to "0" is stored in the storage node.

13. The semiconductor device according to claim 12, wherein: When the data corresponding to "1" is stored in the storage node, the second transistor is turned on; as well as The second transistor is turned off when the data corresponding to "0" is stored in the storage node.

14. The semiconductor device according to claim 13, wherein: When the second word line signal applied to the read word line is high and the second transistor is turned on, a second bit line signal with a high level is applied to the read bit line; as well as When the second word line signal applied to the read word line is low and the second transistor is turned off, the second bit line signal with a low level is applied to the read bit line.

15. The semiconductor device according to claim 13, wherein: The read line receives a second word line signal with a high level to turn on the third transistor; and The third transistor refreshes the data stored in the storage node.

16. A method for operating a semiconductor device, the method comprising: The first word line signal is applied to the gate of the first transistor; The data corresponding to the level of the first bit line signal applied to one terminal of the first transistor is stored in a memory node connected to the second transistor; The second word line signal is applied to one terminal of the second transistor; The second bit line signal corresponding to the data is output to another terminal of the second transistor; The second bit line signal is applied to one terminal of the third transistor; as well as Refresh the data stored in the storage node.

17. The method of claim 16, wherein: When the first word line signal is high, the first transistor is turned on; and When the first word line signal is low, the first transistor is turned off.

18. The method of claim 16, wherein: When the first bit line signal is high, the data is "1"; and When the first bit line signal is low, the data is "0".

19. The method of claim 18, wherein: When the data is "1", the second transistor is turned on; and When the data is "0", the second transistor is turned off.

20. The method of claim 18, wherein: When the data is "1", the second bit line signal has a high level; and When the data is "0", the second bit line signal has a low level.

21. The method of claim 20, wherein: When the second bit line signal is at a high level, the data stored in the storage node is refreshed to "1"; as well as When the second bit line signal is low, the data stored in the storage node is refreshed to "0".

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