Operating method of memory device, memory system, and operating method of memory system

Abstract

An operating method of a memory device, an operating method of a memory system including the memory device, and the memory system are provided. The memory system may include: a memory device including a memory cell array in which active regions of each pair of adjacent memory cells are formed to face each other, the memory cell array including a plurality of memory cells; a controller that controls the storage device; and a buffer memory storing data received from the controller and providing the stored data to the controller.

Description

[0001] Cross-references to related applications This application claims priority to Korean Application No. 10-2024-0114451, filed on August 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to integrated circuit technology, and more particularly to a method of operating a storage device, a storage system including the storage device, and a method of operating the storage system. Background Technology

[0003] Recently, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, there has been a demand for memory capable of storing information in various electronic devices such as computers and portable communication devices. Furthermore, research on memory with various characteristics is also underway.

[0004] The memory studied includes memory that stores data by utilizing the property of switching between different resistance states according to the applied voltage or current. Such memory includes resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses, etc. Summary of the Invention

[0005] In an embodiment, an operation method of a memory device may include: selecting a pair of vertical bit lines from a plurality of vertical bit lines formed by penetrating a word plane; floating the word plane; and applying a first voltage to one of the vertical bit lines in the selected pair and applying a second voltage to the other vertical bit line.

[0006] In an embodiment, an operation method of a storage system may include the steps of: correcting errors in data received from a storage device, accumulating information about addresses where errors have occurred, and storing the accumulated information; identifying a storage cell as a faulty cell when the same information about the faulty address is continuously accumulated; temporarily storing data in storage cells adjacent to the faulty cell; changing the state of the adjacent storage cell to a set state; applying voltages of different levels to the vertical bit lines of the faulty cell and the adjacent storage cell, respectively; and storing the data stored in the temporary storage step in the adjacent storage cell.

[0007] In one embodiment, a storage system may include: a storage device comprising a storage cell array in which the active regions of each pair of adjacent storage cells are formed to face each other, the storage cell array comprising a plurality of storage cells; a controller that controls the storage device; and a buffer memory that stores data received from the controller and provides the stored data to the controller. Attached Figure Description

[0008] Figure 1 A storage cell array according to an embodiment of the present disclosure is shown.

[0009] Figure 2A and Figure 2B The illustration shows storage cells included in a storage cell array according to an embodiment of the present disclosure.

[0010] Figure 3 The illustration shows storage cells included in a storage cell array according to an embodiment of the present disclosure.

[0011] Figure 4 and Figure 5 Write operations on a memory cell array according to embodiments of this disclosure are described.

[0012] Figure 6 and Figure 7 The firing operation of a memory cell array according to an embodiment of this disclosure is described.

[0013] Figure 8 The operation of a storage device according to embodiments of this disclosure is described.

[0014] Figure 9 A storage system according to an embodiment of the present disclosure is shown.

[0015] Figure 10 This is a flowchart describing the operation of a storage system according to embodiments of the present disclosure. Detailed Implementation

[0016] Various embodiments relate to methods of operation for controlling the formation location of active regions in a memory cell and using the formation location to repair faulty cells.

[0017] According to embodiments of this disclosure, the data storage reliability and durability of the memory can be enhanced.

[0018] In the following description, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0019] Figure 1 A storage cell array according to an embodiment of the present disclosure is shown. Figure 1 This is a 3D diagram of a storage cell array. Figure 2A It is a top view of the memory cells included in the memory cell array, and Figure 2B This is a side view of the storage unit.

[0020] refer to Figure 1 , Figure 2A and Figure 2B The memory cell array includes memory cells, vertical bit lines (VBLs), and word planes (WPs).

[0021] In an embodiment, the word plane WP extends in a first direction I and a second direction II. When the memory cell array includes multiple word planes WP, the memory cell array is configured such that the multiple word planes WP extend in the first direction I and the second direction II and are stacked in a third direction III. Each word plane WP includes a conductive material. In this case, Figure 1 At least one word plane WP is shown extending along the first direction I and the second direction II in a plane defined by the first direction I and the second direction II. However, the number of word planes WP is not limited to this. Figure 1 The illustrated embodiment. For example, in another embodiment, the memory cell array includes a plurality of word planes formed on the same plane defined by a first direction I and a second direction II. Furthermore, the plurality of word planes are stacked on a third direction III and included in the memory cell array.

[0022] In this embodiment, the vertical bit lines VBL are formed to extend in the third direction III. Furthermore, the memory cell array is configured to include a plurality of vertical bit lines VBL extending in the third direction III. The plurality of vertical bit lines VBL each penetrate the word plane WP in the third direction III. The vertical bit lines VBL comprise a conductive material. For example, the vertical bit lines VBL are illustrated as cylindrical; however, the embodiment is not limited thereto.

[0023] In this embodiment, the memory material layer is formed around each of a plurality of vertical bit lines VBLs. In this case, the memory material layer comprises a chalcogenide-based material, and the threshold voltage level of the memory material layer varies depending on the direction of the current flowing through it. In this configuration, portions of the memory material layer function as memory cells to perform data storage operations. Figure 2BAs shown, the memory cell corresponds to a portion of the memory material layer disposed between the word plane WP and the vertical bit line VBL. The threshold voltage level of the memory cell changes according to the current direction between the word plane WP and the vertical bit line VBL.

[0024] In summary, the memory cell array according to embodiments of the present disclosure includes: a plurality of word planes (WPs) stacked on a third direction III and extending in a first direction I and a second direction II; a plurality of vertical bit lines (VBLs) extending on the third direction III and penetrating the plurality of word planes (WPs); and a memory material layer surrounding each of the plurality of vertical bit lines (VBLs). Consequently, the memory cell array according to embodiments of the present disclosure includes a plurality of memory cells, each memory cell formed between the word planes (WPs) and the vertical bit lines (VBLs).

[0025] Figure 3 The illustration shows storage cells included in a storage cell array according to an embodiment of the present disclosure. Figure 3 A portion of the memory material layer disposed between the vertical bit line VBL and the word plane WP is shown, and said portion of the memory material layer functions as a memory cell through an ignition operation.

[0026] refer to Figure 3 Through an ignition operation, the portion of the memory material layer located between the word plane WP and the vertical bit line VBL is divided into a first region, Cell_A, and a second region, Cell_B. Cell_A has a lower threshold voltage than Cell_B. Cell_A performs the operation of a memory cell to store data. Cell_B is a region where the threshold voltage does not change within the voltage or current range during which the storage operation is performed in Cell_A. Therefore, Cell_A is used as a data storage region and is referred to as the active region, where a change in threshold voltage occurs within the voltage or current range during the storage operation.

[0027] Therefore, when a voltage is applied to both the word plane WP and the vertical bit line VBL, and the voltage difference between WP and VBL exceeds the threshold voltage level of the active region Cell_A, current flows through Cell_A between WP and VBL. The threshold voltage of Cell_A changes depending on the direction of this current. For example, when current flows from VBL through Cell_A to WP, the threshold voltage of Cell_A is lower than when current flows in the opposite direction from WP to VBL.

[0028] For example, when a first voltage is applied to the word plane WP and a second voltage with a higher level than the first voltage is applied to the vertical bit line VBL, current flows from the vertical bit line VBL through the active region Cell_A to the word plane WP. In this case, the state of the active region Cell_A is changed to the first state.

[0029] On the other hand, when a second voltage is applied to the word plane WP and a first voltage with a lower level than the second voltage is applied to the vertical bit line VBL, current flows from the word plane WP through the active region Cell_A to the vertical bit line VBL. In this case, the state of the active region Cell_A is changed to the second state. The threshold voltage of the active region Cell_A in the first state is different from the threshold voltage in the second state. The voltage difference between the first voltage and the second voltage is greater than the threshold voltage level of the active region Cell_A.

[0030] Figure 4 and Figure 5 Write operations on a memory cell array according to embodiments of this disclosure are described.

[0031] A write operation changes the state of a selected memory cell among multiple memory cells in a memory cell array to either a first state or a second state. A memory cell in the first state has a lower threshold voltage than a memory cell in the second state. The first state is called the set state (SET), and the second state is called the reset state (RST). Therefore, a write operation that changes the state of the selected memory cell to the first state (i.e., the set state (SET)) is called a set write operation (SET WRITE). A write operation that changes the state of the selected memory cell to the second state (i.e., the reset state (RST)) is called a reset write operation (RST WRITE).

[0032] Figure 4 The SETWRITE operation describes the set write operation that changes the state of the selected memory cell to the set state (SET).

[0033] refer to Figure 4A SET WRITE operation is performed by selecting at least one word plane WP1 from a plurality of word planes WP0, WP1, and WP2, and at least one vertical bit line VBL_s from a plurality of vertical bit lines VBL. In this case, a first voltage is applied to the selected word plane WP1, and a second voltage is applied to the selected vertical bit line VBL. The second voltage has a higher level than the first voltage. The first voltage can be a negative voltage, and the second voltage can be a positive voltage. For example, the first voltage is -5 V, and the second voltage is 5 V. During the SET WRITE operation, the unselected word planes WP0 and WP2 are grounded.

[0034] Therefore, during the SET WRITE operation, the write current flows from the selected bit line VBL_s to the selected word plane WP1. In this case, when viewed from a top view of the selected word plane WP1, the write current can be seen flowing from the selected bit line VBL_s through the active region Cell_A to the selected word plane WP1.

[0035] As a result, the threshold voltage of the active region Cell_A during the SET WRITE operation will be set to a level that is lower than the threshold voltage during the RST WRITE operation.

[0036] Therefore, the active region Cell_A formed between the selected word plane WP1 and the selected bit line VBL_s functions as a storage cell, wherein the threshold voltage of the active region Cell_A varies based on the direction of the current flowing through the active region Cell_A.

[0037] Figure 5 The reset write operation RSTWRITE is described, which changes the state of the selected memory cell to the reset state RST.

[0038] refer to Figure 5 A reset write operation (RST WRITE) is performed by selecting at least one word plane WP1 from a plurality of word planes WP0, WP1, and WP2, and at least one vertical bit line VBL_s from a plurality of vertical bit lines VBL. In this case, a first voltage is applied to the selected vertical bit line VBL_s, while a second voltage is applied to the selected word plane WP1. The first voltage has a lower level than the second voltage. The first voltage can be a negative voltage, while the second voltage can be a positive voltage. For example, the first voltage is -5 V, and the second voltage is 5 V. During the reset write operation RST WRITE, the unselected word planes WP0 and WP2 are grounded.

[0039] Therefore, during the reset write operation RST WRITE, the write current flows from the selected word plane WP1 to the selected vertical bit line VBL_s. In this case, when viewed from a top view of the selected word plane WP1, the write current can be seen flowing from the selected word plane WP1 through the active region Cell_A to the selected vertical bit line VBL_s.

[0040] As a result, the threshold voltage of the active region Cell_A during the reset write operation RST WRITE will be formed to have a higher level than the threshold voltage during the set write operation SET WRITE.

[0041] Therefore, the active region Cell_A formed between the selected word plane WP1 and the selected bit line VBL_s functions as a storage cell, wherein the threshold voltage of the active region Cell_A varies based on the direction of the current flowing through the active region Cell_A.

[0042] Figure 6 and Figure 7 The ignition operation of a memory cell array according to an embodiment of this disclosure is described. The ignition operation is used to form a portion of a memory material layer formed between the word plane WP and the vertical bit line VBL as an active region Cell_A. The active region Cell_A formed by the ignition operation is a region having a lower threshold voltage than region Cell_B, which is the remainder of the memory material layer.

[0043] With the word plane WP floating, a first voltage of -5 V is applied to one of the two selected vertical bit lines, and a second voltage of 5 V is applied to the other of the two selected vertical bit lines. The two selected vertical bit lines form a pair.

[0044] In this configuration, current flows from the vertical bit line where a second voltage of 5 V has been applied to it to the vertical bit line where a first voltage of -5 V has been applied. Within the region surrounding the selected vertical bit line pair of memory cells, each region through which the current flows is formed as an active region Cell_A.

[0045] Therefore, in a memory cell array according to an embodiment of the present disclosure, a pair of active regions Cell_A facing each other are formed along selected vertical bit lines during ignition operation.

[0046] When the operation of selecting a vertical bit line pair and applying a first voltage of -5V and a second voltage of 5V to the selected vertical bit line pair is repeated sequentially, paired facing active regions Cell_A are formed. As a result, the active regions of multiple memory cells included in a word plane are arranged in facing pairs, as shown below. Figure 7 As shown.

[0047] As described above, in a memory cell array according to an embodiment of this disclosure, a pair of active regions facing each other are formed based on selected vertical bit line pairs during an ignition operation. Furthermore, by repeating the operation, the active regions of memory cells included in the word plane are formed to face each other.

[0048] Therefore, a storage cell array consists of regularly arranged active regions.

[0049] As mentioned above, Figure 6 and Figure 7 As shown, the ignition operation of the memory cell array is an example of the ignition operation for one of the multiple word planes WP0, WP1 and WP2 stacked on the third direction III.

[0050] In another embodiment, during the ignition operation of the memory cell, a number of word planes among the multiple word planes WP0, WP1 and WP2 are floated, allowing ignition operations to be performed on the floated word planes.

[0051] Figure 8 The operation of a storage device according to embodiments of this disclosure is described. Figure 8 The repair operation for a faulty cell that cannot function properly as a storage unit is shown.

[0052] refer to Figure 8 In cell A, a gap appears in a storage unit (i.e., in the active region Cell_A). The active region Cell_A containing the gap cannot function properly as a storage unit. Gaps may appear in the active region Cell_A when repeated read or write operations are performed on the storage unit. Storage units in the active region Cell_A containing gaps are considered faulty units.

[0053] refer to Figure 8During the repair operation, the vertical bit line closest to the vertical bit line corresponding to the active region Cell_A with the gap is selected. This selected vertical bit line is different from the vertical bit line selected during the ignition operation to pair with the vertical bit line corresponding to the active region Cell_A. Then, the state of the active region corresponding to the selected vertical bit line is set to the SET state. Subsequently, when the word plane WP is floated, a first voltage of -5 V is applied to the vertical bit line corresponding to the active region Cell_A with the gap, and a second voltage of 5 V is applied to the selected vertical bit line.

[0054] In this case, current flows from the active region corresponding to the selected vertical bit line to the vertical bit line corresponding to the active region Cell_A with gaps.

[0055] refer to Figure 8 C, when the current is as Figure 8 As shown in B, during the flow, a new active region Cell_An is formed in the memory cell where gaps appear. The new active region Cell_An is formed in the position or direction closest to the selected vertical bit line.

[0056] When a new active region Cell_An is formed in the faulty cell, no current flows to the active region Cell_A with the gap.

[0057] As a result, the threshold voltage of the new active region Cell_An changes based on the direction of the current between the vertical bit line and the word plane, allowing previously faulty cells to function normally as memory cells.

[0058] In this embodiment, after the active region is regularly formed during the ignition operation, a repair operation for the faulty unit is performed.

[0059] Figure 9 A storage system according to an embodiment of the present disclosure is shown.

[0060] refer to Figure 9 The storage system includes a storage device 100, a controller 200, and a buffer memory 300.

[0061] The storage device 100 includes a storage cell array 110, a read circuit 120, and a write circuit 130.

[0062] like Figure 1As shown in Figure 2, the memory cell array 110 includes a plurality of vertical bit lines, a plurality of word planes, and a plurality of memory material layers. For example, each of the plurality of word planes is formed in a plane defined by a first direction I and a second direction II, and the plurality of word planes are stacked on a third direction III. Each of the plurality of vertical bit lines is formed to penetrate the plurality of stacked word planes on the third direction III, and each of the plurality of vertical bit lines is surrounded by a corresponding memory material layer of the plurality of memory material layers. In this case, a portion of the memory material layer located between the word plane and the vertical bit line serves as a memory cell.

[0063] In an embodiment, such as Figure 6 and Figure 7 As shown, when the word plane is floating, the memory cell array 110 performs an ignition operation by applying a first voltage and a second voltage to a pair of selected vertical bit lines, respectively. Furthermore, by repeatedly selecting the vertical bit line pairs and performing ignition operations on them, active regions facing each other are formed in each pair of memory cells included in the memory cell array 110.

[0064] In one embodiment, the memory cell array 110 is in a state where the ignition operation according to an embodiment of the present disclosure has been completed for all memory cells.

[0065] In one embodiment, the read circuit 120, under the control of the controller 200, senses and determines data stored in the memory cells of the memory cell array 110, and transmits the determined data to the controller 200. The read circuit 120 is configured to: select at least one word plane constituting the memory cell array 110, select at least one vertical bit line, and select at least one memory cell. The read circuit 120 senses and determines the data stored in the selected memory cell, and transmits the determined data to the controller 200.

[0066] In an embodiment, the write circuit 130, under the control of the controller 200, stores data in the memory cells of the memory cell array 110. The write circuit 130 is configured to: select at least one word plane constituting the memory cell array 110, select at least one vertical bit line, and select at least one memory cell. Figure 4 and Figure 5 As shown, the write circuit 130 stores data in the selected memory cell by performing a set write operation or a reset write operation.

[0067] In an embodiment, in response to a request from the host, the controller 200 controls the data to be stored in the memory cell array 110 of the storage device 100 or the data stored in the memory cell array 110 to be output. Furthermore, the controller 200 includes ECC circuitry 210 to check whether the data received from the storage device 100 contains errors and to correct such errors.

[0068] In this embodiment, under the control of the controller 200, the buffer memory 300 stores data received from the controller 200 or outputs the stored data to the controller 200.

[0069] In an embodiment, the storage system configured as described above according to an embodiment of the present disclosure operates as follows.

[0070] In one embodiment, the controller 200 controls the storage device 100 to store data in or output data stored in the storage device 100. In this case, the controller 200 corrects errors in the data received from the storage device 100 via the ECC circuit 210.

[0071] In one embodiment, when errors occur consecutively at the same address, the controller 200 determines that the storage unit at that address is a faulty unit.

[0072] In this embodiment, during the repair operation, the controller 200 selects the vertical bit line closest to the vertical bit line of the faulty unit, and receives data stored in the memory cell of the selected vertical bit line via the read circuit 120. The controller 200 stores the received data in the buffer memory 300. The selected vertical bit line is chosen from among the vertical bit lines that did not pair with the vertical bit line of the faulty unit during the ignition operation. During the repair operation, the read circuit 120 selects the word plane where the faulty unit is located, selects the vertical bit line closest to the vertical bit line of the faulty unit, and reads the data stored in the memory cell corresponding to the selected vertical bit line, thereby transmitting the data to the controller 200.

[0073] Subsequently, the controller 200 performs a SET WRITE operation on the memory cell between the selected word plane and the selected vertical bit line.

[0074] In the SET WRITE operation, when the selected word plane where the faulty cell is located is floated, the controller 200 applies a first voltage of -5V to the vertical bit line of the faulty cell and a second voltage of 5V to the selected vertical bit line. As a result, as... Figure 8 As shown in B, current flows from the selected vertical bit line through the selected word plane to the vertical bit line of the faulty cell. Therefore, as... Figure 8As shown in Figure C, a new active region is formed between the vertical bit line of the faulty cell and the selected word plane. A new active region is formed in the direction of the selected vertical bit line. The controller 200 applies a first voltage of -5V to the vertical bit line of the faulty cell (e.g., ...) via the write circuit 130. Figure 5 (as shown), and a second voltage of 5 V is applied to the selected vertical bit line (as shown) via the write circuit 130. Figure 4 (As shown).

[0075] Subsequently, the controller 200 migrates the data stored in the buffer memory 300 to the memory cell between the selected vertical bit line and the word plane including the faulty cell via the write circuit 130. As a result, after the repair operation of the faulty cell is completed, the data in the memory cell between the selected vertical bit line and the word plane is restored.

[0076] In this way, the storage system according to embodiments of the present disclosure can repair faulty units to enable them to operate normally again, such as performing write or read operations.

[0077] Figure 10 This is a flowchart describing the operation of a storage system according to embodiments of the present disclosure.

[0078] refer to Figure 10 The operation method of the storage system includes: error accumulation management step S1, fault unit determination step S2, temporary data storage step S3, set write execution step S4, simultaneous operation step S5, and data recovery step S6.

[0079] In this embodiment, the error accumulation management step S1 includes: the step of the controller 200 receiving data from the storage device 100 and correcting errors in the received data, and the step of the controller 200 accumulating information about the addresses where errors have occurred and storing the accumulated information.

[0080] In this embodiment, the fault unit determination step S2 includes the step of determining a fault unit based on the accumulated information. In the fault unit determination step S2, when it is determined that the number of times an error has occurred for the same address exceeds a preset number, the corresponding memory unit is determined to be a fault unit.

[0081] When the storage unit is determined to be a faulty unit (yes) in the faulty unit determination step S2, the temporary data storage step S3 is executed.

[0082] On the other hand, if the storage unit is not determined to be a faulty unit (No) in the faulty unit determination step S2, the operation method of the storage system ends. After the operation method ends, the storage system requests the storage device to perform normal operations such as read operations or write operations.

[0083] In this embodiment, the temporary data storage step S3 includes storing data from a memory cell adjacent to the faulty cell in the buffer memory 300. The adjacent memory cell is a memory cell formed between a word plane identical to the word plane of the faulty cell and the vertical bit line closest to the vertical bit line of the faulty cell. Furthermore, the vertical bit line of the adjacent memory cell is a vertical bit line that was not selected in pair with the vertical bit line of the faulty cell during the ignition operation.

[0084] In this embodiment, the set-write execution step S4 includes performing a set-write operation (SET WRITE) on the adjacent memory cell in the temporary data storage step S3. In this case, the state of the adjacent memory cell is changed to the set state (SET). Therefore, through the set-write execution step S4, the state of the adjacent memory cell is changed to have a resistance lower than that of the reset state (RST).

[0085] In an embodiment, the simultaneous operation step S5 includes applying a first voltage of -5V and a second voltage of 5V to the vertical bit line of the faulty cell and the vertical bit line of the adjacent memory cell, respectively, while simultaneously floating the word plane including the faulty cell. For example, the simultaneous operation step S5 includes applying a first voltage of -5V to the vertical bit line of the faulty cell and simultaneously applying a second voltage of 5V to the vertical bit line of the adjacent memory cell. In this case, a new active region is formed in the faulty cell in the direction of the vertical bit line of the adjacent memory cell. As a result, the faulty cell including the new active region operates as a normal memory cell.

[0086] In this embodiment, data recovery step S6 includes: storing data stored in the buffer memory 300 in an adjacent storage cell, wherein a set-write operation has already been performed on the adjacent storage cell in the set-write execution step S4. That is, the data stored in the buffer memory 300 is migrated to the adjacent storage cell. In other words, data recovery step S6 is a step of restoring data to the adjacent storage cell used to repair the faulty cell.

[0087] After data recovery step S6, the operation method ends, and the storage system resumes normal operations such as read or write operations.

[0088] By using the operation method of the storage system according to embodiments of the present disclosure, the storage system can repair faulty units in the storage device.

[0089] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is only for explaining embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Various substitutions, modifications, and changes of all types can be made to the embodiments by those skilled in the art to which this disclosure pertains without departing from the technical concept of this disclosure as defined in the appended claims, and such substitutions, modifications, and changes should be construed as falling within the scope of this disclosure.

Claims

1. A method of operating a storage device, the method comprising: Select a pair of vertical bit lines from multiple vertical bit lines that penetrate the word plane; Make the character plane float; as well as A first voltage is applied to one of the vertical bit lines in the vertical bit line pair, and a second voltage is applied to the other vertical bit line in the vertical bit line pair.

2. The method of operating the storage device according to claim 1, wherein, The operating method is performed during the manufacturing process of the storage device.

3. The method of operating the storage device according to claim 1, wherein, The operation method is performed when a faulty cell is detected in the memory cell corresponding to the one vertical bit line during operation of the memory device.

4. The method of operating the storage device according to claim 1, further comprising: Repeat: Select a vertical bit line pair, apply a first voltage to one vertical bit line, and apply a second voltage to another vertical bit line.

5. The method of operating the storage device according to claim 1, wherein, The first voltage has a lower level than the second voltage.

6. The method of operating the storage device according to claim 5, wherein, The first voltage is a negative voltage, while the second voltage is a positive voltage.

7. The method of operating the storage device according to claim 1, wherein, The selection includes: Select adjacent vertical bit line pairs.

8. A method of operating a storage system including a storage device, the method comprising: Correcting errors in the data received from the storage device, accumulating information about the addresses where the errors have occurred, and storing the accumulated information; The faulty unit is determined based on the accumulated information; Temporarily store the data in the storage unit adjacent to the faulty unit; Change the state of adjacent memory cells to the set state; Voltages with different levels are applied to the vertical bit line of the faulty cell and the vertical bit line of the adjacent memory cell, respectively. as well as The temporarily stored data is migrated to the adjacent storage unit.

9. The operating method according to claim 8, wherein, The method of determining the fault unit based on the accumulated information includes: When it is determined, based on the accumulated information, that the number of times the error has occurred for the address exceeds a preset number, the storage unit corresponding to the address is identified as the faulty unit.

10. The operating method according to claim 8, wherein, The adjacent memory cell is positioned between the vertical bit line adjacent to the vertical bit line of the faulty cell and the word plane including the faulty cell.

11. The operating method according to claim 9, wherein, The temporary storage includes: The data of the adjacent storage units is stored in the buffer memory of the storage system.

12. The operating method according to claim 10, wherein, The changes include: Apply a first voltage to the word plane; and A second voltage with a higher level than the first voltage is applied to the adjacent vertical bit line.

13. The operating method according to claim 12, wherein, Applying voltages with different levels includes: Make the character plane float; Apply the first voltage to the vertical bit line of the faulty cell; and The second voltage is applied to the vertical bit line of the adjacent memory cell.

14. A storage system, comprising: A storage device, the storage device including a storage cell array, the storage cell array including a plurality of storage cells, wherein the active regions of each pair of adjacent storage cells among the plurality of storage cells are configured to face each other; Controller, the controller controlling the storage device; and A buffer memory that stores data received from the controller and provides the stored data to the controller.

15. The storage system according to claim 14, wherein, The controller controls the storage device to store data in the active areas of the plurality of storage cells, and to receive the data stored in the active areas of the plurality of storage cells.

16. The storage system according to claim 15, wherein, The controller corrects errors in the data received from the storage device and manages information about the addresses where the errors have occurred.

17. The storage system according to claim 16, wherein, The controller accumulates information about the address where the error has occurred, stores the accumulated information, and when it is determined based on the accumulated information that the number of times the error has occurred for the address exceeds a preset number, it identifies the storage unit corresponding to the address as a faulty unit.

18. The storage system according to claim 17, wherein, The controller stores the data of the storage unit adjacent to the fault unit in the buffer memory.

19. The storage system according to claim 18, wherein, The adjacent memory cell is a memory cell located between a vertical bit line adjacent to the vertical bit line of the faulty cell and a word plane including the faulty cell.

20. The storage system according to claim 19, wherein, In the operation of repairing the faulty cell, the storage device, under the control of the controller, floats the word plane, applies a first voltage to the vertical bit line of the faulty cell, and applies a second voltage to the adjacent vertical bit line.

21. The storage system according to claim 20, wherein, The first voltage has a lower level than the second voltage.

22. The storage system according to claim 21, wherein, When the operation of applying the first voltage to the vertical bit line of the faulty cell and applying the second voltage to the adjacent vertical bit line is completed, the controller migrates the data stored in the buffer memory to the adjacent memory cell.

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