Data reading method of memory, storage device and storage medium
By utilizing bit flip information in NAND flash memory to determine the type of anomaly and adjusting the read voltage or refreshing the data, the problem of high read repetition rate is solved, improving the performance and reliability of storage products.
Patent Information
- Application Number
- CN202411134548.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2026-03-03
AI Technical Summary
In existing technologies, NAND flash memory has a high reread rate, which leads to increased data reading time and energy consumption. Furthermore, existing optimization methods such as sticky retries and dynamic valley tracking have problems of blindness and excessive resource overhead.
By reading the programming unit, the type of failure bit count anomaly is determined by using bit flip information. The reading voltage is adjusted or a data refresh operation is performed to reduce the reread rate.
It effectively reduces the reread rate of background inspection reads and host reads, improving the performance and reliability of storage products.
Smart Images
Figure CN121601005A_ABST
Abstract
Description
Technical Field
[0001] This application relates primarily to the field of computer technology, and in particular to a data reading method for a memory, a storage device, and a storage medium. Background Technology
[0002] In NAND flash memory, read retry rate is a crucial factor affecting performance. If a data block is read incorrectly for various reasons, the system may attempt to read it multiple times to ensure correct data access. A higher read retry rate means increased time and energy consumption for data read operations. To reduce read retry rate, current products typically perform background data checks. When the FBC (Failure Bit Count) exceeds a certain threshold, data in the same storage block is refreshed or garbage collected. When encountering host reads, sticky retries or dynamic wear leveling are used to optimize Vread (read voltage) and reduce the read retry rate. However, sticky retries may have blind selection issues in the early stages, and the selected read retry level may not be optimal for the current scenario; while using dynamic wear leveling to optimize Vread consumes excessive resources, requiring multiple reads and thus reducing host read bandwidth. Summary of the Invention
[0003] The main objective of this application is to provide a data reading method for a memory to solve the problem of blind rereading in the early background, thereby reducing the reread rate of background inspection reads and host reads and improving the performance of storage products.
[0004] To address the aforementioned problems, this application provides a data reading method for a memory. The method includes: performing a read operation on a programming unit to obtain target data; determining the corresponding failure bit count anomaly type based on bit flip information of the target data; wherein the failure bit count anomaly type includes a first type of anomaly caused by read voltage offset and a second type of anomaly caused by a rise in the trough of the memory cell conduction voltage probability density curve; adjusting the read voltage in response to the first type of anomaly; or performing a data refresh operation or a garbage collection operation in response to the second type of anomaly.
[0005] In one embodiment, performing a read operation on the programming unit to obtain target data includes: performing a read operation on the programming unit to obtain at least two pages of data of the programming unit, the at least two pages of data including low page data; determining the corresponding failure bit count anomaly type based on the bit flip information of the target data includes: determining the corresponding failure bit count anomaly type based on the bit flip information of the at least two pages of data.
[0006] In one embodiment, determining the corresponding failure bit count anomaly type based on bit flip information of at least two pages of data includes: obtaining the first number of bits that are bit 1 in at least two pages of data corresponding to Lx; wherein Lx is the xth waveform of the 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; and determining the corresponding failure bit count anomaly type based on the first number of bits.
[0007] In one embodiment, determining the corresponding failure bit count anomaly type based on bit flip information of at least two pages of data includes: decoding at least two pages of data to obtain decoded data; obtaining a second number of bits in the at least two pages of data and the decoded data that are identical to preset bit values corresponding to Lx and Lx-1; and determining the corresponding failure bit count anomaly type based on the second number of bits; wherein Lx is the x-th waveform among 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; Lx-1 is the (x-1)-th waveform among 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer.
[0008] In one embodiment, the method further includes: in response to at least two page data decoding failures, performing a data refresh operation or a garbage collection operation.
[0009] In one embodiment, adjusting the read voltage includes: adjusting the read voltage using a preset first adjustment level in response to the number of times the data corresponding to La flips to the data corresponding to La-1 is greater than a set first threshold; and adjusting the read voltage using a preset second adjustment level in response to the number of times the data corresponding to L0 flips to the data corresponding to Lb is greater than a set second threshold. The first and second adjustment levels are different, where La is the a-th waveform among 2N waveforms of the memory cell conduction voltage probability density curve, a = 0, 1, ..., 2N-1, Lb is the b-th waveform among 2N waveforms of the memory cell conduction voltage probability density curve, b = 0, 1, ..., 2N-1, and N is a positive integer.
[0010] In one embodiment, after the step of reading the programming unit to obtain the target data, the method further includes: determining whether the failure bit count is less than a set counting threshold; if not, performing a step of determining the corresponding failure bit count exception type based on the bit flip information of the target data.
[0011] In one embodiment, after adjusting the read voltage, the method further includes: determining whether the failure bit count is less than a set counting threshold; if yes, updating the initial data corresponding to the programming unit; if no, performing a data refresh operation or a garbage collection operation.
[0012] To address the aforementioned problems, this application also provides a storage device comprising: a memory; and a processor connected to the memory, the processor being configured to execute a memory data reading method as described in any of the above embodiments.
[0013] To address the aforementioned issues, this application also provides a computer-readable storage medium storing program data, which, when executed by a processor, is used to implement the memory data reading method described in any of the above embodiments.
[0014] By using the above method, the abnormal type that causes the read voltage offset is identified to determine the data status, thereby reducing the host reread rate and improving read effectiveness. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0016] Figure 1 This is a flowchart illustrating the steps of an embodiment of the data reading method for a memory provided in this application;
[0017] Figure 2 This is a schematic diagram of the curve showing the reason for a large FBC in one embodiment of the data reading method for the memory provided in this application;
[0018] Figure 3 This is a schematic diagram of a method for determining the type of failure bit count exception in one embodiment of the memory data reading method provided in this application;
[0019] Figure 4a yes Figure 3 A schematic diagram of partial bit-flipping information in the first embodiment of the Type3 scheme;
[0020] Figure 4b yes Figure 3 A schematic diagram of partial bit-flipping information in the second embodiment of the Type3 scheme;
[0021] Figure 5 This is a schematic diagram of the address layout in an implementation provided in this application;
[0022] Figure 6a This is a schematic diagram of a first adjustment scheme for the read voltage in an embodiment of the data read method for the memory provided in this application;
[0023] Figure 6bThis is a schematic diagram of a second adjustment scheme for the read voltage in one embodiment of the data read method for the memory provided in this application;
[0024] Figure 7 This is a flowchart illustrating an embodiment of the data reading method for a memory provided in this application;
[0025] Figure 8 This is a schematic diagram of the structure of an embodiment of the storage device provided in this application. Detailed Implementation
[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0027] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0029] In flash memory, the read retry rate refers to the ratio of data that needs to be read multiple times to be retrieved from a flash memory device. In flash memory operations, if a data block is read incorrectly for various reasons, the system may attempt to retrieve the data multiple times to ensure correct access. A higher read retry rate means that the time and energy consumed during data retrieval operations will increase accordingly. Read retry rate is generally one of the important indicators for measuring the performance and reliability of flash memory. A lower read retry rate indicates that the flash memory device is more reliable and efficient in reading data, while a higher read retry rate may indicate problems with the memory or its controller, such as storage media aging or the need for repeated error correction code (ECC) calculations. Read retry rate is usually one of the important factors to consider when designing and selecting flash memory devices.
[0030] Currently, when the host computer reads data, sticky retries or dynamic wear leveling are commonly used to optimize read voltage and reduce the reread rate. Sticky retries refer to the system repeatedly attempting to read a data block that cannot be read until it is successfully read or the maximum allowed number of attempts is reached. Dynamic wear leveling, on the other hand, dynamically monitors and records the usage of flash memory cells. The controller can determine when and in which memory cells to write data based on real-time conditions, ensuring a balanced distribution of wear across memory cells and thus improving flash memory lifespan and performance. Therefore, addressing the issue of blind early background rereads to reduce the reread rate of background check reads and host reads is a crucial factor.
[0031] Therefore, this application provides a data reading method for a memory, which finds a suitable reading voltage at a low cost during background data inspection and host reading, thereby judging the risk of data failure and reducing the probability of data loss and reread rate.
[0032] See Figure 1 As shown, Figure 1 This is a schematic flowchart illustrating the steps of an embodiment of the data reading method for a memory provided in this application; specifically, the data reading method for the memory includes the following steps:
[0033] Step S10: Perform a read operation on the programming unit to obtain the target data.
[0034] Optionally, in one embodiment, performing a read operation on the programming unit to obtain target data includes: performing a read operation on the programming unit to obtain at least two pages of data of the programming unit, wherein the at least two pages of data include lower page data.
[0035] In flash memory organization, low-order and high-order data are stored on different physical pages. The physical page containing low-order data is called the Lower Page (LP), and the physical page containing high-order data is called the Upper Page (UP). LP typically refers to the data page stored at the lower address in the physical memory unit, and UP refers to the data page stored at the higher address in the same physical memory unit. The Middle Page (MP) refers to the data page stored at the middle address in the same physical memory unit. In essence, low-order, middle-order, and high-order page data correspond to different data storage states within the memory unit; low-order page data represents data stored under LP, middle-order page data under MP, and high-order page data under HP. Similarly, low-order page decoded data refers to decoded data under LP, middle-order page decoded data refers to decoded data under MP, and high-order page decoded data refers to decoded data under HP.
[0036] Understandably, after prolonged use or when the NAND flash memory cell is of poor quality, the voltage distribution between each state in the programming cells can change. This is because, after long-term use, the behavior of electrons becomes more random and difficult to control, leading to excessive overlap in the distribution area between states and overlapping conduction voltages between different states. When the theoretical read voltage is applied to the programming cell, either programming state near the read voltage may cause the programming cell to conduct, making it impossible to distinguish the state of the programming cell and resulting in data errors. For example, when reading data on a word line, the same read voltage is applied to the gates of all cells on that word line depending on the page being read. Cells in the same programming state will have inconsistent conduction voltages, some biased to the left and some to the right. Cells in different programming states (e.g., TLC has 8 states) will, under normal circumstances, conduction will occur in the state programmed to the left of the read voltage, while conduction will not occur in the state programmed to the right.
[0037] The VT curve (probability density curve of conduction voltage) shifts to the left:
[0038] If the current cell is programmed to the right of the theoretical read voltage, theoretically the cell will not conduct after the read voltage is applied to the cell. However, if the conduction voltage probability density curve shifts significantly to the left, the state curve immediately to the right of the read voltage will intersect with the read voltage. In this case, if the cell is programmed to the left part of the normal distribution with a small probability, the cell cells smaller than the read voltage will conduct, causing the programmed state to be misjudged as the cell being in the state to the left of the read voltage.
[0039] The VT curve (probability density curve of conduction voltage) shifts to the right:
[0040] If the current cell is programmed to the left of the theoretical read voltage, theoretically the cell will conduct after the read voltage is applied. However, if the conduction voltage probability density curve shifts significantly to the right, the state curve immediately to the left of the read voltage will intersect with the read voltage. In this case, if the cell is programmed to the right part of the normal distribution with a small probability, the cell cells above the read voltage will not conduct, causing the programmed state to be misjudged as the cell being in the right part of the read voltage.
[0041] Therefore, the target data is obtained by reading the original data and utilizing the bit-flipping information of the changes before and after.
[0042] Step S20: Determine the corresponding failure bit count anomaly type based on the bit flip information of the target data. The failure bit count anomaly types include a first type of anomaly caused by read voltage offset and a second type of anomaly caused by a rise in the trough of the memory cell conduction voltage probability density curve.
[0043] Understandably, the Fail bit count (FBC), as mentioned in this application, is one of the key parameters characterizing the reliability of 3D NAND devices. A high FBC leads to a significant loss in random read performance, which is detrimental to the QoS of fast storage applications. Therefore, reducing the FBC in 3D NAND Flash is essential.
[0044] like Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the causes of a high FBC (Failure Rate Comparison) in one embodiment of the memory data reading method provided in this application. In flash memory reading, the causes of a high FBC can be broadly categorized into two types: one is caused by a mismatch between the read voltage and the threshold voltage, such as... Figure 2As shown in Case 1, although the Failure Bit Count (FBC) is high, there is no risk to data reliability, and the Failure Bit Count can be significantly reduced by appropriately lowering the read voltage. Another approach is as follows... Figure 2 As shown in Case 2, the read voltage position has been placed near the trough, but because the trough itself is high, the failure bit count (FBC) value is high, and the data reliability risk is high at this time. Furthermore, moving the read voltage position can no longer significantly reduce the failure bit count (FBC) value.
[0045] Therefore, in this application, the bit-flipping information generated during the reading process is used to determine the reliability status of the data and the possible types of data failure. Based on the failure type, the corresponding Retry level is obtained to reduce the reread rate or to refresh the data.
[0046] Optionally, in one embodiment, determining the corresponding failure bit count anomaly type based on the bit flip information of the target data includes: determining the corresponding failure bit count anomaly type based on the bit flip information of at least two pages of data.
[0047] like Figure 3 As shown, Figure 3 This is a schematic diagram illustrating a method for determining the type of failure bit count anomaly in one embodiment of the memory data reading method provided in this application. It is understood that, taking a certain Gray code of TLC as an example, three types of determination methods are provided, such as... Figure 3 As shown, the first method, Type 1, reads three pages of data from a TLC and uses this data to read the RawData within those pages for judgment. In flash memory, RawData likely represents data stored in the flash chip that has not undergone any encoding, compression, or processing. This data is generally considered the most basic and lowest-level data form, which can be directly read and written by the computer system. When specific data stored in flash memory needs to be accessed, the computer system reads this raw data into memory and parses and processes it as necessary. This solution uses TLC as an example; other embodiments also apply to flash memory types including but not limited to SLC / MLC / TLC / QLC / PLC, etc. Δ is a preset value.
[0048] Optionally, in one embodiment, determining the corresponding failure bit count anomaly type based on bit flip information of at least two pages of data includes: obtaining the first number of bits that are bit 1 in at least two pages of data corresponding to Lx; wherein Lx is the xth waveform among 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; and determining the corresponding failure bit count anomaly type based on the first number of bits.
[0049] Understandable, such as Figure 3 As shown in Type 1, the number of bits read from L7 is the number of bits where RLP / RMP / RUP = 1, denoted as the first number of bits; for example, in one embodiment, RLP / RMP / RUP is the Raw Data of LP / MP / UP Read Out; wherein, by reading the number of bits in L7 which is less than or equal to one-eighth of the total number of bits minus Δ, that is, Where Δ > 0, Δ is a preset value based on actual conditions, and L7bits refers to the number of bits in the L7 state where RLP / RMP / RUP = 1, which can be considered a strong retention scenario. A strong retention scenario refers to a usage environment or application scenario with high durability and long-term data retention capabilities. In this scenario, flash memory devices need to maintain data stability and reliability for extended periods to ensure data security and integrity.
[0050] Optionally, in one embodiment, determining the corresponding failure bit count anomaly type based on the bit flip information of at least two pages of data includes: decoding at least two pages of data to obtain decoded data; obtaining a second number of bits in the at least two pages of data and the decoded data that are identical to preset bit values corresponding to Lx and Lx-1; and determining the corresponding failure bit count anomaly type based on the second number of bits; wherein Lx is the x-th waveform among 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; Lx-1 is the (x-1)-th waveform among 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer.
[0051] Regarding the method described above for determining the corresponding failure bit count anomaly type based on the bit flip information of the target data, two different schemes were employed. The first scheme does not require successful decoding, for example... Figure 3The Type 1 approach directly determines the data status by using bit-flipping information to identify whether the data is in a Retention or Read Disturb state, and rereads it based on the data status, without requiring successful decoding. The second approach involves attempting to read data from the programming unit with different Initial Read Offsets until all the necessary data for the programming unit is successfully decoded, or the number of attempts exceeds a set threshold. The Initial Read Offset is typically used for sector or page-level data access in flash memory devices, especially during low-level data operations such as erasing, programming, and reading. Specifying an initial read offset ensures that the system accurately reads data stored at a specified location in the flash memory without errors or data corruption.
[0052] The following describes the solutions that require successful decoding:
[0053] Optionally, in one embodiment, at least two page data include low page data, middle page data, and high page data, and the decoded data includes low page decoded data, middle page decoded data, and high page decoded data; obtaining the second number of bits that are the same as the preset bit values corresponding to Lx and Lx-1 in the at least two page data and decoded data includes: obtaining the second number of bits that are the same as 0 / 0 / 1 / 1 / 0 / 1 in the low page data, middle page data, high page data, low page decoded data, middle page decoded data, and high page decoded data.
[0054] like Figure 3 As shown, in one embodiment, the second method Type 2 reads data from three pages in the programming unit, where the three pages include low-page data, middle-page data, and high-page data; and decodes the data from the three pages to obtain the decoded data of the three pages. Using the data from the three pages and the decoded data of the three pages, the number of second bits in L7 to L6 that are the same as 0 / 0 / 1 / 1 / 0 / 1 is calculated. For example, RLP, RMP, and RUP are the raw data read out by LP, MP, and UP; CLP, CMP, and CUP are the results of LP, MP, and UP after decoding by LDPC / BCH, etc.; when L7 is flipped to L6, for example... Figure 3 The calculation method for bits in ② is as follows: the number of bits that are 0 / 0 / 1 / 1 / 0 / 1 in RLP / RMP / RUP / CLP / CMP / CUP respectively.
[0055] Optionally, in one embodiment, at least two page data include low page data and high page data, and the decoded data includes low page decoded data and high page decoded data; obtaining the second number of bits that are the same as the preset bit values corresponding to Lx and Lx-1 in the at least two page data and decoded data includes: obtaining the second number of bits that are the same as 0 / 1 / 1 / 1 in the low page data, high page data, low page decoded data and high page decoded data.
[0056] like Figure 3 As shown, in one embodiment, the third method Type 3 reads data from two pages in the programming unit, where the two pages include low-page data and high-page data; and decodes the data of the two pages to obtain decoded data for the two pages. Using the data from the two pages and the decoded data of the two pages, the number of second bits in L7 to L6 that are the same as 0 / 1 / 1 / 1 is calculated. For example, RLP and RUP are the raw data read out by LPUP; CLP and CUP are the results of LP / UP after decoding by LDPC / BCH, etc.; L0 is flipped to (L1 / L2 / L3 / L4) (e.g. Figure 3 The calculation method for the bits in ④) is: the number of bits that are 0 / 1 / 1 / 1 in RLP / RUP / CLP / CUP respectively.
[0057] Furthermore, such as Figure 4a and Figure 4b As shown, where Figure 4a yes Figure 3 A schematic diagram of partial bit-flipping information in the first embodiment of the Type3 scheme; Figure 4b yes Figure 3 A schematic diagram of partial bit-flipping information in the second embodiment of the Type 3 scheme; specifically, in Figure 4a and Figure 4b In both of the table diagrams, the FBC value for UP (high page data) is 220 / 4KB, but it is obvious that... Figure 4a The higher value of L7 is due to the improper placement of the read voltage at L7, resulting in FBC = 220; while Figure 4b The reading voltage is set near the trough in L3 / L7, but the overall FBC value is still high; therefore, for Figure 4a In this embodiment, the position of the read voltage at L7 needs to be adjusted, but for Figure 4b In this case, the data needs to be refreshed in a timely manner.
[0058] Understandably, corresponding to the above-described scheme flow, the reading process utilizing bit-flipping information can be either background inspection reading or foreground reading. In traditional programming units, the process of reading multiple pages of data is merged, not performed separately; that is, the traditional process reads the LP (low page data) and separately determines whether the LP's FBC exceeds the limit. However, in this application's scheme, the data of the LP and one or more pages of MP / UP (middle page data / high page data), along with bit-flipping information, are combined and used for comprehensive judgment. The programming unit takes TLC as an example, such as... Figure 5 As shown, Figure 5 This is a schematic diagram of the address layout in an implementation provided in this application; Figure 5 In a programming unit, several pages with the same WL# and Str# are represented, for example, Page 0 / 1 / 2 and Page 42 / 43 / 44 are considered as one programming unit; where Page 0 / 1 / 2 is the logical address of the page. WL is the sub-line index, while Str is the top selector index.
[0059] Optionally, in one embodiment, the method further includes: in response to at least two page data decoding failures, performing a data refresh operation or a garbage collection operation.
[0060] Understandably, since the above solution requires successful decoding, for the decoding failure process, after detecting the decoding failure, the data can be directly refreshed or garbage collected.
[0061] Step S30: In response to a Type I anomaly, adjust the read voltage; or in response to a Type II anomaly, perform a data refresh operation or a garbage collection operation.
[0062] Understandably, the first type of anomaly is due to an unreasonable reading voltage setting. Therefore, when the data is detected as a first type of anomaly, the reading voltage can be adjusted. If it is a second type of anomaly, the FBC is high even if the reading voltage setting is reasonable. Therefore, it is necessary to refresh the data or perform garbage collection.
[0063] There are several different methods for adjusting the reading voltage, which are described below:
[0064] Optionally, in one embodiment, adjusting the read voltage includes: adjusting the read voltage using a preset first adjustment level in response to the number of times the data corresponding to La flips to the data corresponding to La-1 is greater than a set first threshold; and adjusting the read voltage using a preset second adjustment level in response to the number of times the data corresponding to L0 flips to the data corresponding to Lb is greater than a set second threshold. The first and second adjustment levels are different, where La is the a-th waveform among the 2N waveforms of the memory cell conduction voltage probability density curve, a = 0, 1, ..., 2N-1, Lb is the b-th waveform among the 2N waveforms of the memory cell conduction voltage probability density curve, b = 0, 1, ..., 2N-1, and N is a positive integer.
[0065] Understandable, such as Figure 6a and Figure 6b As shown, Figure 6a This is a schematic diagram of a first adjustment scheme for the read voltage in an embodiment of the data read method for the memory provided in this application; Figure 6b This is a schematic diagram of a second adjustment scheme for the read voltage in one embodiment of the data read method for the memory provided in this application. In one embodiment, as... Figure 6a As shown, when reading the initial data of the programming unit, the offset adjustment can be directly performed in the Initial Read Offset. In another embodiment, if a large number of L7 bits flip to L6, it can be determined that the data has undergone a long retention period relative to the Initial Read Offset, and the first adjustment level is used; if a large number of L0 bits flip to L1 to L4, it can be determined that the data has undergone a large amount of Read Disturbance relative to the Initial Read Offset, and the second adjustment level is used; wherein the first adjustment level is set to the retention level provided by the NAND manufacturer, and the second adjustment level is set to the Read Disturbance level provided by the NAND manufacturer.
[0066] Optionally, in one embodiment, after the step of reading the programming unit to obtain the target data, the method further includes: determining whether the failure bit count is less than a set counting threshold; if not, performing a step of determining the corresponding failure bit count exception type based on the bit flip information of the target data.
[0067] Optionally, in one embodiment, after adjusting the read voltage, the method further includes: determining whether the failure bit count is less than a set counting threshold; if yes, updating the initial data corresponding to the programming unit; if no, performing a data refresh operation or a garbage collection operation.
[0068] Understandably, the reading voltage was only adjusted once in the above scheme. However, in other embodiments, the reading voltage can be optimized by adjusting it multiple times to minimize the value of FBC.
[0069] In summary, please refer to Figure 7 As shown, Figure 7 This is a flowchart illustrating an embodiment of the data reading method for a memory provided in this application; where T1 represents setting a counting threshold, the specific threshold being related to the hardware capabilities, and the counting threshold may differ in different embodiments; for example... Figure 7 As shown, after reading the programming unit, the read data needs to be decoded. If decoding fails, garbage collection or data refresh will occur; that is, the bit-flip information of methods Type 2 and Type 3 needs to be obtained, and successful decoding is required. In the above embodiment, method Type 1 is also included, which does not require decoding. After successful decoding, the value of FBC is judged. If its value is greater than or equal to the set counting threshold, the bit-flip information is parsed and its abnormality type is determined, thereby detecting the type of abnormal read voltage. The read voltage is adjusted through multiple schemes to find a suitable read voltage at a low cost, assess the risk of data failure, solve the problem of blind rereading in the early background, reduce the reread rate of background inspection reads and host reads, and improve the performance of storage products.
[0070] This application also provides a storage device 100 to solve the above-mentioned problems, such as... Figure 8 As shown, where Figure 8 This is a schematic diagram of a storage device according to an embodiment of the present application; the storage device 100 includes: a memory 110 and a processor 120; wherein, the processor 120 is connected to the memory 110, and the processor 120 is configured to execute the memory data reading method as described in any of the above embodiments.
[0071] This application also provides a computer-readable storage medium to solve the above problems. The computer-readable storage medium stores program data, which, when executed by a processor, is used to implement the memory data reading method described in any of the above embodiments.
[0072] This application provides a data reading method for a memory, comprising: performing a read operation on a programming unit to obtain target data; determining the corresponding failure bit count anomaly type based on bit flip information of the target data; wherein the failure bit count anomaly type includes a first type of anomaly caused by read voltage offset and a second type of anomaly caused by a rise in the trough of the memory cell conduction voltage probability density curve; adjusting the read voltage in response to the first type of anomaly; or performing a data refresh operation or a garbage collection operation in response to the second type of anomaly.
[0073] By utilizing the byproducts (bit-flipping information) generated during the reading process, the possible data failure types can be determined. Based on the failure type, the corresponding Retry level can be obtained to reduce the reread rate or perform data refresh. This solves the problem of blind background rereads in the early stages, reduces the reread rate of background inspection reads and host reads, and improves the performance of storage products.
[0074] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for reading data from a memory, characterized in that, The data reading method of the memory includes: The programming unit is read to obtain the target data; Based on the bit flip information of the target data, the corresponding failure bit count anomaly type is determined; wherein, the failure bit count anomaly type includes a first type of anomaly caused by read voltage offset and a second type of anomaly caused by the rise of the trough of the memory cell conduction voltage probability density curve; In response to the first type of anomaly, the read voltage is adjusted; or In response to the second type of exception, perform a data refresh operation or a garbage collection operation.
2. The data reading method for a memory according to claim 1, characterized in that, The step of reading the programming unit to obtain the target data includes: A read operation is performed on the programming unit to obtain at least two pages of data for the programming unit, the at least two pages of data including the lower page data; The step of determining the corresponding failure bit count anomaly type based on the bit flip information of the target data includes: Based on the bit flip information of the at least two pages of data, determine the corresponding failure bit count anomaly type.
3. The data reading method for the memory according to claim 2, characterized in that, The step of determining the corresponding failure bit count anomaly type based on the bit flip information of the at least two pages of data includes: Obtain the number of bits that are 1 in at least two pages of data corresponding to Lx; where Lx is the x-th waveform of the 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; The corresponding failure bit count exception type is determined based on the first bit count.
4. The data reading method for the memory according to claim 2, characterized in that, The step of determining the corresponding failure bit count anomaly type based on the bit flip information of the at least two pages of data includes: Decode at least two pages of data to obtain the decoded data; Obtain the number of second bits that have the same preset bit values as Lx and Lx-1 in the at least two pages of data and the decoded data; where Lx is the x-th waveform of the 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; Lx-1 is the (x-1)-th waveform of the 2N waveforms of the memory cell conduction voltage probability density curve, x = 0, 1, ..., 2N-1, and N is a positive integer; The corresponding failure bit count exception type is determined based on the second bit count.
5. The data reading method for a memory according to claim 4, characterized in that, The method further includes: In response to at least two pages of data decoding failure, the steps of performing a data refresh operation or a garbage collection operation are executed.
6. The data reading method for a memory according to claim 1, characterized in that, The adjustment of the read voltage includes: If the number of data flipped from La to La-1 exceeds a set first threshold, the reading voltage is adjusted using a preset first adjustment level. If the number of data flipped from L0 to Lb exceeds a set second threshold, the reading voltage is adjusted using a preset second adjustment level. Wherein, the first adjustment level and the second adjustment level are different, La is the a-th waveform of the 2N waveforms of the memory cell conduction voltage probability density curve, a = 0, 1, ..., 2N-1, Lb is the b-th waveform of the 2N waveforms of the memory cell conduction voltage probability density curve, b = 0, 1, ..., 2N-1, and N is a positive integer.
7. The data reading method for a memory according to claim 1, characterized in that, After the step of reading the programming unit to obtain the target data, the method further includes: Determine if the failure bit count is less than a set counting threshold; If not, proceed with the step of determining the corresponding failure bit count exception type based on the bit flip information of the target data.
8. The data reading method for a memory according to claim 7, characterized in that, After the step of adjusting the read voltage, the method further includes: Determine if the failure bit count is less than a set counting threshold; If so, update the initial data corresponding to the programming unit; If not, perform the steps described for performing a data refresh operation or a garbage collection operation.
9. A storage device, characterized in that, The storage device includes: Memory; A processor connected to the memory, the processor being configured to perform a memory data reading method as described in any one of claims 1-10.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program data, which, when executed by a processor, is used to implement the memory data reading method as described in any one of claims 1-10.