Method and apparatus for processing checksums for in-store computing devices

Abstract

A method, e.g., a computer-implemented method, for processing a checksum for an in-store computing device, e.g., for performing vector matrix multiplication includes determining at least one checksum for the in-store computing device, checking the at least one checksum by a checking device.

Description

Technical Field

[0001] This disclosure relates to a method for processing checksums for in-memory computing devices.

[0002] This disclosure also relates to an apparatus for processing checksums for in-memory computing devices. Summary of the Invention

[0003] Some examples relate to a method for processing checksums for an in-memory computing device, such as a computer-implemented method for performing vector-matrix multiplication, the method comprising: determining at least one checksum for the in-memory computing device; and checking the at least one checksum using a checking device. In some examples, this enables the identification of errors that may exist in the in-memory computing device.

[0004] In some examples, the in-memory computing device may also be referred to as a "dot product engine".

[0005] In some examples, the in-memory computing device can be used for applications in fields such as artificial intelligence and machine learning, for example, to perform computational operations, such as computational operations that can be used when training and / or inferring using neural networks.

[0006] In some examples, the in-memory computing device may be designed at least partially as a digital device or at least partially as an analog device.

[0007] In some examples, the inspection device and the in-memory computing device are arranged in the same target system, for example, on the same carrier, such as a substrate for semiconductor components. This results in a particularly small configuration while enabling the inspection of the in-memory computing device.

[0008] For example, the inspection device has a processor device, such as a central processing unit, such as a CPU, which is capable of establishing at least a temporary data connection with an in-memory computing device via a data connection device, such as a data connection device having a data bus or an on-chip network, wherein the method includes: reading at least one checksum of the in-memory computing device via the processor device; comparing at least one checksum of the in-memory computing device with, for example, a reference checksum pre-stored in a storage device for the processor device via the processor device; optionally, performing measures via the processor device based on the comparison.

[0009] For example, the at least one checksum may be stored at least temporarily in the memory area of ​​the in-memory computing device, for example as the result of (in-memory) computation based on pre-given input data, such as at least one check mode.

[0010] In some examples, the checking device is designed as, for example, a dedicated hardware device, such as a comparator device (e.g., a comparator), wherein the checking device is arranged in a region of the in-memory computing device, for example, integrated into the in-memory computing device, wherein the method includes at least one of the following elements: a) providing at least one reference checksum, for example, in a register storage device; or b) performing a comparison of at least one checksum of the in-memory computing device with at least one reference checksum, or the at least one reference checksum, for example, a byte-by-byte comparison, or c) caching multiple checksums with the comparator device; or d) comparing multiple checksums with corresponding reference checksums, for example, a simultaneous comparison.

[0011] In some examples, it may be specified that, for example, for each column of a storage device in matrix form (with rows and columns) for an in-memory computing device, multiple checksums are provided, for example, transmitted, and then different input vectors are sequentially applied (anlegened) as input data to the in-memory computing device and compared with the checksums assigned to the respective input vectors.

[0012] In some examples, in-memory computing devices can constitute or represent functional blocks, such as those used in semiconductor modules, like chips. For instance, these functional blocks can be characterized by so-called macros, such as in-memory computing (IMC) macros. In some examples, the inspection device can be directly integrated into the in-memory computing device's (IMC) macro, thereby enabling particularly efficient manufacturing.

[0013] Some examples relate to a method according to this disclosure, wherein the checking device is designed as another in-memory computing device, wherein the method includes: temporarily storing at least one of the following elements: a) a reference checksum of inversion, such as bitwise inversion, in the other in-memory computing device, for example as a weight for processing input data for the other in-memory computing device, or b) a reference checksum in the other in-memory computing device, for example as a weight for processing input data for the other in-memory computing device.

[0014] For example, the reference checksum here characterizes the normal operation of the in-memory computing device. Information, such as data or one or more values, that can be determined in the form of a checksum under functional conditions. In other words, if the checksum matches a reference checksum, then it can be inferred, for example, that the in-memory computing device is working correctly. However, if the checksum does not match the reference checksum, it can be inferred, for example, that the in-memory computing device is not working correctly.

[0015] In some examples, the method includes: feeding at least one checksum of the in-memory computing device as input data to the other in-memory computing device; and, with the aid of the other in-memory computing device, performing a first bitwise AND function on the input data and a reference checksum that exists as a weight for processing the input data, wherein the reference checksum is, for example, bitwise inverted. Thus, the checksum of the in-memory computing device can be checked, for example, efficiently by the other in-memory computing device.

[0016] For example, the method includes: feeding a bitwise reversed form of at least one checksum from the in-memory computing device as input data to the other in-memory computing device; and, with the aid of the other in-memory computing device, performing a bitwise AND function on the input data and a reference checksum that serves as a weight for processing the input data. This provides further possibilities for inspection.

[0017] In some examples, the method includes evaluating at least one of the following elements: a) the result of performing the first bitwise AND function, or b) the result of performing the second bitwise AND function, wherein, for example, the evaluation includes at least one of the following elements: a) checking whether the two results each have a pre-given (e.g., arbitrary) value, such as whether it is zero, or b) adding the results and checking whether the sum of the results is zero.

[0018] In some examples, the method includes: feeding at least one checksum of the in-memory computing device as input data to the other in-memory computing device; performing a bitwise AND function on the input data and a reference checksum existing as a weight for processing the input data using the other in-memory computing device; and evaluating, for example, the result of the execution of the bitwise AND function for the at least one checksum, for example by comparing the result with at least one checksum, for example by a comparator device.

[0019] For example, the method includes: simulating the checking device, such as the other in-memory computing device, using the in-memory computing device; at least temporarily using a first storage area of ​​the in-memory computing device, such as a first storage bank, for example, to determine at least one checksum of the in-memory computing device; and at least temporarily using a second storage area of ​​the in-memory computing device, such as a second storage bank, for example, to check the at least one checksum. In some examples, this can avoid providing a separate checking device, since the in-memory computing device can perform this function at least temporarily.

[0020] In some examples, the method includes, for example, determining a plurality of checksums for different storage areas of the in-memory computing device; combining the plurality of checksums into a combined checksum; and checking the combined checksum, for example, by comparing the combined checksum with the combined reference checksum. In some examples, a single comparison of the combined checksum with the combined reference checksum is therefore sufficient to check the plurality of checksums.

[0021] In some examples, combining multiple checksums includes, for example, combining them using conventional checksum methods or checksum methods of the CRC type.

[0022] In some examples, combining multiple checksums includes, for example, concatenating multiple checksums.

[0023] Some examples relate to devices for, for example, in-memory computing means for performing vector-matrix multiplication, wherein the device is designed, for example, configured to perform at least some aspects of this disclosure.

[0024] Some examples relate to a system that includes, for example, an in-memory computing device for performing vector-matrix multiplication and an apparatus according to the present disclosure.

[0025] Some examples relate to a computer-readable storage medium that includes instructions that, when executed by a computer, cause the computer to perform a method according to this disclosure.

[0026] Some examples involve computer programs that include instructions that, when executed by a computer, cause the computer to perform a method according to this disclosure.

[0027] Some examples involve the transmission and / or characterization of data carrier signals according to a computer program of this disclosure.

[0028] Some examples involve the use of methods and / or devices and / or systems and / or computer-readable storage media and / or computer programs and / or data carrier signals according to this disclosure for purposes of at least one of the following: a) checking at least one checksum, or b) checking the functionality of the in-memory computing device, or c) improving reliability and / or security, or d) identifying errors, or e) verifying the stored contents of the in-memory computing device without, for example, reading the stored contents. Attached Figure Description

[0029] Further features, applicability, and aspects of this disclosure are derived from the following description of the examples shown in the accompanying drawings. All features described or illustrated herein, whether individually or in any combination, constitute the subject matter of this disclosure, regardless of their summary in the claims or their references thereto, or their representation or expression in the specification or drawings.

[0030] In the attached figures:

[0031] Figure 1 The flowchart is shown schematically.

[0032] Figure 2 The block diagram is shown schematically.

[0033] Figure 3 The block diagram is shown schematically.

[0034] Figure 4 The flowchart is shown schematically.

[0035] Figure 5 A simplified block diagram is shown schematically.

[0036] Figure 6 The flowchart is shown schematically.

[0037] Figure 7 The flowchart is shown schematically.

[0038] Figure 8 The block diagram is shown schematically.

[0039] Figure 9 The flowchart is shown schematically.

[0040] Figure 10 The block diagram is shown schematically.

[0041] Figure 11 The flowchart is shown schematically.

[0042] Figure 12 The flowchart is shown schematically.

[0043] Figure 13 The block diagram is shown schematically.

[0044] Figure 14 The various aspects of its use are illustrated schematically.

[0045] Figure 15 The various aspects of the in-memory computing device are schematically illustrated.

[0046] Figure 16 The various aspects of the in-memory computing device are schematically illustrated.

[0047] Figure 17 The various aspects of the in-memory computing device are schematically illustrated.

[0048] Figure 18A schematically illustrates various aspects of the in-memory computing device.

[0049] Figure 18B schematically illustrates various aspects of the in-memory computing device. Detailed Implementation

[0050] For example, see Figure 1 and Figure 2 Some examples involve a method, such as a computer-implemented method, for processing data for in-memory computing device 10 (…). Figure 2 The checksum of 100 (The in-memory computing device is used, for example, to perform vector-matrix multiplication, the method comprising: determining 100 ( Figure 1 At least one checksum 12 in the memory computing device 10; using the checking device 20 ( Figure 2 At least one checksum 12 is checked 102. In some examples, this makes it possible to identify errors that may exist in the in-memory computing device 10.

[0051] according to Figure 1 Optional block 104 is denoted by a symbol: for example, the optional execution of measure M1 based on the check 102. For example, element 104 may include: error response 104a, and / or recheck 104b, for example, repeating at least aspect 102 (optionally, for example, aspect 100 in the sense of redetermining, for example, calculating checksum 12).

[0052] In some examples, such as Figure 2 As shown, the in-memory computing device 10 may also be referred to as a "dot product engine," for example, because it is designed to compute the dot product of the components of a matrix or a vector.

[0053] However, in some examples, without limiting the generality, the in-memory computing device 10 may also be alternatively or additionally designed to perform other computing operations, wherein the principles of this disclosure may be applied or adapted in a corresponding manner to the configuration designed in this way in some examples.

[0054] In some examples, such as Figure 2 As shown, the in-memory computing device 10 can be used, for example, in the field of artificial intelligence, such as machine learning applications. The in-memory computing device can be used, for example, to perform computational operations, such as in training and / or inference using neural networks.

[0055] In some examples, such as Figure 2 As shown, the in-memory computing device 10 may be designed at least partially as a digital device or at least partially as an analog device.

[0056] In some examples, such as Figure 2 As shown, the inspection device 20 and the in-memory computing device 10 are arranged in the same target system 30, for example, on the same carrier 30a, such as on a substrate for semiconductor components. This results in a very small configuration while enabling the inspection of the in-memory computing device 10. Optionally, a device 1000 may be provided, which is designed to perform at least some aspects of this disclosure. For example, the device 1000 may also be arranged in the target system 30, for example, on the substrate 30a. In a further example, the device 1000 may also be arranged within the target system 30, and may, for example, establish a data connection at least temporarily with at least one of the components 10, 20.

[0057] For example, see Figure 3 The inspection device 20a has a processor device 22, such as a central processing unit, like a CPU, which is capable of establishing a data connection DV with the in-memory computing device 10 at least temporarily via a data connection device 24, such as a data bus 24a or an on-chip network 24b, wherein, see, for example Figure 4 The method includes: reading at least one checksum 12 of the in-memory computing device 10 via processor device 22; comparing at least one checksum 12 of the in-memory computing device 10 with a reference checksum 12' via processor device 22, wherein the reference checksum 12' is, for example, pre-stored (e.g., at compile time) in a storage device 26 for processor device 22. Figure 3 Optionally, based on the comparison 112, measure M1' is executed by the processor device 22.

[0058] See in some examples Figure 4The optional implementation 114 of measure M1' may further include at least one of elements 104a and 104b (see Figure 1 (and its description above).

[0059] For example, see Figure 3 The at least one checksum 12 may be stored at least temporarily in the storage areas SB1, SB2, ... of the in-memory computing device 10, for example, as the result of an in-memory calculation based on pre-given input data, such as at least one pre-given check pattern.

[0060] In some examples, such as Figure 5 As shown, the inspection devices 20b and 20c are designed as, for example, dedicated hardware devices, such as comparator devices (e.g., comparators), wherein the inspection devices 20b and 20c are arranged in a region of the in-memory computing device 10, for example, integrated into the in-memory computing device 10 (see variant 20b of the inspection device), for example see Figure 6 The method includes at least one of the following elements: a) for example, in register storage device 26a ( Figure 5 In the process of computing device 10, at least one reference checksum 12' is provided; or b) at least one checksum 12' in memory is executed by comparator devices 20b, 20c. Figure 5 (a) a byte-by-byte comparison with one or more of the at least one reference checksum 12'; or (b) caching the multiple checksums 12a, 12b by comparator devices 20b, 20c; or (c) comparing the multiple checksums 12a, 12b with the corresponding reference checksums 12a', 12b' for example, comparing them simultaneously for example, 126a, wherein, for example, the corresponding reference checksums 12a', 12b' can also be stored in register storage device 26a.

[0061] See in some examples Figure 5 The in-memory computing device 10 can constitute or represent functional blocks, such as functional blocks for semiconductor modules, like chips. For example, this functional block can be characterized by so-called macros, such as in-memory computing (IMC) macros. See also: [link to relevant documentation] Figure 5 Inspection devices 20b and 20c can be directly integrated into the in-memory computing device 10 (IMC) macro, for example, thereby enabling particularly efficient manufacturing.

[0062] Some examples (see, for example) Figure 7 , 8 This relates to a method according to the present disclosure, wherein the inspection device 20 ( Figure 1 ) is designed as other in-memory computing devices 10' ( Figure 8), where the method (see Figure 7 This includes: at least temporary storage of at least one of the following 130 elements: a) the other in-memory computing device 10' ( Figure 8 (a) the inversion of the reference checksum 12'-INV in the other in-memory computing device 10', for example, as a weight for processing the input data ED-10' for the other in-memory computing device 10', or (b) the reference checksum 12' in the other in-memory computing device 10', for example, as a weight for processing the input data ED-10' for the other in-memory computing device 10'.

[0063] For example, the reference checksum 12' here characterizes the in-memory computing device 10 ( Figure 8 The checksum 12 refers to information, such as data or one or more values, that can be determined in the form of a checksum 12 under normal functional conditions. In other words, if the checksum 12 matches a reference checksum 12', then it can be inferred, for example, that the in-memory computing device 10 is working correctly. However, if the checksum 12 does not match the reference checksum 12', then it can be inferred, for example, that the in-memory computing device 10 is not working correctly.

[0064] In some examples, such as Figure 7 As shown, the method includes: transmitting at least one checksum 12 of the in-memory computing device 10 as input data ED-10' to the other in-memory computing device 10'; and performing a first bitwise AND function BW-AND-1 on the input data and a reference checksum 12'-INV, which exists as a weight for processing the input data, using the other in-memory computing device 10'. Thus, the checksum 12 of the in-memory computing device 10 can be checked, for example, efficiently by the other in-memory computing device 10'.

[0065] For example, see Figure 7 The method includes: transmitting, 136, a bitwise inverted form 12-INV of at least one checksum 12 of the in-memory computing device 10 as input data ED-10' to the other in-memory computing device 10'; and, with the aid of the other in-memory computing device 10', performing a bitwise AND function BW-AND-2 on the input data 12-INV and a reference checksum 12' which exists as a weight for processing the input data. This provides further possibilities for checking, for example, as an alternative to or supplement to aspects 132 and 134. For example, the transmission 136 may include using an inverting device 13 ( Figure 8 ) Perform inversion 136a to obtain the inverted form 12-INV.

[0066] See in some examples Figure 7 , 8 The bit-inverted checksum 12-INV can be derived from checksum 12, for example, via optional inversion device 13.

[0067] In some examples, see, for example Figure 7 The method includes: evaluating at least one of the following elements: a) the result 14a of the execution 134 of the first bitwise AND function BW-AND-1; or b) the result 14b of the execution 138 of the second bitwise AND function BW-AND-2, wherein, for example, the evaluation 139 includes at least one of the following elements: a) checking 139a whether the two results 14a and 14b each have a pre-given value, e.g., whether they are both zero; or b) adding the results 14a and 14b to 139b, and checking 139c whether the sum 15 of the results 14a and 14b is zero. Therefore, according to Figure 8 Optional block 15 uses symbols to represent at least one of the following elements: a) an optional adder for forming the sum described in 139b, or b) the sum itself.

[0068] according to Figure 8 Configuration, for example, relative to, according to Figure 5 The configuration has advantages: for example, the in-memory computing device 10 or macros that may already exist associated with the in-memory computing device 10, such as IMC macros, do not need to be targeted according to Figure 8 The configuration was changed because additional in-memory computing devices 10' were provided, which could also increase the number of equivalent parts (Gleichteilen).

[0069] In some examples, such as Figure 8 As shown, the other in-memory computing device 10' is arranged in the area of ​​the in-memory computing device 10, for example, directly adjacent to it.

[0070] In some examples, such as Figure 8 As shown, the configuration consisting of these two in-memory computing devices 10 and 10' can, for example, process multiple checksums simultaneously, such as checksums associated with adjacent columns or a specific column of the in-memory computing device 10 and different rows of the in-memory computing device 10. Details regarding the arrangement of rows and columns of the in-memory computing device 10 will be referenced below, for example, with reference to... Figure 15 To illustrate.

[0071] In some examples, it is conceivable to create one or more checksums locally, i.e., directly in the in-memory computing device, where this can be ensured, i.e., by providing additional checksums for the input data, such as other checksums related to the input data, thereby creating a checksum, for example, that can be used to compute the dot product. In some examples, after creating the checksums for computing the dot product, the integrity of the input data is checked.

[0072] In some examples, see, for example Figure 9 , 10 The method includes: transmitting at least one checksum 12 of the in-memory computing device 10 as input data ES-10' to another in-memory computing device 10' ( Figure 10 ); using the other in-memory computing device 10', 142 is performed on the input data ED-10' and the reference checksum 12' which exists as weights for processing the input data. Figure 9 ) Bitwise AND function BW-AND'; evaluate the result 14' of the execution 142 of the bitwise AND function BW-AND', for example, for at least one checksum 12, for example, by comparing the result 14' with at least one checksum 12 144a, for example, by comparing with comparator device 16. According to Figure 10 Configuration and basis Figure 8 It has advantages compared to the configuration: compared to the configuration based on Figure 8 Compared to storage in non-inverted form 12' and inverted form 12'-INV, information for the reference checksum 12' is stored only once in the other in-memory computing device 10'.

[0073] For example, see Figure 11 For example, the method includes: using an in-memory computing device 10 ( Figure 2 ), Simulation 150 inspection device 20 (see also) Figure 2 ), such as other in-memory computing devices 10' (e.g., see Figure 8 , 10 At least temporarily, the first storage area SB1 of the 152-memory computing device 10 will be used (see also...). Figure 3 , 810), for example, a first storage bank, for example, for determining at least one checksum 12 of the in-memory computing device 10; at least temporarily using a second storage area SB2 of the in-memory computing device 10, for example, a second storage bank, for example, for checking at least one checksum 12. In some examples, this can avoid providing a separate checking device 20, because the in-memory computing device 10 can perform the function at least temporarily, wherein, for example, different information to be processed, such as checksums or reference checksums, can be stored in, for example, different storage areas SB1, SB2.

[0074] In some examples, different storage areas SB1, SB2 may have different sizes, or other smaller storage areas or storage units may be provided for processing information associated with (reference) checksums 12, 12', instead of conventional data processing by the in-memory computing device 10.

[0075] In some examples, the in-memory computing device 10 may also have, for example, one or more separate storage areas, such as additional columns and / or additional rows, to temporarily store, for example, one or more checksums. For example, the one or more separate storage areas may only be used when at least one checksum 12 needs to be checked, wherein the check may be performed repeatedly, for example, periodically. This also applies to other examples described in other examples. In other words, in some examples, the check 102 may be performed repeatedly, for example, periodically.

[0076] In some examples, such as Figure 12 As shown, the method includes: determining, for example, more than 160 checksums 12a, 12b... for different storage areas of the in-memory computing device 10; combining the multiple checksums 12a, 12b... into a combined checksum 12ab, for example, by comparing the combined checksum 12ab with a combined reference checksum, for example, by checking the combined checksum 12ab, for example, by comparing it with a combined reference checksum, for example, by checking the multiple checksums 12a, 12b.... In some examples, therefore, a single comparison of the combined checksum 12ab with the combined reference checksum may be sufficient to check the multiple checksums 12a, 12b...

[0077] See in some examples Figure 12 The combination 162 of the plurality of checksums 12a, 12b, ... includes, for example, combination 162a by means of, for example, conventional checksum methods, such as CRC-type checksum methods.

[0078] See in some examples Figure 12 The combination 162 of the multiple checksums 12a, 12b, ... includes, for example, the concatenation 162b of multiple checksums 12a, 12b, ...

[0079] See Figure 13 Some examples relate to a device 1000 for an in-memory computing device 10, for example for performing vector-matrix multiplication, wherein the device 1000 is designed, for example configured to perform at least some aspects of this disclosure.

[0080] In some examples, the device 1000 ( Figure 13 The system includes: a computing device (“computer”) 1002 having at least one computing core, and a storage device 1004 allocated to the computing device 1002 for at least temporarily storing at least one of the following elements: a) data DAT, b) computer program PRG, for example for performing the method according to the described embodiment.

[0081] For example, the data DAT is associated with at least one of the following elements: a) checksum 12, or b) formation of checksum 12, or c) reference checksum 12', or d) comparison of (reference) checksums 12 and 12', or e) results 14a, 14b, 14c, or f) timing (Zeitplan) used to check the checksum 12, or g) at least one check mode 11. Figure 8 For example, the in-memory computing device 10 forms a checksum 12 based on this check mode.

[0082] See further examples. Figure 13 The storage device 1004 includes volatile memory (e.g., random access memory (RAM)) 1004a, and / or non-volatile (NVM) memory (e.g., flash EEPROM) 1004b, or a combination thereof or a combination with other memory types not explicitly mentioned.

[0083] See Figure 13 A further example relates to a computer-readable storage medium SM, which includes instructions PRG that, when executed by a computer 1002, cause the computer to perform the method according to the described embodiment.

[0084] See Figure 13 A further example relates to a computer program PRG that includes instructions that, when executed by a computer 1002, cause the computer 1002 to perform the method according to the described embodiment.

[0085] See Figure 13A further example relates to a data carrier signal (DCS) that represents and / or transmits a computer program (PRG) according to the described embodiment. The DCS can be exchanged, for example, via an optional data interface 1006 of device 1000.

[0086] See in some examples Figure 13 The functionality of device 1000 can be implemented, for example, through pure hardware circuitry, wherein device 1000 can be integrated, for example, into an IMC macro, such as the IMC macro of in-memory computing device 10.

[0087] See in some examples Figure 13 The device 1000 can also be used to implement the processor device 22 ( Figure 3 (at least some aspects of)

[0088] See Figure 2 Some examples relate to system 1, which includes, for example, an in-memory computing device 10 for performing vector-matrix multiplication and a device 1000 according to the present disclosure.

[0089] See Figure 14 Some examples involve the use 300 of at least one of the following elements for purposes of: a) checking at least one checksum 12 as described in 301; b) checking the functionality of the in-memory computing device 10 as described in 302; or c) improving reliability and / or security as described in 303; or d) identifying errors as described in 304; or e) verifying the stored contents of the in-memory computing device 10 as described in 305, without, for example, reading the stored contents.

[0090] Further examples, advantages, and aspects are described below, in which the examples, advantages, and aspects may be combined individually or in any combination with at least one of the aspects described above.

[0091] Figure 15 A digital version of an in-memory computing device is illustrated as an example, which is designed, for example, as a "dot product engine," or DPE. For example, in-memory computing device 10 may have a comparable or at least similar structure.

[0092] For example, according to Figure 15 The DPE has multiple storage cells 50, which are organized, for example, in a matrix, i.e., with multiple columns 51 and rows 52, wherein, for example, the multiple columns 51 are associated with, for example, 64x4 bit lines, and the multiple rows 52 are associated with, for example, 64 word lines.

[0093] according to Figure 15 Element 55 uses symbols to represent multiple adders, in this example, for example, 64 adders, and optional shift registers, and element 56 uses symbols to represent the output (Ausgang) of the DPE, at which the computation result calculated in memory can be output. For example, a checksum 12 is also provided at output 56, as a check pattern 11 that can be predefined as input data. Figure 8 The calculation results.

[0094] For example, according to Figure 15 Each cell in each column of the DPE has a direct connection to the corresponding adder (not shown). In order to apply an input vector that can be formed from the input data, in some examples, multiple lines can be activated simultaneously, for example.

[0095] In some examples, the main difference between a DPE and a regular block memory, such as block memory used for other computing purposes, might be that the regular block memory can only activate and read the contents of a single row (“word line”). In contrast, in some examples, this DPE can activate multiple rows and automatically append the contents of a column.

[0096] In some examples, the columns of the numerical version of the DPE, as exemplified here, may contain a single bit or multiple bits, such as four adjacent bits, which are interpreted as a single value, such as a nibble or a byte. As an example, Figure 15 The number is represented symbolically as four horizontally adjacent bits, which, for example, form a four-bit binary number (Vier-Bit-Zahl) added by an adder. In other words, in some examples, according to... Figure 15 A DPE can be understood as an array of memory cells with adders, which are, for example, groups of columns in the array.

[0097] In some examples, the DPE may have a known access structure (not shown), which, for example, enables reading and / or writing of the contents of the DPE memory cell. In some examples, these access structures may differ slightly from those of conventional memory, for example, because when reading content, these values ​​may be routed through an adder or bypassed.

[0098] The principles of this disclosure can be applied, for example, to in-memory computing device 10, which is at least similar to those according to... Figure 15The DPE is used to check, for example, whether the in-memory computing device 10 is functioning properly, such as in the case of the in-memory computing device 10 being used in a safety-critical target system, such as autonomous driving (e.g., evaluating video data of the environment of a driving vehicle by an artificial intelligence algorithm, where inference is performed, for example, by at least one in-memory computing device 10), and whether the function is functioning properly in the sense of functional safety (e.g., "safety").

[0099] Figure 16 An example of storage cell 50 is shown, in which, for example, a checksum 12 is formed for each column SP1, SP2, ... see, for example, the block arrows jointly indicated by the figure's reference numeral BP.

[0100] In some examples, for instance, for at least some columns, such as all columns SP1, SP2, ..., multiple checksums can be formed, for example, based on multiple different check modes 11, see [reference to...]. Figure 16 Rows a, b, and c. See further examples. Figure 16 For example, by using the principles of this disclosure, multiple checksums can be compared with corresponding reference checksums (see lines a', b', c').

[0101] Figure 17 The illustration shows a possible arrangement of one or more reference checksums associated with storage cell 50 according to some examples, wherein bracket K1 represents a column for at least temporarily storing at least one reference checksum, and bracket K2 represents a row for at least temporarily storing at least one reference checksum.

[0102] See Figure 17 In some examples, the checksum can also be stored in the column itself, for example, at the end of the corresponding column. For this purpose, it can be specified that a holding register for the checksum is set up, which is also connected to the adder tree, for example, to the end of the IMC macro. In some examples, the holding register for the checksum is large enough to hold a number that would cause the adder to overflow when added. In some examples, this overflow means the sum is zero, which can be easily checked, for example, by an OR gate. Thus, the number that can be stored in the holding register for the checksum is, for example, (AdderFullscale - ExpectedTestPatternResult + 1).

[0103] For example, in some cases, if the expected checksum is correct, its sum with the checksum in the last row (or any other row) will be exactly zero. Example: An 8-bit adder, therefore, the maximum value in the adder's output register can be 0xff (hexadecimal) or 255 (decimal). If the expected result of the column operation is, for example, 200, then the value 55+1 should be entered in the last row. This last row would then cause the adder to overflow to zero. But this is precisely under the premise that, without a checksum, the result is exactly 200.

[0104] In some examples, the last line may also be referred to as the "checksum line". However, in some examples, instead of being placed in the last line, the checksum may be placed or at least temporarily stored elsewhere, such as in the first line, for example, in the first position.

[0105] Therefore, in some examples, it is specified that the checksum row is activated together, while other rows are activated, for example, according to the input vector.

[0106] In some examples, it is alternatively possible to test "0xff" when applying the principles of this disclosure, which incurs a relatively small cost, similar to testing "zero". In other words, the appended number will then not produce zero, but 0xff. In some examples, this can be achieved by causing an overflow beyond zero. The correction value in the above example is, for example, 5. In other examples, all numbers other than 0 and 0xff are conceivable, i.e., 0x04, for example, or any other number within the corresponding range of values.

[0107] In some examples, such as instead of overflow, the adder of a DPE can also be extended with the ability to subtract. In this case, for example, the checksum holding register (Halteregister) holds a reference checksum and subtracts it, for example, to achieve a zero value that can be tested relatively easily. This is similar to that described above. In the example, -200 is thus entered as the checksum, or +200 is entered into the adder as an instruction to subtract that number. The result is then zero again.

[0108] Similarly, in some examples, it's possible to test 0xff, which is just as simple as testing zero. Thus, appending a number will not result in zero, but rather 0xff. This can be achieved, for example, by triggering an overflow beyond zero. Therefore, the correction value in the example above would be -201.

[0109] In some examples, alternatively, the adder can be preloaded with a value that, when added to the expected test result, yields zero or another easily checked condition, such as the MSB (most significant bit) being set. This can be specified, for example, if the value in question is obtained from elsewhere rather than from an additional row. In some examples, this preloaded value, added to a regular column result, such as in scalar multiplication, will yield a value that can be tested after computation. In some examples, it is preferable to always test the same value, for example, because this can be done in hardware. In some examples, the preloaded value can supplement the so-called calculated value, so that both together yield...

[0110] Values ​​that can be checked using hardware.

[0111] As an alternative to overflow, in some examples the adder may be very large, such that adding a checksum will activate the MSB (or at least another one), thus, for example, testing whether the MSB is "1" while all the lower bits are "0".

[0112] Figure 18A illustrates possible combinations of multiple checksums associated with storage cell 50 according to some examples, where multiple checksums arranged in the same row are combined into a combined checksum 12ab', for example by CRC method or splicing.

[0113] Figure 18A illustrates possible combinations of multiple checksums associated with storage cell 50 according to some examples, where multiple checksums arranged in the same column are combined into a combined checksum 12ab", for example, by CRC method or splicing.

[0114] In some examples, the combination principle equivalent to that of Figures 18A and 18B can also be applied, for example, to the corresponding reference checksum (not shown).

[0115] In some examples, the principle of combining checksums or reference checksums can also be applied hierarchically, such as recombining the first set of combined checksums, for example, with the second set of checksums that have been combined in its respect, and so on.

[0116] In this case, by selecting a correspondingly large value or range of numbers for the (combined, possibly multi-combined) checksum, the identification of errors can be ensured.

Claims

1. A method for processing checksums for an in-memory computing device (10), such as a computer-implemented method, the in-memory computing device (10) being used, for example, to perform vector-matrix multiplication, the method comprising: Determine at least one checksum (12) of the in-memory computing device (10) (100); Use inspection device (20; 20a; 20b; 20c; 20d) Check at least one checksum (12) as described in (102).

2. The method according to claim 1, wherein the inspection device (20) and the in-memory computing device (10) are arranged in the same target system (30), for example, arranged on the same carrier (30a), for example on a substrate for a semiconductor assembly.

3. The method according to at least one of claims 1 to 2, wherein the inspection device (20a) has a processor device (22), such as a central processing unit, such as a CPU, capable of establishing a data connection (DV) with the in-memory computing device (10) at least temporarily via a data connection device (24), wherein the data connection device has, for example, a data bus (24a) or an on-chip network (24b), wherein the method comprises: The processor device (22) reads (110) the at least one checksum (12) of the in-memory computing device (12); The processor device (22) compares (112) at least one checksum (12) of the in-memory computing device (12) with a reference checksum (12') pre-stored in a storage device (26) for the processor device (22); optionally, the processor device (22) performs (114) measure (M1') based on the comparison (112).

4. The method according to at least one of claims 1 to 2, wherein, The checking devices (20b, 20c) are designed as, for example, dedicated hardware devices, such as comparator devices, wherein the checking devices (20b, 20c) are arranged in a region of the in-memory computing device (10), for example, integrated into the in-memory computing device (10), wherein the method includes at least one of the following elements: a) providing (120) at least one reference checksum (12') in a register storage device (26a), or b) performing (122) a comparison, for example, byte-by-byte, between at least one checksum (12) of the in-memory computing device (10) and a reference checksum or the reference checksum (12'), or c) caching (124) multiple checksums (12a, 12b) by means of the comparator device, or d) comparing (126) multiple checksums (12a, 12b) with corresponding reference checksums (12a', 12b'), for example, comparing simultaneously (126a).

5. The method according to at least one of claims 1 to 2, wherein the inspection device (20d) is designed as another in-memory computing device (10'), wherein the method comprises: At least one of the following elements is temporarily stored (130): a) a reversed, for example bitwise reversed reference checksum (12'-INV) in the other in-memory computing device (10'), for example as a weight for processing input data (ED-10') for the other in-memory computing device (10'), or b) a reference checksum (12') in the other in-memory computing device (10'), for example as a weight for processing input data (ED-10') for the other in-memory computing device (10').

6. The method according to claim 5, wherein the method comprises: At least one checksum (12) of the in-memory computing device (10) is fed as input data (ED-10') to (132) the other in-memory computing device (10'); with the aid of the other in-memory computing device (10'), a first bitwise AND function (BW-AND) is performed on the input data (ED-10') and a reference checksum (12'-INV) which exists as a weight for processing the input data (ED-10'), wherein the reference checksum is, for example, bitwise inverted.

7. The method according to claim 5 or 6, wherein the method comprises: The bitwise inverted form (12-INV) of at least one checksum (12) of the in-memory computing device (10) is transmitted (136) to the other in-memory computing device (10') as input data (ED-10'); with the aid of the other in-memory computing device (10'), a bitwise AND function (138) is performed on the input data (ED-10') and the reference checksum (12') which exists as a weight for processing the input data (ED-10').

8. The method according to at least one of claims 6 to 7, wherein the method comprises: Evaluate (139) at least one of the following elements: a) the result (14a) of performing the first bitwise AND function (BW-AND-1) as described in (134), or b) the result (14b) of performing the second bitwise AND function (BW-AND-1) as described in (138). in For example, the evaluation (139) includes at least one of the following elements: a) checking (139a) whether the two results (14a, 14b) have pre-given values, such as whether they are zero, or b) adding the results (14a, 14b) together (139b) and checking (139c) whether the sum (15) of the results (14a, 14b) is zero.

9. The method according to at least one of claims 5 to 8, wherein the method comprises: At least one checksum (12) of the in-memory computing device (10) is fed as input data (ED-10') to the other in-memory computing device (10') (140); with the aid of the other in-memory computing device (10'), a bitwise AND function (BW-AND') is performed (142) on the input data (ED-10') and a reference checksum (12') which exists as a weight for processing the input data (ED-10'); for example, the result (14') of the execution (142) of the bitwise AND function (BW-AND') for the at least one checksum (12) is evaluated (144) by a comparator device (16), for example, by comparing the result (14') with the at least one checksum (12) (144a).

10. The method according to at least one of the preceding claims, the method comprising: The in-memory computing device (10) is used to simulate (150) the inspection device (20; 20a; 20b； 20c； 20d), for example, the other in-memory computing device (10'); at least temporarily using (152) a first storage area of ​​the in-memory computing device (10), for example, a first storage bank (SB1), for example, for determining (100) the at least one checksum (12) of the in-memory computing device (10); at least temporarily using (154) a second storage area of ​​the in-memory computing device (10), for example, a second storage bank (SB2), for example, for checking (102) the at least one checksum (12).

11. The method according to at least one of the preceding claims, the method comprising: For example, for different storage areas of the in-memory computing device (10), a plurality of checksums (12a, 12b, ...) are determined (160); the plurality of checksums (12a, 12b, ...) are combined (162) into a combined checksum (12ab); for example, the combined checksum (12ab) is checked (164) by comparing (164a) the combined checksum (12ab) with the combined reference checksum (12ab').

12. A device (1000) for an in-memory computing device (10), said in-memory computing device being used, for example, to perform vector-matrix multiplication, wherein, The device (1000) is designed, for example configured, to perform at least some aspects of the method according to at least one of the preceding claims.

13. A system (1) comprising, for example, an in-memory computing device (10) for performing vector-matrix multiplication and a device (1000) according to claim 12.

14. A computer-readable storage medium (SM) comprising instructions (PRG) that, when executed by a computer (1002), cause the computer to perform the method according to at least one of claims 1 to 11.

15. A computer program (PRG) comprising instructions that, when executed by a computer (1002), cause the computer to perform the method according to at least one of claims 1 to 11.

16. A data carrier signal (DCS) that transmits and / or characterizes the computer program (PRG) according to claim 15.

17. The method (1000) according to at least one of claims 1 to 11 and / or the device (1000) according to claim 12 and / or the system (1) according to claim 13 and / or the computer-readable storage medium (SM) according to claim 14 and / or the computer program (PRG) according to claim 15 and / or the data carrier signal (DCS) according to claim 16 are used (300) for at least one of the following elements: a) checking (301) the at least one checksum (12), or b) checking (302) the functionality of the in-memory computing device (10), or c) improving (303) reliability and / or security, or d) identifying (304) errors, or e) verifying the stored contents of the in-memory computing device (10) without, for example, reading the stored contents.

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