Nonvolatile memory device capable of detecting bonding defects and defect detection method thereof

Abstract

A nonvolatile memory device includes: a cell array including memory cells connected to word lines; a voltage generator generating a word line voltage and supplying the word line voltage to the word line; a word line bond electrically connecting the voltage generator and the word line; and a bond defect detection circuit connected to a first node between the voltage generator and the word line bond, and detecting a voltage level of the first node in a pre-charge portion or a development portion of the word line to determine whether there is a defect in the word line bond, a pre-charge speed of the word line is detected in the pre-charge portion to identify an open circuit defect or a resistance defect, and a discharge speed of the word line that has been pre-charged is detected in the development portion to identify a short circuit defect in the word line bond.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 1-2024-0113207, filed on August 23, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a non-volatile memory device capable of detecting bonding defects and a method for detecting such defects. Background Technology

[0004] Non-volatile memory devices can store data even when power is off. While volatile memory devices are primarily used as main memory in computers, non-volatile memory devices are used as high-capacity storage for data. Recently, to improve the integration of semiconductor memory devices, active research has been conducted on non-volatile memory devices such as vertical NAND flash memory devices, which stack memory cells in a three-dimensional manner. Furthermore, to achieve high-performance and high-density non-volatile memory devices, hybrid bonding techniques that directly bond dies forming cell arrays with dies forming control logic are being actively researched. When NAND flash memory is formed using hybrid bonding, performance very close to that of a monolithic design can be provided, with almost no power or signal loss.

[0005] However, alignment between dies is a problem in achieving hybrid bonding. Bonding defects can only be minimized when there are no alignment errors between the bonded chips. Bonding defects can occur due to various factors, but they can be electrically categorized into three types: open-circuit defects, resistance defects, and short-circuit defects. However, there is currently no testing technology capable of detecting all of these diverse types of bonding defects. Summary of the Invention

[0006] Embodiments of this disclosure provide a non-volatile storage device capable of detecting bonding defects by type, and a method for detecting bonding defects therewith.

[0007] According to one aspect of the embodiments, a non-volatile memory device includes: a cell array including memory cells connected to word lines; a voltage generator configured to generate word line voltages and provide word line voltages to word lines; a word line junction configured to electrically connect the voltage generator and the word lines; and a junction defect detection circuit connected to a first node between the voltage generator and the word line junction, and configured to detect the voltage level of the first node in a pre-charged portion or a development portion of the word line to determine whether a defect exists in the word line junction, wherein the junction defect detection circuit is further configured to: detect the pre-charge rate of the word line in the pre-charged portion to identify open-circuit defects or resistance defects, and detect the discharge rate of the pre-charged word line in the development portion to identify short-circuit defects in the word line junction.

[0008] According to one aspect of the embodiments, a method for detecting bonding defects in a non-volatile memory device, the non-volatile memory device sending word line voltages generated by a voltage generator to word lines of a cell array via word line bonding, the method comprising: pre-charging a word line with the word line voltage; using a counter to count a first time from the pre-charging time when the voltage level of the word line becomes higher than a reference voltage to generate a first detection count; and identifying bonding defects of the word line based on the first detection count, wherein the bonding defect is an open-circuit defect or a resistance defect.

[0009] According to one aspect of the embodiments, a non-volatile memory device includes: a memory cell connected to a word line; a voltage generator configured to generate a word line voltage and provide the word line voltage to the word line; a word line bonding configured to electrically connect the voltage generator and the word line; a buck circuit connected to a first node between the voltage generator and the word line bonding to reduce the level of the word line voltage and provide the reduced word line voltage as a detection voltage to a second node; and a bonding defect detection circuit configured to detect the level of the detection voltage in a pre-charged portion or a development portion of the word line to determine whether there is a defect in the word line bonding, wherein the bonding defect detection circuit is further configured to: detect the pre-charge speed of the word line in the pre-charged portion based on the level of the detection voltage to identify an open-circuit defect or a resistive defect, and detect the discharge speed of the pre-charged word line in the development portion to identify a short-circuit defect in the word line bonding. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a diagram illustrating the manufacturing process of a non-volatile storage device according to an embodiment;

[0012] Figure 2This is a diagram that briefly illustrates a detectable bonding defect in a non-volatile storage device according to an embodiment;

[0013] Figure 3 This is a cross-sectional view showing a non-volatile storage device according to an embodiment;

[0014] Figure 4 This is a block diagram illustrating a storage system according to an embodiment;

[0015] Figure 5 This is a block diagram illustrating a non-volatile storage device according to an embodiment;

[0016] Figure 6 This illustrates the configuration according to an embodiment. Figure 5 A circuit diagram of the structure of the memory blocks in the cell array;

[0017] Figure 7 This is a block diagram illustrating the configuration of a joint defect detector according to an embodiment;

[0018] Figure 8 It is shown Figure 7 Waveform diagram of the joint defect test operation of the joint defect detector;

[0019] Figure 9 This is a flowchart illustrating a test operation for defect detection performed in a joint defect detector according to an embodiment;

[0020] Figure 10 To show in more detail Figure 9 Flowchart of step S120;

[0021] Figure 11 To show in more detail Figure 9 Flowchart of step S150;

[0022] Figure 12 This illustrates an embodiment. Figure 5 A block diagram of a joint defect detector;

[0023] Figure 13A and Figure 13B According to the embodiments Figure 12 The circuit diagram of the step-down circuit;

[0024] Figure 14 This illustrates an embodiment. Figure 12 A block diagram of the configuration of the joint defect detector;

[0025] Figure 15 It is shown that it is provided to Figure 14 A graph showing the first and second reference values ​​of the comparator;

[0026] Figure 16 It is shown Figure 14 Waveform diagram of the joint defect test operation of the joint defect detector; and

[0027] Figure 17 This is a block diagram illustrating a storage system including a non-volatile storage device according to an embodiment. Detailed Implementation

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary. Reference numerals are indicated in detail in the exemplary embodiments, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals are used in the specification and drawings to denote the same or similar parts.

[0029] Figure 1 This is a diagram illustrating the manufacturing process of a non-volatile storage device according to an embodiment. (Reference) Figure 1 The non-volatile memory device 1200 can be formed as a stacked semiconductor memory by applying a wafer bonding method.

[0030] Integrated circuits are formed on each of the first wafer WF1 and the second wafer WF2. For example, a memory cell array can be formed on the first wafer WF1, and peripheral circuitry can be formed on the second wafer WF2. The peripheral circuitry includes voltage generators, page buffers, decoders, control circuitry, etc. Specifically, the peripheral circuitry may include a junction defect detector (BDD), word line switches, and / or block switches.

[0031] A first wafer WF1 and a second wafer WF2, on which an integrated circuit is formed, are bonded using a hybrid bonding method. That is, the metals (e.g., copper) of the first wafer WF1 and the second wafer WF2 are bonded together, and the dielectrics (e.g., oxide films) of the first wafer WF1 and the second wafer WF2 are also bonded together. For bonding, the surfaces of the first wafer WF1 and the second wafer WF2 are treated by planarization and cleaning processes. The dielectrics are then bonded by applying pressure under low-pressure conditions. See also Figure 2 Item 30. Finally, the metal filling the upper and lower through holes is bonded by heat treatment.

[0032] The already bonded wafers WF1 and WF2 are cut into multiple chips. Each cut chip is then provided as a stacked non-volatile memory device 1200 in which the upper semiconductor die and the lower semiconductor die are bonded.

[0033] The non-volatile memory device 1200 includes a bonding defect detector (BDD). The BDD can detect word line load characteristics based on the magnitude of the bonding resistance during defect testing of the non-volatile memory device 1200. For example, the BDD can detect changes in the pre-charge rate or rise slope of the pre-charge voltage in the pre-charge portion of the word line. Furthermore, the BDD can detect the discharge rate of the pre-charged word line in the development portion of the word line. Due to the characteristics of the BDD described above, the non-volatile memory device 1200 can detect all types of defects, including open-circuit defects, resistance defects, and short-circuit defects.

[0034] Figure 2 This is a diagram that briefly illustrates bonding defects that can be detected in non-volatile memory devices. (Reference) Figure 2 The junction defects that appear in the non-volatile storage device 1200 can be broadly represented as open circuit defects, resistance defects and short circuit defects.

[0035] An open circuit defect indicates a disruption of the electrical connection between the upper metal 10 formed on the upper die and the lower metal 20 formed on the lower die after the bonding process. In other words, a bubble 40 may form between the upper metal 10 and the lower metal 20. During the high-temperature annealing process used to bond the upper metal 10 and the lower metal 20, the upper metal 10 and the lower metal 20 may not have expanded sufficiently. In this case, the upper metal 10 and the lower metal 20 may not adhere and may be electrically blocked.

[0036] A resistance defect indicates a reduced contact area due to misalignment of the upper metal 10 and lower metal 20. Specifically, a resistance defect is defined as a defect where the bonding resistance Rb increases because the upper metal 10 and lower metal 20 do not make sufficient contact with each other. If a resistance defect exists, reliability problems such as overheating and reduced signal levels may occur due to the increased bonding resistance.

[0037] A short-circuit defect refers to a state in which an electrical short circuit 41 occurs between the junction (10, 20) formed by the upper metal 10 and the lower metal 20 and the junction (11, 21) formed by the adjacent upper metal 11 and lower metal 21. In this case, signal transmission problems may occur due to charge leakage when a word line is pre-charged or developed.

[0038] The non-volatile memory device 1200 can detect the pre-charge rate of the word line voltage VWL using a junction defect detector (BDD). Additionally, the BDD can detect the discharge rate of the word line voltage VWL during the development phase of the word line. In both the pre-charge and development phases of the word line, the BDD can detect all open-circuit defects, resistance defects, and short-circuit defects.

[0039] Figure 3 This is a cross-sectional view illustrating a non-volatile storage device according to an embodiment. (Reference) Figure 3 The non-volatile memory device 1200 may have a chip-to-chip (C2C) structure. To form the non-volatile memory device 1200 with a C2C structure, an upper chip including cell regions (CELL) is fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERI) is fabricated on a second wafer different from the first wafer. Subsequently, the non-volatile memory device 1200 with a C2C structure is formed by bonding the upper chip and the lower chip at a bonding surface (I-I').

[0040] The peripheral circuitry area (PERI) may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220 formed on the first substrate 210, a first metal layer 230 connected to each of the plurality of circuit elements 220, and a second metal layer 240 formed on the first metal layer 230. In one embodiment, the first metal layer 230 may be formed of tungsten, which has relatively high resistance, and the second metal layer 240 may be formed of copper, which has relatively low resistance.

[0041] An interlayer insulating layer 215 is disposed on the first substrate 210 to cover a plurality of circuit elements 220, a first metal layer 230, and a second metal layer 240, and may include an insulating material such as silicon oxide or silicon nitride. A lower bonding metal 270 may be formed on the second metal layer 240 of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metal 270 of the peripheral circuit region PERI can be electrically connected to the upper bonding metal 370 of the cell region CELL by a bonding method, and the lower bonding metal 270 and the upper bonding metal 370 may be formed of aluminum, copper, or tungsten.

[0042] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate (310) and a common source line (320). On the second substrate (310), multiple word lines (331, 332, 333, 334, 335, 336, 337, 338; 330) may be stacked along a third direction (D3) perpendicular to the upper surface of the second substrate (310).

[0043] In the bit line bonding region BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 310 and penetrate the word line 330, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 350 and the second metal layer 360. For example, the first metal layer 350 may be a bit line contact, and the second metal layer 360 may be a bit line.

[0044] In the word line bonding area (WLBA), word lines 330 may extend along a first direction D1 parallel to the upper surface of the second substrate 310 and may be connected to a plurality of cell contact plugs (341, 342, 343, 344, 345, 346, 347; 340). Word lines 330 and cell contact plugs 340 may be connected to each other at pads provided by extending at least some of the word lines 330 at different lengths along the first direction D1. A first metal layer 350 and a second metal layer 360 may be sequentially connected to the lower portion of the cell contact plugs 340 connected to the word lines 330. Cell contact plugs 340 may be connected to the peripheral circuitry area (PERI) via an upper bonding metal 370 of the cell area (CELL) and a lower bonding metal 270 of the peripheral circuitry area (PERI) in the word line bonding area (WLBA).

[0045] Cell contact plug 340 sends the word line voltage VWL provided by voltage generator 1250 of peripheral circuit area PERI to word line 330. The word line voltage VWL generated from voltage generator 1250 is sent to cell contact plug 340 and word line 330 via lower bonding metal 270 and upper bonding metal 370 connected to the upper portions of first metal layer 230 and second metal layer 240. Here, the junction combining lower bonding metal 270 and upper bonding metal 370 is referred to as word line junction 400. The word line junction 400 for providing word line voltage VWL to each of word lines 330 is formed by lower bonding metal 270 and upper bonding metal 370.

[0046] If a bonding defect occurs between the upper bonding metal 370 and the lower bonding metal 270, normal transmission of the word line voltage VWL is impossible. Therefore, a bonding defect detector 1260 is provided to detect bonding defects in the upper bonding metal 370 and the lower bonding metal 270. The bonding defect detector 1260 can detect the pre-charge characteristics or development characteristics of each of the word lines 330 to identify the type of bonding defect. For example, if the pre-charge rate of any word line is detected to be greater than a reference value, the bonding defect detector 1260 can determine the corresponding word line bonding as an open-circuit defect. Alternatively, if the pre-charge rate of any word line is detected to be less than a reference value, the bonding defect detector 1260 can determine the corresponding word line bonding as a resistance defect. Furthermore, if the development rate of any word line is detected to be less than a reference value, the bonding defect detector 1260 can determine the corresponding word line bonding as a short-circuit defect.

[0047] As described above, the non-volatile memory device 1200 includes a bonding defect detector 1260. The bonding defect detector 1260 can detect word line load characteristics based on the amplitude of the bonding resistance during defect testing of the non-volatile memory device 1200. Through the word line load characteristic detection function described above, the non-volatile memory device 1200 can detect all of the open-circuit defects, resistance defects, and short-circuit defects of the word line bonding 400.

[0048] Figure 4 This is a block diagram illustrating a storage system according to an embodiment. (Reference) Figure 4 The storage system 1000 may include a host 1100 and at least one non-volatile storage device 1200. Here, the host 1100 may be a memory controller, and the storage system 1000 may be a data storage medium, such as a memory card, USB memory, SSD, etc. Alternatively, the host 1100 may be a test device, and the non-volatile memory device 1200 may be a device under test (DUT) in which the presence of a bonding defect is detected. In the following text, the host 1100 will be considered as a test device for detecting bonding defects.

[0049] Host 1100 can send a test command TST_CMD or a request to non-volatile storage device 1200 to detect bonding defects. In response to the test command TST_CMD, non-volatile storage device 1200 will provide a bonding defect detection result BDDR. Then, if the DUT is normal, host 1100 designates it as good and performs an analysis corresponding to the type of bonding defect for the DUT with bonding defects.

[0050] The non-volatile memory device 1200 may include a cell array 1210 and peripheral circuitry 1270. The peripheral circuitry 1270 may include a bonding defect detector 1260. As described above, the bonding defect detector 1260 can detect word line load characteristics based on the amplitude of the bonding resistance of each word line during defect testing of the non-volatile memory device 1200. Through the word line load characteristic detection function described above, the non-volatile memory device 1200 can detect all open-circuit defects, resistance defects, and short-circuit defects in word line bonding. The bonding defect detector 1260 can provide the detected bonding defect detection result (BDDR) to the host 1100.

[0051] Figure 5 This is a block diagram illustrating a non-volatile storage device according to an embodiment. (Reference) Figure 5 The non-volatile storage device 1200 may include a cell array 1210, a row decoder 1220, a page buffer circuit 1230, a control logic circuit 1240, a voltage generator 1250, and a junction defect detector 1260.

[0052] Cell array 1210 is connected to row decoder 1220 via word line WL and select lines SSL and GSL. Cell array 1210 is connected to page buffer circuit 1230 via bit line BL. Cell array 1210 may include multiple NAND cell strings. The channel of each cell string may be formed vertically on the substrate. Cell array 1210 will include multiple memory cells forming the cell strings. By providing voltage to bit line BL or word line WL, multiple memory cells can be programmed, erased, and read. Programming operations can be performed on a page basis, and erasing operations can be performed on a block basis.

[0053] The row decoder 1220 can select any one of the memory blocks in the cell array 1210 in response to the row address R_ADDR. The row decoder 1220 can also select any one of the word lines of the selected memory block in response to the row address R_ADDR. The row decoder 1220 delivers a word line voltage VWL corresponding to the operating mode to the word line of the selected memory block. During programming operations, the row decoder 1220 delivers programming and verification voltages to the selected word lines and a write pass voltage to the unselected word lines. During read operations, the row decoder 1220 sends a read voltage to the selected word lines and a read pass voltage to the unselected word lines. During test operations, the row decoder 1220 can sequentially select multiple word lines and perform pre-charging and development of the word line voltage VWL.

[0054] Page buffer circuit 1230 operates as a write driver or a sense amplifier. During programming operations, page buffer circuit 1230 sends a bit line voltage corresponding to the data to be programmed to bit line BL of cell array 1210. During data read operations or verification read operations, page buffer circuit 1230 detects the data stored in the selected memory cell via bit line BL.

[0055] Control logic circuit 1240 responds to an externally sent command CMD to control page buffer circuit 1230, row decoder 1220, and voltage generator 1250. Control logic circuit 1240 can control voltage generator 1250, page buffer circuit 1230, and row decoder 1220 to perform programming, reading, and erasing operations on selected memory cells according to command CMD. Control logic circuit 1240 can send the row address R_ADDR to row decoder 1220 and provide pump enable signal PUMP_En to voltage generator 1250.

[0056] Specifically, the control logic circuit 1240 may include a test controller 1245. The test controller 1245 generates an enable signal (Enk, k=1, 2, 3) to activate the junction defect detector 1260 in response to a test command TST_CMD from the host 1100. The test controller 1245 sequentially activates or deactivates the enable signal Enk to send the word line voltage VWL output from the voltage generator 1250 to the selected word line. Furthermore, the test controller 1245 can control the pre-charge and development processes for the selected word line to support the detection operation of the junction defect detector 1260. The operation of the test controller 1245 will be described in more detail using the waveform diagrams described below.

[0057] Voltage generator 1250 generates various types of word line voltages VWL to be supplied to each word line and voltages to be supplied to the blocks (e.g., well regions) forming memory cells, according to control logic circuitry 1240. The word line voltages VWL to be supplied to each word line include a programming voltage Vpgm, a write pass voltage Vpass, a read voltage Vrd, and a read pass voltage Vread. In a test mode used to identify defects in word line bonding, voltage generator 1250 generates word line voltages VWL for pre-charging the selected word line.

[0058] The bonding defect detector 1260 precharges the selected word line in response to the enable signal Enk from the test controller 1245. The bonding defect detector 1260 can identify open-circuit or resistive defects in the word line bonding WLB by detecting the precharge rate or rise slope of the precharge voltage of the selected word line. Furthermore, the bonding defect detector 1260 detects the development characteristics of the precharged word line in response to the enable signal Enk from the test controller 1245. Based on the detected development characteristics, the bonding defect detector 1260 can identify whether the corresponding word line bonding WLB has a short-circuit defect. The bonding defect detector 1260 can provide the presence and type of detected defects in the word line bonding WLB as a bonding defect detection result BDDR. The bonding defect detection result BDDR will be provided to the host 1100 requesting the testing of the non-volatile memory device 1200.

[0059] As described above, the non-volatile memory device 1200 can identify the presence and type of defects in the word line bonding WLB using the bonding defect detector 1260. Specifically, the bonding defect detector 1260 can detect all open-circuit defects, resistance defects, and short-circuit defects in a single word line precharge operation. The bonding defect detector 1260 can provide the bonding defect detection result BDDR generated as a detection result to the host 1100.

[0060] Figure 6 This illustrates the configuration according to an embodiment. Figure 5 A circuit diagram illustrating the structure of a cell array of memory blocks. (Reference) Figure 6 Cell strings CS are formed between bit lines BL0, BL1, BL2 and BL3 and the common source line CSL to configure the memory block BLK.

[0061] Multiple cell strings are formed between bit line BL0 and common source line CSL. The string select transistor SST of cell string CS is connected to the corresponding bit line BL. The ground select transistor GST of cell string CS is connected to common source line CSL. Memory cells MC are provided between the string select transistor SST and the ground select transistor GST of cell string CS.

[0062] Each cell string CS includes a ground selection transistor GST. The ground selection transistor included in the cell string CS can be controlled by a ground selection line GSL. Alternatively, cell strings corresponding to each row can be controlled by different ground selection lines.

[0063] The circuit structure of a memory cell included in a memory block BLK has been briefly described above. However, the circuit structure of the illustrated memory block is a simplified structure for ease of explanation, and actual memory blocks are not limited to the example shown. That is, it will be well understood that a physical block may include more semiconductor layers, bit lines BL, and string select lines SSL.

[0064] Figure 7 This illustrates an embodiment. Figure 5 A block diagram illustrating the configuration of the joint defect detector. (Refer to...) Figure 7 The junction defect detector 1260 can detect the pre-charge or development characteristics of the word line (WLi, 'i' is a natural number) that provides the word line voltage VWL to it.

[0065] When the joint defect test begins, the test controller (1245, see...) Figure 5 The first enable signal En1 and the second enable signal En2 are activated to a high level. The power switch PSW is turned on according to the activation of the first enable signal En1. Then, the word line voltage VWL supplied from the voltage generator 1250 is sent to the first node N1 and the word line WLi via the bonding resistor Rb. That is, the pre-charging of the word line WLi occurs through the first enable signal En1. The pre-charging speed of the word line WLi is affected by the word line load resistor Rl. However, the value of the word line load resistor Rl is considered to be constant. Therefore, the pre-charging speed of the word line WLi can be determined according to the bonding resistor Rb corresponding to the characteristics of the word line bonding WLB.

[0066] The junction defect detector 1260 can detect the pre-charge speed or development characteristics of the word line WLi, which vary according to the amplitude of the junction resistance Rb. For this purpose, the junction defect detector 1260 may include a comparator 1261, a counter 1263, a register 1265, and a decision circuit 1267.

[0067] Comparator 1261 compares the word line voltage VWL sent to the first node N1 with a reference voltage Vref. When the word line voltage VWL becomes higher than the reference voltage Vref, comparator 1261 sets the comparison result Vout high. When the word line voltage VWL becomes lower than the reference voltage Vref, comparator 1261 sets the comparison result Vout low.

[0068] Counter 1263 begins counting at a preset period upon activation of the second enable signal En2. Counter 1263 outputs the count value CNT to register 1265. When the third enable signal En3 is activated, counter 1263 can initialize or reset the positive count value CNT.

[0069] Register 1265 latches the count value CNT output from counter 1263 based on the comparison result Vout. Then, register 1265 transmits the latched count value CNT to the determination circuit 1267 as the detection count Tout. Specifically, register 1265 can latch the count value CNT when the comparison result Vout in the pre-charge section of word line WLi transitions from low to high, and output the latched count value CNT as the detection count Tout. Additionally, register 1265 latches the count value CNT when the comparison result Vout in the development section of word line WLi transitions from high to low. Then, register 1265 transmits the latched count value CNT to the determination circuit 1267 as the detection count Tout.

[0070] The determination circuit 1267 identifies the presence and type of bonding defects based on the detection count Tou. Specifically, the determination circuit 1267 can determine the type of bonding defect based on the detection count Tou occurring during the pre-charge portion of the word line WLi. If the detection count Tou is less than a first reference value Tref1, the determination circuit 1267 can determine that the pre-charge speed of the word line WLi is higher than a reference speed. In other words, if the detection count Tou is less than the first reference value Tref1, the determination circuit 1267 can determine that an open-circuit defect exists. On the other hand, if the detection count Tou is greater than a second reference value (Tref2 > Tref1), the determination circuit 1267 can determine that the pre-charge speed of the word line WLi is lower than a reference speed. In other words, if the detection count Tou is greater than the second reference value Tref2, the determination circuit 1267 can determine that a resistance defect exists. If the detection count Tou falls between the first reference value Tref1 and the second reference value Tref2, the determination circuit 1267 can determine that no bonding defect exists.

[0071] The determination circuit 1267 can determine the type of bonding defect based on the detection count Tout occurring in the development portion of the word line WLi. The determination circuit 1267 can provide the determined type of bonding defect as a bonding defect detection result BDDR. If the detection count Tout is less than the third reference value Tref3, the determination circuit 1267 can determine that the discharge rate of the word line WLi is higher than the reference. That is, if the detection count Tout is less than the third reference value Tref3, the determination circuit 1267 can determine that the bonding defect is a short-circuit defect. On the other hand, if the detection count Tout is greater than the third reference value Tref3 or does not occur, the determination circuit 1267 can determine that the pre-charge rate of the word line WLi is lower than the reference. That is, if the detection count Tout is greater than the third reference value Tref3 or does not occur, the determination circuit 1267 can determine that there is no short-circuit defect.

[0072] As described above, the joint defect detector 1260 can output the presence or type of joint defect as a joint defect detection result BDDR value based on the pre-charge or development characteristics of the detected word line WLi.

[0073] Figure 8 It is shown in Figure 7 Waveform of the joint defect test performed in the joint defect detector. (Reference) Figure 8 The bonding defect detector 1260 can read out the pre-charging speed and development speed of the word line WLi being pre-charged in response to enable signals En1, En2 and En3 to identify the type of bonding defect.

[0074] At time T0, the bonding defect test begins. Test controller (1245, see...) Figure 5 The first enable signal En1 and the second enable signal En2 are activated to a high level, and the third enable signal En3 is deactivated. The power switch PSW is turned on according to the activation of the first enable signal En1, and the word line voltage VWL is sent to the first node N1. The word line voltage VWL sent to the first node N1 precharges the word line WLi via the junction resistor Rb. According to the activation of the second enable signal En2, the counter (1263, see...) Figure 7 The counting operation is activated. That is, counter 1263 can increment or decrement the count value CNT sequentially.

[0075] The waveform of the word line voltage VWL pre-charged to word line WLi is illustrated as three curves based on the bonding resistor Rb. First, curve C1 shows the change in word line voltage VWL when the bonding resistor Rb is at an appropriate magnitude, i.e., a normal value. Curve C2 shows the change in word line voltage VWL when the bonding resistor Rb is small and the time constant is relatively small. In other words, curve C2 shows a relatively fast rate of increase in word line voltage VWL. Curve C3 shows the change in word line voltage VWL when the bonding resistor Rb is larger and the time constant increases compared to the normal condition. In other words, curve C3 shows a relatively slow rate of increase in word line voltage VWL.

[0076] First, when the test operation is performed with the bonding resistor Rb normal, the word line voltage VWL changes as shown in the first curve C1. Therefore, the first detection count Tout1 at the point where the word line voltage VWL becomes higher than the reference voltage Vref is latched by register 1265. The first detection count Tout1 is identified by the determination circuit 1267 as being within the normal range. Therefore, the determination circuit 1267 outputs the bonding defect detection result BDDR as normal.

[0077] If the test operation is performed when the amplitude of the bonding resistor Rb is less than the normal value, the change in the word line voltage VWL will be represented by the second curve C2. Therefore, the second detection count Tout2 at the point when the word line voltage VWL becomes higher than the reference voltage Vref is latched by register 1265. The second detection count Tout2 will be identified as an open circuit defect by the decision circuit 1267. Therefore, the decision circuit 1267 will output the bonding defect detection result BDDR as an open circuit defect.

[0078] If the test operation is performed when the amplitude of the bonding resistor Rb is greater than the normal value, the change in the word line voltage VWL will be represented by the third curve C3. Therefore, the third detection count Tout3 at the point when the word line voltage VWL becomes higher than the reference voltage Vref is latched by register 1265. The third detection count Tout3 will be identified as a resistance defect by the decision circuit 1267. Therefore, the decision circuit 1267 will output the bonding defect detection result BDDR as a resistance defect.

[0079] The precharge period tPRCH of word line WLi ends at time T2, and simultaneously, the reset period tRST begins. The reset indicator counter 1263 is reset during the reset period tRST. That is, the precharge word line voltage VWL is maintained during the reset period tRST, and only counter 1263 is initialized. To this end, during the reset period tRST, the test controller 1245 maintains the first enable signal En1 and the second enable signal En2 at a high level, and outputs the third enable signal En3 at a high level. In response to the third enable signal En3 transitioning to a high level, counter 1263 initializes the count value CNT.

[0080] Starting from time T3, the development period tDEV begins. Test controller 1245 switches the first enable signal En1 low to disconnect the power switch PSW. Then, the supply of word line voltage VWL to word line WLi stops, and the development of pre-charged word line WLi occurs. Simultaneously, the counting operation of the initialized counter 1263 begins upon activation of the second enable signal En2.

[0081] During the development period tDEV, short-circuit defects in word line bonding are detected. A short-circuit defect in word line bonding is identified if the charge charged in word line WLi is over-discharged at a high speed. The development characteristics of word line WLi in the case of a short-circuit defect are shown by the fourth curve C4. The fourth detection count Tout4 at the point when the level of word line voltage VWL becomes lower than the reference voltage Vref is latched by register 1265. The fourth detection count Tout4 is identified as a short-circuit defect by the decision circuit 1267. Then, the decision circuit 1267 outputs the bonding defect detection result BDDR as a short-circuit defect. At the end of the development period tDEV at time T4, the test controller 1245 deactivates the first enable signal En1 and the second enable signal En2 to a low level and activates the third enable signal En3 to a high level. Then, the counter 1263 can be re-initialized.

[0082] The above describes the detection operation of open-circuit defects, resistance defects, and short-circuit defects by the joint defect detector 1260. The joint defect detector 1260 can easily identify the type of joint defect by reading the pre-charge speed and development characteristics of the word line WLi, which is pre-charged in response to the enable signals En1, En2, and En3, using the counter 1263.

[0083] Figure 9 This is a flowchart illustrating a test operation for defect detection performed in a joint defect detector according to an embodiment. (Refer to...) Figure 9 The junction defect detector 1260 can detect all of the open circuit defects, resistance defects, and short circuit defects by pre-charging the selected word line once.

[0084] In step S110, the engagement defect detector 1260 receives a test control signal or enable signal from the test controller 1245. The test controller 1245 activates the first enable signal En1 and the second enable signal En2 to a high level, and deactivates the third enable signal En3 to a low level. Then, the power switch PSW is turned on, and the counter (1263, see...) Figure 7 The counting operation is activated.

[0085] In step S120, the word line voltage VWL is sent to word line WLi according to the conduction of the power switch PSW. Then, open-circuit defect or resistance defect detection is performed during the pre-charge period of word line WLi. For example, by using comparator (1261, see reference) Figure 7 The time point at which the word line voltage VWL becomes higher than the reference voltage Vref is detected. Then, the count value CNT at that time point is latched as the detection count Tout in register (1265, see [reference]). Figure 7 In the determination circuit (1267, see...) Figure 7 The detection count Tout determines whether the bonding defect corresponds to an open circuit defect, a resistance defect, or a normal word line bonding. Furthermore, the determination circuit 1267 outputs the bonding defect detection result BDDR based on the determination result.

[0086] In step S130, counter 1263 is reset. To reset counter 1263, test controller 1245 maintains the first enable signal En1 and the second enable signal En2 at a high level, and changes the third enable signal En3 to a high level. In response to the third enable signal En3 changing to a high level, counter 1263 initializes the count value CNT.

[0087] In step S140, the bonding defect detector 1260 receives a test control signal from the test controller 1245. The test controller 1245 switches the first enable signal En1 low to disconnect the power switch PSW. Then, the supply of word line voltage VWL to word line WLi is stopped, and the development of pre-charged word line WLi begins. Simultaneously, the second enable signal En2 is maintained at a high level, and the third enable signal En3 is deactivated to a low level. Then, the counting operation of the initialized counter 1263 begins.

[0088] In step S150, the presence of a short-circuit defect in the word line junction is detected by detecting the development characteristics of the voltage charging in the word line WLi. If the charge charging in the word line WLi discharges excessively at a high speed, it can be identified as a short-circuit defect in the word line junction. The count value CNT at the time point when the level of the word line voltage VWL becomes lower than the reference voltage Vref is latched in register 1265 as a detection count Tout. And based on the detection count Tout, the presence or absence of a short-circuit defect is identified.

[0089] The above describes the detection methods for open-circuit defects, resistance defects, and short-circuit defects using the junction defect detector 1260. The junction defect detector 1260 can easily identify the types of junction defects by analyzing the pre-charge and evolution characteristics of the readout word line WLi.

[0090] Figure 10 To show in more detail Figure 9 The flowchart for step S120. Refer to... Figure 10 The bonding defect detector 1260 can identify the type of bonding defect by detecting the pre-charge speed of the word line WLi. That is, the bonding defect detector 1260 can determine whether the bonding defect in the pre-charge portion of the word line WLi corresponds to an open circuit defect, a resistance defect, or normal word line bonding.

[0091] In step S121, counter 1263 is initialized. The count value CNT can be initialized to "0" by activation of the third enable signal En3 from test controller 1245. After initialization, the counting operation of counter 1263 begins.

[0092] In step S122, the power switch PSW is turned on according to the activation of the first enable signal En1. Then, the word line WLi is pre-charged by the word line voltage VWL provided from the voltage generator 1250.

[0093] In step S123, the comparator (1261, reference) performs the calculation. Figure 7The process detects the point in time when the word line voltage VWL, which is being pre-charged, becomes higher than the reference voltage Vref. If the word line voltage VWL is determined to be higher than the reference voltage Vref ('yes' direction), the process proceeds to step S125. On the other hand, if the word line voltage VWL is determined to be no higher than the reference voltage Vref ('no' direction), the process proceeds to step S124.

[0094] In step S124, the count value CNT of counter 1263 is incremented. Then, the process returns to step S123 to perform a comparison between the positive precharge word line voltage VWL and the reference voltage Vref, based on the incremented count value (CNT+1).

[0095] In step S125, the count value CNT at the point where the word line voltage VWL is higher than the reference voltage Vref is determined by register (1265, see...). Figure 7 The latched count value CNT is output from register 1265 as the detection count Tout. The detection count Tout is provided to the decision circuit 1267.

[0096] In step S126, the determination circuit 1267 compares the detection count Tout with a reference value. That is, the determination circuit 1267 determines the type or presence of a bonding defect based on the magnitude of the detection count Tout. If the detection count Tout is less than the first reference value Tref1, the process proceeds to step S127. On the other hand, if the detection count Tout is greater than or equal to the first reference value Tref1 and less than or equal to the second reference value (Tref2>Tref1), the process proceeds to step S128. And if the detection count Tout is greater than the second reference value Tref2, the process proceeds to step S129.

[0097] In step S127, the determination circuit 1267 determines that the pre-charge speed of the word line WLi corresponds to an open-circuit defect. Furthermore, the determination circuit 1267 outputs the determination result as the bonding defect detection result BDDR.

[0098] In step S128, the determination circuit 1267 determines that there is no bonding defect. That is, the determination circuit 1267 determines that the amplitude of the bonding resistance Rb is within the normal range. Furthermore, the determination circuit 1267 outputs a determination result corresponding to the normal condition as the bonding defect detection result BDDR.

[0099] In step S129, the determination circuit 1267 determines that the pre-charge speed of the word line corresponds to a resistance defect. The determination circuit 1267 then outputs the determination result corresponding to the resistance defect as the bonding defect detection result BDDR.

[0100] The method for detecting bonding defects in the pre-charge speed of word line WLi has been described above. In the pre-charge section of word line WLi, bonding defect detector 1260 can identify open-circuit defects and resistance defects respectively.

[0101] Figure 11 To show in more detail Figure 9 The flowchart for step S150. Refer to... Figure 11 The junction defect detector 1260 can identify short-circuit defects in the junction by detecting the development characteristics of the word line WLi. That is, the junction defect detector 1260 can determine whether a short-circuit defect exists by detecting whether there is leakage current in the development portion of the pre-charged word line WLi.

[0102] In step S151, counter 1263 is initialized. Counter 1263 is reset upon activation of the third enable signal En3 from test controller 1245. The count value CNT is then initialized to '0'. After initialization, the counting operation of counter 1263 begins.

[0103] In step S152, when the first enable signal En1 goes low, the power switch PSW is turned off. Then, the word line WLi, pre-charged to the word line voltage VWL level, begins to develop. If there is leakage current between word line junctions, the development or discharge rate of word line WLi will be faster.

[0104] In step S153, the comparator (1261, reference) is used to... Figure 7 The process detects the point in time when the evolving word line voltage VWL becomes lower than the reference voltage Vref. If the word line voltage VWL is determined to be lower than the reference voltage Vref ('yes' direction), the process proceeds to step S154. On the other hand, if it is determined that the word line voltage VWL is not lower than the reference voltage Vref ('no' direction), the process proceeds to step S157.

[0105] In step S154, the count value CNT at the time point when the word line voltage VWL becomes lower than the reference voltage Vref is determined by register (1265, see...). Figure 7 The latched count value CNT is output from register 1265 as the detection count Tout. The detection count Tout is provided to the decision circuit 1267.

[0106] In step S155, the determination circuit 1267 compares the detection count Tout with the third reference count Tref3. If the detection count Tout is lower than the third reference count Tref3, the process proceeds to step S156. On the other hand, if the detection count Tout is not less than the third reference count Tref3, the process proceeds to step S159.

[0107] In step S156, the determination circuit 1267 identifies the bonding defect as a short-circuit defect. Then, the determination circuit 1267 outputs the determination result as the bonding defect detection result BDDR.

[0108] In step S157, it is determined whether the current count value CNT has reached the maximum development count M_dev. If it is determined that the current count value CNT has reached the maximum development count M_dev ('yes' direction), the process proceeds to step S159. On the other hand, if it is determined that the current count value CNT has not reached the maximum development count M_dev ('no' direction), the process proceeds to step S158.

[0109] In step S158, counter 1263 increments the count value CNT. Then, the process returns to step S153 to perform a comparison between the word line voltage VWL and the reference voltage Vref, based on the incremented count value (CNT+1).

[0110] In step S159, the determination circuit 1267 determines that there is no bonding defect. That is, the determination circuit 1267 determines that there is no leakage in the word line bonding and determines that it is normal. Then, the determination circuit 1267 outputs the bonding defect detection result BDDR corresponding to the normal determination result.

[0111] The short-circuit defect detection method for word line bonding has been described above by detecting the development characteristics of word line WLi. Through the above process, the bonding defect detector 1260 can identify the presence of short-circuit defects in the development portion of word line WLi.

[0112] Figure 12 This illustrates an embodiment. Figure 5 A block diagram of a joint defect detector. (Refer to...) Figure 12 Another embodiment of the junction defect detector 1260' may include a buck circuit 1262 that shifts the precharged and developed word line voltage VWL level to a low voltage.

[0113] The word line voltage VWL generated by voltage generator 1250 is provided as a high voltage for programming or read operations. On the other hand, a page buffer circuit (1230, see...) is formed therein. Figure 5 ) or control logic circuit (1240, see Figure 5 The peripheral circuit of 1270 (see 1270) Figure 4It can be driven under low voltage conditions. Furthermore, the drive voltage supplied to the peripheral circuitry 1270 gradually decreases according to the low power trend of the non-volatile memory device 1200 or the mobile device. Finally, in order to detect the pre-charge and evolution characteristics of the word line voltage VWL supplied in the high voltage region (HV region) in the low voltage region (LV region), a configuration for voltage drop is required. Therefore, the junction defect detector 1260' may include a buck circuit 1262 for shifting the level of the word line voltage VWL to a low voltage.

[0114] When the test begins, the test controller (1245, see...) Figure 5 The first enable signal En1 and the second enable signal En2 are activated to a high level, and the third enable signal En3 is deactivated to a low level. The first power switch PSW1 is turned on according to the activation of the first enable signal En1. Then, the word line voltage VWL supplied from the voltage generator 1250 is sent to the first node N1 and is sent to the word line WLi via the junction resistor Rb. According to the activation of the first enable signal En1, the word line WLi is precharged to the high word line voltage VWL.

[0115] The junction defect detector 1260' can detect the precharge speed or development characteristics of word line WLi by reducing the word line voltage VWL sent to the first node N1 to a low voltage level. For this purpose, the junction defect detector 1260' may include a comparator 1261, a buck circuit 1262, a counter 1263, a register 1265, and a decision circuit 1267. Furthermore, a second power switch PSW2 is included to set the development start voltage Vds of the second node N2 during the development portion of the word line voltage VWL. The second power switch PSW2 is controlled by a third enable signal En3 provided to the counter 1263.

[0116] Comparator 1261 compares the reduced word line voltage VWL' of the second node N2 after level shifting of the word line voltage VWL with the reference voltage Vref. Comparator 1261 sets the comparison result Vout high when the reduced word line voltage VWL' compared to the reference voltage Vref becomes high. Comparator 1261 can also set the comparison result Vout low when the reduced word line voltage VWL' compared to the reference voltage Vref becomes low. Specifically, in the reset section of counter 1263, where the third enable signal En3 is activated, the second node N2 can be reset to the development start voltage Vds. That is, when the second power switch PSW is turned on via the third enable signal En32, the reduced word line voltage VWL' sent to the second node N2 is set to the development start voltage Vds.

[0117] Counter 1263 begins counting at a preset period upon activation of the second enable signal En2. Counter 1263 outputs the count value CNT to register 1265. When the third enable signal En3 is activated, counter 1263 initializes or resets the count value CNT. At this time, the voltage at the second node N2, which constitutes the input of comparator 1261, is also initialized to the development start voltage Vds.

[0118] Register 1265 latches the count value CNT output from counter 1263 based on the comparison result Vout. Then, register 1265 provides the latched count value CNT as a detection count Tout to the decision circuit 1267. Specifically, register 1265 can generate the detection count Tout when the comparison result Vout transitions from low to high during the pre-charge phase of word line WLi. Furthermore, register 1265 can generate the detection count Tout in response to the comparison result Vout transitioning from high to low during the development phase of word line WLi.

[0119] The determination circuit 1267 identifies the presence and type of bonding defects based on the detection count Tout. If the detection count Tout in the pre-charge portion of the word line is less than the first reference value Tref1, the determination circuit 1267 can determine that it is an open-circuit defect. On the other hand, if the detection count Tout is greater than the second reference value (Tref2>Tref1), the determination circuit 1267 can determine that it is a resistance defect. If the detection count Tout in the pre-charge portion of the word line is equal to or greater than the first reference value Tref1 and equal to or less than the second reference value Tref2, the determination circuit 1267 can determine that it is normal and there is no bonding defect.

[0120] The determination circuit 1267 can determine the type of bonding defect based on the detection count Tout occurring in the development portion of the word line WLi. If the detection count Tout is less than the third reference value Tref3, the determination circuit 1267 can determine that the discharge rate of the word line WLi is higher than the reference value. That is, if the detection count Tout is less than the third reference value Tref3, the determination circuit 1267 can determine that the bonding defect is a short-circuit defect. On the other hand, if the detection count Tout is greater than the third reference value Tref3 or does not occur, it can be determined that there is no short-circuit defect.

[0121] As described above, the bonding defect detector 1260' can identify the presence and type of bonding defects by monitoring the word line voltage VWL' that has dropped to a low voltage level.

[0122] Figure 13A and Figure 13B According to the embodiments Figure 12 The circuit diagram of the step-down circuit. Figure 13A This illustrates the configuration of the step-down circuit 1262a using a coupling capacitor Cc. Figure 13B This illustrates the use of a voltage divider circuit to construct a step-down circuit 1262b.

[0123] refer to Figure 13A According to one embodiment, the buck circuit 1262a can use a coupling capacitor Cc to reduce the voltage from the voltage generator (1250, see...) Figure 5 The word line voltage VWL is supplied to the first node N1. The word line voltage VWL' reduced by the coupling capacitor Cc can be sent to the second node N2 connected to the input of comparator 1261. The drop ratio of the word line voltage VWL to the reduced word line voltage VWL' can be controlled by selecting the capacitance of the coupling capacitor Cc.

[0124] refer to Figure 13B According to another embodiment, the buck circuit 1262b can reduce the word line voltage VWL supplied from the voltage generator 1250 to the first node N1 by voltage division. The word line voltage VWL supplied to the first node N1 can be distributed using at least two resistors R1 and R2 connected in series. And the voltage divided to resistor R2 can be used as the reduced word line voltage VWL' and provided to the input of comparator 1261. The decrease ratio of the word line voltage VWL to the reduced word line voltage VWL' can be controlled by adjusting the resistance ratio of resistors R1 and R2.

[0125] Figure 14 This illustrates an embodiment. Figure 12 A block diagram illustrating the configuration of the joint defect detector. (Reference) Figure 14 The bonding defect detector 1260' detects level changes in the reduced word line voltage VWL' provided by the buck circuit 1262 to identify the type of bonding defect. For this purpose, the bonding defect detector 1260' may include a second power switch PSW2, a comparator 1261, a buck circuit 1262, a counter 1263, registers 1265a and 1265b, a decision circuit 1267, and a fuse 1269.

[0126] When the first enable signal En1 and the second enable signal En2 are activated to a high level, the first power switch (PSW1, reference) Figure 12 The circuit is turned on. Then, a word line voltage VWL is supplied to the first node N1. The word line voltage VWL supplied to the first node N1 precharges the word line WLi via the junction resistor Rb. At the same time, the word line voltage VWL' reduced by the buck circuit 1262 will be supplied to the second node N2.

[0127] Comparator 1261 compares the decreased word line voltage VWL' supplied to the second node N2 with the reference voltage Vref. Comparator 1261 sets the comparison result Vout high when the decreased word line voltage VWL' becomes higher than the reference voltage Vref. Comparator 1261 sets the comparison result Vout low when the decreased word line voltage VWL' falls below the reference voltage Vref.

[0128] The second node N2, i.e., the input terminal of comparator 1261, is reset to the development start voltage Vds in the reset section of counter 1263. That is, when the third enable signal En3 is activated in the reset section, the second power switch PSW2 is turned on. Then, the second node N2, pre-charged using the reduced word line voltage VWL', can be reset to the development start voltage Vds. The development start voltage Vds must be higher than the reference voltage Vref.

[0129] In the development phase where the third enable signal En3 is deactivated, the development of the decreased word line voltage VWL' of the second node N2 begins at the level of the development start voltage Vds. At this time, when the decreased word line voltage VWL' becomes lower than the reference voltage Vref, the comparator 1261 switches the comparison result Vout to a low level.

[0130] Counter 1263 begins counting at a preset period upon activation of the second enable signal En2. Counter 1263 outputs the count value CNT to registers 1265a and 1265b. When the third enable signal En3 is activated, counter 1263 initializes or resets the positive count value CNT. At this time, the voltage at the second node N2, which constitutes the input of comparator 1261, is also reset to the development start voltage Vds.

[0131] Registers 1265a and 1265b generate detection counts (Tout1, Tout2) for a decreased word line voltage VWL' in response to the comparison result Vout in each of the precharge and development sections. First register 1265a latches the count value CNT output from counter 1263 at the point when the comparison result Vout transitions from low to high. The latched count value CNT is output by first register 1265a as the first detection count Tout1. Conversely, second register 1265b latches the count value CNT output from counter 1263 at the point when the comparison result Vout transitions from high to low. For this purpose, an inverted comparison result Vout can be provided to second register 1265b. The latched count value CNT is output by second register 1265b as the second detection count Tout2.

[0132] The determination circuit 1267 determines the presence and type of bonding defect based on the detection counts (Tout1, Tout2). The determination circuit 1267 may include, for example, a first comparator 1267a and a second comparator 1267b for identifying open-circuit or resistive defects during the pre-charge period. Furthermore, the determination circuit 1267 may include a third comparator 1267c for identifying the presence of short-circuit defects during the development phase.

[0133] In the pre-charge section, a first detection count Tout1 provided from the first register 1265a is supplied to a first comparator 1267a and a second comparator 1267b. The first comparator 1267a outputs a high level when the first detection count Tout1 is less than a first reference value Tref1. That is, when the first detection count Tout1 is less than the first reference value Tref1, the first comparator 1267a determines that an open-circuit defect exists. On the other hand, the first comparator 1267a outputs a low level when the first detection count Tout1 is equal to or greater than the first reference value Tref1. That is, if the first detection count Tout1 is greater than or equal to the first reference value Tref1, the first comparator 1267a determines that no open-circuit defect exists.

[0134] The second comparator 1267b outputs a high level when the first detection count Tout1 is greater than the second reference value Tref2. That is, if the first detection count Tout1 is greater than the second reference value Tref2, the second comparator 1267b determines that a resistance defect exists. Conversely, the second comparator 1267b outputs a low level when the first detection count Tout1 is less than or equal to the second reference value Tref2. That is, if the first detection count Tout1 is less than or equal to the second reference value Tref2, the second comparator 1267b determines that a resistance defect does not exist. Therefore, if both the first comparator 1267a and the second comparator 1267b output low levels, it can be determined that neither an open-circuit defect nor a resistance defect exists.

[0135] In the development section, a second detection count Tout2 provided from the second register 1265b is supplied to a third comparator 1267c. The third comparator 1267c outputs a high level when the second detection count Tout2 is less than the third reference value Tref3. That is, if the second detection count Tout2 is less than the third reference value Tref3, the third comparator 1267c determines that a short-circuit defect exists. Conversely, the third comparator 1267c outputs a low level when the second detection count Tout2 is equal to or greater than the third reference value Tref3. That is, if the second detection count Tout2 is greater than or equal to the third reference value Tref3, the third comparator 1267c determines that a short-circuit defect does not exist.

[0136] The electric fuse 1269 provides first to third reference values ​​Tref1, Tref2, and Tref3 to comparators 1267a, 1267b, and 1267c of the determination circuit 1267 for identifying the type of bonding defect. The first to third reference values ​​Tref1, Tref2, and Tref3 provided by the electric fuse 1269 can be programmed by an external device of the non-volatile storage device 1200.

[0137] As described above, the bonding defect detector 1260' can easily identify the presence or absence of bonding defects and the type of bonding defects by monitoring the reduced word line voltage VWL'.

[0138] Figure 15 It is shown that it is provided to Figure 14 A graph showing the first and second reference values ​​of the comparator. (Refer to...) Figure 15 The word line junctions of the detection count Tout follow a normal distribution. Therefore, the determination circuit 1267 can identify whether there is an open circuit defect, normal operation, or resistance defect by comparing the first detection count Tout1 with the first reference value Tref1 and the second reference value Tref2 according to the ranges contained therein.

[0139] In the pre-charge section, the first comparator 1267a compares the first detection count Tout1 with the first reference value Tref1. If the first detection count Tout1 is less than the first reference value Tref1, an open-circuit defect can be identified. In the pre-charge section, the second comparator 1267b compares the first detection count Tout1 with the second reference value Tref2. If the first detection count Tout1 is greater than the second reference value Tref2, a resistance defect can be identified. On the other hand, if the first detection count Tout1 in the pre-charge section is a value between the first reference value Tref1 and the second reference value Tref2, the determination circuit 1267 can determine that there is no open-circuit defect or resistance defect.

[0140] The first reference value Tref1 and the second reference value Tref2 can be programmed into the electric fuse 1269 based on values ​​obtained through various tests or experiments.

[0141] Figure 16 It is shown Figure 14 Waveform diagram of the joint defect test operation of the joint defect detector. (Reference) Figure 16In response to the first enable signal En1, the word line WLi is precharged to the word line voltage VWL. Simultaneously, the reduced word line voltage VWL', lowered by the de-energizing circuit 1262, is compared with a reference voltage Vref by comparator 1261. The junction defect detector 1260' can read the precharge and evolution characteristics of the reduced word line voltage VWL' to identify the type of junction defect.

[0142] At time T0, a bonding defect test begins using a reduced word line voltage VWL'. The test controller (1245, see...) Figure 5 The first enable signal En1 and the second enable signal En2 are activated to a high level, and the third enable signal En3 is deactivated. When the first enable signal En1 is activated, the first power switch PSW1 is turned on, and the word line voltage VWL is sent to the first node N1. The word line voltage VWL sent to the first node N1 precharges the word line WLi via the junction resistor Rb. At the same time, the reduced word line voltage VWL' brought down by the voltage reduction circuit 1262 is sent to the comparator 1261. When the second enable signal En2 is activated, the counter (1263, see...) Figure 14 The counting operation is activated. That is, counter 1263 can sequentially increment or decrement the count value CNT.

[0143] Curve C0 shows the word line voltage VWL pre-charged to word line WLi. The word line voltage VWL is provided at a high voltage level. On the other hand, the waveform of the reduced word line voltage VWL', depending on the bonding resistor Rb, is exemplarily illustrated as three curves. First, the first curve C1 shows the change in the reduced word line voltage VWL' when the bonding resistor Rb is of a normal value. The second curve C2 shows the change in the reduced word line voltage VWL' when the bonding resistor Rb is smaller. That is, the reduced word line voltage VWL' shown by the second curve C2 rises relatively quickly. The third curve C3 shows the change in the reduced word line voltage VWL' when the bonding resistor Rb is larger. That is, the pre-charge rate of the reduced word line voltage VWL' can be determined by the bonding resistor Rb corresponding to the characteristics of the word line bonding WLB.

[0144] First, when the bonding resistor Rb is at a normal value, if a test operation is performed, the change in the reduced word line voltage VWL' will be represented by the first curve C1. Therefore, the detection count Tout_a at the point in time when the reduced word line voltage VWL' becomes higher than the reference voltage Vref is latched by the first register 1265a. The detection count Tout_a will be identified by the determination circuit 1267 as being within the normal range. Therefore, the determination circuit 1267 will output the bonding defect detection result BDDR as normal.

[0145] When the test operation is performed with the bonding resistor Rb being a certain amount smaller than the normal value, the change in the reduced word line voltage VWL' is represented by the second curve C2. Therefore, the detection count Tout_b at the point where the reduced word line voltage VWL' becomes higher than the reference voltage Vref is latched by the first register 1265a. The detection count Tout_b will be identified as an open-circuit defect by the decision circuit 1267. Therefore, the decision circuit 1267 outputs the bonding defect detection result BDDR as an open-circuit defect.

[0146] When a test is performed with the bonding resistor Rb being a certain amount larger than its normal value, the change in the reduced word line voltage VWL' is represented by the third curve C3. Therefore, the detection count Tout_c at the point where the reduced word line voltage VWL' becomes higher than the reference voltage Vref can be latched by the first register 1265a. The detection count Tout_c will be identified as a resistance defect by the determination circuit 1267. Therefore, the determination circuit 1267 outputs the bonding defect detection result BDDR as a resistance defect.

[0147] At time T1, the precharge portion tPRCH of word line WLi ends, and simultaneously, the reset portion tRST begins. The third enable signal En3 in the reset portion tRST transitions from low to high. Then, the reduced word line voltage VWL' is initialized to the development start voltage Vds. Here, the development start voltage Vds must be higher than the reference voltage Vref. Additionally, counter 1263 is also initialized with the count value CNT.

[0148] At time T2, the development phase tDEV of word line WLi begins. Test controller 1245 switches the first enable signal En1 low to turn off the first power switch PSW1. Then, the supply of word line voltage VWL to word line WLi is stopped, and pre-charged development of word line WLi occurs. Additionally, when the third enable signal En3 is deactivated, the development of the reduced word line voltage VWL' begins from the initial development start voltage Vds. Simultaneously, the counting operation of the initialized counter 1263 begins upon activation of the second enable signal En2.

[0149] In the development section tDEV, comparator 1261 transitions the comparison result Vout to a low level when the reduced word line voltage VWL' becomes lower than the reference voltage Vref. That is, when leakage exists as shown in curve C4, the reduced word line voltage VWL' becomes lower than the reference voltage Vref. At this time, the second register 1265b latches the detection count Tout2. The third comparator 1267c of the decision circuit 1267 compares the detection count Tout2 with the third reference value Tref3. If the detection count Tout2 is less than the third reference value Tref3, the third comparator 1267c determines that a short-circuit defect exists. On the other hand, if no detection count Tout2 is output during the development of the maximum count M_dev, or if the detection count Tout2 is greater than the third reference value Tref3, the third comparator 1267c determines that no short-circuit defect exists.

[0150] At time T4, the development phase tDEV ends. At this time, the test controller 1245 deactivates the first enable signal En1 and the second enable signal En2 to a low level and activates the third enable signal En3 to a high level. Then, the counter 1263 is initialized.

[0151] The defect detection operation using the reduced word line voltage VWL' of the junction defect detector 1260' has been described above. The junction defect testing operation using the reduced word line voltage VWL' via the buck circuit 1262 makes it possible for the junction defect detector 1260' to operate in a low-voltage environment. Therefore, all types of open-circuit defects, resistance defects, and short-circuit defects in word line junctions can be detected by pre-charging a single word line WLi.

[0152] Figure 17 This is a block diagram illustrating a storage system including a non-volatile storage device according to an embodiment. (Reference) Figure 17 The storage system 2000 includes a host 2100 and a storage device 2200 implemented as a solid-state drive. In an example embodiment, the storage device 2200 may include a reference... Figures 1 to 16 The description includes several non-volatile storage devices 2230.

[0153] Storage device 2200 exchanges signals SIG with host 2100 via signal connector 2201 and receives power PWR via power connector 2202. Storage device 2200 includes SSD controller 2210, multiple non-volatile memory 2230, buffer memory 2250, and auxiliary power supply 2270.

[0154] SSD controller 2210 can control multiple non-volatile memories 2230 in response to a SIG signal received from host 2100. The multiple non-volatile memories 2230 can operate under the control of SSD controller 2210. Auxiliary power supply 2270 is connected to host 2100 via power connector 2202. Auxiliary power supply 2270 can receive and charge power PWR from host 2100. When the power supply from host 2100 is not smooth, auxiliary power supply 2270 can provide power to storage device 2200. Buffer memory 2250 can be used as a buffer memory for storage device 2200.

[0155] In an example embodiment, each of the plurality of non-volatile memories 2230 may include a bonding defect detector 2240. Each of the plurality of non-volatile memories 2230 may identify the presence or absence of defects in word line bonding WLBs and the type of defects by means of the bonding defect detector 2240. Specifically, all types of open-circuit defects, resistance defects, and short-circuit defects may be detected by means of the bonding defect detector 2240.

[0156] The specific embodiments described above are examples. These embodiments may include various design changes or modifiable embodiments. Various techniques can be used to modify and implement these embodiments. Therefore, the scope of this disclosure is not limited to the above embodiments and should be defined by the claims and their equivalents.

Claims

1. A non-volatile storage device, comprising: Cell array, including memory cells connected to word lines; A voltage generator is configured to generate word line voltages and provide the word line voltages to the word lines. The word line junction is configured to electrically connect the voltage generator and the word line; as well as A bonding defect detection circuit is connected to a first node between the voltage generator and the word line bonding, and is configured to detect the voltage level of the first node in the pre-charge portion or the development portion of the word line to determine whether a defect exists in the word line bonding. The joint defect detection circuit is also configured as follows: The pre-charge speed of the word lines is detected in the pre-charge section to identify open-circuit defects or resistance defects, and In the development section, the discharge rate of pre-charged word lines is detected to identify short-circuit defects in word line connections.

2. The non-volatile storage device according to claim 1, wherein, The joint defect detection circuit includes: The comparator is configured to compare the voltage level of the first node with a reference voltage; The counter is configured to perform a counting operation based on a first enable signal and reset based on a second enable signal; The register is configured to latch the counter's count output based on the comparator's output, and output the count output as a detection count; and The determination circuit is configured to determine the defect type of word line bonding based on the detection count.

3. The non-volatile storage device according to claim 2, wherein, The register is configured as follows: The count output is latched based on the voltage level of the first node in the pre-charge section becoming higher than the reference voltage; and The count output is latched when the voltage level of the first node in the development section becomes lower than the reference voltage.

4. The non-volatile storage device according to claim 2, wherein, The determination circuit is also configured to determine, in the pre-charge section, that the defect is an open-circuit defect based on the detection count being less than a first reference value.

5. The non-volatile storage device according to claim 4, wherein, The determination circuit is also configured to determine, in the pre-charge section, that the defect is a resistance defect based on a second reference value that is greater than or higher than the first reference value.

6. The non-volatile storage device according to claim 5, wherein, The determination circuit is also configured to determine that the result is normal in the pre-charge section based on the detection count being greater than a first reference value and less than a second reference value.

7. The non-volatile storage device according to claim 6, wherein, The determination circuit is also configured to determine, in the development section, that a defect is a short-circuit defect based on a detection count that is less than a third reference value.

8. The non-volatile storage device according to claim 2, further comprising: The power switch is configured to send word line voltage to the first node based on a third enable signal.

9. The non-volatile storage device according to claim 8, further comprising: The test controller is configured to generate a first enable signal, a second enable signal, and a third enable signal. in, The test controller is also configured to activate a second enable signal so that the counter is reset when the precharge section ends.

10. A method for detecting bonding defects in a non-volatile memory device, the non-volatile memory device sending word line voltages generated by a voltage generator to word lines of a cell array via word line bonding, the method comprising: Pre-charge the word lines using word line voltage; When the voltage level of the word line becomes higher than the reference voltage from the pre-charge time, a counter is used to count the first time to generate the first detection count; as well as The first detection count is used to identify bonding defects in word lines. Among them, the joint defect is either an open circuit defect or a resistance defect.

11. The method according to claim 10, wherein, Identifying a bonding defect includes: identifying the bonding defect as an open circuit defect based on a first detection count being less than a first reference value.

12. The method according to claim 11, wherein, Identifying joint defects also includes: identifying the absence of joint defects based on a first detection count that is greater than or equal to a first reference value and less than or equal to a second reference value.

13. The method according to claim 12, wherein, Identifying a bonding defect further includes: identifying the bonding defect as a resistance defect based on the first detection count being greater than or equal to the second reference value.

14. The method of claim 10, further comprising: Reset the counter; The word lines, which are pre-charged using the word line voltage, are electrically separated from the voltage generator; When the word line's development level falls below the reference voltage, a second time interval is counted to generate a second detection count; and The second detection count is used to identify word line bonding defects. Among them, the junction defect identified based on the second detection count is a short-circuit defect.

15. The method according to claim 14, wherein, There is no short-circuit defect when the development level of the word line does not fall below the reference voltage.

16. A non-volatile storage device, comprising: Storage unit, connected to word line; A voltage generator is configured to generate word line voltages and provide the word line voltages to the word lines. The word line junction is configured to electrically connect the voltage generator and the word line; A step-down circuit is connected to a first node between the voltage generator and the word line junction to reduce the level of the word line voltage and provides the reduced word line voltage as a detection voltage to a second node. as well as The bonding defect detection circuit is configured to detect the level of the detection voltage in the pre-charge portion or the development portion of the word line to determine whether there is a bonding defect in the word line. The joint defect detection circuit is also configured as follows: The pre-charge speed of word lines is detected in the pre-charge section based on the level of the detection voltage to identify open-circuit defects or resistance defects, and In the development section, the discharge rate of pre-charged word lines is detected to identify short-circuit defects in word line connections.

17. The non-volatile storage device according to claim 16, wherein, The joint defect detection circuit includes: The comparator is configured to compare the detected voltage with a reference voltage; A counter that performs a counting operation based on a first enable signal and is reset based on a second enable signal; The first register is configured to latch the count output of a counter based on the output of a comparator at a first time point when the detection voltage becomes higher than the reference voltage in the precharge section, and to provide the count output as the first detection count; The second register is configured to latch the count output of a comparator based on a second time point when the detected voltage becomes lower than the reference voltage in the development section, and to provide the count output as a second detection count; and The determination circuit is configured to compare a first detection count or a second detection count with a reference value to determine the type of defect in the word line junction.

18. The non-volatile storage device according to claim 17, further comprising: The first power switch is configured to send word line voltage to the first node based on a third enable signal.

19. The non-volatile storage device according to claim 18, further comprising: The second power switch is configured to initialize the second node to the development start voltage based on the second enable signal when the pre-charging phase ends.

20. The non-volatile storage device according to claim 19, further comprising: A programmable fuse is configured to provide a reference value to the decision circuit.

Images