Flash memory particle screening and grading method
By integrating multiple flash memory chips for parallel testing on a printed circuit board, and combining a dynamic threshold model and the K-Means algorithm, the problems of low efficiency and accuracy in flash memory chip testing are solved, enabling efficient and automated screening and grading of chips to meet the needs of different customer types.
Patent Information
- Application Number
- CN202511712854.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-03-03
AI Technical Summary
Existing technologies suffer from low testing efficiency for flash memory chips, inconsistent testing conditions, difficulty in accurately analyzing yield, and inability to reflect interference between multiple chips, resulting in a high false positive rate and failing to meet the needs of different customer types.
By integrating multiple flash memory chips onto the same printed circuit board and employing a parallel testing approach, the main control unit uniformly schedules parallel data write and read operations. Combined with a dynamic threshold model and K-Means algorithm, multi-dimensional parameter analysis is performed to achieve automated screening and grading of the chips.
It improves testing efficiency and accuracy, reduces human error, enables precise classification of particle performance, ensures that particle applications are consistent with customer needs, and reduces customer complaints and after-sales risks.
Smart Images
Figure CN121601018A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of memory technology and relates to a method for screening and grading flash memory chips. Background Technology
[0002] With the rapid development of solid-state drive (SSD) technology, flash memory chips, as a core component of SSDs, are crucial to the performance and stability of the entire device due to their quality and reliability. However, the quality of flash memory chips on the market varies significantly, and using good and bad chips together poses a great risk to end products. Furthermore, with the advancement of NAND flash storage technology, the market offers an increasing number of different chip types from various manufacturers, requiring software systems to adapt to them, and simultaneously increasing the testing workload for these systems.
[0003] Traditionally, performance verification is typically performed on individual chips / particles on separate test boards, including functional, endurance, and data retention tests. This approach suffers from low efficiency, inconsistent testing conditions, and data susceptibility to environmental influences. Firstly, the inability to guarantee consistent testing environments limits the accuracy of test results. Secondly, it makes accurate yield analysis difficult and fails to reflect real-world issues such as interference / coupling between multiple particles. Finally, significant test bias and a high false positive rate can easily lead to misjudgments of particle performance.
[0004] To address these issues, a new method for screening and grading flash memory chips is urgently needed. This method should improve testing efficiency and accuracy, achieve multi-level fine-grained classification of chip performance, provide the most suitable chips for different product grades, and accurately distinguish customer types (high requirements / low reliability requirements), ensuring strict consistency between chip application and customer needs, thereby reducing customer complaints and after-sales risks. Simultaneously, this method should also have automated processes to improve testing efficiency, reduce human error, and be suitable for large-scale chip screening and smart manufacturing production lines. Summary of the Invention
[0005] This invention provides a method for screening and grading flash memory chips. This method integrates multiple chips together for testing, which solves the problems of low testing efficiency, inconsistent testing conditions, difficulty in accurately analyzing yield, and inability to reflect interference between multiple chips in the prior art.
[0006] The present invention provides a method for screening and grading flash memory chips, comprising the following steps: S1 integrates multiple flash memory chips on the same printed circuit board and sets test parameters including bad block threshold, IO rate threshold and new bad block marker; S2 performs data write operations, using a parallel write method to write data to multiple physical blocks of each flash memory chip; S3 performs data read operations, using a parallel read method to read data from multiple physical blocks of each flash memory chip, and records the read latency; S4 collects multi-dimensional parameter data for each flash memory chip, including at least the number of bad blocks, IO rate, and a new bad block marker to indicate whether a new bad block has appeared. S5 inputs the multi-dimensional parameter data into the dynamic threshold model for analysis. The dynamic threshold model is trained on historical test data using a clustering algorithm. Based on the output of the dynamic threshold model, each flash memory chip is assessed for its qualification and performance is graded.
[0007] Furthermore, the printed circuit board in step S1 is equipped with a main control unit and multiple flash memory chip interfaces. All flash memory chips are connected to the main control unit through a parallel bus, and the main control unit uniformly schedules and executes parallel data writing and data reading operations.
[0008] Furthermore, when the main control unit performs parallel data write and data read operations, it adaptively selects a parallel test strategy based on the physical surface type of each flash memory chip. When the flash memory chip adopts a multi-physical surface design, a test strategy is selected for multi-physical surface writing mode and multi-physical surface reading mode; When the flash memory chip adopts a dual-solid-plane design, a test strategy is selected for dual-solid-plane writing mode and dual-solid-plane reading mode; When the flash memory chip adopts a single physical surface design, a test strategy is selected for single physical surface writing mode and single physical surface reading mode.
[0009] Furthermore, the method for obtaining the IO rate in step S4 is as follows: the main control unit records the total delay from sending the read command to the last data being read, and calculates the IO rate of this read based on the total delay and the total amount of data read.
[0010] Furthermore, the method for establishing the dynamic threshold model in step S5 is as follows: collect historical test data of flash memory chips to form a sample set, perform unsupervised clustering analysis on the sample set, and determine the dynamic threshold for grading judgment based on the clustering results.
[0011] Furthermore, the unsupervised clustering analysis is the K-Means algorithm, and the steps for establishing the dynamic threshold model include: S51 collects historical test data of flash memory chips to form a sample set. The test data includes bad block information, latency information, IO rate, and newly added bad block markers. S52 extracts the feature vector of each flash memory chip and performs Z-score normalization on the feature vector dataset; wherein, the feature vector of each flash memory chip includes X = (Initial bad block count, IO rate slope, average latency, new bad block marker, temperature variance, solid surface type); S53 uses the K-Means algorithm to cluster the standardized feature vector dataset, and uses the centroid feature value of each cluster as the dynamic threshold of that category.
[0012] Furthermore, the slope of the IO rate in the feature vector is obtained by measuring the IO rate multiple times at different time points during the test to form a sequence, and then performing linear fitting on the sequence, using the slope value obtained from the fitting as the IO rate slope.
[0013] Furthermore, it also includes the step of periodically or trigger-based updating the dynamic threshold model, the updating step including: S501 Update Trigger: The model update process is triggered when the number of newly tested flash memory chips reaches a preset threshold or when the preset time period since the last model update has elapsed. S502 Data Integration: The feature vector data of all new test particles since the last update are integrated with the historical feature vector dataset to form a new training dataset; S503 model retraining: The K-Means algorithm is used to re-cluster the new training dataset to calculate new cluster centroid feature values; S504 Threshold Update: The new cluster centroid feature value is used as the updated dynamic threshold for each category, replacing the old threshold for subsequent analysis and classification of flash memory chips.
[0014] Furthermore, the model retraining described in step S503 adopts an incremental learning approach, specifically: using the old cluster centroid as the initial centroid, iterative calculation is performed using only the newly added particle feature vector data to quickly converge to the new cluster centroid.
[0015] Furthermore, after the model update step, there is also a model optimization step: calculating the silhouette coefficient of the current clustering result to evaluate the clustering quality; if the silhouette coefficient is lower than the preset quality threshold, the number of clusters K of the K-Means algorithm is automatically adjusted, and the clustering analysis is performed again.
[0016] Compared with the prior art, the beneficial effects of the present invention are: (1) This invention integrates multiple particle media on the same PCB board and uses an automatic test program to analyze the yield of particles. A large number of particles can be tested at the same time, which significantly improves the testing efficiency, overcomes the problem of low efficiency of traditional single particle testing, and effectively solves the problems of inconsistent testing environment and data being easily affected by the environment in traditional methods.
[0017] (2) By automatically acquiring multi-dimensional parameters such as the number of bad blocks, IO rate, and newly added bad block markers, and comparing them with preset thresholds, this invention can accurately determine the current real state and potential risks of particles, effectively solving the problems of inaccurate test results and high misjudgment rate in traditional methods; and realizes full-process automated acquisition of key parameters, automatic calculation of differences, and automatic comparison and judgment, abandoning the inefficient traditional manual interpretation and recording methods, significantly reducing human error, and improving the accuracy and reliability of testing.
[0018] (3) The present invention compares the total number of bad blocks with a preset threshold to accurately distinguish customer types (high reliability requirements / low reliability requirements), ensuring strict consistency between particle usage and customer needs; by using IO rate gradient division and whether new bad blocks are added as judgment criteria, multi-level fine classification of particle performance can be achieved, providing the most suitable particles for different grades of products, improving customer matching degree, and reducing customer complaints and after-sales risks. Attached Figure Description
[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a flowchart of the flash memory chip screening and grading method provided by the present invention.
[0021] Figure 2 yes Figure 1 Flowchart for establishing the dynamic threshold model in step S5.
[0022] Figure 3 yes Figure 1 Flowchart of dynamic threshold model update in step S5. Detailed Implementation
[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0024] like Figure 1 As shown, the present invention provides a method for screening and grading flash memory chips, comprising the following steps: S1 integrates multiple flash memory chips on the same printed circuit board and sets test parameters including bad block threshold, IO rate threshold, and new bad block marker.
[0025] Each flash memory chip employs a solid face design, and each solid face contains multiple solid blocks.
[0026] In one embodiment of the present invention, the printed circuit board (PCB) is provided with a main control unit (such as FPGA or ASIC) and multiple flash memory chip interfaces. All flash memory chips are connected to the main control unit through a parallel bus (such as data bus, address bus, control bus), and the main control unit uniformly schedules and executes parallel data writing and data reading operations.
[0027] S2 performs data write operations, using a parallel write method to write data to multiple physical blocks of each flash memory chip.
[0028] In one embodiment of the present invention, the master control unit simultaneously sends write commands and addresses to all connected flash memory chips via a parallel bus. To improve the single-transfer rate, the electrical interface for data writing adopts DDR (Double Data Rate) mode. The master control unit adaptively selects a write strategy (such as Single-Plane or Multi-Plane programming) based on the number of planes of the flash memory chips to maximize write parallelism.
[0029] S3 performs data read operations, using a parallel read method to read data from multiple physical blocks of each flash memory chip, and records the read latency.
[0030] As one embodiment of the present invention, the main control unit uses a Ping-Pong operation mode for pipeline scheduling: The S31 main control unit first sends a read command and address to particle A.
[0031] While S32 is preparing data inside particle A (tR time), the master control unit immediately switches to particle B and sends it a read command and address.
[0032] When the master control unit starts reading data from the data buffer of particle A via the bus, particle B is in the internal data preparation stage, while particle C may be receiving a read command.
[0033] In this way, the command sending, internal particle preparation, and bus data transmission are parallelized, significantly improving the overall test throughput. Simultaneously, the main control unit records the latency of each read operation.
[0034] In steps S2 and S3, when the main control unit performs parallel data write and data read operations, it adaptively selects a parallel test strategy based on the physical surface type of each flash memory chip: When the flash memory chip adopts a multi-physical surface design, a test strategy is selected for multi-physical surface writing mode and multi-physical surface reading mode; When the flash memory chip adopts a dual-solid-plane design, a test strategy is selected for dual-solid-plane writing mode and dual-solid-plane reading mode; When the flash memory chip adopts a single physical surface design, a test strategy is selected for single physical surface writing mode and single physical surface reading mode.
[0035] S4 collects multi-dimensional parameter data for each flash memory chip, including at least the number of bad blocks, IO rate, and a new bad block marker to indicate whether a new bad block has appeared.
[0036] The method for obtaining bad block information is as follows: when the main control unit reads each physical block, it sends a Read Status command. If the status register shows that the read failed, the logic inside the main control unit marks the physical block as a bad block and updates the bad block count of the flash memory chip.
[0037] The method for obtaining the IO rate is as follows: the main control unit records the total delay from sending the read command to the last data being read, and calculates the IO rate of the read based on the total delay and the total amount of data read.
[0038] The method for determining whether new bad blocks have been added is as follows: compare the differences between the bad block map before and after the test to determine whether new bad blocks were generated during the test. If new bad blocks are added, they are marked as 1; if no new bad blocks are added, they are marked as 0.
[0039] S5 inputs the multi-dimensional parameter data into the dynamic threshold model for analysis, and performs qualification judgment and performance classification for each flash memory chip based on the output of the dynamic threshold model.
[0040] The dynamic threshold model is obtained by training historical test data through a clustering algorithm. The model establishment method is as follows: collect historical test data of flash memory chips to form a sample set, perform unsupervised clustering analysis on the sample set, and determine the dynamic threshold used for grading judgment based on the clustering results.
[0041] In one embodiment of the present invention, the unsupervised clustering analysis is the K-Means algorithm.
[0042] like Figure 2 As shown, the steps for establishing the dynamic threshold model include: S51 collects historical test data of flash memory chips to form a sample set. The test data includes bad block information, latency information, IO rate, and newly added bad block markers.
[0043] The latency information includes the command latency and data transmission latency for each read operation.
[0044] S52 extracts the feature vector of each flash memory chip and performs Z-score normalization on the feature vector dataset; wherein, the feature vector of each flash memory chip includes X = (Initial bad block count, IO rate slope, average latency, new bad block marker, temperature variance, solid surface type).
[0045] The IO rate slope in the feature vector is obtained by measuring the IO rate multiple times at different time points during the test to form a sequence, performing linear fitting on the sequence, and using the resulting slope value as the IO rate slope. The IO rate slope reflects the stability of particle performance.
[0046] S53 uses the K-Means algorithm to cluster the standardized feature vector dataset, and uses the centroid feature value of each cluster as the dynamic threshold of that category.
[0047] For example, the cluster is divided into 3 classes, with their centroids representing prototypes of high, medium, and low performance levels, respectively.
[0048] The training process of the dynamic threshold model also includes a step of periodically or trigger-based updating of the dynamic threshold model.
[0049] like Figure 3 As shown, the update steps of the dynamic threshold model include: S501 Update Trigger: The model update process is triggered when the number of newly tested flash memory chips reaches a preset threshold or when the preset time period since the last model update has elapsed.
[0050] S502 Data Integration: The feature vector data of all new test particles since the last update are integrated with the historical feature vector dataset to form a new training dataset.
[0051] S503 model retraining: The K-Means algorithm is used to re-cluster the new training dataset to calculate new cluster centroid feature values.
[0052] The model retraining adopts an incremental learning approach, which involves using the old cluster centroids as the initial centroids and iteratively calculating using only the newly added particle feature vector data to quickly converge to the new cluster centroids.
[0053] S504 Threshold Update: The new cluster centroid feature value is used as the updated dynamic threshold for each category, replacing the old threshold for subsequent analysis and classification of flash memory chips.
[0054] Following the model update step, a model optimization step is also included: calculating the silhouette coefficient of the current clustering results to evaluate the clustering quality; if the silhouette coefficient is lower than a preset quality threshold, the number of clusters K in the K-Means algorithm is automatically adjusted, and the clustering analysis is performed again. Model optimization is to ensure that the model can always adapt to changes in data distribution.
[0055] The grading method for step S5 is as follows: (1) Qualification judgment: If the total number of bad blocks does not exceed the threshold and there are no new bad blocks, then it is qualified.
[0056] (2) Performance grading: The feature vector of qualified particles is compared with the dynamic threshold (cluster centroid) and assigned to the nearest category to determine its performance level.
[0057] High performance: Recommended for enterprise / data center SSDs.
[0058] Medium performance: Recommended for mainstream commercial / consumer SSDs.
[0059] Low performance: Recommended for entry-level consumer electronics (such as USB flash drives).
[0060] Example 1: Dual-solid-surface particle test A method for screening and grading flash memory chips includes the following steps: Step S1: Initialize the test environment and configure test parameters. Specifically: Step S11: Connect 8 flash memory chips to 8 flash memory chip interfaces on the same printed circuit board. Each flash memory chip adopts a dual solid surface design, and each solid surface contains 4 solid blocks.
[0061] Step S12: Set test parameter thresholds: bad block threshold = 5, IO rate threshold = 1000MB / s, new bad block flag = 1, that is, when there is a new bad block, it is marked as 1, and when there is no new bad block, it is marked as 0.
[0062] Step S13: Initialize the test program and configure the data read / write interface to use DDR mode; data read scheduling uses Ping-Pong operation mode.
[0063] Step S2: Perform the data write operation. Specifically: Step S21: Using a dual-plane writing method, data is written in parallel to the entity pages of the four entity blocks in the two entity planes.
[0064] Step S22: Write data via a 64-bit data bus, with the write rate controlled between 100MB / s and 200MB / s.
[0065] Step S23: Set up a 512KB data buffer on each entity face to temporarily store the data to be written.
[0066] Step S3: Perform data reading operation. Specifically: Step S31: Using a dual-solid-plane reading method, data is read in parallel from the entity pages of the four entity blocks in the two entity planes.
[0067] Step S32: Switch the read channel using the ping-pong operation, with a 10ms interval between each switch.
[0068] Step S33: Record the latency information of reading data, and control the latency threshold between 10μs and 50μs.
[0069] Step S4: Collect multi-dimensional parameter data for each flash memory chip. Specifically: (1) Collect bad block information for each entity surface and calculate the total number of bad blocks; (2) Determine if any new bad blocks have appeared; (3) Calculate the IO rate: The main control unit records the total delay from sending the read command to the last data being read, and calculates the IO rate of the read based on the total delay and the total amount of data read.
[0070] Step S5: Input the multi-dimensional parameter data into the dynamic threshold model for analysis. Based on the output of the dynamic threshold model, determine the qualification and performance classification of each flash memory chip. Specifically: Extract feature vectors (e.g., initial bad block count = 2, IO rate slope = -0.1, average latency = 25μs, new bad block marker = 0, temperature variance = 0.5, solid surface type = 2). Input the trained K-Means model (K=3). The model determines that the particle belongs to the "high-performance" cluster.
[0071] Grading result: Qualified, high performance. Recommended application: PCIe 4.0 enterprise-class SSD.
[0072] Example 2: Single-solid surface particle test A method for screening and grading flash memory chips includes the following steps: Step S1: Initialize the test environment and configure test parameters. Specifically: Step S11: Connect 16 flash memory chips to 16 flash memory chip interfaces on the same printed circuit board. Each flash memory chip adopts a single solid surface design and contains 8 solid blocks.
[0073] Step S12: Set test threshold parameters: bad block threshold = 10, IO rate threshold = 800MB / s, add bad block marker = 1 (mark as soon as it appears).
[0074] Step S13: Initialize the test program and configure the data read / write interface to use DDR mode; data read scheduling uses Ping-Pong operation mode.
[0075] Step S2: Perform the data write operation. Specifically: Step S21: Using the single entity face writing method, data is written in parallel to the entity pages of 8 entity blocks in one entity face.
[0076] Step S22: Write data through a 32-bit data bus, with the write rate controlled between 80MB / s and 150MB / s.
[0077] Step S23: Set up a 1MB data buffer on the solid surface to temporarily store the data to be written.
[0078] Step S3: Perform data reading operation. Specifically: Step S31: Using a single entity face reading method, data is read in parallel from the entity pages of 8 entity blocks in one entity face.
[0079] Step S32: Switch the read channel using the ping-pong operation, with a 20ms interval between each switch.
[0080] Step S33: Record the latency information of reading data, and control the latency threshold between 20μs and 80μs.
[0081] Step S4: Collect multi-dimensional parameter data for each flash memory chip. Specifically: (1) Collect bad block information for each entity surface and calculate the total number of bad blocks; (2) Determine if any new bad blocks have appeared; (3) Calculate the IO rate: The main control unit records the total delay from sending the read command to the last data being read, and calculates the IO rate of the read based on the total delay and the total amount of data read.
[0082] Step S5: Input the multi-dimensional parameter data into the dynamic threshold model for analysis. Based on the output of the dynamic threshold model, determine the qualification and performance classification of each flash memory chip. Specifically: Extract feature vectors (e.g., initial bad block count = 6, IO rate slope = -1.5, average latency = 60μs, new bad block marker = 0, temperature variance = 1.2, solid surface type = 1).
[0083] The input model determines that the particle belongs to the "medium performance" cluster.
[0084] Grading result: Pass, medium performance. Recommended application: Mainstream commercial SSDs with SATA interface.
[0085] This invention integrates multiple particulate media onto the same PCB board and uses an automated test program to analyze the yield of the particles. Large batches of particles can be tested simultaneously, which significantly improves testing efficiency and overcomes the low efficiency problem of traditional single-particle testing. It also effectively solves the problems of inconsistent testing environments and data susceptibility to environmental influences in traditional methods.
[0086] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for screening and grading flash memory chips, characterized in that, Includes the following steps: S1 integrates multiple flash memory chips on the same printed circuit board and sets test parameters including bad block threshold, IO rate threshold and new bad block marker; S2 performs data write operations, using a parallel write method to write data to multiple physical blocks of each flash memory chip; S3 performs data read operations, using a parallel read method to read data from multiple physical blocks of each flash memory chip, and records the read latency; S4 collects multi-dimensional parameter data for each flash memory chip, including at least the number of bad blocks, IO rate, and a new bad block marker to indicate whether a new bad block has appeared. S5 inputs the multi-dimensional parameter data into the dynamic threshold model for analysis. The dynamic threshold model is trained on historical test data using a clustering algorithm. Based on the output of the dynamic threshold model, each flash memory chip is assessed for its suitability and performance is graded.
2. The flash memory chip screening and grading method according to claim 1, characterized in that, The printed circuit board in step S1 is equipped with a main control unit and multiple flash memory chip interfaces. All flash memory chips are connected to the main control unit through a parallel bus, and the main control unit uniformly schedules and executes parallel data writing and data reading operations.
3. The flash memory chip screening and grading method according to claim 2, characterized in that, When the main control unit performs parallel data write and data read operations, it adaptively selects a parallel test strategy based on the physical surface type of each flash memory chip. When the flash memory chip adopts a multi-physical surface design, a test strategy is selected for multi-physical surface writing mode and multi-physical surface reading mode; When the flash memory chip adopts a dual-solid-plane design, a test strategy is selected for dual-solid-plane writing mode and dual-solid-plane reading mode; When the flash memory chip adopts a single physical surface design, a test strategy is selected for single physical surface writing mode and single physical surface reading mode.
4. The flash memory chip screening and grading method according to claim 1, characterized in that, The method for obtaining the IO rate in step S4 is as follows: the main control unit records the total delay from sending the read command to the last data being read, and calculates the IO rate of the read based on the total delay and the total amount of data read.
5. The flash memory chip screening and grading method according to claim 1, characterized in that, The method for establishing the dynamic threshold model in step S5 is as follows: collect historical test data of flash memory chips to form a sample set, perform unsupervised clustering analysis on the sample set, and determine the dynamic threshold for grading judgment based on the clustering results.
6. The flash memory chip screening and grading method according to claim 5, characterized in that, The unsupervised clustering analysis is the K-Means algorithm, and the steps for establishing the dynamic threshold model include: S51 collects historical test data of flash memory chips to form a sample set. The test data includes bad block information, latency information, IO rate, and newly added bad block markers. S52 extracts the feature vector of each flash memory chip and performs Z-score normalization on the feature vector dataset; wherein, the feature vector of each flash memory chip includes X = (Initial bad block count, IO rate slope, average latency, new bad block marker, temperature variance, solid surface type); S53 uses the K-Means algorithm to cluster the standardized feature vector dataset, and uses the centroid feature value of each cluster as the dynamic threshold of that category.
7. The flash memory chip screening and grading method according to claim 6, characterized in that, The method for obtaining the IO rate slope in the feature vector is as follows: during the test, the IO rate is measured multiple times at different time points to form a sequence, and the sequence is linearly fitted. The slope value obtained from the fitting is used as the IO rate slope.
8. The flash memory chip screening and grading method according to claim 6, characterized in that, It also includes the step of periodically or trigger-based updating the dynamic threshold model, the update step including: S501 Update Trigger: The model update process is triggered when the number of newly tested flash memory chips reaches a preset threshold or when the preset time period since the last model update has elapsed. S502 Data Integration: The feature vector data of all new test particles since the last update are integrated with the historical feature vector dataset to form a new training dataset; S503 model retraining: The K-Means algorithm is used to re-cluster the new training dataset to calculate new cluster centroid feature values; S504 Threshold Update: The new cluster centroid feature value is used as the updated dynamic threshold for each category, replacing the old threshold for subsequent analysis and classification of flash memory chips.
9. The flash memory chip screening and grading method according to claim 8, characterized in that, The model retraining described in step S503 adopts an incremental learning approach, specifically: the old cluster centroid is used as the initial centroid, and iterative calculation is performed using only the newly added particle feature vector data to quickly converge to the new cluster centroid.
10. The flash memory chip screening and grading method according to claim 8, characterized in that, Following the model update step, there is also a model optimization step: calculating the silhouette coefficient of the current clustering results to evaluate the clustering quality; if the silhouette coefficient is lower than the preset quality threshold, the number of clusters K in the K-Means algorithm is automatically adjusted, and the clustering analysis is performed again.