Redundancy check code calculation circuit, redundancy check code calculation method and chip

Abstract

The invention discloses a redundancy check code calculation circuit, a redundancy check code calculation method and a chip, and belongs to the technical field of communication. The calculation circuit comprises a mask module, a calculation module and a correction module. Wherein the mask module is used for replacing invalid data with mask data to obtain second input data under the condition that the invalid data exists in the first input data, and transmitting the second input data to the calculation module; the calculation module is used for calculating according to the second input data to obtain a first redundancy check code and transmitting the first redundancy check code to the correction module; and the correction module is used for correcting the first redundancy check code to obtain a second redundancy check code. Through the calculation circuit, calculation of the input data containing invalid data is achieved, the correct redundancy check code is obtained, and resources used by the calculation circuit are few.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a redundancy check code calculation circuit, calculation method, and chip. Background Technology

[0002] In the field of communication technology, Cyclic Redundancy Check (CRC) is a common error detection technique for data transmission. The sending end calculates the redundancy check code (CBC) of a message using a certain algorithm, appends the CBC to the message, and sends both the message and the CBC to the receiving end. The receiving end checks the message and the CBC using the same algorithm and determines whether an error occurred during transmission based on the check result. Therefore, the CBC is a very important data type in communication technology, and how to calculate it has become a crucial technical problem that needs to be solved. Summary of the Invention

[0003] This application provides a redundancy check code calculation circuit, calculation method, and chip, which can calculate the correct redundancy check code from input data containing invalid data. The technical solution includes the following contents.

[0004] In a first aspect, a redundancy check code calculation circuit is provided, the calculation circuit including a mask module, a calculation module and a correction module;

[0005] The masking module is used to replace invalid data with masked data when invalid data exists in the first input data to obtain second input data, and then transmit the second input data to the calculation module.

[0006] The calculation module is used to calculate a first redundancy check code based on the second input data and transmit the first redundancy check code to the correction module.

[0007] The correction module is used to correct the first redundancy check code to obtain the second redundancy check code.

[0008] Secondly, a redundancy check code calculation circuit is provided, the calculation circuit including a processing module and multiple calculation modules, each calculation module having a different calculation length;

[0009] The processing module is used to transmit the first input data to the first calculation module when there is invalid data in the first input data, wherein the first input data includes initial valid data.

[0010] The calculation module is used to calculate the fourth input data and obtain the target calculation result;

[0011] The fourth input data includes the initial valid data, or the target calculation result of the previous calculation module and the remaining valid data in the initial valid data that has not been calculated. The target calculation result of the last calculation module is the redundancy check code of the first input data.

[0012] Thirdly, a method for calculating a redundancy check code is provided, the method comprising:

[0013] If invalid data exists in the first input data, the invalid data is replaced with masked data by the masking module to obtain the second input data.

[0014] The calculation module calculates the first redundancy check code based on the second input data.

[0015] The first redundancy check code is corrected by the correction module to obtain the second redundancy check code.

[0016] In one possible implementation, the method further includes:

[0017] The first control signal is obtained through the mask module, and the invalid data is determined from the first input data based on the first control signal. The first control signal is used to indicate the position of the invalid data in the first input data.

[0018] In one possible implementation, the correction module includes at least one correction submodule; the step of correcting the first redundancy check code to obtain the second redundancy check code through the correction module includes:

[0019] The third input data is corrected by the correction submodule to obtain the target correction result, wherein the third input data is the first redundancy check code or the target correction result of the previous correction submodule.

[0020] The target correction result of the last correction submodule is the second redundancy check code.

[0021] In one possible implementation, the correction submodule includes a selector and at least one correction unit, each correction unit corresponding to a different correction length; the step of correcting the third input data through the correction submodule to obtain the target correction result includes:

[0022] The correction unit performs a correction of the corresponding length on the third input data to obtain a candidate correction result, and then transmits the candidate correction result to the selector.

[0023] The selector selects the target correction result from the third input data and the various candidate correction results.

[0024] In one possible implementation, the correction submodule further includes a register; the method further includes:

[0025] The third input data is stored in the register;

[0026] The third input data is read from the register by the correction unit;

[0027] The third input data is read from the register using the selector.

[0028] In one possible implementation, the first input data is M data units, the invalid data is N data units, the correction submodule is one, the correction unit is M-1, the correction length of the j-th correction unit is j, and M is greater than N;

[0029] The step of selecting the target correction result from the third input data and the various candidate correction results through the selector includes:

[0030] Using the selector, when N is 0, the third input data is selected as the target correction result; when N is not 0, the target correction result with a correction length of N is selected from the candidate correction results.

[0031] In one possible implementation, the first input data consists of M data units, the invalid data consists of N data units, the correction submodules are log2M in number, and the i-th correction submodule includes a correction unit with a correction length of 2. b M is greater than N, and b is an integer;

[0032] The step of selecting the target correction result from the third input data and the various candidate correction results through the selector includes:

[0033] Using the selector of the i-th correction submodule, when the target parameter is less than 2 b In the case where the third input data is selected as the target correction result, and the target parameter is not less than 2... b In the case of N, the candidate correction result is selected as the target correction result, and the target parameter is N or the difference between N and the corrected length.

[0034] In one possible implementation, the first input data consists of M data units, the invalid data consists of N data units, and there are L correction submodules, with the i-th correction submodule comprising 2... a -1 correction units, the correction length of the j-th correction unit is j×2.b M is greater than N, L is less than log2M, and a and b are both integers;

[0035] The step of selecting the target correction result from the third input data and the various candidate correction results through the selector includes:

[0036] Using the selector of the i-th correction submodule, when the target parameter is less than 2 b In the case where the third input data is selected as the target correction result, and the target parameter is not less than (2 a -1)×2 b In this case, choose option 2. a The candidate correction results of -1 correction units are the target correction results, where the target parameter is not less than k×2. b And less than (k+1)×2 b In the case where the candidate correction result of the k-th correction unit is selected as the target correction result, the target parameter is N or the difference between N and the corrected length, and k takes the value 1 to 2. a Integers in -2.

[0037] In one possible implementation, the step of calculating the first redundancy check code based on the second input data by the calculation module includes:

[0038] The calculation module calculates the first redundant check code based on the second input data and the check parameters.

[0039] The step of correcting the first redundancy check code to obtain the second redundancy check code through the correction module includes:

[0040] The correction module corrects the first redundancy check code according to the correction parameters to obtain the second redundancy check code, wherein the correction parameters are calculated based on the check parameters.

[0041] Fourthly, a method for calculating a redundancy check code is provided, the method comprising:

[0042] In the event that invalid data exists in the first input data, the processing module transmits the first input data to the first of the multiple calculation modules. The calculation lengths of each calculation module are different. The first input data includes the initial valid data.

[0043] The calculation module calculates the fourth input data to obtain the target calculation result.

[0044] The fourth input data includes the initial valid data, or the target calculation result of the previous calculation module and the remaining valid data in the initial valid data that has not been calculated. The target calculation result of the last calculation module is the redundancy check code of the first input data.

[0045] In one possible implementation, the processing module includes a controller; the step of transmitting the first input data to the first computing module among a plurality of computing modules through the processing module when invalid data exists in the first input data includes:

[0046] The controller acquires a first control signal, and determines whether the invalid data exists in the input data based on the first control signal. The first control signal is used to indicate the position of the invalid data in the input data.

[0047] The controller transmits the first input data to the first computing module in the event of invalid data.

[0048] In one possible implementation, the processing module further includes a first computing submodule; the method further includes:

[0049] The controller transmits the first input data to the first calculation submodule when the first input data does not contain invalid data.

[0050] The redundancy check code is calculated by the first calculation submodule based on the first input data.

[0051] In one possible implementation, each of the computing modules includes a selector and at least one second computing submodule, each second computing submodule corresponding to a different computing length;

[0052] The step of calculating the fourth input data through the calculation module to obtain the target calculation result includes:

[0053] The second calculation submodule performs a calculation of the corresponding length on the fourth input data to obtain a candidate calculation result, and then transmits the candidate calculation result to the selector.

[0054] The selector selects the target calculation result from the fourth input data and each candidate calculation result.

[0055] In one possible implementation, the computing module further includes registers; the method further includes:

[0056] The fourth input data is stored in the register.

[0057] The second calculation submodule reads the fourth input data from the register;

[0058] The fourth input data is read from the register using the selector.

[0059] In one possible implementation, the first input data consists of M data units, the initial valid data consists of T data units, the calculation modules are log2M in number, and the i-th calculation module includes a second calculation submodule, the calculation length of which is 2. b M is greater than T, and b is an integer;

[0060] The step of selecting the target calculation result from the fourth input data and the various candidate calculation results through the selector includes:

[0061] Using the selector of the i-th calculation module, when the specified parameter is less than 2... b In the case where the fourth input data is selected as the target calculation result, and the specified parameter is not less than 2... b In the case of T, the candidate calculation result is selected as the target calculation result, and the specified parameter is T or the difference between T and the calculated length.

[0062] In one possible implementation, the first input data consists of M data units, the initial valid data consists of T data units, and there are L calculation modules, with the i-th calculation module comprising 2... a -1 second computation submodules, the computation length of the j-th second computation submodule is j×2. b M is greater than T, L is less than log2M, and a and b are both integers;

[0063] The step of selecting the target calculation result from the fourth input data and the various candidate calculation results through the selector includes:

[0064] Using the selector of the i-th calculation module, when the specified parameter is less than 2... b In the case where the fourth input data is selected as the target calculation result, and the specified parameter is not less than (2 a -1)×2 b In this case, choose option 2. a -1 candidate calculation results of the second calculation submodule are the target calculation results, where the specified parameter is not less than k×2 b And less than (k+1)×2 bIn the case where the candidate calculation result of the kth second calculation submodule is selected as the target calculation result, the specified parameter is T or the difference between T and the calculated length, and k takes the value 1 to 2. a Integers in -2.

[0065] Fifthly, a chip is provided, the chip including computing circuitry as shown in the first aspect for performing the computing method shown in the third aspect, or the chip including computing circuitry as shown in the second aspect for performing the computing method shown in the fourth aspect.

[0066] In a sixth aspect, an electronic device is provided, the electronic device including computing circuitry as shown in the first aspect for performing the computing method shown in the third aspect, or the chip including computing circuitry as shown in the second aspect for performing the computing method shown in the fourth aspect.

[0067] The technical solution provided in this application brings at least the following beneficial effects:

[0068] In the technical solution provided in this application, when the first input data contains invalid data that cannot be used for calculation, a masking module replaces the invalid data with masking data that can be used for calculation to obtain the second input data. Since the second input data includes masking data, it is therefore erroneous, causing the first redundancy check code calculated by the calculation module based on the second input data to be an incorrect result. Based on this, a correction module corrects the first redundancy check code to obtain a correct second redundancy check code.

[0069] By replacing invalid data in the input data with mask data, the length of the input data is fixed. This allows a single computation module to perform calculations on any input data, eliminating the need for separate computation modules for different input data lengths, effectively reducing chip resource consumption. Since the length of the redundancy check code is much shorter than the length of the input data, the computational load involved in correcting the redundancy check code through the correction module is less than that of using different computation modules to calculate input data of corresponding lengths. This results in less resource consumption for the correction module, but significantly improved computational performance. Therefore, the computational circuit of this application has low resource consumption and high computational performance, enabling rapid calculation of the redundancy check code. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0071] Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application;

[0072] Figure 2 This is a structural diagram of a redundancy check code calculation circuit provided in an embodiment of this application;

[0073] Figure 3 This is a schematic diagram of a splicing matrix provided in an embodiment of this application;

[0074] Figure 4 This is a schematic diagram of a square matrix provided in an embodiment of this application;

[0075] Figure 5 This is a schematic diagram of a square matrix after binarization provided in an embodiment of this application;

[0076] Figure 6 This is a schematic diagram of a correction parameter provided in an embodiment of this application;

[0077] Figure 7 This is a schematic diagram of a redundancy check code calculation circuit provided in an embodiment of this application;

[0078] Figure 8 This is a schematic diagram of a correction module provided in an embodiment of this application;

[0079] Figure 9 This is a schematic diagram of another redundancy check code calculation circuit provided in an embodiment of this application;

[0080] Figure 10 This is a schematic diagram of another redundancy check code calculation circuit provided in the embodiments of this application;

[0081] Figure 11 This is a schematic diagram of a redundancy check code calculation circuit provided in an embodiment of this application;

[0082] Figure 12 This is a schematic diagram of a redundancy check code calculation circuit provided in an embodiment of this application;

[0083] Figure 13 This is a schematic diagram of a redundancy check code calculation circuit provided in an embodiment of this application;

[0084] Figure 14 This is a flowchart illustrating a method for calculating a redundancy check code provided in an embodiment of this application;

[0085] Figure 15 This is a flowchart illustrating a method for calculating a redundancy check code provided in an embodiment of this application;

[0086] Figure 16This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application;

[0087] Figure 17 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0088] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0089] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0090] In the field of communication technology, the sending end can calculate the redundancy check (CDR) code of a message according to a certain algorithm, append the CDR code to the message, and send the message and CDR code to the receiving end. The receiving end verifies the message and CDR code using the same algorithm and determines whether an error occurred in the message during transmission based on the verification result. Therefore, in the field of communication technology, the CDR code is a very important data element, and how to calculate the CDR code has become a pressing technical problem that needs to be solved.

[0091] In response, this application provides a redundancy check code calculation circuit, which can calculate the correct redundancy check code from input data containing invalid data, and the calculation circuit uses fewer resources.

[0092] like Figure 1 As shown, Figure 1This is a schematic diagram of a computer system provided in an embodiment of this application. The computer system includes a terminal device 101 and a server 102. The terminal device 101 has a client installed and running, and the target object 103 can interact with the server 102 through the client. The terminal device 101 may include a redundancy check code calculation circuit provided in this embodiment of the application. The calculation circuit calculates the redundancy check code for the message and transmits the message and the redundancy check code to the server 102. Alternatively, the server 102 may include a redundancy check code calculation circuit provided in this embodiment of the application. The calculation circuit calculates the redundancy check code for the message and transmits the message and the redundancy check code to the terminal device 101. Optionally, the calculation circuit may be located on a chip in the terminal device 101 or the server 102.

[0093] Server 102 provides background services for the client installed on terminal device 101. In one possible implementation, server 102 undertakes the main computing work, and terminal device 101 undertakes the secondary computing work. Alternatively, server 102 undertakes the secondary computing work, and terminal device 101 undertakes the main computing work. Or, terminal device 101 and server 102 collaborate on computing using a distributed computing architecture.

[0094] Optionally, the terminal device 101 can be any electronic device product capable of human-computer interaction with the user through one or more methods such as a keyboard, touchpad, remote control, voice interaction, or handwriting device. For example, the terminal device 101 can be a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, PC (Personal Computer), mobile phone, PDA (Personal Digital Assistant), wearable device, PPC (Pocket PC), smart car system, smart TV, etc.

[0095] Terminal device 101 can refer to one of a plurality of terminal devices. This embodiment uses terminal device 101 as an example. Those skilled in the art will know that the number of terminal devices 101 can be more or less. For example, there may be only one terminal device 101, or there may be dozens or hundreds of terminal devices 101, or more. This application embodiment does not limit the number or type of terminal devices 101.

[0096] Server 102 can be a single server, a server cluster consisting of multiple servers, or any of the following: a cloud computing platform or a virtualization center. This embodiment of the application does not limit this. Server 102 communicates directly or indirectly with terminal device 101 via a wired or wireless network. Server 102 has data receiving, data processing, and data sending functions. Of course, server 102 may also have other functions, which are not limited in this embodiment of the application.

[0097] Those skilled in the art should understand that the terminal device 101 and server 102 described above are merely illustrative examples. Other existing or future terminal devices or servers that are applicable to this application should also be included within the scope of protection of this application, and are hereby incorporated by reference.

[0098] This application provides a redundancy check code calculation circuit, such as... Figure 2 As shown, the calculation circuit includes a mask module 10, a calculation module 20, and a correction module 30. Figure 2 In the structural diagrams mentioned below, black circles are used to identify input terminals, and white circles are used to identify output terminals. For example... Figure 2 As shown, the output of the mask module 10 is connected to the input of the calculation module 20, and the output of the calculation module 20 is connected to the input of the correction module 30.

[0099] The masking module 10 is used to replace invalid data with masked data when invalid data exists in the first input data, to obtain the second input data, and then transmit the second input data to the calculation module 20.

[0100] The calculation module 20 is used to calculate the first redundancy check code based on the second input data and transmit the first redundancy check code to the correction module 30.

[0101] The correction module 30 is used to correct the first redundancy check code to obtain the second redundancy check code.

[0102] The full name of the redundancy check code is Cyclic Redundancy Check (CRC) code. In the field of communication technology, CRC is a commonly used error detection technique for data transmission. The sending end can calculate the CRC code of the message according to a certain algorithm, append the CRC code to the message, and send the message and CRC code to the receiving end. The receiving end checks the received message and CRC code according to the same algorithm, and determines whether the message has been corrupted during transmission based on the check result.

[0103] When calculating the redundancy check code, the message can be divided into multiple data blocks. For example, when the chip uses a data width of 1024 bits (128 bytes), the message can be divided into multiple data blocks, with each block consisting of 128 bytes. Then, each block of data is processed sequentially. Generally, only one block of data can be calculated per clock cycle. The calculation result of the previous block is used to calculate the next block, and the calculation result of the last block is the redundancy check code. Because the calculation of subsequent data depends on the calculation results of previous data, multiple blocks of data cannot be calculated in parallel within the same clock cycle; only one block can be calculated within one clock cycle.

[0104] Typically, the length of non-tail data is fixed, while the length of tail data is variable. For example, when dividing a message into multiple tail data blocks using 128 bytes per block, the non-tail data is 128 bytes, while the tail data can be any length from 1 byte to 128 bytes. When calculating each tail data block, the length of the input data is the chip's data bit width. If the input data includes non-tail data, generally, there is no invalid data. For example, if the non-tail data is 128 bytes, inputting 128 bytes of data will result in no invalid data. If the input data includes tail data, the input data may or may not contain invalid data. For example, if the tail data is 128 bytes, inputting 128 bytes of data will result in no invalid data; if the tail data is 28 bytes, inputting 128 bytes of data will result in 120 bytes of invalid data.

[0105] In this embodiment, the length of the first input data is equal to the data bit width of the chip. The first input data includes a single data segment obtained after dividing the message. The first input data may or may not contain invalid data. It is understood that invalid data is data that cannot be used for CRC calculation. The data in the first input data other than invalid data is valid data. The first input data contains valid data, which is data that can be used for CRC calculation. For example, invalid data includes the character "-", and valid data includes the numbers 0 or 1.

[0106] If invalid data exists in the first input data, the masking module 10 replaces the invalid data with mask data, thereby transforming the first input data into the second input data. The mask data is data that can be used for CRC calculation; for example, the mask data includes the digit 0, or the mask data includes the digit 1. That is, the first input data includes valid data and invalid data, and the second input data includes valid data and mask data. This application embodiment does not limit the mask data; exemplarily, the mask data is 0.

[0107] The masking module 10 transmits second input data to the calculation module 20. The calculation module 20 calculates a first redundancy check code based on the second input data. Since the second input data contains masking data, the first redundancy check code is an incorrect redundancy check code, which can be denoted as CRC32E. The calculation module 20 transmits the first redundancy check code to the correction module 30, and the correction module 30 corrects the first redundancy check code to obtain a second redundancy check code. The second redundancy check code is a correct redundancy check code, which can be denoted as CRC32C.

[0108] The calculation module 20 is used to calculate the first redundancy check code based on the second input data and the verification parameters; the correction module 30 is used to correct the first redundancy check code based on the correction parameters to obtain the second redundancy check code, and the correction parameters are calculated based on the verification parameters.

[0109] In this embodiment, the calculation module 20 can obtain the verification parameters of a certain algorithm. These verification parameters can be randomly generated or generated according to the algorithm's standard. For example, the verification parameters for the CRC32 algorithm can be generated according to the generative formula G(x) = x³² + x²⁶ + x²³ + x²² + x¹⁶ + x¹² + x¹¹ + x¹⁰ + x⁸ + x⁷ + x⁵ + x⁴ + x² + x + 1. These verification parameters can be converted to hexadecimal data 0x104C11DB7. The calculation module 20 calculates the second input data based on the verification parameters to obtain the first redundancy check code.

[0110] As mentioned above, a message includes at least one data frame, and the calculation result of the previous data frame is used to calculate the next data frame. Generally, an initial value can be obtained first. For the first data frame, the first data frame is calculated based on the check parameter and the initial value, yielding the calculation result for the first data frame. For non-first data frames, the non-first data frames are calculated based on the check parameter and the calculation result of the previous data frame, yielding the calculation result for the non-first data frame. The initial value and the calculation result of the previous data frame are collectively referred to as the reference data. Performing CRC calculation on each data frame involves XORing the check parameter, the reference data, and the data frame to obtain the result, which is a linear operation. CRC calculation can be represented using a matrix. For ease of description, the following example uses a chip with a data width of 1 byte and the CRC32 algorithm to perform CRC calculation on one data frame, illustrating the calculation process. It is understood that the calculation principles for other data widths and other algorithms are similar and will not be elaborated upon here.

[0111] In this example, since the data width is 1 byte, the length of one data cycle is 1 byte. The input calculation module 20 has two variables: one is the 1-byte current data cycle, which can be represented by parameter D; the other is the 4-byte initial value or the calculation result of the previous data cycle, which can be represented by parameter CRC32_P. The output of the calculation module 20 is the 4-byte calculation result of the current data cycle, which can be represented by parameter CRC32. Since 1 byte equals 8 bits, D = [d7d6…d1d0], CRC32 = [c 31 c 30 … c1 c0]. The calculation module 20 can perform CRC calculation according to CRC32=[D CRC32_P]·A, where A represents the check parameter, which is a 40-row, 32-column matrix and is a constant matrix generated by the CRC32 algorithm. Based on this, the CRC calculation formula can be expressed as the following formula (1), where “·” in the following text is the matrix dot product symbol.

[0112]

[0113] When invalid data exists in the first input data, for example, if the length of the first input data is M bytes and N bytes are invalid data, the invalid data in the first input data is replaced with mask data to obtain the second input data. When performing CRC calculation on the second input data, since the second input data contains mask data, the CRC calculation result, i.e., the first redundancy check code, is an incorrect redundancy check code obtained by calculating N extra bytes of mask data. To address this, this embodiment uses a correction module 30 to correct the first redundancy check code according to correction parameters, thereby reversing the CRC calculation of the N bytes of mask data to obtain the correct CRC calculation result, i.e., the second redundancy check code.

[0114] Since CRC calculation is a matrix calculation, the inverse operation can be achieved by multiplying the matrix by its inverse. However, in the above formula (1), the check parameter A is not a square matrix and therefore does not have an inverse matrix. Therefore, in this embodiment, invalid data is replaced with mask data, and the inverse matrix is ​​obtained by transforming formula (1). The process of determining the inverse matrix is ​​illustrated below using the example of replacing invalid data with 0.

[0115] In this example, assuming that there is 1 byte of invalid data in one batch of data, after replacing the invalid data with 0, the mask data D1 = [0 0 0……0 0] is obtained. At this time, all the data in one batch is mask data. Based on the mask data, formula (1) can be transformed to obtain the following formula (2).

[0116]

[0117] Formula (2) above can be simplified to CRC32 = CRC32_P·A1, where A1 is a 32-row, 32-column square matrix with an inverse matrix. In this case, the erroneous CRC calculation result can be corrected to the correct calculation result by using the inverse matrix. The inverse matrix is ​​the correction parameter in the embodiment of this application.

[0118] If the invalid data is N bytes, then the mask data is also N bytes. The first redundancy check (CRC32E) satisfies: CRC32E = CRC32C·A1·A1…·A1, where CRC32C represents the second redundancy check (the correct redundancy check), and the number of A1 values ​​is N. The correction module 30 uses the inverse matrix A1... -1 (i.e., the correction parameter) can correct the first redundancy check code to the second redundancy check code CRC32C = CRC32E·A -1 ·A -1 …·A -1 A -1 The number is N.

[0119] When performing CRC calculations, the chip uses binary Boolean operations. Boolean operations are linear operations, involving only addition and multiplication. Boolean operations only involve the data 0 and 1. Addition is: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 0; multiplication is: 0 × 0 = 0, 0 × 1 = 0, 1 × 0 = 0, 1 × 1 = 1. Therefore, Boolean addition differs from ordinary mathematical operations and requires some adjustments to replace regular addition with Boolean addition. Optionally, the result of a regular addition operation can be binarized, making odd numbers 1 and even numbers 0. In this case, the regular addition operation can be transformed into a Boolean addition operation.

[0120] As mentioned above, the correction parameters are calculated based on the check parameters. Since the chip uses Boolean operations, the correction parameters are a matrix composed of data 0s and 1s. In this example, the check parameters and the setting matrix can be concatenated to obtain a concatenated matrix, where the setting matrix is ​​the diagonal matrix excluding the last row. A square matrix A1 is constructed based on the concatenated matrix; matrix A1 is used to convert correct redundancy check codes into incorrect ones. The correction parameters are determined based on the inverse of matrix A1. The following section uses the CRC32 algorithm as an example to illustrate the process of constructing the correction parameters.

[0121] In this example, assuming the invalid data is 1 byte, to calculate the square matrix A1 in formula (2), we first need to construct the concatenation matrix Ab corresponding to when the invalid data is 1 bit. For the CRC32 algorithm, such as Figure 3As shown, the verification parameter 0x104C11DB7 can be converted into a binary matrix, as shown in label 301. The binary matrix and the setting matrix are concatenated to obtain the concatenated matrix Ab. The setting matrix is ​​the diagonal matrix excluding the last row, as shown in label 302. The first row of the concatenated matrix Ab is the binary matrix. The remaining part of the concatenated matrix Ab, excluding the first row, is the setting matrix. That is, in the remaining part of the concatenated matrix Ab excluding the first row, elements (2,1), (3,2), (4,3), (5,6), ... (32,31) are 1, forming a diagonal line, and other elements are 0.

[0122] Next, the eighth power of the concatenated matrix Ab is calculated to obtain the square matrix A1, i.e., A1 = Ab^8, where "^" is the power sign. For example... Figure 4 As shown, the square matrix A1 is not a binary matrix and contains non-binary elements as indicated by label 401. Therefore, square matrix A1 is binarized to convert it into a binary matrix. Figure 5 As shown, by binarizing the square matrix A1, the non-binary elements (as shown by label 401) are converted into binary elements (as shown by label 501), resulting in a binary matrix. This binary matrix contains only binary elements, i.e., only elements 0 and 1. Next, the inverse operation is performed on the binarized square matrix A1, and the result is binarized to obtain the correction parameter B1, where B1 = A1. -1 =A1^-1, A1 -1 The inverse matrix of the square matrix A1 after binarization is represented by the correction parameter B1 as follows: Figure 6 As shown.

[0123] Optionally, the first redundancy check code crc_in is corrected according to the correction parameter B1 using the Verilog code shown below to obtain the second redundancy check code crc_out. This process corresponds to a correction of length 1. Verilog code is a hardware description language commonly used to describe hardware circuits in FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) designs.

[0124] function bit[31:0]crc_rb_1bytes(bit[31:0]crc_in);

[0125] logic[31:0]crc_out;

[0126] crc_out

[31] =crc_in[7]^crc_in[6]^crc_in[4]^crc_in[2]^crc_in[0];

[0127] crc_out

[30] =crc_in[6]^crc_in[5]^crc_in[3]^crc_in[1];

[0128] crc_out

[29] =crc_in[5]^crc_in[4]^crc_in[2]^crc_in[0];

[0129] crc_out

[28] =crc_in[4]^crc_in[3]^crc_in[1];

[0130] crc_out

[27] =crc_in[3]^crc_in[2]^crc_in[0];

[0131] crc_out

[26] =crc_in[2]^crc_in[1];

[0132] crc_out

[25] =crc_in[7]^crc_in[6]^crc_in[4]^crc_in[2]^crc_in[1];

[0133] crc_out

[24] =crc_in[6]^crc_in[5]^crc_in[3]^crc_in[1]^crc_in[0];

[0134] crc_out

[23] =crc_in

[31] ^crc_in[5]^crc_in[4]^crc_in[2]^crc_in[0];

[0135] crc_out

[22] =crc_in

[30] ^crc_in[7]^crc_in[6]^crc_in[3]^crc_in[2]^crc_in[1]^crc_in[0];

[0136] crc_out

[21] =crc_in

[29] ^crc_in[7]^crc_in[5]^crc_in[4]^crc_in[1];

[0137] crc_out

[20] =crc_in

[28] ^crc_in[6]^crc_in[4]^crc_in[3]^crc_in[0];

[0138] crc_out

[19] =crc_in

[27] ^crc_in[5]^crc_in[3]^crc_in[2];

[0139] crc_out

[18] =crc_in

[26] ^crc_in[4]^crc_in[2]^crc_in[1];

[0140] crc_out

[17] =crc_in

[25] ^crc_in[3]^crc_in[1]^crc_in[0];

[0141] crc_out

[16] =crc_in

[24] ^crc_in[2]^crc_in[0];

[0142] crc_out

[15] =crc_in

[23] ^crc_in[7]^crc_in[6]^crc_in[4]^crc_in[2]^crc_in[1]^crc_in[0];

[0143] crc_out

[14] =crc_in

[22] ^crc_in[6]^crc_in[5]^crc_in[3]^crc_in[1]^crc_in[0];

[0144] crc_out

[13] =crc_in

[21] ^crc_in[5]^crc_in[4]^crc_in[2]^crc_in[0];

[0145] crc_out

[12] =crc_in

[20] ^crc_in[4]^crc_in[3]^crc_in[1];

[0146] crc_out

[11] =crc_in

[19] ^crc_in[7]^crc_in[6]^crc_in[4]^crc_in[3];

[0147] crc_out

[10] =crc_in

[18] ^crc_in[7]^crc_in[5]^crc_in[4]^crc_in[3]^crc_in[0];

[0148] crc_out[9]=crc_in

[17] ^crc_in[7]^crc_in[3]^crc_in[0];

[0149] crc_out[8]=crc_in

[16] ^crc_in[6]^crc_in[2];

[0150] crc_out[7]=crc_in

[15] ^crc_in[7]^crc_in[6]^crc_in[5]^crc_in[4]^crc_in[2]^crc_in[1]^crc_in[0];

[0151] crc_out[6]=crc_in

[14] ^crc_in[7]^crc_in[5]^crc_in[3]^crc_in[2]^crc_in[1];

[0152] crc_out[5]=crc_in

[13] ^crc_in[6]^crc_in[4]^crc_in[2]^crc_in[1]^crc_in[0];

[0153] crc_out[4]=crc_in

[12] ^crc_in[7]^crc_in[6]^crc_in[5]^crc_in[4]^crc_in[3]^crc_in[2]^crc_in[1];

[0154] crc_out[3]=crc_in

[11] ^crc_in[7]^crc_in[5]^crc_in[3]^crc_in[1];

[0155] crc_out[2]=crc_in

[10] ^crc_in[6]^crc_in[4]^crc_in[2]^crc_in[0];

[0156] crc_out[1]=crc_in[9]^crc_in[7]^crc_in[6]^crc_in[5]^crc_in[4]^crc_in[3]^crc_in[2]^crc_in[1]^crc_in[0];

[0157] crc_out[0]=crc_in[8]^crc_in[7]^crc_in[5]^crc_in[3]^crc_in[1];

[0158] crc_rb_1bytes=crc_out;

[0159] return crc_rb_1bytes;

[0160] endfunction

[0161] In the Verilog code above, `crc_out[i]` represents the i-th element in the second redundancy check code, and `crc_in[j]` represents the j-th element in the first redundancy check code, where both i and j take values ​​from 0 to 31. By calculating the i-th column element of the correction parameter B1 with `crc_in[31:0]`, `crc_out[i]` is obtained. For example, for "crc_out

[31] = crc_in[7]^crc_in[6]^crc_in[4]^crc_in[2]^crc_in[0]", the 31st column element of the correction parameter B1 and the first redundancy check code can be used to calculate the 31st element `crc_out

[31] ` in the second redundancy check code. For example, ... Figure 6 As shown in label 601, for the 31st column element from right to left (i.e., the 0th column element from left to right) in the correction parameter B1, the elements in the 0th, 2nd, 4th, 6th, and 7th rows from bottom to top are all non-zero elements, and the remaining elements are zero elements. Based on this, crc_in[0], crc_in[2], crc_in[4], crc_in[6], and crc_in[7] are selected from the first redundancy check code crc_in[31:0], and the XOR operation result of each selected element is calculated to obtain crc_out

[31] . The operation principle of other elements in the second redundancy check code is similar and will not be described in detail here.

[0162] In summary, for any element in the second redundancy check code, an element is selected from the first redundancy check code based on the non-zero elements in the corresponding column of the correction parameter B1. Specifically, the element's index in the second redundancy check code matches the column index in the correction parameter B1, and the selected element's index in the first redundancy check code matches the column index of the non-zero element. An XOR operation is performed on each selected element to obtain the XOR result, which is the element in the second redundancy check code.

[0163] The correction module can correct the first redundancy check code according to the correction parameter B1. As mentioned above, assuming the invalid data is N bytes, the first redundancy check code is an erroneous redundancy check code obtained by over-calculating N bytes of mask data. Therefore, assuming a correction of length 1 can reverse the calculation of the 1-byte mask data, a correction of length N is needed on the first redundancy check code according to the correction parameter B1 to reverse the calculation of the N-byte mask data.

[0164] It is understandable that the correction parameter B1 is the parameter used for correction of length 1. When correcting the first redundancy check code of length N according to the correction parameter B1, it can be done step by step, that is: first, calculate the dot product of the first redundancy check code and the correction parameter to obtain the first correction result, which corrects the data of length 1. Then, calculate the dot product of the first correction result and the correction parameter to obtain the second correction result, which also corrects the data of length 1. Then, calculate the dot product of the second correction result and the correction parameter to obtain the third correction result, which again corrects the data of length 1, and so on, until the Nth correction result is obtained, thus correcting the data of length N (i.e., obtaining the second redundancy check code). Alternatively, the correction of the data of length N can be performed all at once. In this case, the parameter used for correction of length N is calculated according to the correction parameter B1. Optionally, the correction parameter B1 can be raised to the Nth power, and then the result of the exponentiation can be binarized to obtain the parameter used for correction of length N. The dot product of the first redundancy check code and the parameter used for correction of length N is calculated to obtain the second redundancy check code.

[0165] The functions of each module have been introduced above. The detailed structure and implementation principle of each function will be introduced below.

[0166] In an exemplary embodiment, the masking module 10 is further configured to acquire a first control signal and determine invalid data from the first input data based on the first control signal, wherein the first control signal is used to indicate the position of the invalid data in the first input data.

[0167] like Figure 7 As shown, in one clock cycle, the first input data is input to the mask module 10 of the computing circuit. The length of the first input data is the data bit width of the chip, for example, the length of the first input data is M bytes, where M is a positive integer. The first input data includes one data cycle, which is valid data, and the length of the valid data is less than or equal to M bytes. In addition, a first control signal is also input to the mask module 10. The first control signal is used to indicate the position of invalid data in the first input data. For example, if the first input data is M bytes, assuming the first control signal indicates MN, it is equivalent to the first control signal indicating that the data from the 1st to the Nth bytes is valid data, and the data from the (N+1)th to the Mth bytes is invalid data, where N is 0 or a positive integer less than M.

[0168] After receiving the first control signal and the first input data, if the first control signal indicates that there is no invalid data in the first input data, the masking module 10 does not need to perform masking processing and directly transmits the first input data to the calculation module 20. In this case, the calculation module 20 performs CRC calculation on the first input data, obtains a redundancy check code, and transmits the redundancy check code to the correction module 30. Since the first input data does not include mask data, the correction module 30 receives a correct redundancy check code, and based on this, the correction module 30 directly outputs the redundancy check code. If the first control signal indicates that there is invalid data in the first input data, the masking module 10 replaces the invalid data in the first input data with mask data according to the first control signal, obtains the second input data, and transmits the second input data to the calculation module 20. In this case, the calculation module 20 calculates an incorrect first redundancy check code based on the second input data, and after the correction module 30 corrects the first redundancy check code, it obtains a correct second redundancy check code.

[0169] By indicating the position of invalid data in the first input data using the first control signal, the invalid data in the first input data can be accurately located, so as to facilitate masking of invalid data and reduce the need to mask valid data, thereby reducing the probability of masking errors.

[0170] Furthermore, when a message includes multiple data frames, generally, if the first input data includes non-tail data, it does not include invalid data; if the first input data includes tail data, it may or may not include invalid data. For example, with a data width of 128 bytes, for a 257-byte message, the first two data frames are both 128 bytes, and the tail data is 1 byte. In this case, if the first input data includes tail data, there are 127 bytes of invalid data. Since the calculation result of the previous data frame is used to calculate the next data frame, therefore, if... Figure 7 As shown, the redundancy check code of the non-tail data determined by the calculation module 20 is a correct redundancy check code. This redundancy check code can be input into the calculation module 20, which then performs CRC calculation on the next data based on it. The redundancy check code of the tail data determined by the calculation module 20 can be either correct or incorrect, and can be input into the calculation module 20 or not. Since there is no next data for the tail data, even if an incorrect redundancy check code is input into the calculation module 20, it will not cause any impact.

[0171] In an exemplary embodiment, such as Figure 8As shown, the correction module 30 includes at least one correction submodule 31. Multiple correction submodules 31 are connected in series, meaning the output of one correction submodule 31 is connected to the input of the next correction submodule 31. The correction submodule 31 is used to correct the third input data to obtain the target correction result. The third input data is either a first redundancy check code or the target correction result of the previous correction submodule; the target correction result of the last correction submodule 31 is a second redundancy check code.

[0172] In this embodiment, the first redundancy check code is input to the first correction submodule 31. The first correction submodule 31 corrects the first redundancy check code according to the correction parameters to obtain the first target correction result, and transmits the first target correction result to the second correction submodule 31. The second correction submodule 31 corrects the first target correction result according to the correction parameters to obtain the second target correction result, and transmits the second target correction result to the third correction submodule 31. The third correction submodule 31 corrects the second target correction result according to the correction parameters to obtain the third target correction result, and transmits the third target correction result to the fourth correction submodule 31. This process continues until the target correction result of the last correction submodule 31 is obtained, and this target correction result is the second redundancy check code.

[0173] It should be noted that any correction submodule 31 can perform zero-length correction (i.e., no correction) or correction of the corresponding length on the third input data. The implementation method of correcting the third input data according to the correction parameter can be found in the description above regarding "correcting the first redundancy check code for a length of N according to the correction parameter B1". The implementation principles of the two are similar and will not be repeated here.

[0174] By dividing the correction module 30 into multiple serially connected correction sub-modules 31, the correction of the first redundancy check code is achieved stepwise through each correction sub-module 31. As mentioned above, invalid data of different lengths corresponds to different correction lengths. By combining the correction lengths of each correction sub-module 30, the first redundancy check code corresponding to invalid data of different lengths can be corrected to the correct result, improving the practicality of the correction module 30. Furthermore, in this embodiment, there is no need to set up different correction modules for invalid data of different lengths; instead, a single correction module 30 corrects the first redundancy check code corresponding to invalid data of different lengths, significantly reducing resource utilization.

[0175] Optionally, such as Figure 7As shown, each correction submodule 31 includes a selector 311 and at least one correction unit 312. The output of each correction unit 312 is connected to the input of the selector 311, and each correction unit 312 corresponds to a different correction length. The correction unit 312 is used to perform correction of the corresponding length on the third input data to obtain candidate correction results, and transmits the candidate correction results to the selector 311. The selector 311 is used to select the target correction result from the third input data and the candidate correction results.

[0176] In this embodiment of the application, the same correction submodule 31 includes correction units 312 with different correction lengths. Figure 7 The n-byte correction unit corresponds to a correction of length n, where n takes any value from 1 to N-1. The third input data can be input into any correction unit 312. The correction unit 312 performs the corresponding length correction processing on the third input data according to the correction parameters to obtain a candidate correction result, which is then transmitted to the selector 311. Alternatively, the calculation module 20 or the previous correction submodule 31 transmits the third input data to the selector 311. The selector 311 selects either the third input data or a candidate correction result from the input, using the selected data as the target correction result.

[0177] Optionally, such as Figure 7 As shown, selector 311 is used to acquire a second control signal and select a target correction result from the third input data and various candidate correction results based on the second control signal. The second control signal is used to indicate the correction length corresponding to the target correction result. For example, if the second control signal indicates 0, it means the correction length is 0, and selector 311 selects the third input data as the target correction result. As another example, if the second control signal indicates 7, it means the correction length is 7, and selector 311 selects the candidate correction result obtained after performing a correction of length 7 on the third input data as the target correction result.

[0178] By setting correction units 312 with different correction lengths, correction processing of different lengths can be performed on the correction units 312. By selecting the data before correction or the correction result of arbitrary length through the selector 311, it is possible to make the correction submodule 31 not correct the third input data or to perform correction of the third input data of arbitrary length. This facilitates the combination of correction lengths of various correction submodules 31, and realizes the correction of the first redundancy check code corresponding to invalid data of different lengths into the correct result, thereby improving the practicality of the correction module 30.

[0179] In one possible implementation, such as Figure 9As shown, the correction submodule 31 also includes a register 313, the output of which is connected to the input of each correction unit 312 and the input of the selector 311. The register 313 is used to store the third input data; the correction unit 312 is also used to read the third input data from the register; and the selector 311 is also used to read the third input data from the register.

[0180] In this embodiment, the calculation module 20 or the previous correction submodule 31 transmits the third input data to the register 313 in the next correction submodule 31, so that the register 313 stores the third input data. By storing the third input data, the possibility of data loss can be reduced, so that the correction unit 312 and the selector 311 can read the third input data and complete the correction of the error redundancy check code.

[0181] As mentioned above, the correction module 30 includes at least one correction submodule 31, and each correction submodule 31 includes at least one correction unit 312. In this regard, embodiments of this application provide the correction module 30 as shown in implementations A to C below.

[0182] In implementation method A, the first input data consists of M data units, the invalid data consists of N data units, there is one correction submodule 31, and M-1 correction units 312. The correction length of the j-th correction unit 312 is j, and M is greater than N. The selector 311 is used to select the third input data as the target correction result when N is 0, and to select the target correction result with a correction length of N from the candidate correction results when N is not 0.

[0183] In this application, the data unit is a basic unit used to measure data volume and storage capacity, and can be a byte or a bit, etc. For ease of description, the data unit in this application and the embodiments above and below will be used as an example.

[0184] The length of the first input data is equal to the data bit width of the chip. Assuming the data bit width is M bytes, then the length of the first input data is M bytes. The first input data includes valid data. If the length of the valid data is less than the length of the first input data, then the first input data includes invalid data. The length of the invalid data is any one from 1 to M-1 bytes. For ease of description, the length of the invalid data is denoted as N, where M is a positive integer, N is 0 or a positive integer, and M is greater than N.

[0185] like Figure 7As shown, the correction module 30 includes a correction submodule 31, which includes M-1 correction units 312. Each correction unit corresponds to a different correction length. Assuming j takes any value from 1 to M-1, the correction length of the j-th correction unit 312 is j. Figure 7 In this context, a correction unit 312 with a correction length of j is called a j-byte correction unit. For example, 128 bytes of input data requires correction units ranging from 1 to 127 bytes.

[0186] In this example, M bytes of first input data are input to the calculation circuit. If the first input data does not contain invalid data, the masking module 10 transmits the first input data to the calculation module 20. The calculation module 20 performs CRC calculation on the first input data to obtain a redundancy check code, and transmits the redundancy check code to the correction submodule 31. For example, for 128 bytes of input data, a 128-byte calculation module 20 is needed to perform CRC calculation on the input data. The correction unit 312, consisting of bytes 1 to M-1, sequentially corrects the redundancy check code with lengths from 1 to M-1, obtaining M-1 candidate correction results. Since the first input data does not contain invalid data, the redundancy check code before correction is the correct result, while the candidate correction result after correction is the incorrect result. Based on this, the selector 311 selects the redundancy check code before correction.

[0187] If the first input data of M bytes includes N bytes of invalid data, the masking module 10 replaces the invalid data with mask data to obtain the second input data of M bytes, and transmits the second input data to the calculation module 20. The calculation module 20 performs CRC calculation on the second input data to obtain the first redundancy check code, and transmits the first redundancy check code to the correction submodule 31. The correction unit 312 of bytes 1 to M-1 sequentially corrects the first redundancy check code for lengths of 1 to M-1, obtaining M-1 candidate correction results. Since the second input data includes mask data, the first redundancy check code is an erroneous result and needs to be corrected for a length of N. Among the M-1 candidate correction results, there is a corrected candidate correction result of length N. Based on this, the selector 311 selects the corrected candidate correction result of length N as the second redundancy check code.

[0188] By setting correction units for each correction length, it is possible to correct the erroneous first redundancy check code to the corresponding length for invalid data of any length, thereby obtaining the correct second redundancy check code and improving the practicality of the computing circuit.

[0189] Generally, the length of the redundancy check code is shorter than the length of the input data. For example, performing CRC32 calculation on 128 bytes of input data yields a 32-bit redundancy check code, whose length is much smaller than the length of the input data. Furthermore, the correction process mainly involves multiplying the correction parameters and the redundancy check code, a relatively simple calculation logic. Therefore, multiple correction units require fewer chip resources, including transistors or SRAM (Static Random-Access Memory).

[0190] In implementation method B, the first input data consists of M data units, the invalid data consists of N data units, the correction submodule 31 has log2M elements, and the i-th correction submodule 31 includes a correction unit 312 with a correction length of 2. b M is greater than N, and b is an integer. The selector 311 of the i-th correction submodule 31 is used when the target parameter is less than 2. b In the case of selecting the third input data as the target correction result, with the target parameter not less than 2... b In this case, the candidate correction result is selected as the target correction result, and the target parameter is N or the difference between N and the corrected length.

[0191] like Figure 9 As shown, the correction module 30 includes multiple correction submodules 31. For a data width of M bytes, a maximum of log2M correction submodules 31 can be used. For example, for a data width of 128 bytes, a maximum of log2 128 = 7 correction submodules 31 can be used. In this case, each correction submodule 31 includes only one correction unit 312. Since the computing circuit uses the fewest correction units 312, the chip resources used by the computing circuit are also minimized.

[0192] Let i take any integer from 1 to log2 M, where log2 M is an integer. In this case, the correction unit 312 in the i-th correction submodule 31 corresponds to 2. b The correction length is b = log2M - i. For example, when log2 128 = 7, the correction unit 312 in the first correction submodule 31 corresponds to 2. (7-1) =64 correction length, the correction unit 312 in the second correction submodule 31 corresponds to 2 (7-2) =32 correction length, the correction unit 312 in the third correction submodule 31 corresponds to 2 (7-3) =16 correction length, the correction unit 312 in the 4th correction submodule 31 corresponds to 2 (7-4) =8 correction length, the correction unit 312 in the 5th correction submodule 31 corresponds to 2 (7-5)=4 correction length, the correction unit 312 in the 6th correction submodule 31 corresponds to 2 (7-6) =2 correction length, the correction unit 312 in the 7th correction submodule 31 corresponds to 2 (7-7) =1 correction length. In Figure 9 In this context, a correction unit 312 with a correction length of j is called a j-byte correction unit. For example, a 1-byte correction unit corresponds to a correction length of 1.

[0193] In this example, M bytes of first input data are input to the computing circuit. If the first input data does not contain invalid data, the masking module 10 transmits the first input data to the computing module 20. The computing module 20 performs CRC calculation on the first input data to obtain a redundancy check code, and transmits the redundancy check code to the first correction submodule 31. The correction unit 312 in the first correction submodule 31 performs a correction on the redundancy check code with a length of... The correction process yields candidate correction results. Since the first input data does not include invalid data, the redundancy check code before correction is the correct result, while the candidate correction result after correction is the incorrect result. Based on this, the selector 311 in the first correction submodule 31 selects the redundancy check code before correction. Similarly, the correction units 312 in subsequent correction submodules 31 perform corrections of the corresponding length, but the selector 311 only selects the redundancy check code before correction.

[0194] If the first input data of M bytes includes N bytes of invalid data, the masking module 10 replaces the invalid data with masked data to obtain the second input data of M bytes, and transmits the second input data to the calculation module 20. The calculation module 20 performs CRC calculation on the second input data to obtain the first redundancy check code, and transmits the first redundancy check code to the first correction submodule 31.

[0195] The correction unit 312 in the first correction submodule 31 performs a length of correction on the first redundancy check code. The correction process yields candidate correction results. At this point, since no correction processing has been performed, the target parameter is the length of the invalid data, i.e., the target parameter is N. If the target parameter is less than... Then, selector 311 in the first correction submodule 31 selects the first redundancy check code as the target correction result. At this time, the corrected length is 0. If the target parameter is greater than or equal to Then, selector 311 in the first correction submodule 31 selects the candidate correction result as the target correction result. At this time, the corrected length is... Selector 311 transmits the target correction result to the second correction submodule 31.

[0196] The correction unit 312 in the second correction submodule 31 performs a length-based correction on the target correction result of the first correction submodule 31. The correction is performed to obtain candidate correction results. At this point, the target parameter is the difference between the length of the invalid data and the corrected length, i.e., the target parameter is N or... If the target parameter is less than Then, selector 311 in the second correction submodule 31 selects the target correction result of the first correction submodule 31 as the target correction result. At this time, the corrected length remains unchanged. If the target parameter is greater than or equal to... Then, selector 311 in the second correction submodule 31 selects the candidate correction result as the target correction result. At this time, the corrected length increases. Selector 311 transmits the target correction result to the third correction submodule 31.

[0197] The correction unit 312 in the third correction submodule 31 performs a length-based correction on the target correction result of the second correction submodule 31. The correction is performed to obtain candidate correction results. At this point, the target parameter is the difference between the length of the invalid data and the corrected length, i.e., the target parameter is N or... or N- or If the target parameter is less than Then, selector 311 in the third correction submodule 31 selects the target correction result of the second correction submodule 31 as the target correction result. At this time, the corrected length remains unchanged. If the target parameter is greater than or equal to... Then, selector 311 in the third correction submodule 31 selects the candidate correction result as the target correction result. At this time, the corrected length increases. Selector 311 transmits the target correction result to the fourth correction submodule 31.

[0198] This process continues until the target correction result of the last correction submodule is obtained, which is the second redundancy check code. The implementation principle of this application embodiment is explained below using M=128 and N=77 as an example. The correction lengths corresponding to the correction units in each correction submodel have been described above and will not be repeated here.

[0199] In this example, the correction unit 312 in the first correction submodule 31 corresponds to a correction length of 64. Since 77 is greater than 64, the selector 311 selects the candidate correction result as the target correction result, and the target parameter is 77-64=13. The correction unit 312 in the second correction submodule 31 corresponds to a correction length of 32. Since 13 is less than 32, the selector 311 selects the input target correction result, and the target parameter remains 13. The correction unit 312 in the third correction submodule 31 corresponds to a correction length of 16. Since 13 is less than 16, the selector 311 selects the input target correction result, and the target parameter remains 13. The correction unit 312 in the fourth correction submodule 31 corresponds to a correction length of 8. Since 13 is greater than 8, the selector... 311 selects the candidate correction result as the target correction result, and the target parameter is 13-8=5. The correction unit 312 in the fifth correction submodule 31 corresponds to a correction length of 4. Since 5 is greater than 4, the selector 311 selects the candidate correction result as the target correction result, and the target parameter is 5-4=1. The correction unit 312 in the sixth correction submodule 31 corresponds to a correction length of 2. Since 1 is less than 2, the selector 311 selects the input target correction result, and the target parameter is still 1. The correction unit 312 in the seventh correction submodule 31 corresponds to a correction length of 1. Since 1 equals 1, the selector 311 selects the candidate correction result as the target correction result, and the target parameter is 1-1=0. The target correction result is a correct redundancy check code.

[0200] Therefore, for a data width of 128 bytes, the computing circuit only requires 7 levels of correction submodules 31, and each correction submodule 31 requires only one correction unit 312. In this way, the computing circuit uses the least amount of resources. In other words, by using multiple levels of correction submodules 31, the number of correction units can be greatly reduced, thus reducing the use of chip resources.

[0201] For a data width of 128 bytes, the calculation circuit includes a 128-byte calculation module 20 for performing CRC calculation on the 128-byte input data. The calculation circuit also includes seven correction units 312, which perform correction processes of lengths 64, 32, 16, 8, 4, 2, and 1 respectively. The correction process of length 1 is used to correct erroneous calculations of 1 byte. Through the seven correction units 312, erroneous calculations from 1 to 127 bytes can be corrected, ensuring that for any input data, the calculation circuit of this embodiment can obtain the correct redundancy check code. Other data widths are similar; the calculation circuit of this embodiment can be used to calculate the correct redundancy check code for input data containing any valid data.

[0202] In implementation C, the first input data consists of M data units, the invalid data consists of N data units, and there are L correction submodules 31. The i-th correction submodule 31 includes 2... a -1 correction unit 312, the correction length of the j-th correction unit 312 is j×2 b M is greater than N, L is less than log2M, and a and b are both integers. The selector 311 of the i-th correction submodule 31 is used when the target parameter is less than 2. b In the case of selecting the third input data as the target correction result, the target parameter is not less than (2 a -1)×2 b In this case, choose option 2. a -1 The candidate correction result of correction unit 312 is the target correction result, where the target parameter is not less than k×2 b And less than (k+1)×2 b In this case, the candidate correction result of the k-th correction unit 312 is selected as the target correction result, and the target parameter is N or the difference between N and the corrected length, where k takes the value 1 to 2. a Integers in -2.

[0203] like Figure 10 As shown, the correction module 30 includes multiple correction submodules 31. For a data width of M bytes, a maximum of log₂M correction submodules 31 can be used. In this example, there are L correction submodules 31, where L is an integer greater than 1 and less than log₂M. For example, for a data width of 128 bytes, a maximum of log₂¹²⁸ = 7 correction submodules 31 can be used. In practical applications, 2, 3, 4, 5, or 6 correction submodules 31 can be used. In this case, each correction submodule 31 includes at least one correction unit 312. Because the computing circuit uses fewer correction units 312 and fewer correction submodules 31, the computing circuit uses fewer chip resources and has higher output efficiency.

[0204] Let i take any integer value from 1 to L. In this case, the i-th correction submodule 31 includes 2 a -1 correction unit, where 'a' is a positive integer, meaning 'a' can take values ​​of 1, 2, 3, or 4, etc. In practical applications, every two correction submodules 31 can correspond to the same or different 'a', thus corresponding to the same or different correction units. Let j take values ​​from 1 to 2. a Any integer in -1, in this case, the j-th correction unit 312 corresponds to j×2. b The correction length, in,

[0205] For example, when log2128 = 7, assuming L = 2, then the first correction submodule 31 can include 2 3 -1 = 7 correction units, b = 7 - 3 = 4, and the 1st to 7th correction units 312 correspond to 2 respectively. 4 =16, 2×2 4 =32, 3×2 4 =48, 4×2 4 =64, 5×2 4 =80, 6×2 4 =96, 7×2 4 =112 correction length. The second correction submodule 31 may include 2 4 -1 = 15 correction units, b = 7 - 3 - 4 = 0, and the 1st to 15th correction units 312 correspond to 2 respectively. 0 =1, 2×2 0 =2, 3×2 0 =3, 4×2 0 =4, 5×2 0 =5, 6 × 2 0 =6, 7 × 2 0 =7, 8 × 2 0 =8, 9 × 2 0 =9, 10×2 0 =10, 11 × 2 0 =11, 12 × 2 0 =12, 13 × 2 0 =13, 14 × 2 0 =14, 15 × 2 0 =15 correction length.

[0206] For example, when log2128 = 7, assuming L = 3, then the first correction submodule 31 can include 2 2 -1 = 3 correction units, b = 7 - 2 = 5, the first to third correction units 312 correspond to 2 respectively. 5 =32, 2×2 5 =64, 3×2 5 =96 correction length. The second correction submodule 31 may include 2 2 -1 = 3 correction units, b = 7 - 2 - 2 = 3, the first to third correction units 312 correspond to 2 respectively. 3 =8, 2×2 3 =16, 3×2 3 =24 correction length. The third correction submodule 31 may include 2 3 -1 = 7 correction units, b = 7 - 2 - 2 - 3 = 0, and the 1st to 7th correction units 312 correspond to the correction lengths 1 to 7 respectively.

[0207] In this example, M bytes of first input data are input to the computing circuit. If the first input data does not contain invalid data, the masking module 10 transmits the first input data to the computing module 20. The computing module 20 performs CRC calculation on the first input data to obtain a redundancy check code, and transmits the redundancy check code to the first correction submodule 31. The j-th correction unit 312 in the first correction submodule 31 performs a length j×2 correction on the redundancy check code. b The correction process yields candidate correction results. Since the first input data does not include invalid data, the redundancy check code before correction is the correct result, while the candidate correction result after correction is the incorrect result. Based on this, the selector 311 in the first correction submodule 31 selects the redundancy check code before correction. Similarly, the correction units 312 in subsequent correction submodules 31 perform corrections of the corresponding length, but the selector 311 only selects the redundancy check code before correction.

[0208] If the first input data of M bytes includes N bytes of invalid data, the masking module 10 replaces the invalid data with masked data to obtain the second input data of M bytes, and transmits the second input data to the calculation module 20. The calculation module 20 performs CRC calculation on the second input data to obtain the first redundancy check code, and transmits the first redundancy check code to the first correction submodule 31.

[0209] The correction unit 312 in the first correction submodule 31 performs a correction of the first redundancy check code with a length of j×2. b The correction process yields candidate correction results. At this point, since no correction processing has been performed, the target parameter is the length of the invalid data, i.e., the target parameter is N. If the target parameter is less than 2... b If the first correction submodule 31 selects the first redundancy check code as the target correction result, then the corrected length is 0. If the target parameter is greater than or equal to (2 a -1)×2 b Then the selector 311 in the first correction submodule 31 selects the (2)th... a -1) candidate correction results are used as the target correction result. At this time, the corrected length is (2 a -1)×2 b If the objective parameter is greater than or equal to k×2 b And less than (k+1)×2 b Then, selector 311 in the first correction submodule 31 selects the k-th candidate correction result as the target correction result. At this time, the corrected length is k×2. b k takes values ​​from 1 to 2 a Any integer in -2. Selector 311 transmits the target correction result to the second correction submodule 31.

[0210] The working principle of each subsequent correction submodule is similar to that of the first correction submodule, and will not be repeated here. Corrections are performed sequentially by each correction submodule, ultimately yielding the target correction result of the last correction submodule, which is the second redundancy check code. The implementation principle of this application's embodiment is explained below using M=128 and N=77 as an example.

[0211] In one example, the calculation circuit includes two correction submodules. The first correction submodule includes seven correction units with correction lengths of 16, 32, 48, 64, 80, 96, and 112, respectively. The second correction submodule includes 15 correction units with correction lengths from 1 to 15, respectively. After the first redundancy check code is input into the first correction submodule, it undergoes correction by the seven correction units with lengths of 16, 32, 48, 64, 80, 96, and 112, resulting in seven candidate correction results. Since 77 is between 64 and 80, the selector selects the candidate correction result corresponding to correction length 64 as the target correction result. The target parameter is then 77 - 64 = 13. The target correction result is input into the second correction submodule, undergoing correction by the seven correction units with lengths from 1 to 15, resulting in 15 candidate correction results. Since 13 is between 13 and 14, the selector selects the candidate correction result corresponding to correction length 13 as the target correction result. The target correction result is the second redundancy check code.

[0212] In another example, the calculation circuit includes three correction submodules. The first correction submodule includes three correction units with correction lengths of 32, 64, and 96 respectively. The second correction submodule includes three correction units with correction lengths of 8, 16, and 24 respectively. The third correction submodule includes seven correction units with correction lengths of 1 to 7 respectively. After the first redundancy check code is input into the first correction submodule, it undergoes correction with lengths of 32, 64, and 96 sequentially by the seven correction units, resulting in three candidate correction results. Since 77 is between 64 and 96, the selector selects the candidate correction result corresponding to correction length 64 as the target correction result. At this time, the target parameter is 77-64=13. The target correction result is input into the second correction submodule, undergoing correction with lengths of 8, 16, and 24 sequentially by the three correction units, resulting in three candidate correction results. Since 13 is between 8 and 16, the selector selects the candidate correction result corresponding to correction length 8 as the target correction result. At this time, the target parameter is 77-64-8=5. The target correction result is input into the third correction submodule, and then corrected sequentially by seven correction units with lengths from 1 to 7, resulting in seven candidate correction results. Since 5 is between 5 and 6, the selector selects the candidate correction result corresponding to correction length 5 as the target correction result. At this time, the target correction result is the second redundancy check code.

[0213] Therefore, for a data width of 128 bytes, the calculation circuit requires any one of 2 to 6 correction submodules 31. Each correction submodule 31 requires at least one correction unit 312. In this case, the calculation circuit can reduce the number of correction units and reduce the use of chip resources. At the same time, since the correction submodule 31 has fewer stages, it can output the CRC calculation result faster, making the calculation circuit more in line with the comprehensive factors such as peripheral data grading and chip resources, and the performance of the calculation circuit is better.

[0214] It should be noted that the above description uses a 128-byte data width as an example. Other data widths are similar. The correct redundancy check code can be obtained by calculating the input data containing any valid data through the computing circuit of this application embodiment.

[0215] Furthermore, the above description uses bytes as the data unit to illustrate the implementation principle of this application's embodiments. In practical applications, other data units are also applicable to this application's embodiments. For example, when the data unit is bits, CRC calculation and correction can be completed based on the implementation principle of this application's embodiments to obtain the correct redundancy check code.

[0216] In the computing circuit provided in this embodiment, if the first input data contains invalid data that cannot be used for calculation, the invalid data is replaced with mask data that can be used for calculation by a masking module to obtain the second input data. Since the second input data includes mask data, the second input data is erroneous, causing the first redundancy check code calculated by the computing module based on the second input data to be an incorrect result. Based on this, the correct second redundancy check code can be obtained by correcting the first redundancy check code by a correction module.

[0217] By replacing invalid data in the input data with mask data, the length of the input data is fixed. This allows a single calculation module to perform calculations on any input data, eliminating the need for separate calculation modules for different lengths of input data, effectively reducing chip resource consumption. Since the length of the redundancy check code is much shorter than the length of the input data, the computational load involved in correcting the redundancy check code through the correction module is less than that of using different calculation modules to calculate input data of corresponding lengths. This results in less resource consumption for the correction module, but significantly improved computational performance. Therefore, the calculation circuit of this embodiment has low resource consumption and high computational performance, enabling rapid calculation of the redundancy check code.

[0218] This application also provides a redundancy check code calculation circuit, such as... Figure 11 As shown, the computing circuit includes a processing module 40 and multiple computing modules 50, wherein each computing module 50 has a different computing length. Figure 11In the structural diagrams mentioned below, black circles are used to identify input terminals, and white circles are used to identify output terminals. For example... Figure 11 As shown, the output of the processing module 40 is connected to the input of the first calculation module 50, and the output of the previous calculation module 50 is connected to the input of the next calculation module 50.

[0219] The processing module 40 is used to transmit the first input data to the first calculation module 50 when there is invalid data in the first input data. The first input data includes initial valid data. The calculation module 50 is used to calculate the fourth input data to obtain the target calculation result.

[0220] The fourth input data includes initial valid data, or the target calculation result of the previous calculation module 50 and the remaining valid data in the initial valid data that has not been calculated. The target calculation result of the last calculation module 50 is the redundancy check code of the first input data.

[0221] As described above regarding CRC, the first input data includes one frame of data from the message. When the length of one frame of data equals the data width, the first input data does not include invalid data. When the length of one frame of data is less than the data width, the first input data includes invalid data. The data in the first input data, excluding invalid data, constitutes the initial valid data. The length of the initial valid data is less than or equal to the data width.

[0222] Assuming M is the length of the first input data and N is the length of the invalid data, the initial valid data consists of MN data units. When performing CRC calculation on the initial valid data, CRC calculation needs to be performed on MN data units to obtain a redundancy check code. Optionally, the redundancy check code can be obtained by performing the calculation on all MN data units at once using the initial value and check parameters. Alternatively, the redundancy check code can be obtained by performing the calculation on each of the MN data units sequentially using the initial value and check parameters. For example, the CRC calculation can be performed on the first data unit using the initial value and check parameters to obtain the result. The calculation result of the previous data unit is used together with the check parameters to perform the CRC calculation on the next data unit to obtain the result. The calculation result of the last data unit is the result of the initial valid data calculation.

[0223] In this example, each calculation module 50 corresponds to a different calculation length. If invalid data exists in the first input data, the processing module 40 transmits the first input data to the first calculation module 50. Since the initial valid data has not been calculated, the remaining valid data that has not been calculated is the initial valid data. The first calculation module 50 calculates the initial valid data to obtain valid data of the corresponding length, resulting in the target calculation result, where the length is 0 or a positive integer. Then, based on the initial valid data and the calculated valid data, the remaining valid data that has not been calculated is updated, and the first calculation module 50 transmits the target calculation result and the remaining valid data that has not been calculated to the second calculation module 50. The second calculation module 50 calculates the remaining valid data based on the target calculation result of the first calculation module 50 to obtain the target calculation result, where the length is 0 or a positive integer. Then, based on the initial valid data and the calculated valid data, the remaining valid data that has not been calculated is updated, and the second calculation module 50 transmits the target calculation result and the remaining valid data that has not been calculated to the third calculation module 50. The processing methods of the third calculation module 50 and subsequent calculation modules 50 are similar to those of the first calculation module 50 and the second calculation module 50, and will not be repeated here.

[0224] Following the above method, the initial valid data is calculated step by step by multiple calculation modules 50 to obtain the target calculation result of the last calculation module 50. The target calculation result is the correct redundancy check code corresponding to the initial valid data.

[0225] In one possible implementation, such as Figure 12 As shown, the processing module 40 includes a controller 41. The controller 41 is used to acquire a first control signal, determine whether there is invalid data in the input data based on the first control signal, and the first control signal is used to indicate the position of invalid data in the input data; the controller 41 is also used to transmit the first input data to the first calculation module when invalid data exists.

[0226] In this example, within one clock cycle, first input data is input to the processing module 40 of the computing circuit. The length of the first input data is the data bit width of the chip, for example, the length of the first input data is M bytes, where M is a positive integer. The first input data includes a single data step, which is the initial valid data, and the length of the initial valid data is less than or equal to M bytes. In addition, a first control signal is also input to the processing module 40. The first control signal is used to indicate the position of invalid data in the first input data. For example, if the first input data is M bytes, assuming the first control signal indicates MN, it is equivalent to the first control signal indicating that bytes 1 to N are valid data, and bytes N+1 to M are invalid data, where N is 0 or a positive integer less than M.

[0227] The processing module 40 includes a controller 41. After receiving the first control signal and the first input data, if the first control signal indicates that there is invalid data in the first input data, the controller 41 transmits the first input data to the first calculation module 50 according to the first control signal, so that each calculation module 50 can perform calculations on the first input data step by step to obtain the correct redundancy check code.

[0228] By indicating the position of invalid data in the first input data through the first control signal, it is possible to accurately determine whether there is invalid data in the first input data. In the event of invalid data, the controller 41 controls multiple calculation modules 50 to perform CRC calculation to ensure that the correct redundancy check code is obtained.

[0229] In one possible implementation, such as Figure 12 As shown, the processing module 40 further includes a first calculation submodule 42, the calculation length of which is equal to the data bit width. The controller 41 is also configured to transmit the first input data to the first calculation submodule 42 when there is no invalid data in the first input data; the first calculation submodule 42 is configured to calculate a redundancy check code based on the first input data.

[0230] After receiving the first control signal and the first input data, if the first control signal indicates that there is no invalid data in the first input data, it means that the length of the initial valid data is equal to the data bit width. In this case, the controller 41 transmits the first input data to the first calculation submodule 42 according to the first control signal, so that the first calculation submodule 42 can calculate the first input data to obtain the correct redundancy check code. The calculation method will not be described in detail here.

[0231] For example, when the data width is M bytes, the length of the first input data is M bytes. The first calculation submodule 42 used to perform CRC calculation on the M bytes of data is called the M-byte first calculation submodule 42. If there is no invalid data in the first input data, the controller 41 transmits the first input data to the first calculation submodule 42, and the M-byte first calculation submodule 42 is used to perform CRC calculation on the first input data to obtain the redundancy check code.

[0232] Understandably, when a message includes multiple data frames, generally, if the first input data includes non-tail data, it does not include invalid data; if the first input data includes tail data, it may or may not include invalid data. For example, with a data width of 128 bytes, for a 257-byte message, the first two data frames are both 128 bytes, and the tail data is 1 byte. In this case, if the first input data includes tail data, there are 127 bytes of invalid data. Since the calculation result of the previous data frame is used to calculate the next data frame, therefore, if... Figure 12 As shown, the redundancy check code of the non-tail data determined by the first calculation submodule 42 is a correct redundancy check code. This redundancy check code can be input into the first calculation submodule 42 so that the first calculation submodule 42 can perform CRC calculation on the next data based on the redundancy check code.

[0233] By indicating the position of invalid data in the first input data through the first control signal, it is possible to accurately determine whether there is invalid data in the first input data. In the case that there is no invalid data, the controller 41 controls the first calculation submodule 42 to perform CRC calculation to ensure that the correct redundancy check code is obtained.

[0234] Optionally, such as Figure 12 or Figure 13 As shown, each calculation module 50 includes a selector 51 and at least one second calculation submodule 52, each second calculation submodule 52 corresponding to a different calculation length. The second calculation submodule 52 is used to perform calculations of the corresponding length on the fourth input data, obtain candidate calculation results, and transmit the candidate calculation results to the selector 51; the selector 51 is used to select the target calculation result from the fourth input data and each candidate calculation result.

[0235] In this embodiment, the same calculation module 50 includes second calculation sub-modules 52 with different calculation lengths. The fourth input data can be input into any of the second calculation sub-modules 52, which then performs calculations on the fourth input data to obtain data of the corresponding length, resulting in candidate calculation results, which are then transmitted to the selector 51. Furthermore, the processing module 40 or the previous calculation module 50 transmits the fourth input data to the selector 51, which selects either the fourth input data or a candidate calculation result from the input, using the selected data as the target calculation result.

[0236] Optionally, such as Figure 12 or Figure 13As shown, selector 51 is used to acquire a second control signal and select a target calculation result from the fourth input data and various candidate calculation results according to the second control signal. The second control signal is used to indicate the calculation length corresponding to the target calculation result. For example, if the second control signal indicates 0, it means that the calculation length is 0, then selector 51 selects the fourth input data as the target calculation result. As another example, if the second control signal indicates 7, it means that the calculation length is 7, then selector 51 selects the candidate calculation result obtained after calculating the data of length 7 in the fourth input data as the target calculation result.

[0237] By setting a second calculation submodule 52 with different calculation lengths, CRC calculations are implemented for data of different lengths. The selector 51 selects either the data before calculation or the calculation result of arbitrary length, allowing the calculation module 50 to either not calculate the fourth input data or perform calculations on the fourth input data of arbitrary length. This facilitates the combination of calculation lengths of each calculation module 50, enabling the calculation of correct redundancy check codes from initial valid data of different lengths, thus improving the practicality of the calculation circuit.

[0238] In an exemplary embodiment, such as Figure 12 or Figure 13 As shown, each calculation module 50 also includes a register 53. It should be noted that in practical applications, the calculation module 50 may not include register 53, and register 53 will not affect the function of the calculation circuit. Register 53 is used to store the fourth input data; the second calculation submodule 52 is also used to read the fourth input data from register 53; the selector 51 is also used to read the fourth input data from register 53.

[0239] In this embodiment, the processing module 40 or the previous calculation module 50 transfers the fourth input data to the register 53 in the next calculation module 50, so that the register 53 stores the fourth input data. By storing the fourth input data, the possibility of data loss can be reduced, so that the second calculation submodule 52 and the selector 51 can read the fourth input data and complete the calculation of the valid data.

[0240] As mentioned above, the computing module 50 includes at least one second computing submodule 52. In this regard, embodiments of this application provide a computing module 50 as shown in implementations D to E below.

[0241] In implementation method D, the first input data consists of M data units, the initial valid data consists of T data units, the number of calculation modules is log2M, and the i-th calculation module includes a second calculation submodule with a calculation length of 2. b M is greater than T, and b is an integer.

[0242] The selector for the i-th calculation module is used when the specified parameter is less than 2. b In this case, select the fourth input data as the target calculation result, provided the specified parameter is not less than 2. b In this case, select the candidate calculation result as the target calculation result, and specify the parameter as T or the difference between T and the calculated length.

[0243] like Figure 12 As shown, the computing circuit includes multiple computing modules 50. For a data width of M bytes, a maximum of log2M computing modules 50 can be used. For example, for a data width of 128 bytes, a maximum of log2128 = 7 computing modules 50 can be used. In this case, each computing module 50 includes only one second computing submodule 52. Since the computing circuit uses the fewest possible second computing submodules 52, the chip resources used by the computing circuit are also minimized.

[0244] Let i take any integer from 1 to log2M, where log2M is an integer. In this case, the second calculation submodule 52 in the i-th calculation module 50 corresponds to 2. b The correction length is b = log2M - i. For example, when log2128 = 7, the second calculation submodule 52 in the first calculation module 50 corresponds to 2. (7-1) = 64 calculation length, the second calculation submodule 52 in the second calculation module 50 corresponds to 2 (7-2) =32 calculation length, the second calculation submodule 52 in the third calculation module 50 corresponds to 2 (7-3) =16 calculation length, the second calculation submodule 52 in the fourth calculation module 50 corresponds to 2 (7-4) =8 calculation length, the second calculation submodule 52 in the 5th calculation module 50 corresponds to 2 (7-5) =4 is the computation length, and the second computation submodule 52 in the 6th computation module 50 corresponds to 2. (7-6) =2 is the calculation length, and the second calculation submodule 52 in the 7th calculation module 50 corresponds to 2. (7-7) The calculation length is 1. In Figure 12 In this context, the second computational submodule 52 with a computation length of j is called a j-byte second computational submodule. For example, a 1-byte second computational submodule corresponds to a computation length of 1.

[0245] In this example, M bytes of first input data are input to the computing circuit. If the first input data does not contain invalid data, the controller 41 transmits the first input data to the first computing submodule 42. The first computing submodule 42 performs an M-byte CRC calculation on the first input data to obtain a redundancy check code, and transmits the redundancy check code to the first computing module 50. Since the remaining valid data that has not been calculated is 0, the selector 51 in the first computing module 50 selects the redundancy check code. Similarly, the selectors 51 in subsequent computing modules 50 will only select the redundancy check code.

[0246] If the first input data of M bytes includes N bytes of invalid data and T bytes of initial valid data, then the controller 41 transmits the first input data to the first calculation module 50. The second calculation submodule 52 in the first calculation module 50 processes the first input data into a process of length M. The calculation yields candidate results. Since the first input data to the first calculation module 50 has not been processed, the specified parameter is the length of the initial valid data, i.e., the specified parameter is T. If the specified parameter is less than... Then, selector 51 in the first calculation module 50 selects the initial valid data as the target calculation result. At this time, the calculated length is 0, and the specified parameter is still T. If the specified parameter is greater than or equal to... Then, selector 51 in the first calculation module 50 selects the candidate calculation result as the target calculation result. At this time, the calculated length is... The specified parameter is Selector 51 transmits the target calculation result to the second calculation module 50.

[0247] The second calculation submodule 52 in the second calculation module 50 performs the target calculation results of the first calculation module 50. The length is calculated, yielding candidate results. At this point, the specified parameter is T or... If the specified parameter is less than Then, selector 51 in the second calculation module 50 selects the target calculation result of the first calculation module 50 as the target calculation result. At this time, the calculated length remains unchanged, and the specified parameter is T or If the specified parameter is greater than or equal to Then, selector 51 in the second calculation module 50 selects the candidate calculation result as the target calculation result. At this time, the calculated length increases. Selector 51 transmits the target calculation result to the third calculation module 50.

[0248] This process continues until the target calculation result of the last calculation module 50 is obtained, which is a redundancy check code. The implementation principle of this embodiment is explained below using M=128 and T=77 as an example. The calculation lengths corresponding to the second calculation sub-modules 52 in each calculation module 50 have been described above and will not be repeated here.

[0249] In this example, the second calculation submodule 52 in the first calculation module 50 corresponds to a calculation length of 64. Since 77 is greater than 64, the selector 51 selects the candidate calculation result as the target calculation result, and the specified parameter is 77-64=13. The second calculation submodule 52 in the second calculation module 50 corresponds to a calculation length of 32. Since 13 is less than 32, the selector 51 selects the input target calculation result, and the specified parameter is still 13. The second calculation submodule 52 in the third calculation module 50 corresponds to a calculation length of 16. Since 13 is less than 16, the selector 51 selects the input target calculation result, and the specified parameter is still 13. The second calculation submodule 52 in the fourth calculation module 50 corresponds to a calculation length of 8. Since 13 is greater than 8, the selector 51 selects the target calculation result. Selector 51 selects a candidate calculation result as the target calculation result, and the specified parameter is 13-8=5. The second calculation submodule 52 in the fifth calculation module 50 corresponds to a calculation length of 4. Since 5 is greater than 4, selector 51 selects a candidate calculation result as the target calculation result, and the specified parameter is 5-4=1. The second calculation submodule 52 in the sixth calculation module 50 corresponds to a calculation length of 2. Since 1 is less than 2, selector 51 selects the input target calculation result, and the specified parameter is still 1. The second calculation submodule 52 in the seventh calculation module 50 corresponds to a calculation length of 1. Since 1 equals 1, selector 51 selects a candidate calculation result as the target calculation result, and the specified parameter is 1-1=0. The target calculation result is a correct redundancy check code.

[0250] Therefore, for a data width of 128 bytes, the computing circuit only requires 7 levels of computing modules 50, and each computing module 50 requires only one second computing submodule 52. This minimizes the resources used by the computing circuit. In other words, by using multiple levels of computing modules 50, the number of second computing submodules can be greatly reduced, thus reducing the use of chip resources.

[0251] For a data width of 128 bytes, the calculation circuit includes a first calculation submodule 42 of 128 bytes for calculating 128 bytes of valid data. The calculation circuit also includes seven second calculation submodules 52, which perform calculations for lengths of 64, 32, 16, 8, 4, 2, and 1 bytes respectively. Through these seven second calculation submodules 52, valid data from 1 to 127 bytes can be calculated. Based on this, the correct redundancy check code can be obtained for any input data using the calculation circuit of this embodiment. Other data widths are similar; the correct redundancy check code can be obtained by calculating input data containing any valid data using the calculation circuit of this embodiment.

[0252] In implementation method E, the first input data consists of M data units, the initial valid data consists of T data units, and there are L calculation modules. The i-th calculation module includes 2... a -1 second computation submodules, the computation length of the j-th second computation submodule is j×2. b M is greater than T, L is less than log2M, and a and b are both integers.

[0253] The selector for the i-th calculation module is used when the specified parameter is less than 2. b In the case of selecting the fourth input data as the target calculation result, and with the specified parameter not less than (2 a -1)×2 b In this case, choose option 2. a -1 The candidate calculation results of the second calculation submodule are the target calculation results, provided that the specified parameters are not less than k×2. b And less than (k+1)×2 b In this case, the candidate calculation result of the k-th second calculation submodule is selected as the target calculation result, and the specified parameter is T or the difference between T and the calculated length, where k takes the value 1 to 2. a Integers in -2.

[0254] like Figure 13 As shown, the computing circuit includes multiple computing modules 50. For a data width of M bytes, a maximum of log₂M computing modules 50 can be used. In this example, there are L computing modules 50, where L is an integer greater than 1 and less than log₂M. For example, for a data width of 128 bytes, a maximum of log₂¹²⁸ = 7 computing modules 50 can be used. In practical applications, 2, 3, 4, 5, or 6 computing modules 50 can be used. In this case, each computing module 50 includes at least one second computing submodule 52. Because the computing circuit uses fewer computing modules 50 and fewer second computing submodules 52, the computing circuit uses fewer chip resources and has higher output efficiency.

[0255] Let i take any integer value from 1 to L. In this case, the i-th calculation module 50 includes 2 a -1 second calculation submodule 52, where a is a positive integer, meaning a can take the value 1, 2, 3, or 4, etc. In practical applications, every two calculation modules 50 can correspond to the same or different a, and thus can correspond to the same or different second calculation submodules 52. Let j take the value 1 to 2. a For any integer in -1, in this case, the j-th second calculation submodule 52 corresponds to j×2. b The calculated length, in,

[0256] For example, when log2128 = 7, assuming L = 2, then the first calculation module 50 can include 2. 3 -1 = 7 second calculation submodules 52, b = 7 - 3 = 4, the 1st to 7th second calculation submodules 52 correspond to 2 respectively. 4 =16, 2×2 4 =32, 3×2 4 =48, 4×2 4 =64, 5×2 4 =80, 6×2 4 =96, 7×2 4 =112 calculation length. The second calculation module 50 can include 2 4 -1 = 15 second calculation submodules 52, b = 7 - 3 - 4 = 0, the 1st to 15th second calculation submodules 52 correspond to 2 respectively. 0 =1, 2×2 0 =2, 3×2 0 =3, 4×2 0 =4, 5×2 0 =5, 6 × 2 0 =6, 7 × 2 0 =7, 8 × 2 0 =8, 9 × 2 0 =9, 10×2 0 =10, 11 × 2 0 =11, 12 × 2 0 =12, 13 × 2 0 =13, 14 × 2 0 =14, 15 × 2 0 =15 is the calculation length.

[0257] For example, when log2128 = 7, assuming L = 3, then the first calculation module 50 can include 2 2 -1 = 3 second calculation submodules 52, b = 7 - 2 = 5, the first to third second calculation submodules 52 correspond to 2 respectively. 5 =32, 2×25 =64, 3×2 5 = 96 calculation length. The second calculation module 50 can include 2 2 -1 = 3 second calculation submodules 52, b = 7 - 2 - 2 = 3, the first to third second calculation submodules 52 correspond to 2 respectively. 3 =8, 2×2 3 =16, 3×2 3 =24 calculation length. The third calculation module 50 can include 2 3 -1 = 7 second calculation sub-modules 52, b = 7-2-2-3 = 0, the first to seventh second calculation sub-modules 52 correspond to the calculation lengths of 1 to 7 respectively.

[0258] In this example, M bytes of first input data are input to the computing circuit. If the first input data does not contain invalid data, the controller 41 transmits the first input data to the first computing submodule 42. The first computing submodule 42 performs an M-byte CRC calculation on the first input data to obtain a redundancy check code, and transmits the redundancy check code to the first computing module 50. Since the remaining valid data that has not been calculated is 0, the selector 51 in the first computing module 50 selects the redundancy check code. Similarly, the selectors 51 in subsequent computing modules 50 will only select the redundancy check code.

[0259] If the first input data of M bytes includes N bytes of invalid data and T bytes of initial valid data, then the controller 41 transmits the first input data to the first calculation module 50. The second calculation submodule 52 in the first calculation module 50 performs j×2 operations on the initial valid data. b The length is calculated to obtain candidate calculation results. At this point, since the initial valid data input to the first calculation module 50 has not been calculated, the specified parameter is the length of the initial valid data, i.e., the specified parameter is T. If the specified parameter is less than 2... b Then, selector 51 in the first calculation module 50 selects the initial valid data as the target calculation result. At this time, the calculated length is 0, and the specified parameter is T. If the specified parameter is greater than or equal to (2 a -1)×2 b Then selector 51 in the first calculation module 50 selects the (2)th... a -1) candidate calculation results are used as the target calculation result. At this time, the calculated length is (2 a -1)×2 b The specified parameter is T-(2) a -1)×2 b If the specified parameter is greater than or equal to k×2 b And less than (k+1)×2 bThen, selector 51 in the first calculation module 50 selects the k-th candidate calculation result as the target calculation result. At this time, the calculated length is k×2. b The specified parameter is Tk×2 b k takes values ​​from 1 to 2 a Any integer in -2. Selector 51 transmits the target calculation result to the second calculation module 50.

[0260] The subsequent calculation modules operate on a similar principle to the first calculation module, and will not be repeated here. Each calculation module performs calculations sequentially, ultimately yielding the target calculation result of the last module, which is a redundancy check code. The implementation principle of this application's embodiment is explained below using M=128 and T=77 as an example.

[0261] In one example, the calculation circuit includes two calculation modules. The first calculation module includes seven second calculation sub-modules with calculation lengths of 16, 32, 48, 64, 80, 96, and 112, respectively. The second calculation module includes 15 second calculation sub-modules with calculation lengths of 1 to 15, respectively. After initial valid data is input into the first calculation module, the seven second calculation sub-modules perform calculations of lengths 16, 32, 48, 64, 80, 96, and 112, resulting in seven candidate calculation results. Since 77 falls between 64 and 80, the selector selects the candidate calculation result corresponding to a calculation length of 64 as the target calculation result. In this case, the specified parameter is 77 - 64 = 13. The target calculation result and the remaining valid data are input into the second calculation module. The seven second calculation sub-modules perform calculations of lengths 1 to 15, resulting in 15 candidate calculation results. Since 13 falls between 13 and 14, the selector selects the candidate calculation result corresponding to a calculation length of 13 as the target calculation result. In this case, the target calculation result is a redundancy check code.

[0262] Therefore, for a data width of 128 bytes, the calculation circuit requires any of 2 to 6 calculation modules 50. Each calculation module 50 requires at least one second calculation submodule 52. In this way, the calculation circuit can reduce the number of second calculation submodules and reduce the use of chip resources. At the same time, since the number of calculation modules is smaller, the CRC calculation result can be output faster, making the calculation circuit more in line with the comprehensive factors such as peripheral data stamping and chip resources, and the performance of the calculation circuit is better.

[0263] It should be noted that the above description uses a 128-byte data width as an example. Other data widths are similar. The correct redundancy check code can be obtained by calculating the input data containing any valid data through the computing circuit of this application embodiment.

[0264] Furthermore, the above description uses bytes as the data unit to illustrate the implementation principle of this application's embodiments. In practical applications, other data units are also applicable to this application's embodiments. For example, when the data unit is bits, CRC calculation can be completed based on the implementation principle of this application's embodiments to obtain the correct redundancy check code.

[0265] In the computing circuit provided in this application embodiment, since the computing lengths of each computing module are different, when invalid data exists in the first input data, multiple computing modules gradually perform various computing length calculations on the initial valid data. This achieves combined calculations of various computing lengths on input data containing invalid data, resulting in a correct redundancy check code. By combining the computing lengths of each computing module, the number of series or parallel circuits is reduced, chip resource consumption is reduced, and the performance of the computing circuit is improved.

[0266] This application also provides a method for calculating a redundancy check code, which can be applied to the aforementioned computer system, such as... Figure 14 As shown, this method can be derived from, for example... Figure 2 The computational circuit shown is used to execute the method, which includes the following steps.

[0267] Step 1401: If invalid data exists in the first input data, the invalid data is replaced with mask data by the mask module to obtain the second input data.

[0268] Step 1402: The calculation module calculates the first redundancy check code based on the second input data.

[0269] Step 1403: Correct the first redundancy check code using the correction module to obtain the second redundancy check code.

[0270] In one possible implementation, the method further includes: obtaining a first control signal through a mask module, determining invalid data from the first input data based on the first control signal, wherein the first control signal is used to indicate the position of the invalid data in the first input data.

[0271] In one possible implementation, the correction module includes at least one correction submodule; step 1403 includes: correcting the third input data through the correction submodule to obtain a target correction result, wherein the third input data is a first redundancy check code or the target correction result of the previous correction submodule; wherein the target correction result of the last correction submodule is a second redundancy check code.

[0272] In one possible implementation, the correction submodule includes a selector and at least one correction unit, each correction unit corresponding to a different correction length; the correction of the third input data by the correction submodule to obtain the target correction result includes: performing correction of the third input data of the corresponding length by the correction unit to obtain candidate correction results, transmitting the candidate correction results to the selector; and selecting the target correction result from the third input data and each candidate correction result by the selector.

[0273] In one possible implementation, the correction submodule further includes a register; the method also includes: storing third input data in the register; reading the third input data from the register through the correction unit; and reading the third input data from the register through a selector.

[0274] In one possible implementation, the first input data consists of M data units, the invalid data consists of N data units, there is one correction submodule, there are M-1 correction units, the correction length of the j-th correction unit is j, and M is greater than N.

[0275] The selector selects the target correction result from the third input data and each candidate correction result, including: selecting the third input data as the target correction result when N is 0, and selecting the target correction result with a correction length of N from each candidate correction result when N is not 0.

[0276] In one possible implementation, the first input data consists of M data units, the invalid data consists of N data units, the number of correction submodules is log2M, and the i-th correction submodule includes a correction unit with a correction length of 2. b M is greater than N, and b is an integer.

[0277] The target correction result is selected from the third input data and various candidate correction results using a selector, including: selecting the target correction result from the selector of the i-th correction submodule when the target parameter is less than 2. b In the case of selecting the third input data as the target correction result, with the target parameter not less than 2... b In this case, the candidate correction result is selected as the target correction result, and the target parameter is N or the difference between N and the corrected length.

[0278] In one possible implementation, the first input data consists of M data units, the invalid data consists of N data units, and there are L correction submodules, with the i-th correction submodule comprising 2... a -1 correction units, the correction length of the j-th correction unit is j×2. b M is greater than N, L is less than log2M, and a and b are both integers.

[0279] The target correction result is selected from the third input data and various candidate correction results using a selector, including: selecting the target correction result from the selector of the i-th correction submodule when the target parameter is less than 2. b In the case of selecting the third input data as the target correction result, the target parameter is not less than (2 a -1)×2 b In this case, choose option 2. a The candidate correction results of -1 correction units are the target correction results, where the target parameter is not less than k×2. b And less than (k+1)×2 b In this case, the candidate correction result of the k-th correction unit is selected as the target correction result, and the target parameter is N or the difference between N and the corrected length, where k takes the value 1 to 2. a Integers in -2.

[0280] In one possible implementation, step 1402 includes: calculating a first redundancy check code by a calculation module based on the second input data and the check parameters.

[0281] Step 1403 includes: obtaining a second redundancy check code by correcting the first redundancy check code according to the correction parameters through the correction module, wherein the correction parameters are calculated based on the check parameters.

[0282] It should be noted that the implementation principle of the embodiments in this application is the same as... Figures 2 to 10 The implementation principles of the related embodiments are similar, and will not be repeated here.

[0283] In the above method, if the first input data contains invalid data that cannot be used for calculation, the invalid data is replaced with mask data that can be used for calculation by the masking module to obtain the second input data. Since the second input data includes mask data, the second input data is erroneous, causing the first redundancy check code calculated by the calculation module based on the second input data to be an incorrect result. Based on this, the correct second redundancy check code can be obtained by correcting the first redundancy check code by the correction module.

[0284] By replacing invalid data in the input data with mask data, the length of the input data is fixed. This allows a single calculation module to perform calculations on any input data, eliminating the need for separate calculation modules for different input data lengths, effectively reducing chip resource consumption. Since the length of the redundancy check code is much shorter than the length of the input data, the computational load involved in correcting the redundancy check code through the correction module is less than that of using different calculation modules to calculate input data of corresponding lengths. This results in less resource consumption for the correction module, but significantly improved computational performance. Therefore, the calculation circuit involved in this embodiment has low resource consumption and high computational performance, enabling rapid calculation of the redundancy check code.

[0285] This application also provides a method for calculating a redundancy check code, which can be applied to the aforementioned computer system, such as... Figure 15 As shown, the method is as follows Figure 11 The computational circuit shown is used to execute the method, which includes the following steps.

[0286] Step 1501: If invalid data exists in the first input data, the processing module transmits the first input data to the first calculation module among multiple calculation modules. The calculation lengths of each calculation module are different, and the first input data includes initial valid data.

[0287] Step 1502: Calculate the fourth input data using the calculation module to obtain the target calculation result.

[0288] The fourth input data includes initial valid data, or the target calculation result of the previous calculation module and the remaining valid data in the initial valid data that has not been calculated. The target calculation result of the last calculation module is the redundancy check code of the first input data.

[0289] In one possible implementation, the processing module includes a controller; step 1501 includes: acquiring a first control signal through the controller, determining whether there is invalid data in the input data based on the first control signal, the first control signal being used to indicate the position of invalid data in the input data; and transmitting the first input data to the first calculation module through the controller if invalid data exists.

[0290] In one possible implementation, the processing module further includes a first calculation submodule; the method further includes: transmitting the first input data to the first calculation submodule via the controller if there is no invalid data in the first input data; and calculating a redundancy check code by the first calculation submodule based on the first input data.

[0291] In one possible implementation, any computation module includes a selector and at least one second computation submodule, each second computation submodule corresponding to a different computation length.

[0292] Step 1502 includes: performing a calculation of the corresponding length on the fourth input data through the second calculation submodule to obtain candidate calculation results, and transmitting the candidate calculation results to the selector; and selecting the target calculation result from the fourth input data and each candidate calculation result through the selector.

[0293] In one possible implementation, the computation module further includes a register; the method further includes: storing fourth input data in the register; reading the fourth input data from the register through the second computation submodule; and reading the fourth input data from the register through a selector.

[0294] In one possible implementation, the first input data consists of M data units, the initial valid data consists of T data units, the number of calculation modules is log2M, and the i-th calculation module includes a second calculation submodule with a calculation length of 2. b M is greater than T, and b is an integer.

[0295] The target computation result is selected from the fourth input data and various candidate computation results using a selector, including: using the selector of the i-th computation module, when the specified parameter is less than 2. b In this case, select the fourth input data as the target calculation result, provided the specified parameter is not less than 2. b In this case, select the candidate calculation result as the target calculation result, and specify the parameter as T or the difference between T and the calculated length.

[0296] In one possible implementation, the first input data consists of M data units, the initial valid data consists of T data units, and there are L calculation modules, with the i-th calculation module comprising 2... a -1 second computation submodules, the computation length of the j-th second computation submodule is j×2. b M is greater than T, L is less than log2M, and a and b are both integers.

[0297] The target computation result is selected from the fourth input data and various candidate computation results using a selector, including: using the selector of the i-th computation module, when the specified parameter is less than 2. b In the case of selecting the fourth input data as the target calculation result, and with the specified parameter not less than (2 a -1)×2 b In this case, choose option 2. a -1 The candidate calculation results of the second calculation submodule are the target calculation results, provided that the specified parameters are not less than k×2. b And less than (k+1)×2 b In this case, the candidate calculation result of the k-th second calculation submodule is selected as the target calculation result, and the specified parameter is T or the difference between T and the calculated length, where k takes the value 1 to 2. a Integers in -2.

[0298] It should be noted that the implementation principle of the embodiments in this application is the same as... Figures 11 to 13 The implementation principles of the related embodiments are similar, and will not be repeated here.

[0299] In the above method, since the calculation lengths of each calculation module are different, when invalid data exists in the first input data, multiple calculation modules gradually perform calculations of various lengths on the initial valid data. This achieves combined calculations of various lengths on input data containing invalid data, resulting in the correct redundancy check code. By combining the calculation lengths of each calculation module, the number of series or parallel circuits is reduced, chip resource consumption is reduced, and the performance of the computing circuit is improved.

[0300] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in the above optional embodiments are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant regions. For example, the first input data involved in this application were all obtained with full authorization.

[0301] Figure 16 A structural block diagram of a terminal device 1600 provided in an exemplary embodiment of this application is shown. The terminal device 1600 includes a processor 1601 and a memory 1602.

[0302] Processor 1601 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1601 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1601 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1601 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1601 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0303] The memory 1602 may include one or more computer-readable storage media, which may be non-transitory. The memory 1602 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1602 are used to store at least one computer program, which is executed by the processor 1601 to implement the redundancy check code calculation method provided in the method embodiments of this application.

[0304] In some embodiments, the terminal device 1600 may optionally include a peripheral device interface 1603 and at least one peripheral device. The processor 1601, memory 1602, and peripheral device interface 1603 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1603 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: radio frequency circuitry 1604, display screen 1605, camera assembly 1606, audio circuitry 1607, and power supply 1608.

[0305] Peripheral interface 1603 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1601 and memory 1602. In some embodiments, processor 1601, memory 1602 and peripheral interface 1603 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1601, memory 1602 and peripheral interface 1603 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0306] The radio frequency (RF) circuit 1604 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1604 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1604 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1604 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 1604 can communicate with other terminals through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1604 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0307] Display screen 1605 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1605 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1601 for processing. In this case, display screen 1605 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1605, disposed on the front panel of terminal device 1600; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal device 1600 or in a folded design; in still other embodiments, display screen 1605 may be a flexible display screen, disposed on a curved or folded surface of terminal device 1600. Furthermore, display screen 1605 may also be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1605 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0308] The camera assembly 1606 is used to acquire images or videos. Optionally, the camera assembly 1606 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1606 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0309] The audio circuit 1607 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1601 for processing, or input to the radio frequency circuit 1604 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each located at a different part of the terminal device 1600. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1601 or the radio frequency circuit 1604 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1607 may also include a headphone jack.

[0310] Power supply 1608 is used to power the various components in terminal device 1600. Power supply 1608 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1608 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, and a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0311] In some embodiments, the terminal device 1600 further includes one or more sensors 1609. The one or more sensors 1609 include, but are not limited to: an accelerometer 1611, a gyroscope 1612, a pressure sensor 1613, an optical sensor 1614, and a proximity sensor 1615.

[0312] Accelerometer 1611 can detect the magnitude of acceleration along the three coordinate axes of a coordinate system established by terminal device 1600. For example, accelerometer 1611 can be used to detect the components of gravitational acceleration along the three coordinate axes. Processor 1601 can control display screen 1605 to display the user interface in either a landscape or portrait view based on the gravitational acceleration signal acquired by accelerometer 1611. Accelerometer 1611 can also be used for games or for acquiring user motion data.

[0313] The gyroscope sensor 1612 can detect the orientation and rotation angle of the terminal device 1600. The gyroscope sensor 1612 can work in conjunction with the accelerometer sensor 1611 to acquire the user's 3D movements on the terminal device 1600. Based on the data acquired by the gyroscope sensor 1612, the processor 1601 can perform the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0314] The pressure sensor 1613 can be disposed on the side bezel of the terminal device 1600 and / or on the lower layer of the display screen 1605. When the pressure sensor 1613 is disposed on the side bezel of the terminal device 1600, it can detect the user's grip signal on the terminal device 1600, and the processor 1601 can perform left / right hand recognition or quick operation based on the grip signal collected by the pressure sensor 1613. When the pressure sensor 1613 is disposed on the lower layer of the display screen 1605, the processor 1601 can control the operable controls on the UI interface based on the user's pressure operation on the display screen 1605. The operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0315] Optical sensor 1614 is used to collect ambient light intensity. In one embodiment, processor 1601 can control the display brightness of display screen 1605 based on the ambient light intensity collected by optical sensor 1614. Specifically, when the ambient light intensity is high, the display brightness of display screen 1605 is increased; when the ambient light intensity is low, the display brightness of display screen 1605 is decreased. In another embodiment, processor 1601 can also dynamically adjust the shooting parameters of camera assembly 1606 based on the ambient light intensity collected by optical sensor 1614.

[0316] The proximity sensor 1615, also known as a distance sensor, is typically located on the front panel of the terminal device 1600. The proximity sensor 1615 is used to detect the distance between the user and the front of the terminal device 1600. In one embodiment, when the proximity sensor 1615 detects that the distance between the user and the front of the terminal device 1600 is gradually decreasing, the processor 1601 controls the display screen 1605 to switch from a screen-on state to a screen-off state; when the proximity sensor 1615 detects that the distance between the user and the front of the terminal device 1600 is gradually increasing, the processor 1601 controls the display screen 1605 to switch from a screen-off state to a screen-on state.

[0317] Those skilled in the art will understand that Figure 16 The structure shown does not constitute a limitation on the terminal device 1600, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0318] Figure 17 This is a schematic diagram of the server structure provided in the embodiments of this application. The server 1700 can vary considerably due to different configurations or performance. It may include one or more processors 1701 and one or more memories 1702. The one or more memories 1702 store at least one computer program, which is loaded and executed by the one or more processors 1701 to implement the redundancy check code calculation method provided in the above-described method embodiments. For example, the processor 1701 is a CPU. Of course, the server 1700 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server 1700 may also include other components for implementing device functions, which will not be elaborated here.

[0319] In an exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer program, which is loaded and executed by a processor to enable an electronic device to implement any of the above-described methods for calculating redundancy check codes.

[0320] Optionally, the aforementioned computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0321] In an exemplary embodiment, a computer program is also provided, which is at least one such computer program, loaded and executed by a processor, to enable the electronic device to implement any of the above-described methods for calculating redundancy check codes.

[0322] In an exemplary embodiment, a computer program product is also provided, which stores at least one computer program that is loaded and executed by a processor to enable an electronic device to implement any of the above-described methods for calculating redundancy check codes.

[0323] In an exemplary embodiment, a chip is also provided, the chip including a redundancy check code calculation circuit as shown above, for executing the corresponding redundancy check code calculation method. This application embodiment does not limit the type of chip; exemplarily, the chip includes at least one of a smart network interface card, FPGA, ASIC, or ALM (Adaptive Logic Module).

[0324] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0325] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0326] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A redundancy check code calculation circuit, characterized in that, The computing circuit includes a mask module, a computing module, and a correction module; The masking module is used to replace invalid data with masking data when invalid data exists in the first input data to obtain second input data, and then transmit the second input data to the calculation module. The calculation module is used to calculate a first redundancy check code based on the second input data and transmit the first redundancy check code to the correction module. The correction module is used to correct the first redundancy check code to obtain the second redundancy check code.

2. The computing circuit according to claim 1, characterized in that, The masking module is further configured to acquire a first control signal, and determine the invalid data from the first input data based on the first control signal, wherein the first control signal is used to indicate the position of the invalid data in the first input data.

3. The computing circuit according to claim 1 or 2, characterized in that, The correction module includes at least one correction sub-module; The correction submodule is used to correct the third input data to obtain the target correction result. The third input data is the first redundancy check code or the target correction result of the previous correction submodule. The target correction result of the last correction submodule is the second redundancy check code.

4. The computing circuit according to claim 3, characterized in that, The correction submodule includes a selector and at least one correction unit, each correction unit corresponding to a different correction length; The correction unit is used to perform correction on the third input data of a corresponding length, obtain a candidate correction result, and transmit the candidate correction result to the selector; The selector is used to select the target correction result from the third input data and the various candidate correction results.

5. The computing circuit according to claim 4, characterized in that, The correction submodule also includes a register; The register is used to store the third input data; The correction unit is also configured to read the third input data from the register; The selector is also used to read the third input data from the register.

6. The computing circuit according to claim 4, characterized in that, The first input data consists of M data units, the invalid data consists of N data units, the correction submodule is one, the correction unit is M-1, the correction length of the j-th correction unit is j, and M is greater than N; The selector is used to select the third input data as the target correction result when N is 0, and to select the target correction result with a correction length of N from the candidate correction results when N is not 0.

7. The computing circuit according to claim 4, characterized in that, The first input data consists of M data units, the invalid data consists of N data units, the correction submodules are log2M in number, and the i-th correction submodule includes a correction unit with a correction length of 2. b M is greater than N, and b is an integer; The selector of the i-th correction submodule is used when the target parameter is less than 2. b In the case where the third input data is selected as the target correction result, and the target parameter is not less than 2... b In the case of N, the candidate correction result is selected as the target correction result, and the target parameter is N or the difference between N and the corrected length.

8. The computing circuit according to claim 4, characterized in that, The first input data consists of M data units, the invalid data consists of N data units, and there are L correction submodules, with the i-th correction submodule comprising 2... a -1 correction units, the correction length of the j-th correction unit is j×2. b M is greater than N, L is less than log2M, and a and b are both integers; The selector of the i-th correction submodule is used when the target parameter is less than 2. b In the case where the third input data is selected as the target correction result, and the target parameter is not less than (2 a -1)×2 b In this case, choose option 2. a The candidate correction results of -1 correction units are the target correction results, where the target parameter is not less than k×2. b And less than (k+1)×2 b In the case where the candidate correction result of the k-th correction unit is selected as the target correction result, the target parameter is N or the difference between N and the corrected length, and k takes the value 1 to 2. a Integers in -2.

9. The computing circuit according to claim 1 or 2, characterized in that, The calculation module is used to calculate the first redundant check code based on the second input data and the check parameters. The correction module is used to correct the first redundancy check code according to the correction parameters to obtain the second redundancy check code, wherein the correction parameters are calculated based on the check parameters.

10. A redundancy check code calculation circuit, characterized in that, The computing circuit includes a processing module and multiple computing modules, each with a different computing length. The processing module is used to transmit the first input data to the first calculation module when there is invalid data in the first input data, wherein the first input data includes initial valid data. The calculation module is used to calculate the fourth input data and obtain the target calculation result; The fourth input data includes the initial valid data, or the target calculation result of the previous calculation module and the remaining valid data in the initial valid data that has not been calculated. The target calculation result of the last calculation module is the redundancy check code of the first input data.

11. The computing circuit according to claim 10, characterized in that, The processing module includes a controller; The controller is configured to acquire a first control signal and determine whether the invalid data exists in the input data based on the first control signal, wherein the first control signal is configured to indicate the position of the invalid data in the input data; The controller is also configured to transmit the first input data to the first computing module in the event of the presence of invalid data.

12. The computing circuit according to claim 11, characterized in that, The processing module further includes a first calculation submodule; The controller is further configured to transmit the first input data to the first calculation submodule when the invalid data is not present in the first input data. The first calculation submodule is used to calculate the redundancy check code based on the first input data.

13. The computing circuit according to any one of claims 10 to 12, characterized in that, Each of the calculation modules includes a selector and at least one second calculation sub-module, and each second calculation sub-module corresponds to a different calculation length; The second calculation submodule is used to perform a calculation of the corresponding length on the fourth input data, obtain a candidate calculation result, and transmit the candidate calculation result to the selector; The selector is used to select the target calculation result from the fourth input data and each candidate calculation result.

14. The computing circuit according to claim 13, characterized in that, The computing module also includes registers; The register is used to store the fourth input data; The second calculation submodule is further configured to read the fourth input data from the register; The selector is also used to read the fourth input data from the register.

15. The computing circuit according to claim 13, characterized in that, The first input data consists of M data units, the initial valid data consists of T data units, the calculation module has log2M elements, and the i-th calculation module includes a second calculation submodule, the calculation length of which is 2. b M is greater than T, and b is an integer; The selector of the i-th calculation module is used when the specified parameter is less than 2. b In the case where the fourth input data is selected as the target calculation result, and the specified parameter is not less than 2... b In the case of T, the candidate calculation result is selected as the target calculation result, and the specified parameter is T or the difference between T and the calculated length.

16. The computing circuit according to claim 13, characterized in that, The first input data consists of M data units, the initial valid data consists of T data units, and there are L calculation modules, with the i-th calculation module comprising 2... a -1 second computation submodules, the computation length of the j-th second computation submodule is j×2. b M is greater than T, L is less than log2M, and a and b are both integers; The selector of the i-th calculation module is used when the specified parameter is less than 2. b In the case where the fourth input data is selected as the target calculation result, and the specified parameter is not less than (2 a -1)×2 b In this case, choose option 2. a -1 candidate calculation results of the second calculation submodule are the target calculation results, where the specified parameter is not less than k×2 b And less than (k+1)×2 b In the case where the candidate calculation result of the kth second calculation submodule is selected as the target calculation result, the specified parameter is T or the difference between T and the calculated length, and k takes the value 1 to 2. a Integers in -2.

17. A method for calculating a redundancy check code, characterized in that, The method includes: If invalid data exists in the first input data, the invalid data is replaced with masked data by the masking module to obtain the second input data. The calculation module calculates the first redundancy check code based on the second input data. The first redundancy check code is corrected by the correction module to obtain the second redundancy check code.

18. A method for calculating a redundancy check code, characterized in that, The method includes: In the event that invalid data exists in the first input data, the processing module transmits the first input data to the first of the multiple calculation modules. The calculation lengths of each calculation module are different. The first input data includes the initial valid data. The calculation module calculates the fourth input data to obtain the target calculation result. The fourth input data includes the initial valid data, or the target calculation result of the previous calculation module and the remaining valid data in the initial valid data that has not been calculated. The target calculation result of the last calculation module is the redundancy check code of the first input data.

19. A chip, characterized in that, The chip includes a computing circuit as described in any one of claims 1 to 9 or a computing circuit as described in any one of claims 10 to 16.

20. An electronic device, characterized in that, The electronic device includes a computing circuit as described in any one of claims 1 to 9 or a computing circuit as described in any one of claims 10 to 16.

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