Decision feedback equalizer with reset

Abstract

The invention relates to a decision feedback equalizer with reset. An apparatus including decision feedback equalizer (DFE) reset circuitry is provided. The DFE reset circuitry includes synchronization circuitry and is configured to receive a DFE reset signal to initiate a reset operation of a DFE, generate a first control signal based on the DFE reset signal, and generate a second control signal based on the first control signal. And transmitting the first control signal to vary a data signal generated in a summator circuit of the DFE to affect the reset operation of the DFE.

Description

[0001] Cross-reference of related applications

[0002] This application is a non-provisional application that claims priority to U.S. Provisional Patent Application No. 63 / 685,440, filed August 21, 2024, entitled “Decision Feedback Equalizer with Reset,” which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure generally relate to the field of input buffers and decision feedback equalizers (DFEs) for memory devices. More specifically, embodiments of this disclosure relate to improving the reset capability of DFEs. Background Technology

[0004] The operating rate of memory devices (including the data rate of the memory devices) increases over time. As a side effect of this speed increase, data errors due to distortion may increase. For example, inter-symbol interference may occur between transmitted data, whereby previously received data may affect currently received data (e.g., previously received data affects and interferes with subsequently received data). One way to correct this interference is by using a decision feedback equalizer (DFE) circuit, which can be programmed to counteract (i.e., eliminate or mitigate) the effect of the channel on transmitted data.

[0005] To ensure proper operation of the DFE circuit, a reliable input signal should be available. Additionally, as the operating rate increases (e.g., as the data rate increases), the DFE should be able to correct inter-symbol interference at a rate at least matching the incoming data rate.

[0006] The embodiments disclosed herein may address one or more of the problems set forth above. Summary of the Invention

[0007] According to one aspect of the present invention, an apparatus is provided. The apparatus includes: a decision feedback equalizer (DFE) reset circuit system, comprising a synchronization circuit system, wherein the DFE reset circuit system is configured to: receive a DFE reset signal to initiate a reset operation of the DFE; generate a first control signal based on the DFE reset signal; and transmit the first control signal to modify a data signal generated in a summer circuit of the DFE to influence the reset operation of the DFE.

[0008] According to another aspect of the present invention, an apparatus is provided. The apparatus includes: tap signal control logic comprising: a first output configured to be coupled to a summer circuit of a decision feedback equalizer (DFE) in a memory device; a second output configured to be coupled to the summer circuit of the DFE; and a control input configured to be coupled to a DFE reset circuitry to receive a control signal to select, in conjunction with a reset operation of the DFE, a first signal to be transmitted from the first output and a second signal to be transmitted from the second output.

[0009] According to another aspect of the present invention, an apparatus is provided. The apparatus includes: a decision feedback equalizer (DFE) circuit comprising: a summer circuit configured to receive a data signal from a series of data signals; and a dual-tailed latch circuit coupled to the summer circuit to receive a first output signal generated by the summer circuit, wherein the dual-tailed latch circuit includes a first stage, a second stage coupled to the first stage, and a third stage coupled to the second stage, wherein the dual-tailed latch is utilized in the reset operation of the DFE circuit when no reset latch is present in any of the first, second, and third stages, and when none of the first, second, and third stages of the dual-tailed latch directly receives a reset signal generated based on a control signal generated from outside the DFE to initiate a reset of the DFE. Attached Figure Description

[0010] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the accompanying drawings, in which:

[0011] Figure 1 This is a simplified block diagram illustrating certain features of a memory device according to embodiments of the present disclosure;

[0012] Figure 2 This describes an embodiment according to the present disclosure. Figure 1 A block diagram of a data transceiver for the I / O interface;

[0013] Figure 3 Description of embodiments according to this disclosure Figure 2 A block diagram of an embodiment of a data transceiver;

[0014] Figure 4 Description of embodiments according to this disclosure Figure 2 A high-level diagram of the decision feedback equalizer for data transceivers;

[0015] Figure 5 Description of embodiments according to this disclosure Figure 4 A block diagram of the first embodiment of the DFE;

[0016] Figure 6 Description of embodiments according to this disclosure Figure 4 A block diagram of a second embodiment of the DFE;

[0017] Figure 7 Description of the combination of embodiments according to this disclosure Figure 6 The second embodiment of the DFE utilizes the first embodiment of the circuit system;

[0018] Figure 8 Description of the combination of embodiments according to this disclosure Figure 7 The first embodiment of the circuit system utilizes the first embodiment of the reset circuit system;

[0019] Figure 9 Description of the combination of embodiments according to this disclosure Figure 7 The first embodiment of the circuit system utilizes the first embodiment of the control circuit system;

[0020] Figure 10 Description of the combination of embodiments according to this disclosure Figure 6 The second embodiment of the DFE utilizes a second embodiment of the reset circuit system;

[0021] Figure 11 Description of the combination of embodiments according to this disclosure Figure 10 The second embodiment of the reset circuit system utilizes a second embodiment of the control circuit; and

[0022] Figure 12 Description of the combination of embodiments according to this disclosure Figure 10 The second embodiment of the reset circuit system and Figure 11 The second embodiment of the control circuit system utilizes the second embodiment of the circuit system. Detailed Implementation

[0023] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve developer-specific goals that may vary depending on the implementation, such as compliance with system-related and business-related constraints. Furthermore, it should be understood that this development work may be complex and time-consuming, but remains a routine task of design, fabrication, and manufacturing for those of ordinary skill in the art who benefit from this disclosure.

[0024] Using a decision feedback equalizer (DFE) in a memory device to perform distortion correction techniques can be valuable, for example, for accurately compensating for distortion in received data from the memory device. This ensures that accurate values ​​are stored in the memory of the memory device. The DFE can use previous bit data to create correction values ​​to compensate for distortion caused by (a number of) previously received data bits. For example, the most recent previous bit may have a greater distortion effect on the current bit compared to bits transmitted several data points before, thus causing the correction value to differ between the two bits. In cases where these levels need to be corrected, the DFE can operate to correct distortion in the transmitted bits.

[0025] Resetting a DFE can be useful between memory operations. However, as operating speeds continue to increase, there may not be sufficient time to complete a DFE reset operation before another memory operation is performed. Therefore, different architectures for reducing DFE reset operation time are considered and described herein. For example, one embodiment of a resettable DFE includes one or more dual-tailed latches that are used in conjunction with the DFE reset operation without using any reset latches disposed within the dual-tailed latches. Additionally, the reset operation can be performed without the circuitry of the dual-tailed latches directly receiving a reset signal (e.g., the RstHi signal and / or the RstHiF signal).

[0026] Now turn to the diagram. Figure 1 This is a simplified block diagram illustrating certain features of the memory device 10. Specifically, Figure 1 The block diagram is a functional block diagram illustrating certain functionalities of the memory device 10. According to one embodiment, the memory device 10 may be a Double Data Rate 5 (DDR5) synchronous dynamic random access memory (DDR5 SDRAM or DDR5) device. Compared to previous generations of DDR SDRAM, the various features of DDR5 SDRAM allow for reduced power consumption, greater bandwidth, and greater storage capacity. However, more generally, the memory device 10 may be a random access memory (RAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including Double Data Rate SRAM devices), flash memory and / or phase-change memory (PCM) devices, and / or other chalcogenide-based memories, such as self-select memory (SSM), Double Data Rate 4 (DDR4) synchronous dynamic random access memory (DDR4) device, low-power Double Data Rate 4 (LPDDR4) synchronous dynamic random access memory (LPDDR5) SDRAM, Double Data Rate 6 (DDR6) synchronous dynamic random access memory (DDR6 or DDR6), or another type of device.

[0027] Memory device 10 may include a plurality of memory banks 12. For example, memory banks 12 may be DDR5 SDRAM memory banks. Memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be understood, each DIMM may contain a plurality of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may contain one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a plurality of memory banks 12. For DDR5, memory banks 12 may be further arranged to form memory bank groups. For example, for 8 gigabit (GB) DDR5 SDRAM, the memory chip may contain 16 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 2 memory banks. For example, for 16GB DDR5 SDRAM, the memory chip may contain 32 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 4 memory banks. Depending on the application and design of the overall system, various other configurations, organization and sizes of the memory bank 12 on the memory device 10 may be utilized.

[0028] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with external devices. The command interface 14 is configured to provide several signals (e.g., signal 15) from an external device (not shown) (e.g., a processor or controller) (e.g., present in a host device coupled to the memory device 10). The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0029] As will be understood, command interface 14 may include, for example, several circuits to ensure proper handling of signal 15, such as clock input circuitry 18 and command address input circuitry 20. Command interface 14 may receive one or more clock signals from an external device. Typically, Double Data Rate (DDR) memory utilizes a differential pair of system clock signals, referred herein to as the true clock signal (Clk_t) and the complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t intersects with the falling complementary clock signal Clk_c, while the negative clock edge indicates the rising transition of the falling true clock signal Clk_t and the complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0030] Clock input circuit 18 receives a true clock signal (Clk_t) and a complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator 30, such as a delay-locked loop (DLL) circuit. Internal clock generator 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. For example, the phase-controlled internal clock signal LCLK is supplied to input / output (I / O) interface 16 and used as a timing signal to determine the output timing for reading data.

[0031] The internal clock signal CLK can also be provided to various other components within the memory device 10 and can be used to generate various additional internal clock signals. For example, the internal clock signal CLK can be provided to the command decoder 32. The command decoder 32 can receive command signals from the command bus 34 and can decode the command signals to provide various internal commands. For example, the command decoder 32 can provide command signals to the internal clock generator 30 via the bus 36 to coordinate the generation of the phase control internal clock signal LCLK. For example, the phase control internal clock signal LCLK can be used to time data passing through the I / O interface 16.

[0032] Furthermore, command decoder 32 can decode commands (e.g., read commands, write commands, mode register set commands, activation commands, etc.) and provide access to a specific memory bank 12 corresponding to the command via bus path 40. As will be understood, memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to memory bank 12. In one embodiment, each memory bank 12 includes a memory bank control block 22, which provides decoding (e.g., row decoders and column decoders) and other features (e.g., timing control and data control) to facilitate the execution of commands to and from memory bank 12. Memory bank 12 and memory bank control block 22 may be collectively referred to as memory array 23.

[0033] Memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device (e.g., a processor). In one embodiment, the command / address bus may be a 14-bit bus to accommodate command / address signals (CA<13:0>). The command / address signals are timed to command interface 14 using clock signals (Clk_t and Clk_c). For example, the command interface may include command address input circuitry 20 configured to receive and transmit commands to provide access to memory bank 12 via command decoder 32. Additionally, command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables memory device 10 to process commands input on the CA<13:0> bus. Access to a specific memory bank 12 within memory device 10 is command-encoded on the CA<13:0> bus.

[0034] Additionally, command interface 14 can be configured to receive several other command signals. For example, a die-terminated command / address (CA_ODT) signal can be provided to facilitate proper impedance matching within memory device 10. For example, a reset command (RESET_n) can be used during power-on to reset command interface 14, status registers, state machines, and the like. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing of a particular memory device 10. A mirroring (MIR) signal can also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex signals so that they can be exchanged to implement a certain route to the memory device 10. Various signals can also be provided to facilitate testing of memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to put memory device 10 into a test mode for connectivity testing.

[0035] Command interface 14 can also be used to provide an alarm signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, if a Cyclic Redundancy Check (CRC) error is detected, an alarm signal (ALERT_n) can be transmitted from memory device 10. Other alarm signals may also be generated. Furthermore, the bus and pins used for transmitting the alarm signal (ALERT_n) from memory device 10 can be used as input pins during certain operations (e.g., connectivity test modes performed using the TEN signal, as described above).

[0036] Data can be sent to and from memory device 10 by transmitting and receiving data signals 44 via I / O interface 16 using the commands and timing signals discussed above. More specifically, data can be sent to or retrieved from memory bank 12 via data bus 46, which includes multiple bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For some memory devices (e.g., DDR5 SDRAM memory devices), I / O signals can be divided into high and low bytes. For example, for x16 memory devices, I / O signals can be divided into high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the high and low bytes of the data signals.

[0037] To allow for higher data rates within memory device 10, some memory devices (e.g., DDR memory devices) may utilize a data strobe signal commonly referred to as the DQS signal. The DQS signal is driven by an external processor or controller transmitting data (e.g., for write commands) or by memory device 10 itself (e.g., for read commands). For read commands, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For write commands, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_c), the data strobe (DQS) signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during read and write operations. For example, for some memory devices (e.g., DDR5 SDRAM memory devices), the differential pair of the DQS signal can be divided into high and low data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the high and low bytes of data sent to and from memory device 10.

[0038] An impedance (ZQ) calibration signal can also be provided to memory device 10 via I / O interface 16. The ZQ calibration signal can be provided to a reference pin and used to tune the output driver and die top termination (ODT) values ​​by adjusting the pull-up and pull-down resistors of memory device 10 across process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance to calibrate the input impedance to a known value. As will be understood, a precision resistor is typically coupled between the ZQ pin on memory device 10 and GND / VSS external to memory device 10. This resistor acts as a reference for adjusting the internal ODT and drive strength of the I / O pin.

[0039] Additionally, a loopback signal can be provided to memory device 10 via I / O interface 16. The loopback signal can be used during testing or debugging phases to configure memory device 10 in a mode where signals are looped back through memory device 10 via the same pin. For example, the loopback signal can be used to configure memory device 10 to test its data output. The loopback may contain both data and strobe signals, or it may contain only data. This is typically intended to monitor the data captured by memory device 10 at I / O interface 16.

[0040] As will be understood, various other components (such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of memory device 10), etc.) can also be incorporated into the memory system incorporating memory device 10. Therefore, it should be understood that only [the following is provided] Figure 1 A block diagram is used to highlight certain functional features of the memory device 10 to aid in a detailed description thereafter.

[0041] In some embodiments, the memory device 10 may be housed in (physically integrated into the host device or otherwise connected to the host device) or otherwise connected to the host device. The host device may include any of a desktop computer, laptop computer, pager, cellular phone, personal notebook, portable audio player, control circuitry, camera, etc. The host device may also be a network node, such as a router, server, or client (e.g., a computer of the types previously described). The host device may be some other kind of electronic device, such as a photocopier, scanner, printer, game console, television, set-top box video distribution or recording system, cable TV box, personal digital media player, factory automation system, automotive computer system, or medical device. (The terms used to describe these different instances of the system (such as many other terms used herein) may share some indications and therefore should not be interpreted narrowly due to the other items listed.)

[0042] Therefore, the host device can be a processor-based device, which may include a processor, such as a microprocessor, that controls system functions and requests within the host. Furthermore, any host processor may include multiple processors sharing system control. The host processor may be directly or indirectly coupled to additional system components of the host, such that the host processor controls the operation of the host by executing instructions that can be stored within or outside the host.

[0043] As discussed above, the host can write data to and read data from the memory device 10, thereby enabling the memory device 10 to operate as volatile memory, such as double data rate DRAM (e.g., DDR5 SDRAM). In some embodiments, the host may also include separate non-volatile memory, such as read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate based memory, and / or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.) and other types of memory devices (e.g., storage devices), such as solid-state drives (SSDs), multimedia cards (MMCs), secure digital cards (SDs), compressed flash (CF) cards, or any other suitable devices. Furthermore, it should be understood that the host may include one or more external interfaces (such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE 1394 (FireWire), or any other suitable interface), and one or more input devices for allowing users to input data into the host, such as buttons, switches, keyboards, light pens, styluses, mice, and / or voice recognition systems. The host may also optionally include output devices (such as a display coupled to the processor) and network interface devices (such as network interface cards (NICs)) for interfacing with a network (such as the Internet). As will be understood, depending on the application of the host, it may include many other components.

[0044] The host is operable to transfer data to the memory device 10 for storage and to read data from the memory device 10 to perform various operations at the host. Therefore, to facilitate these data transfers, in some embodiments, the I / O interface 16 may include a data transceiver 48 that operates to receive DQ signals from the I / O interface 16 and transmit DQ signals to the I / O interface 16.

[0045] Figure 2The I / O interface 16 of the memory device 10 is generally described, and more specifically, the data transceiver 48 is described. As described, the data transceiver 48 of the I / O interface 16 may include a DQ connector 50, a DQ transceiver 52, and a serializer / deserializer 54. It should be noted that in some embodiments, multiple data transceivers 48 may be used, thereby enabling each individual data transceiver 48 to be used in conjunction with, for example, the corresponding high and low I / O signals (e.g., DQ<15:8> and DQ<7:0>) of the high and low bytes of the data signal. Thus, the I / O interface 16 may include multiple data transceivers 48, each data transceiver 48 corresponding to one or more I / O signals (e.g., including a corresponding DQ connector 50, DQ transceiver 52, and serializer / deserializer 54).

[0046] The DQ connector 50 may be, for example, a pin, a pad, or a combination thereof, or another type of interface operated to receive DQ signals, for example, for transferring data to the memory array 23 as part of a data write operation. Additionally, the DQ connector 50 may be operated to transmit DQ signals from the memory device 10, for example, for transferring data from the memory array 23 as part of a data read operation. To facilitate these data reads / writes, a DQ transceiver 52 is present in the data transceiver 48. In some embodiments, for example, the DQ transceiver 52 may receive a clock signal generated by an internal clock generator 30 as a timing signal for determining the output timing of a data read operation from the memory array 23. The clock signal transmitted by the internal clock generator 30 may be based on one or more timing signals received by the memory device 10 at the clock connector 56 (e.g., pins, pads, or combinations thereof) and routed to the internal clock generator 30 via the clock input circuitry 18. Therefore, the DQ transceiver 52 may receive a clock signal generated by the internal clock generator 30 as a timing signal for determining the output timing of a data read operation from the memory array 23.

[0047] For example, Figure 2 The DQ transceiver 52 can also receive one or more DQS signals to operate in a strobed data mode as part of a data write operation. These signals can be received at a DQS connector 58 (e.g., pins, pads, combinations thereof) and routed to the DQ transceiver 52 via the DQS transceiver 60, which operates to control the data strobing mode via selective transmission of the DQS signal to the DQ transceiver 52. Therefore, the DQ transceiver 52 can receive DQS signals to control data write operations to the memory array 23.

[0048] As described above, the data transceiver 48 can operate in several modes to facilitate the transfer of data to and from the memory device 10 (e.g., the transfer of data to and from the memory array 23). For example, to allow for higher data rates within the memory device 10, a data strobing mode utilizing a DQS signal may be present. The DQS signal may be driven by an external processor or controller that transmits data such as data received by the DQS connector 58 (e.g., pins, pads, combinations thereof) (e.g., for write commands). In some embodiments, the DQS signal is used as a clock signal to capture corresponding input data.

[0049] In addition, such as Figure 2 As described, the data transceiver 48 further includes a serializer / deserializer 54 that operates to convert serial data bits (e.g., a serial bit stream) into parallel data bits (e.g., a parallel bit stream) for transmission along the data bus 46 during data write operations of the memory device 10. Similarly, the serializer / deserializer 54 operates to convert parallel data bits (e.g., a parallel bit stream) into serial data bits (e.g., a serial bit stream) during read operations of the memory device 10. In this way, the serializer / deserializer 54 operates to convert data of a serial format received from, for example, a host device into a parallel format suitable for storage in the memory array 23. Similarly, the serializer / deserializer 54 operates to convert data of a parallel format received from, for example, the memory array 23 into a serial format suitable for transmission to the host device.

[0050] Figure 3 The data transceiver 48 is described as including a DQ connector 50 coupled to the data transfer bus 51, a DQ receiver 62, a DQ transmitter 64 (which, combined with the DQ receiver 62, forms the DQ transceiver 52), a deserializer 66, and a serializer 68 (which, combined with the deserializer 66, forms a serializer / deserializer 54). In operation, a host (e.g., the host processor or other memory device described above) is operable to transmit data in serial form across the data transfer bus 51 to the data transceiver 48 as part of a data write operation to the memory device 10. This data is received at the DQ connector 50 and transmitted to the DQ receiver 62. For example, the DQ receiver 62 may perform one or more operations on the data (e.g., amplify, drive data signals, etc.) and / or may operate as a data latch until a corresponding DQS signal for coordinating (e.g., controlling) the transmission of data to the deserializer 66 is received. As part of the data write operation, the deserializer 66 is operable to convert (e.g., transform) the data from a format in which it is transmitted along the data transfer bus 51 (e.g., serial form) to a format for transmitting the data to the memory array 23 for storage therein (e.g., parallel form).

[0051] Similarly, during a read operation (e.g., reading data from memory array 23 and transmitting the read data to the host via data transfer bus 51), serializer 68 can receive data read from memory array 23 in one format (e.g., parallel format) used by memory array 23 and can convert (e.g., transform) the received data into a second format (e.g., serial format) so that the data is compatible with one or more of data transfer bus 51 and / or the host. The converted data can be transmitted from serializer 68 to DQ transmitter 64, whereby one or more operations can be performed on the data (e.g., de-amplification, driving data signals, etc.). Additionally, DQ transmitter 64 can operate as a latch for the received data until, for example, a clock signal is received from internal clock generator 30 to coordinate (e.g., control) the transmission of data to DQ connector 50 for transmission along data transfer bus 51 to one or more components of the host.

[0052] In some embodiments, data received at DQ connector 50 may be distorted. For example, data received at DQ connector 50 may be affected by inter-symbol interference (ISI), where previously received data interferes with subsequently received data. For example, due to the increased amount of data transmitted across data transport bus 51 to DQ connector 50, data received at DQ connector 50 may be distorted relative to data transmitted by the host. One technique to mitigate (e.g., cancel or eliminate) this distortion and effectively reverse the effects of ISI is to apply equalization operations to the data. Figure 4 This describes an embodiment of an equalizer that can be used in this equalization operation.

[0053] Figure 4 This describes an embodiment of an equalizer, specifically a decision feedback equalizer (DFE) 70. As illustrated, DFE 70 represents an N-tap DFE 70, where "N" is a positive integer value. For example, a 1-tap DFE, a 2-tap DFE, a 3-tap DFE, a 4-tap DFE, or another N-tap DFE can be implemented as DFE 70. DFE 70 can be coupled with... Figure 3 The deserializer 66 or DQ receiver 62 is placed separately or placed in Figure 3 The deserializer 66 or DQ receiver 62 is internal. In operation, the binary output (e.g., from a latch or decision limiter) is captured in one or more data latches or data registers. In this embodiment, these data latches or data registers may be housed in the deserializer 66, and the values ​​stored in the data latches or data registers may be latched or transmitted along paths 72, 74, and 76.

[0054] When a data bit is received at DQ receiver 62, it can be identified as being transmitted from the host as bit "x(t)" and can be received at time t0 as a distorted bit x (e.g., bit x has been distorted due to ISI). This occurs before the distorted bit x is received at DQ receiver 62 (e.g., at time t immediately preceding time t0). -1 The most recent bit received can be identified as x-1 and is described as being transmitted from data latch 78 along path 72. The bit received before the distortion bit x is received at DQ receiver 62 (e.g., immediately following time t) -1 The previous time t -2 The next nearest bit received can be identified as x-2 and is described as being transmitted from data latch 80 along path 74. This process can continue with additional latches up to latch 82, which corresponds to the Nth latch and is transmitted before the received distorted bit x at DQ receiver 62 (e.g., immediately following time t). -N-1 The previous time t -N The least recent bit (xN) received is transmitted along path 76. Bits x-1, x-2, ... xN can be considered as bit groups that interfere with the received distorted bit x (e.g., bits x-1, x-2, ... xN cause ISI to the host transmitted bit x), and DFE 70 is operable to cancel the distortion caused to the host transmitted bit x by bit groups x-1, x-2, ... xN.

[0055] Therefore, the values ​​latched or transmitted along paths 72, 74, and 76 can respectively correspond to the most recent previous data values ​​(e.g., previous bits x-1, x-2, ... xN) transmitted from DQ receiver 62 to be stored in memory array 23. These previously transmitted bits are fed back along paths 72, 74, and 76 and used to generate weighted taps 86 (e.g., h1), 88 (e.g., h2), and 90 (e.g., hn) arranged along paths 72, 74, and 76. Weighted taps 86, 88, and 90 can each correspond to a corresponding adjustment (e.g., voltage) that can be added to the received input signal (e.g., data received from DQ connector 50, such as distortion bit x) by summer 84 (e.g., summing amplifier). In other embodiments, weighted taps 86, 88, and 90 may be combined with an initial reference value to produce an offset corresponding to or mitigating distortion of the received data (e.g., mitigating distortion of distorted bit x). In some embodiments, weighting the taps to reflect the most recent previously received data (e.g., bit x-1 and weighted tap 86) may have a stronger influence on the distortion of the received data (e.g., distorted bit x) than bits received at earlier times (e.g., bits x-2 and xN). DFE 70 is operable to generate magnitudes and polarities for weighted taps 86, 88, and 90 attributable to each previous bit to collectively cancel out the distortion caused by those previously received bits.

[0056] For example, in this embodiment, each of the previously received bits x-1, x-2, x-3, and x-4 (as bit xN) may have one of two values ​​(e.g., binary 0 or 1), which is transmitted to deserializer 66 for transmission to memory array 23 and, additionally, latched or stored in registers for subsequent transmission along corresponding paths 72, 74, 76 and an additional path corresponding to the previously received bit x-3. In this example, for bit groups x-1, x-2, x-3, and x-4, hexadecimal (e.g., 2...) 4 A number of possible binary combinations (e.g., 0000, 0001, 0010, ..., 1110 or 1111) will be possible. DFE 70 operates to select and / or generate corresponding tap values ​​for determining the presence of any of the aforementioned sixteen combinations (e.g., based on received values ​​along paths 72, 74, 76 and additional paths corresponding to previously received bit x-3) to adjust the input values ​​received from DQ connector 50 (e.g., distortion bit x) or modify the reference values ​​subsequently applied to the input values ​​received from DQ connector 50 (e.g., distortion bit x) in order to eliminate ISI distortion from previous bits (e.g., bit groups x-1, x-2, x-3, and x-4) in the data stream.

[0057] The use of distortion correction (e.g., DFE 70) can be beneficial, ensuring that data transmitted from DQ connector 50 is correctly represented in memory array 23 without distortion. As described above, a distortion correction circuitry (e.g., an equalizer) may be included as part of DQ receiver 62, but may not need to be physically located there (e.g., it may be coupled to DQ receiver 62 instead). In some embodiments, the distortion correction circuitry may be operable to provide previously transmitted bit data to correct distorted bits x (e.g., bits distorted due to ISI and / or system distortion) transmitted via channel 92 (e.g., connections, transmission lines, and / or conductive materials).

[0058] Figure 5 The DFE 94 is described as an embodiment of the equalizer discussed above. DFE 94 represents a half-rate DFE receiver, where data (from channel 92) is received at half the data rate transmitted along channel 92 at both edges of the clock signal. As illustrated, DFE 94 represents a 2-tap DFE. However, other variations are considered, such as a 1-tap DFE, a 3-tap DFE, a 4-tap DFE, or another N-tap DFE, which can be implemented as DFE 94. DFE 94 can be... Figure 3 The deserializer 66 or DQ receiver 62 is placed separately or placed in Figure 3 The internal components of the deserializer 66 or DQ receiver 62.

[0059] DFE 94 includes first-stage summers 96, each receiving a second weighted tap (e.g., h2) as a feedback signal. Additionally, the first-stage summers 96 receive a data stream (e.g., bits x, x-1, x-2, etc.) along channel 92. Additionally, DFE 94 is a speculative equalizer. Therefore, the first weighted tap (e.g., h1) is transmitted as input to the second-stage summers 98. As illustrated, the first weighted tap is implemented speculatively, so positive weighted tap values ​​(e.g., +h1) and negative weighted tap values ​​(e.g., –h1) are provided to the second-stage summers 98.

[0060] DFE 94 further includes latches 100, 102, 104, and 106 (e.g., a data limiter). These latches 100, 102, 104, and 106 are controlled by a clock signal CLK. CLK may be a half-rate clock signal, whereby latches 100 and 102 sample data on the rising edge of CLK to produce an even number of data bits, which are output from DFE 94 along path 108. Similarly, latches 104 and 106 sample data on the falling edge of CLK to produce an odd number of data bits, which are output from DFE 94 along path 110. Sampled data from latches 100 and 102 is transmitted to selection circuit 112, while sampled data from latches 104 and 106 is transmitted to selection circuit 114. Selection circuits 112 and 114 can be 2:1 multiplexers.

[0061] As explained, selection circuit 112 is controlled by a feedback signal transmitted along path 116, and selection circuit 114 is controlled by a feedback signal transmitted along path 118. In operation, the feedback signal along path 116 is used to select the correct weighted tap value by selecting the corresponding input to selection circuit 112 corresponding to the correct weighted tap value to be applied (e.g., +h1 or –h1) as a signal output from selection circuit 112. Similarly, the feedback signal along path 118 is used to select the correct weighted tap value by selecting the corresponding input to selection circuit 114 corresponding to the correct weighted tap value to be applied (e.g., +h1 or –h1) as a signal output from selection circuit 114. Furthermore, as explained, the feedback signal along path 116 provides the selection signal to the even-numbered portion of DFE 94 (i.e., the upper part of DFE 94), since any previous bit is determined by the odd-numbered portion of DFE 94 (including latch 120), and the feedback signal along path 118 provides the selection signal to the odd-numbered portion of DFE 94 (i.e., the lower part of DFE 94), since any previous bit is determined by the even-numbered portion of DFE 94 (including latch 122).

[0062] In operation, the tap signal path of Tap1 (i.e., providing h1 to the second-stage summer 98) is t clk-to-Q +tu, where t clk-to-Q This is the clock-to-Q delay of the corresponding latch 100, 102, 104, or 106 for a given (e.g., selected) path, and tu is the propagation delay of the corresponding selection circuit 112, 114 for the given (e.g., selected) path. However, the tap signal path of Tap2 (i.e., providing h2 to the first-stage summer 96) is greater than the tap signal path of Tap1. The tap signal path of Tap2 is t clk-to-Q +tu+ts, where tclk-to-Q ts is the clock-to-Q delay of the corresponding latch 100, 102, 104 or 106 for the given (e.g., selected) path, tu is the propagation delay of the corresponding selection circuit 112, 114 for the given (e.g., selected) path, and ts is the settling time attributable to the first-stage summer 96.

[0063] As operating speed increases, the propagation delays described above, particularly those relating to tap signal paths such as Tap1 and Tap2, may affect the operation of DFE 94. This could be attributed to the propagation delay (e.g., tu) of the corresponding selection circuits 112, 114 for a given (e.g., selected) path. In fact, with increased operating speed, the tap signal path of Tap1 (i.e., providing h1 to the second-stage summer 98) or the tap signal path of Tap2 (i.e., providing h2 to the first-stage summer 96) may arrive, for example, after data is provided from channel 92, primarily due to the propagation delay (e.g., tu) of the corresponding selection circuits 112, 114 for a given (e.g., selected) path. Consequently, the weighting associated with one or both of h1 and h2 will not be correctly applied to the data (i.e., bits) being transmitted to the first-stage summer 96 and / or the second-stage summer 98.

[0064] Figure 6 The DFE 124, described as an embodiment of the equalizer discussed above, overcomes the delay problem associated with the propagation delay (e.g., tu) of the corresponding selection circuits 112, 114 of a given (e.g., selected) path in the DFE 94. The DFE 124 represents a half-rate unmultiplexed (non-multiplexed) DFE receiver, where data (from channel 92) is received at half the data rate transmitted along channel 92 at both edges of the clock signal. However, there is no unmultiplexed MUX delay (i.e., tu propagation delay), for example, with... Figure 5 The delay associated with DFE 94. As illustrated, DFE 124 represents a 4-tap DFE. However, other variations are possible, such as a 1-tap DFE, a 2-tap DFE, a 3-tap DFE, or another N-tap DFE, which can be implemented as DFE 124. DFE 124 can be associated with... Figure 3 The deserializer 66 or DQ receiver 62 is placed separately or placed in Figure 3 The internal components of the deserializer 66 or DQ receiver 62.

[0065] Several distortion bits may be transmitted from channel 92 to amplification device 126 and from amplification device 126 to DFE 124. Amplification device 126 may be, for example, a variable gain amplifier. In some embodiments, amplification device may be a two-stage amplifier, wherein one of the stages of the amplifier has continuous-time linear equalization (CTLE). Distortion bits may be transmitted simultaneously to DFE 124 with a DQ reference signal having a predetermined voltage (VRDQ). VRDQ may represent a threshold (e.g., voltage level) for determining whether a transmitted bit received by DQ connector 50 is logic low (e.g., 0) or logic high (e.g., 1). Thus, data bits may be received at a first input of amplification device 126 and the reference signal (e.g., VRDQ) may be received at a second input of amplification device 126.

[0066] In some embodiments, as described above, Figure 6 The amplification device 126 may represent a variable gain amplifier and a continuous-time linear equalizer (CTLE). The output of the variable gain amplifier (e.g., Xs(t)) may be set to a predetermined level (e.g., a set value), such as a value between approximately 0.5 and 2.0 times the DC reference signal input to the variable gain amplifier, or another level. The CTLE may be operated to, for example, mitigate inter-symbol interference (ISI). More specifically, the CTLE typically operates to compensate for losses in the data stream caused by, for example, channel 92 (resulting in distortion bits). The CTLE may also typically be operated to amplify the higher frequency content of the data stream to equalize these effects on the data stream (i.e., to boost the higher frequency content, thus making it practically equivalent to the amplitude at the lower frequency components of the data stream). Thus, in addition to the variable gain amplifier, the CTLE may also be operated to provide a more reliable signal to the DFE 124 (e.g., to increase the reliability of one or more of the distortion bits).

[0067] In some embodiments, the CTLE may be integrated into the amplification device 126 (e.g., as part of a stage of a variable gain amplifier). However, it should be noted that the CTLE circuitry may instead be arranged separately (i.e., in series) from the variable gain amplifier used in the amplification device. As illustrated, the amplification device 126 receives data bits along channel 92 and a reference signal VRDQ (e.g., a DQ reference signal or “Vref”), and transmits the amplified result along path 128 to the summer 130.

[0068] In the illustrated example, DFE 124 can be operated to correct distortion from distorted bits (e.g., bit x) using taps weighted with previously described bit data. The data for the given bit (e.g., logic 1 or logic 0) can be passed through an amplification device and transmitted via path 128 to summer 130. The magnitude and polarity of the weighted tap 86 (e.g., h1) can cancel the total distortion caused by bit x-1 via summer 130, which operates as a current summer that applies current to distorted bit x to cancel the distortion caused by bit x-1. The resulting signal output from summer 130 is transmitted to a double-tailed latch 132 in the even-bit portion of DFE 124 (i.e., the upper described portion of DFE 124) and a double-tailed latch 134 in the odd-bit portion of DFE 124 (i.e., the lower described portion of DFE 94). Dual-tailed latch 132 may include latches 115 and 117, while dual-tailed latch 134 may include latches 119 and 121. In operation, latches 115 and 117 may operate in a manner similar to, for example, latches 100 and 122, and latches 119 and 121 may operate in a manner similar to, for example, latches 104 and 120. However, as illustrated, there is no selection circuit 112 or selection circuit 114, and therefore, there is no corresponding tu as a propagation delay in DFE 124. This can save approximately, for example, 60 picoseconds, 70 picoseconds, 80 picoseconds, 90 picoseconds, 100 picoseconds, or another amount of time relative to the cycle time margin of DFE 124, and relative to the cycle time margin of DFE 94.

[0069] Path 123 serves as a feedback path operation to transfer the first weighted tap (h1) from the output of latch 115 to the summer 130 located in the odd-numbered portion of DFE 124. Similarly, path 125 serves as a feedback path operation to transfer the first weighted tap (h1) from the output of latch 119 to the summer 130 located in the even-numbered portion of DFE 124. Additionally, as explained, the output timing of latch 115 is controlled by the DQS signal, while the output timing of latch 117 is controlled by the inverted DQS signal, DQSB. The output timing of latch 119 is controlled by DQSB, and the output timing of latch 121 is controlled by DQS. The signal generated by latch 115 is based on the output of summer 130 located in the even-numbered portion of DFE 124, adjusted by a second weighted tap (h2) received along path 127 from the output of latch 117, a fourth weighted tap (h4) received along path 127 from the output of latch 117, and a third weighted tap (h3) received along path 129 from the output of latch 121. As described above, the output of latch 115 is the signal modified by the aforementioned weighted taps (h2, h3, and h4) and transmitted along path 123, where the output is used to generate a first weighted tap (h1) transmitted to summer 130 located in the odd-numbered portion of DFE 124. Additionally, the output of latch 115 is transmitted to latch 117 as an input signal.

[0070] Latch 117 generates an output controlled by the DQSB signal, and depending on the operating state of the dual-tailed latch 132, this output is transmitted along path 127 to latch 115 as a second weighted tap (h2) or a fourth weighted tap (h4), or to latch 119 as a third weighted tap (h3). For example, whether the output is transmitted along path 127 to latch 115 as the second weighted tap (h2), the fourth weighted tap (h4), or the third weighted tap (h3) depends on the phase (e.g., 0°, 90°, 180°, or 270°) of the DQSB signal applied as the control signal for latch 117. The output of latch 117 is also transmitted as an even number of data bits, which are output from DFE 124 along path 108.

[0071] As further explained, the signal generated by latch 119 is based on the output of summer 130 located in the odd-numbered portion of DFE 124, adjusted by a second weighted tap (h2) received along path 133 from the output of latch 121, a fourth weighted tap (h4) received along path 133 from the output of latch 121, and a third weighted tap (h3) received along path 131 from the output of latch 117. As described above, the output of latch 119 is the signal obtained by the aforementioned weighted taps (h2, h3, and h4) and is transmitted along path 125, where the output is used to generate a first weighted tap (h1) transmitted to summer 130 located in the even-numbered portion of DFE 124. Additionally, the output of latch 119 is transmitted to latch 121 as an input signal to latch 117.

[0072] Latch 121 generates an output controlled by the DQSB signal, and depending on the operating state of the dual-tailed latch 134, this output is transmitted along path 133 to latch 119 as a second weighted tap (h2) or a fourth weighted tap (h4), or along path 129 to latch 115 as a third weighted tap (h3). For example, whether the output is transmitted along path 133 to latch 119 as the second weighted tap (h2), the fourth weighted tap (h4), or the third weighted tap (h3) depends on the phase (e.g., 0°, 90°, 180°, or 270°) of the DQS signal applied as a control signal for latch 117. The output of latch 121 is also transmitted as odd data bits, which are output from DFE 124 along path 110.

[0073] Regarding the first weighted tap (h1) provided to each of the summers 130, it should be noted that the signal transmitted to the summer 130 can be selectively positive (i.e., +h1) or negative (i.e., –h1) depending on the choice of the summer. That is, the first weighted tap can be provided as both a positive weighted tap value (e.g., +h1) and a negative weighted tap value (e.g., –h1). Additionally, in operation, the tap signal path of Tap1 (i.e., providing h1 to the summer 130) is t clk-to-Q +ts, where t clk-to-Q ts is the clock-to-Q delay of the corresponding latch 115, 117, 119, or 121 for a given (e.g., selected) path, and ts is the settling time attributable to the summer 130. The tap signal path of Tap2 is t clk-to-Q In this way, tu (i.e., the propagation delay of any selected circuit) is omitted from DFE 124 and ts is the settling time attributable to the first-stage summer 96.

[0074] Because tu is omitted in DFE 124, the propagation delay described above with respect to DFE 94 can be avoided as the operating speed increases. For example, as the operating speed increases, the tap signal path of Tap2 (i.e., providing h2 to the first-stage dual-tailed latches 132 and 134) can arrive, for example, before data is provided from channel 92. Therefore, the weighting associated with h2 will be correctly applied to the data (i.e., bits) transmitted to the corresponding latches 115 and 119.

[0075] Figure 7 Examples of embodiments of the summer 130 and the dual-tailed latch 132 of the DFE (e.g., DFE 124) are described below. In operation, the summer 130 receives Xm and Xp signals from, for example, an amplification device 126 as part of Xs(t). The Xm and Xp signals can be used, for example, for tap polarity selection. Additionally, the summer 130 receives TapNP and TapNM signals, which may correspond to, for example, weighted tap values ​​hn transmitted to the summer 130 as positive and negative values. It should be noted that "N" can be an integer representing the level of the summer 130 in an N-tap DFE. For example, in a four-tap DFE, "N" can be 0 to 3. The summer 130 also receives TapNBias signals at transistors 135 and 136, which are used to control the range and step size of the corresponding TapNP signal received at transistor 138 or the TapNM signal received at transistor 140. Finally, the summer 130 receives a selection signal (SelDFE) along path 142, which is used to select / output a negative tap value for the hN tap value applied in the summer 130.

[0076] Xm and Xp (e.g., as the output of summer 130) can be transferred to a corresponding double-tailed latch, such as double-tailed latch 132 of DFE 124 when N=0. Therefore, although double-tailed latch 132 is described for illustrative purposes, the following discussion applies to additional double-tailed latches of DFE 124. In some embodiments, double-tailed latch 132 (and double-tailed latch 134 and any additional double-tailed latches utilized in a multi-tap DFE) may comprise multiple stages, such as a first stage 144, a second stage 146, and a third stage 148. Although three stages are described, fewer or more stages may be used. The first stage 144 of double-tailed latch 132 includes transistors (e.g., MOSFET transistors) 150, 152, 154, 156, and 158. Specifically, transistors 154 and 156, and transistor 158, may be n-type transistors. Furthermore, transistors 150 and 152 may be p-type transistors. The DQS input signal (e.g., UDQS_t / LDQS_t) can be connected to the gates of transistors 150, 152, and 158 to time the signals received by transistors 150, 152, and 158 to sense and amplify one or more signals at the first stage 144. For example, the DQ input signal (e.g., DQ<15:8> / DQ<7:0>) can be connected to the gate of transistor 154. A voltage reference (VRDQ) can be connected to the gate of transistor 156. Additionally, a voltage source (VDD) 160 can be coupled to the sources of transistors 150 and 152. The total current flowing through transistor 158 (I0) is... total )162 is equal to the first current (I) flowing through transistors 150 and 154 through the output node 166 of the first stage 144 Xm coupled between transistors 150 and 154. m )164 plus the second current (I) flowing through transistors 152 and 156 via the output node 170 (Xp) of the first stage 144. p )168. Xm at node 166 and Xp at node 170 can be output from the first stage 144 to the second stage 146 (sensing stage) after being generated by the DQS input signal.

[0077] For example, when the DQS input signal is low, transistor 158 is turned off and the voltage Xm at node 166 and the voltage Xp at node 170 are reset and precharged to VDD 160 through transistors 150 and 152. That is, when the DQS input signal is low, the first stage 144 can be in the precharge phase.

[0078] Conversely, when the DQS input signal is high, stage 144 can be in generation mode. In generation mode, transistors 150 and 152 are turned off and transistor 158 is turned on. Transistors 154 and 156 can be turned on by the DQ input signal and the reference voltage VRDQ, respectively. Transistors 154 and 156 draw differential current proportional to the potential difference between the voltage of the DQ input signal and the reference voltage. The differential current due to voltage discharge allows the differential voltage between Xm at node 166 and Xp at node 170 to increase (e.g., differential gain) relative to the differential voltage between the DQ input signal voltage and the voltage reference. That is, the differential voltage is amplified and a portion of the voltages of Xm at node 166 and Xp at node 170 is discharged to ground / VSS.

[0079] During generation mode, the capacitive load (Cload) at node 170 Xp ) can be passed through current I p Discharge, and the capacitive load (Cload) at node 166. Xm ) can be passed through current I m Discharge. Capacitive load Cload Xm This may be attributed to the parasitic capacitance across the terminals of transistors 150 and 152, along with the parasitic capacitance in the second stage 146 (coupled to node 166). Similarly, the capacitive load Cload... Xp This may be attributed to the parasitic capacitance across the terminals of transistors 152 and 156, along with the parasitic capacitance coupled to the second stage 146 at node 170. Specifically, the voltage Xm at node 166 can be defined using the following equation:

[0080]

[0081] Where V xm UI is the voltage of Xm at node 166, and UI is a unit interval based on the operating frequency. Similarly, the voltage of Xp at node 170 can be defined using the following equation:

[0082]

[0083] Where V xp It is the voltage at node 170, Xp. Therefore, V xp With V xm The voltage difference (Vdiff) between them can be expressed as the following equation:

[0084]

[0085] Where N equals Cload Xp and Cload Xm Vdiff is inversely proportional to the propagation delay of the DQ input signal through the dual-tailed latch 132.

[0086] Figure 7 The circuit diagram of the second stage 146 of the dual-tailed latch 132 is additionally shown. As illustrated, the second stage 146 includes transistors (e.g., MOSFET transistors) 174, 176, 178, 180, 182, 184, 186, and 187. Specifically, transistors 172, 174, 180, 184, and 187 may be n-type transistors. Furthermore, transistors 176, 178, 182, and 186 may be p-type transistors. DQSB may be an inverted data strobe signal (e.g., UDQS_c / LDQS_c) complementary to the DQS input signal. DQSB may be connected to the gate of transistor 176. Additionally, VDD 160 may be coupled to the source of transistor 176.

[0087] When Xm and Xp discharge due to the DQS input signal transitioning high, transistors 172 and 174 are turned off due to their respective gates being coupled to Xm and Xp. This precharges output node 188 (i.e., Yp) and output node 190 (i.e., Ym), which is due to DQSB being low when the DQS input signal is high. As Xm and Xp charge due to the DQS input signal transitioning low, transistors 172 and 174 are turned on, while transistor 176 is turned off. Due to the difference between Xm and Xp, the discharge of Yp at node 188 and Ym at node 190 may occur at different times / rates. Using this difference, a differential voltage is established through transistors 172 and 174 and passed to transistors 178, 180, 182, and 184.

[0088] Additionally, as described above, the second stage 146 further includes transistors 186 and 187. Transistor 186 is operable to reset the second stage 146 based on the value of the received signal RstHiF received at the gate of transistor 186. Similarly, transistor 187 is operable to reset the second stage 146 based on the value of the received signal RstHi (e.g., the inverted signal of RstHiF) received at the gate of transistor 187. For example, when RstHiF is high and RstHi is low, transistor 186 does not affect the voltage at node 188 and transistor 187 does not affect the voltage at node 190 (i.e., Yp and Ym are unaffected). However, when RstHiF is low and RstHi is high, transistor 186 allows VDD 160 to be connected to node 188 and transistor 187 allows node 190 to be connected to ground / VSS, thereby causing a change in the voltages of Yp and Ym. In this way, Yp and Ym can be controlled and reset based on the value of RstHiF.

[0089] Figure 7The circuit diagram of the third stage 148 of the dual-tailed latch 132 is also shown. As illustrated, the third stage 148 includes an SR flip-flop. The SR flip-flop can be implemented using NOR gates 192 and 194. NOR gate 192 receives Ym from node 190 and outputs Zp from node 196. Similarly, NOR gate 194 receives Yp from node 188 and outputs Zm from node 198. In this way, Zp and Zm represent the resulting output signals generated by the dual-tailed latch 132 for the given data input to DFE 124.

[0090] The third stage 148 further includes transistors (e.g., MOSFET transistors) 200, 202, 204, and 205. Specifically, transistors 202 and 205 may be n-type transistors, while transistors 200 and 204 may be p-type transistors. Transistors 200 and 204 may be coupled to NOR gates 192 and 194, respectively. Similarly, transistors 202 and 205 may be coupled to nodes 196 and 198, respectively. Each of transistors 200 and 205 may receive a signal RstHi at its respective gate, and transistors 202 and 204 may receive a signal RstHiF (the inverted signal of RstHi) at their respective gates.

[0091] In operation, transistors 200, 202, 204, and 205 operate to reset the third stage 148 based on the values ​​of the received signals RstHi and RstHiF received at the respective gates of transistors 200, 202, 204, and 205. For example, when RstHiF is high and RstHi is low, transistors 204 and 205 do not affect either node 196 or node 198 (i.e., Zp and Zm are unaffected). However, when RstHiF is low and RstHi is high, transistors 204 and 205 allow VDD 160 to be connected to node 196 and allow ground / VSS to be connected to node 198, thereby causing a voltage change in Zp and Zm. In this way, Zp and Zm can be controlled and reset based on the values ​​of RstHiF and RstHi.

[0092] As described above, the reset of the dual-tailed latch 132 and therefore the DFE 124 can be achieved using the RstHiF signal (and the RstHi signal). The reset of the DFE 124 may be useful, for example, between write operations, for initializing the DFE 124 for a new write operation. Figure 8 Explanation based on Figure 7An embodiment of the DFE reset circuit system 206 is described, which operates to generate RstHiF and RstHi signals for resetting the DFE 124. In some embodiments, a single DFE reset circuit system 206 may be implemented for an N-tap DFE. In other embodiments, a corresponding DFE reset circuit system 206 may be implemented for each tap of the N-tap DFE.

[0093] As described, the DFE reset circuit system 206 includes an AND gate 208 that receives the DFEresetPre0 signal at input 210 (e.g., an input pin). The DFEresetPre0 signal may be an externally generated signal (e.g., generated outside of the DFE 124) that is transmitted to the DFE reset circuit system 206 as a control signal to initiate a reset of the DFE 124. The AND gate 208 also includes an input 212 (e.g., an input pin) that receives a buffered version of the DFEresetPre0 signal. The buffering of the DFEresetPre0 signal may be implemented via one or more buffer circuits 214. The amount of buffering applied to the DFEresetPre0 signal can be varied by increasing or decreasing the number of buffer circuits 214 used.

[0094] In operation, when either the DFEresetPre0 signal or the buffered DFEresetPre0 signal is high (e.g., "1") at inputs 210 and 212, the AND gate 208 outputs a high signal from its output 215 (e.g., an output pin). Similarly, if one or both of the DFEresetPre0 signal and the buffered DFEresetPre0 signal are low (e.g., "0") at inputs 210 and 212, the AND gate 208 outputs a low signal from its output 215. As illustrated, the DFE reset circuit system 206 also includes an OR gate 216.

[0095] The OR gate 216 of the DFE reset circuit system 206 includes an input 218 (e.g., an input pin), an input 220 (e.g., an input pin), and an output 222 (e.g., an output pin). Input 218 may receive an enable signal. The enable signal may be a signal generated externally to the DFE reset circuit system 206 (e.g., generated externally from DFE 124) and transmitted as a control signal. For example, in some embodiments, the enable signal is high whenever DFE 124 is activated, and low otherwise. In other embodiments, for example, the enable signal may be set high when a reset operation of DFE 124 is about to be performed.

[0096] Input 220 of OR gate 216 can be coupled to output 215 of AND gate 208 to receive a signal generated by AND gate 208. In operation, when either (or both) the signal at input 218 or input 220 is high, OR gate 216 transmits a DFEreset0 signal with a high value (e.g., "1") from output 222. Similarly, when both signals at input 218 and input 220 are low, OR gate 216 transmits a DFEreset0 signal with a high value (e.g., "1") from output 222. As illustrated, the DFEreset0 signal transmitted from OR gate 216 can be transmitted to NAND gate 224. For example, the DFEreset0 signal transmitted from OR gate 216 can be transmitted to input 226 (e.g., an input pin) of NAND gate 224. NAND gate 224 may also include inputs 226 and 228. Input 228 can receive a DQS signal and input 230 can receive an enable signal, which may be the same as or different from the enable signal received at input 218 of NOR gate 216.

[0097] NAND gate 224 also includes an output 232 (e.g., an output pin) for transmitting the RstHi signal generated by NAND gate 224. For example, when in operation, if any (or all) of the DFEreset0 signal at input 226, the DQS signal at input 228, and the enable signal at input 230 are low, then NAND gate 224 generates a high signal as the RstHi signal. Similarly, if all of the DFEreset0 signal at input 226, the DQS signal at input 228, and the enable signal at input 230 are high, then NAND gate 224 generates a low signal as the RstHi signal. The generated RstHi signal can be coupled from output 232 of NAND gate 224 to transistors 187, 200, and 205 for the reset operation of DFE 124, as described above. Figure 7 As described.

[0098] like Figure 8 Additionally, the output 232 of NAND gate 224 is coupled to the input 234 of inverter 236 (e.g., an input pin). Inverter 236 also includes an output 238 that transmits the generated RstHiF signal (i.e., the inverted signal of RstHi). The output 238 of inverter 236 can be coupled to transistors 186, 202, and 204 for the reset operation of DFE 124, as described above. Figure 7 As described.

[0099] Figure 9 Explanation can be combined Figure 8The DFE reset circuit system 206 uses tap signal control logic 240. In some embodiments, a single tap signal control logic 240 may be implemented for an N-tap DFE. In other embodiments, a corresponding tap signal control logic 240 may be implemented for each tap of the N-tap DFE. As illustrated, the tap signal control logic 240 may include a multiplexer 242 having an input 244 (e.g., an input pin), an input 246, an output 248 (e.g., an output pin), and an output 250. The multiplexer 242 receives a TapNP0 signal (e.g., a zero-phase tap signal from a TapNP signal) at input 244 and a TapNM0 signal (e.g., a zero-phase tap signal from a TapNM signal) at input 244. In operation, the multiplexer 242 selectively transmits the signals received at inputs 244 and 246 from outputs 248 and 250 as the TapNP signal and the TapNM signal, respectively. Output 248 is coupled to transistor 138 of summer 130, and output 250 is coupled to transistor 140 of summer 130 and used for the purposes described above. Figure 7 The described method generates Xm and Xp.

[0100] Figure 9 Tap signal control logic 240 and Figure 8 Each of the DFE reset circuit systems 206 is used to generate control signals to influence the operation of DFE 124 by changing Xm and Xp or by resetting DFE 124. It should be noted that the DFE reset circuit system 206 contains only asynchronous circuitry. That is, no timing circuitry is used in conjunction with the DFE reset circuit system 206 to generate the RstHi and RstHiF signals. In some embodiments, this may affect the reset operation of DFE 124. For example, environmental and / or manufacturing variations may affect the operation of DFE reset circuit system 206 (i.e., the operation of the asynchronous circuitry therein), particularly as the signal speed of memory device 10 increases (e.g., at or above 9 Gbps). For example, changes in process, voltage, and temperature (PVT) may affect the operation of DFE reset circuit system 206, causing transmission delays in the RstHi and RstHiF signals. These delays can, for example, extend the DFE reset operation to the time period during which memory device 10 is performing a memory operation (e.g., a memory write), thereby causing errors in the memory operation. Furthermore, the transmission delays of the RstHi and RstHiF signals are out of sync with other delays experienced in the memory device 10, which is at least partly attributable to the use of only asynchronous circuitry in the DFE reset circuit system 206.

[0101] Figure 10An embodiment of a DFE reset circuit system 252 operating using a synchronous circuit (e.g., a circuit whose output is triggered by a clock signal or another signal at a clock input) is described. As illustrated, the DFE reset circuit system 252 includes a D-type flip-flop 254 having an input 256 (e.g., an input pin) and an output 258 (e.g., an output pin). The input 256 receives an enable signal and transmits that enable signal as a TapHDFEreset signal from the output 258 based on the DFEresetPre0 signal received at the clock input 260 of the D-type flip-flop 254. In this way, the DFE reset circuit system 252 utilizes the same DFEresetPre0 as that used in conjunction with the DFE reset circuit system 206. That is, the DFE reset circuit system 252 can replace the external signal (e.g., generated externally from the DFE 124) that is transmitted to the DFE reset circuit system 206 as a control signal to initiate the reset of the DFE 124.

[0102] In some embodiments, a control or enable signal may also be generated and transmitted to the D-type flip-flop 254. For example, the NAND gate 262 may include an input 264 that receives an EnableDFE signal and an input 266 that receives a DFEsetF signal (which may be an inverted signal of the DFEset signal generated by the DFE reset circuit system 252). Based on the signals received at inputs 264 and 266, a signal generated from the NAND gate 262 is transmitted from the output 268 to the D-type flip-flop 254, for example as an enable or other control signal.

[0103] The DFE reset circuit system 252 further includes a D-type flip-flop 270 having an input 272 (e.g., an input pin) and an output 274 (e.g., an output pin). The input 272 receives an enable signal (e.g., the same enable signal received at the input 256 of the D-type flip-flop 254), and transmits that enable signal as a DFEset0 signal based on the DQSF0 (i.e., the phase-controlled DSQ signal) received at the clock input 276 of the D-type flip-flop 270 (e.g., the DFEset signal corresponds to the zero phase, whereby the phase changes from zero to 180 and then to 270 and back to zero during operation).

[0104] In some embodiments, a control or enable signal may also be generated and transmitted to the D-type flip-flop 270. For example, NAND gate 278 may include an input 280 that receives an EnableDFE signal and an input 282 that receives a TapHDFEreset signal from the output 258 of D-type flip-flop 254. A signal generated from NAND gate 278 based on the signals received at inputs 264 and 266 is transmitted from output 284 to D-type flip-flop 270, for example as an enable or other control signal. In this way, the output of D-type flip-flop 254, based on the DFEresetPre0 signal, controls the operation of D-type flip-flop 270, and thus controls the generated DFEset0 signal transmitted from output 274 of D-type flip-flop 270. In some embodiments, output 274 may be further coupled to input 286 (e.g., an input pin) of inverter 288. Inverter 288 also includes an output 290 that transmits the inverted signal generated as the DFEset0 signal.

[0105] Figure 11 Explanation can be combined Figure 10 The DFE reset circuit system 252 uses tap signal control logic 292. In some embodiments, a single tap signal control logic 292 may be implemented for an N-tap DFE. In other embodiments, a corresponding tap signal control logic 292 may be implemented for each tap of the N-tap DFE. As illustrated, the tap signal control logic 292 may include a multiplexer 294 having an input 296 (e.g., an input pin), an input 298, an output 300 (e.g., an output pin), and an output 302. The multiplexer 294 receives a TapNP0 signal (e.g., a zero-phase tap signal from a TapNP signal) at input 296 and a TapNM0 signal (e.g., a zero-phase tap signal from a TapNM signal) at input 298. In operation, the multiplexer 294 selectively transmits the signals received at inputs 296 and 298 from outputs 300 and 302 as the TapNP signal and the TapNM signal, respectively.

[0106] The operation of multiplexer 294 can be controlled via a signal received at control input 304. Control input 304 can be coupled to the output 274 of D-type flip-flop 270. In this way, multiplexer 294 is... Figure 9 The difference between the multiplexer 242 and the one is that... Figure 9Multiplexer 242 does not receive its control signal (i.e., selection signal) from DFE reset circuit system 206, while multiplexer 294 receives its control signal from DFE reset circuit system 252. When a reset operation is to occur, the value of DFEset0 changes, thereby switching the polarity of the TapNP signal transmitted from output 300 of multiplexer 294 and the polarity of the TapNM signal transmitted from output 302 by, for example, the transmission of the TapNP0 signal from input 296 to output 302 and the transmission of the TapNM0 signal from input 298 to output 302. By reversing the polarity of the TapNP and TapNM signals, a reset operation of DFE 124 can be performed.

[0107] Figure 12 Explain the summer 130 and the DFE (e.g., which can be combined with...). Figure 10 DFE reset circuit system 252 and Figure 11 An embodiment of the dual-tailed latch 132 (DFE 124) used in the tap signal control logic 292. Figure 12 The summer 130 and Figure 7 The summer is the same as 130; however, Figure 12 The summer 130 receives the TapNP signal from the tap signal control logic 292 at transistor 138 and TapNM signal transistor 140. Therefore, when a reset operation is performed, the polarity switching of the TapNP and TapNM signals causes a change in the Xm and Xp signals of the summer 130.

[0108] The Xm and Xp signals are transmitted to the corresponding dual-tailed latches, for example, dual-tailed latch 132 of DFE 124 when N=0. Therefore, although dual-tailed latch 132 is described for illustrative purposes, the following discussion applies to additional dual-tailed latches of DFE 124. In some embodiments, dual-tailed latch 132 (and dual-tailed latch 134 and any additional dual-tailed latches utilized in a multi-tap DFE) may comprise multiple stages, such as a first stage 144, a second stage 308, and a third stage 310. Although three stages are described, fewer or more stages may be used. Figure 12 The first stage 144 of the dual-tailed latch 132 in the middle Figure 7 The first level is the same as 144. However, with Figure 12 Level 144 from Figure 12 The summer 130 receives the Xm and Xp signals, and the first stage 144 changes the signal during a reset operation. Figure 12 The values ​​of the Xm and Xp signals received by the first stage 144.

[0109] Figure 12 Additionally, a circuit diagram of the second stage 308 of the dual-tailed latch 132 is shown. As illustrated, the second stage 308 is connected to... Figure 7The second stage 146 is the same, except that transistors 186 and 187 have been removed. In this way, Figure 12 The second level 308 and Figure 7 The second stage 146 differs in that it does not include a reset latch (i.e., transistors 186 and 187). Similarly, Figure 12 This section describes the circuit diagram of the third stage 310 of the dual-tailed latch 132. As explained, the third stage 310 is connected to... Figure 7 The third stage 148 is the same, except that transistors 200, 202, 204, and 205 have been removed. In this way, Figure 12 The third level 310 and Figure 7 The third stage 148 differs in that it does not include a reset latch (i.e., transistors 200, 202, 204, and 205). Therefore, Figure 12 This describes a dual-tailed latch 132 that can be used in the reset operation of the DFE 124 without using any reset latch that directly receives a reset signal (e.g., the RstHi signal and / or the RstHiF signal).

[0110] therefore, Figure 12 The dual-tailed latch 132 is more Figure 7 The dual-tailed latch 132 is simpler and smaller in size, while still allowing the DFE 124 to be reset. By controlling and modifying the Xm and Xp signals generated in the summer 130, the Yp, Ym, Zp, and Zm signals can be subsequently controlled in the second stage 308 and the third stage 310, respectively. Furthermore, since the DRE reset signal is generated in the DFE reset circuit system 252 using a synchronous circuit system, environmental factors (e.g., PVT) affecting the memory device 10, such as the generation of the DFEresetPre0 and DSQF0 signals, are considered when using the DFEset0 signal to implement the DFE 124 reset operation, based on the DFEresetPre0 and DSQF0 signals as timing signals. In this way, the chance of timing mismatch between the reset operation and memory operation is reduced, which in turn allows the reset operation to be performed at a faster data rate (i.e., the signal speed of the memory device 10, e.g., at or above 9 Gbps). Furthermore, removing the reset latches in the second stage 308 and the third stage 310 (i.e., transistors 186, 187, 200, 202, 204, and 205) can be attributed to removing the load associated with the reset latches, thus allowing for increased memory margin. Additionally, only swapping... Figure 7 DFE reset circuit system 206 and Figure 10 The DFE reset circuit system 252 allows Figure 12 The dual-tailed latch 132 is implemented with its associated operational gain.

[0111] While various modifications and alternatives may be made to this disclosure, specific embodiments have been shown by way of example in the accompanying drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims.

[0112] The references to the techniques presented and claimed herein, and their application to them, explicitly improve the technical field and are therefore not abstract, intangible, or purely theoretical, refer to practical material objects and concrete examples. Furthermore, if any claim appended to this specification contains one or more elements designated as “a component for [performing] [the function]…” or “a step for [performing] [the function]…”, then such elements are intended to be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, such elements are intended not to be interpreted in accordance with 35U.SC112(f).

Claims

1. An apparatus comprising: A decision feedback equalizer (DFE) reset circuit system, comprising a synchronization circuit system, wherein the DFE reset circuit system is configured to: Receive the DFE reset signal to initiate the DFE reset operation; A first control signal is generated based on the DFE reset signal; and The first control signal is transmitted to change the data signal generated in the summer circuit of the DFE to affect the reset operation of the DFE.

2. The apparatus of claim 1, wherein the DFE reset circuit system includes a first flip-flop, the first flip-flop including a first input configured to receive the DFE reset signal.

3. The apparatus of claim 2, wherein the first input includes the first clock input of the first trigger.

4. The apparatus of claim 3, wherein the first trigger includes a first output configured to transmit a second control signal based on the DFE reset signal.

5. The apparatus of claim 4, further comprising a second flip-flop, the second flip-flop including a second clock input configured to receive a timing signal generated based on at least one data strobe signal of a memory device including the DFE.

6. The apparatus of claim 5, wherein the second trigger includes an enable input configured to receive an activation signal to activate the second trigger.

7. The apparatus of claim 6, further comprising a logic element coupled to the first output and the enable input, wherein the logic element is configured to generate the activation signal at least in part based on the second control signal.

8. The apparatus of claim 5, wherein the second trigger includes a second output configured to transmit the first control signal.

9. An apparatus comprising: Tap signal control logic, which includes: The first output is configured to be coupled to the summer circuit of the decision feedback equalizer (DFE) in the memory device. A second output, configured to couple to the summer circuit of the DFE; and A control input, configured to be coupled to the DFE reset circuitry to receive a control signal to select, in conjunction with the DFE reset operation, a first signal to be transmitted from the first output and a second signal to be transmitted from the second output.

10. The apparatus of claim 9, wherein the first output is configured to be coupled to the first gate of the first transistor of the summer circuit.

11. The apparatus of claim 10, wherein the second output is configured to couple to the second gate of the second transistor of the summer circuit.

12. The apparatus of claim 11, wherein the first output is configured to transmit a TapNP signal as the first signal to the first gate, wherein the TapNP signal corresponds to a weighted tap value having one of a positive or negative value transmitted to the summer circuit.

13. The apparatus of claim 12, wherein the second output is configured to transmit a TapNM signal as the second signal to the second gate, wherein the TapNM signal corresponds to a weighted tap value having the other of the positive and negative values ​​transmitted to the summer circuit.

14. The apparatus of claim 13, wherein the tap signal control logic is configured to invert the polarity of each of the TapNP signal and the TapNM signal based on the control signal in conjunction with the reset operation of the DFE.

15. An apparatus comprising: The decision feedback equalizer (DFE) circuit includes: A summer circuit configured to receive a data signal from a series of data signals; and A dual-tailed latch circuit coupled to the summer circuit to receive a first output signal generated by the summer circuit, wherein the dual-tailed latch circuit includes a first stage, a second stage coupled to the first stage, and a third stage coupled to the second stage, wherein the dual-tailed latch is used in the reset operation of the DFE circuit when there is no reset latch in any of the first stage, the second stage, and the third stage, and when none of the first stage, the second stage, and the third stage of the dual-tailed latch directly receives a reset signal generated based on a control signal generated from outside the DFE to initiate the reset of the DFE.

16. The apparatus of claim 15, wherein the summer circuit is configured to generate the first output signal based on the data signal.

17. The apparatus of claim 16, wherein the summer circuit includes a first transistor including a first gate, wherein the summer circuit is configured to receive a TapNP signal at the first gate, wherein the TapNP signal corresponds to a weighted tap value having one of a positive or negative value transmitted to the summer circuit.

18. The apparatus of claim 17, wherein the summer circuit includes a second transistor, the second transistor including a second gate, wherein the second transistor is disposed in parallel with the first transistor, wherein the summer circuit is configured to receive a TapNM signal at the second gate, wherein the TapNM signal corresponds to a weighted tap value having the other of the positive and negative values ​​transmitted to the summer circuit.

19. The apparatus of claim 18, further comprising tap signal control logic coupled to the summer circuit, wherein the tap signal control logic is configured to invert the respective polarity of each of the TapNP signal and the TapNM signal based on a second control signal received at the tap signal control logic in conjunction with the reset of the DFE.

20. The apparatus of claim 19, further comprising a DFE reset circuit system coupled to the tap signal control logic, wherein the DFE reset circuit system is configured to receive the reset signal and generate the second control signal based on the reset signal.

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