Digital subarray remote control system and control method

Abstract

The invention discloses a digital sub-array remote control system and a control method, and aims to solve the problems of low remote debugging efficiency and the like of the current digital sub-array. The system comprises a computer, a network switch, an array surface network distributor and a digital subarray, the array surface network distribution comprises a plurality of micro-control units, and a flash memory and an Ethernet switching chip are mounted on each micro-control unit; a plurality of Ethernet physical layer chips are mounted on the Ethernet switch chip, and each Ethernet physical layer chip is correspondingly connected with one network transformer; the network transformer is used for connecting the digital sub-array or a network transformer or a network switch in other Ethernet switch chips; a micro-control unit, an internal Ethernet physical layer chip and an internal network transformer in the digital sub-array form an Ethernet path with an array surface network distributor, a network switch and a computer; an internal micro-control unit detects an IP address provided by array network allocation and carries out initialization configuration; and the computer controls the digital subarrays through an Ethernet access.

Description

Technical Field

[0001] This invention relates to the field of digital subarray remote control technology, and in particular to a digital subarray remote control system and control method. Background Technology

[0002] Digital subarrays, as a radar array configuration that combines antenna elements, transceiver components, frequency conversion modules, main control units, field programmable gate arrays (FPGAs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs), are numerous and usually integrated and installed on the exterior of ship decks, elevator towers, etc. This makes it difficult, time-consuming, and labor-intensive to debug, update, and manage the health of the main control unit FPGAs.

[0003] In existing technologies, the remote debugging and loading methods for radar digital subarrays typically utilize flash memory (FLASH) to store configuration data, complex programmable logic devices (CPLDs) to generate configuration timing, and multiplex the installation communication optical fiber to complete the remote loading of the digital subarray.

[0004] While existing remote commissioning and loading methods for radar digital subarrays have solved the problem of dynamic reconfiguration of devices in unreachable radar locations, they do not consider the inefficiencies and high time costs caused by the need for serial program updates for a large number of digital subarrays. Furthermore, due to the complexity and size of radar systems, and the fact that digital subarrays contain many critical components, built-in tests (BITs) in radar systems cannot fully, comprehensively, and intuitively display the health status and fault alarms of the components within the digital subarray. Summary of the Invention

[0005] This invention provides a remote control system and method for digital subarrays to solve the problems of low efficiency in remote debugging and loading of digital subarrays and incomplete health monitoring information in the prior art.

[0006] The digital subarray remote control system of this invention includes: a computer, a network switch, an array network allocation, and a digital subarray; the network switch is communicatively connected to the computer. The array network allocation includes multiple microcontrollers, each of which is connected to a flash memory and an Ethernet switching chip via a serial peripheral interface (SPI) bus; the flash memory is used to store the configuration information of the microcontroller; the microcontroller is used to configure the Ethernet switching chip according to the configuration information; Each of the Ethernet switching chips is equipped with multiple Ethernet physical layer chips, and each Ethernet physical layer chip is connected to a network transformer. At least one of the Ethernet switching chips is connected to the network switch via a network transformer attached to it, and the remaining Ethernet switching chips are all connected to a network transformer of one of the at least one Ethernet switching chips via a network transformer attached to them; that is, all the remaining network transformers that are not connected to the network switch and are not connected to the network transformer are connected to one of the digital subarrays. The digital subarray's internal microcontroller unit, internal Ethernet physical layer chip, internal network transformer, array network allocation, network switch, and computer form an Ethernet path; The internal microcontroller unit is used to detect the Internet Protocol IP address provided by the array network and to initialize and configure the internal Ethernet physical layer chip. The computer controls the digital subarray via the Ethernet path.

[0007] According to some embodiments of the present invention, the internal microcontroller unit is used for: After initialization and configuration are completed, the system periodically communicates with the main control unit (FPGA) inside the digital subarray via a Universal Asynchronous Receiver / Transmitter Protocol (PART) to obtain the real-time status of the functional modules inside the digital subarray from the FPGA.

[0008] According to some embodiments of the present invention, the internal microcontroller unit is used for: After obtaining a remote debugging request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted. The Xilinx Virtual Cable XVC Protocol Request message is obtained from the computer via the Ethernet channel, parsed into a Joint Working Test Group JTAG Timing Request signal, and then sent to the FPGA. The system receives the JTAG timing acknowledgment signal returned by the FPGA, converts it into an XVC protocol reply message, and returns it to the computer via the Ethernet path.

[0009] According to some embodiments of the present invention, the internal microcontroller unit is used for: After obtaining Ethernet data packets from the computer to poll for the online status of the digital subarray via the Ethernet channel, the periodic communication with the FPGA is interrupted, and the online status of the digital subarray is reported to the computer via the Ethernet channel. The system obtains single-board query or polling query commands from the computer through the Ethernet channel, and reports the working status information of the digital subarray to the computer through the Ethernet channel.

[0010] According to some embodiments of the present invention, the internal microcontroller unit is used for: After receiving the programming request message broadcast by the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted, and an erase command is sent to the internal flash memory of the digital subarray. Once the internal flash memory has completed the erase operation, an erase completion flag is sent back to the computer via the Ethernet path. The programming data stream is obtained from the computer via the Ethernet channel, parsed, and then written into the internal flash memory. The write completion flag is sent back to the computer via the Ethernet channel.

[0011] According to some embodiments of the present invention, the computer is used for: If no erase completion flag or write completion flag is received from an internal microcontroller unit within a preset time period, the program will repeatedly send a program request message or program data stream to that internal microcontroller unit.

[0012] In the digital subarray remote control method of this invention, the digital subarray remote control method is based on a digital subarray remote control system; the digital subarray remote control system includes: a computer, a network switch, an array network allocation, and a digital subarray; the network switch is communicatively connected to the computer; The array network allocation includes multiple microcontrollers, each of which is connected to a flash memory and an Ethernet switching chip via a serial peripheral interface (SPI) bus; each Ethernet switching chip is connected to multiple Ethernet physical layer chips, and each Ethernet physical layer chip is connected to a network transformer. At least one of the Ethernet switching chips is connected to the network switch via a network transformer attached to it, and the remaining Ethernet switching chips are all connected to a network transformer of one of the at least one Ethernet switching chips via a network transformer attached to them; that is, all the remaining network transformers that are not connected to the network switch and are not connected to the network transformer are connected to one of the digital subarrays. The digital subarray's internal microcontroller unit, internal Ethernet physical layer chip, internal network transformer, array network allocation, network switch, and computer form an Ethernet path; The method includes: The microcontroller obtains configuration information from the flash memory to configure the Ethernet switching chip; The internal microcontroller unit detects the Internet Protocol (IP) address provided by the array network and initializes the internal Ethernet physical layer chip. The internal microcontroller unit communicates periodically with the main control unit (FPGA) inside the digital subarray via a universal asynchronous transceiver protocol to obtain the real-time status of the functional modules inside the digital subarray from the FPGA. The internal microcontroller receives control information from the computer via the Ethernet channel, interrupts periodic communication with the FPGA, and completes corresponding actions.

[0013] According to some embodiments of the present invention, the internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After obtaining a remote debugging request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted. The Xilinx Virtual Cable XVC Protocol Request message is obtained from the computer via the Ethernet channel, parsed into a Joint Working Test Group JTAG Timing Request signal, and then sent to the FPGA. The system receives the JTAG timing acknowledgment signal returned by the FPGA, converts it into an XVC protocol reply message, and returns it to the computer via the Ethernet path.

[0014] According to some embodiments of the present invention, the internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After obtaining Ethernet data packets from the computer to poll for the online status of the digital subarray via the Ethernet channel, the periodic communication with the FPGA is interrupted, and the online status of the digital subarray is reported to the computer via the Ethernet channel. The system obtains single-board query or polling query commands from the computer through the Ethernet channel, and reports the working status information of the digital subarray to the computer through the Ethernet channel.

[0015] According to some embodiments of the present invention, the internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After receiving the programming request message broadcast by the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted, and an erase command is sent to the internal flash memory. Once the internal flash memory has completed the erase operation, an erase completion flag is sent back to the computer via the Ethernet path. The programming data stream is obtained from the computer via the Ethernet channel, parsed, and then written into the internal flash memory. The write completion flag is sent back to the computer via the Ethernet channel.

[0016] This invention designs a method that uses a three-level cascade of internal Ethernet physical layer chips, array network allocation, and network switches within a digital subarray, combined with the IP address lines provided by the array network allocation, to construct Ethernet data hardware paths from multiple digital subarrays to a computer at the physical layer. This enables remote control of digital subarrays in inaccessible locations, such as debugging, broadcast loading, status display, and fault alarms, even when the phased array radar antenna array is mounted at a high elevation. This solves the problems of low efficiency and excessive manpower and time costs in debugging, updating, and maintaining software, and monitoring, managing, and troubleshooting hardware for digital subarrays.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of the embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of the digital subarray remote control system in an embodiment of the present invention; Figure 2 This is a schematic diagram of the composition of the digital subarray in an embodiment of the present invention; Figure 3 This is a flowchart of the remote control method for digital subarrays in an embodiment of the present invention; Figure 4 This is a flowchart of the remote debugging process for the digital subarray in an embodiment of the present invention; Figure 5 This is a flowchart of the digital subarray health monitoring process in an embodiment of the present invention; Figure 6 This is a flowchart of the digital subarray broadcast loading process in an embodiment of the present invention. Detailed Implementation

[0019] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art. Furthermore, in some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0020] The digital subarray remote control system of this invention includes: a computer, a network switch, an array network allocation, and a digital subarray; the network switch is communicatively connected to the computer. The array network allocation includes multiple microcontroller units (MCUs). Each MCU is connected to a flash memory and an Ethernet switching chip via a Serial Peripheral Interface (SPI) bus. The flash memory is used to store the configuration information of the MCU. The MCU is used to configure the Ethernet switching chip according to the configuration information. This configuration information can be flexibly configured. Each of the Ethernet switching chips is equipped with multiple Ethernet physical layer chips, and each Ethernet physical layer chip is connected to a network transformer. At least one of the Ethernet switching chips is connected to the network switch via a network transformer attached to it, and the remaining Ethernet switching chips are all connected to a network transformer of one of the at least one Ethernet switching chips via a network transformer; that is, all the remaining network transformers that are not connected to the network switch and not connected to the network transformer are connected to a digital subarray. It should be clarified that "at least one Ethernet switching chip" here can refer to one, two, or more Ethernet switching chips, with the number of chips in "at least one Ethernet switching chip" being less than the number of chips in "multiple Ethernet switching chips." "The remaining Ethernet switching chips" can be understood as the remaining Ethernet switching chips among the "multiple Ethernet switching chips" excluding the "at least one Ethernet switching chip" which is directly connected to the network switch via a network transformer. Each of the "remaining Ethernet switching chips" selects one Ethernet switching chip from the "at least one Ethernet switching chip" for connection, and the connection is achieved through an attached network transformer. For example, if the number of multiple Ethernet switching chips is N, where n Ethernet switching chips are directly connected to the network switch via an attached network transformer, and the remaining Nn Ethernet switching chips are connected to any one of the n Ethernet switching chips via a network transformer. In summary, the network transformer is used to connect the network transformer or network switch to the digital subarray or other Ethernet switching chips.

[0021] This enables Ethernet communication between the computer and each digital subarray; the computer's instruction information can be transmitted through its connected Ethernet switching chip to other connected Ethernet switching chips, and then further transmitted to the digital subarray.

[0022] The digital subarray's internal microcontroller unit, internal Ethernet physical layer chip, internal network transformer, array network allocation, network switch, and computer form an Ethernet path; The internal microcontroller unit is used to detect the Internet Protocol (IP) address provided by the array network and to initialize and configure the internal Ethernet physical layer chip. The computer controls the digital subarray via the Ethernet channel, including functions such as debugging, broadcast loading, status display, and fault alarms.

[0023] This invention designs a method that uses a three-level cascade of internal Ethernet physical layer chips, array network allocation, and network switches in a digital subarray, combined with the IP address lines provided by the array network allocation, to construct an Ethernet data hardware path from multiple digital subarrays to a computer at the physical layer. This enables remote control of digital subarrays in inaccessible locations, such as when the phased array radar antenna array is mounted at a high elevation. It solves the problems of low efficiency and excessive manpower and time costs in debugging, updating, and maintaining software, and monitoring, managing, and troubleshooting hardware for digital subarrays.

[0024] Based on the above embodiments, further variant embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in each variant embodiment.

[0025] According to some embodiments of the present invention, the internal microcontroller unit is used for: After initialization and configuration are completed, periodic communication is established with the FPGA inside the digital subarray via the Universal Asynchronous Receiver / Transmitter Protocol to obtain the real-time status of the functional modules inside the digital subarray from the FPGA.

[0026] According to some embodiments of the present invention, the internal microcontroller unit is used for: After obtaining a remote debugging request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted. The Xilinx Virtual Cable (XVC) protocol request message is obtained from the computer via the Ethernet channel, parsed into a Joint Test Action Group (JTAG) timing request signal, and then sent to the FPGA. The system receives the JTAG timing acknowledgment signal returned by the FPGA, converts it into an XVC protocol reply message, and returns it to the computer via the Ethernet path.

[0027] According to some embodiments of the present invention, the internal microcontroller unit is used for: After obtaining Ethernet data packets from the computer to poll for the online status of the digital subarray via the Ethernet channel, the periodic communication with the FPGA is interrupted, and the online status of the digital subarray is reported to the computer via the Ethernet channel. The system obtains single-board query or polling query commands from the computer through the Ethernet channel, and repeatedly or sequentially reports the working status information of the digital subarray to the computer through the Ethernet channel.

[0028] According to some embodiments of the present invention, the internal microcontroller unit is used for: After receiving the broadcast programming request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted, and an erase command is sent to the internal flash memory of the digital subarray. It should be noted that the computer sends the programming request message via broadcast, so all digital subarrays can achieve near-parallel erasure and programming commands. The internal flash memory is connected to the internal microcontroller unit.

[0029] Once the internal flash memory has completed the erase operation, an erase completion flag is sent back to the computer via the Ethernet path. The programming data stream is obtained from the computer via the Ethernet channel, parsed, and then written into the internal flash memory. The write completion flag is sent back to the computer via the Ethernet channel.

[0030] According to some embodiments of the present invention, the computer is used for: If no erase completion flag or write completion flag is received from an internal microcontroller unit within a preset time period, the program will repeatedly send a program request message or program data stream to that internal microcontroller unit.

[0031] Furthermore, the retransmission mechanism has a limited number of attempts. When the preset threshold is exceeded, retransmission will cease, the computer will print out the IP address of the corresponding failed subarray, and proceed to the next state.

[0032] In the digital subarray remote control method of this invention, the digital subarray remote control method is based on a digital subarray remote control system; the digital subarray remote control system includes: a computer, a network switch, an array network allocation, and a digital subarray; the network switch is communicatively connected to the computer; The array network allocation includes multiple microcontrollers, each of which is connected to a flash memory and an Ethernet switching chip via an SPI bus; each Ethernet switching chip is equipped with multiple Ethernet physical layer chips, and each Ethernet physical layer chip is connected to a network transformer. At least one of the Ethernet switching chips is connected to the network switch via a network transformer attached to it, and the remaining Ethernet switching chips are all connected to a network transformer of one of the at least one Ethernet switching chips via a network transformer; that is, all the remaining network transformers that are not connected to the network switch and not connected to the network transformer are connected to a digital subarray. The internal microcontroller unit, internal Ethernet physical layer chip, internal network transformer of the digital subarray, the array network allocation, the network switch and the computer form an Ethernet path; The method includes: The microcontroller obtains configuration information from the flash memory to configure the Ethernet switching chip; The internal microcontroller unit detects the IP address provided by the array network and initializes the configuration of the internal Ethernet physical layer chip; The internal microcontroller unit communicates periodically with the FPGA inside the digital subarray via a universal asynchronous transceiver protocol to obtain the real-time status of the functional modules inside the digital subarray from the FPGA. The internal microcontroller receives control information from the computer via the Ethernet channel, interrupts periodic communication with the FPGA, and completes corresponding actions.

[0033] This invention designs a method that uses a three-level cascade of internal Ethernet physical layer chips, array network allocation, and network switches within a digital subarray, combined with the IP address lines provided by the array network allocation, to construct Ethernet data hardware paths from multiple digital subarrays to a computer at the physical layer. This enables remote control of digital subarrays in inaccessible locations, such as debugging, broadcast loading, status display, and fault alarms, even when the phased array radar antenna array is mounted at a high elevation. This solves the problems of low efficiency and excessive manpower and time costs in debugging, updating, and maintaining software, and monitoring, managing, and troubleshooting hardware for digital subarrays.

[0034] Based on the above embodiments, further variant embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in each variant embodiment.

[0035] According to some embodiments of the present invention, the internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After obtaining a remote debugging request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted. After obtaining the XVC protocol request message from the computer via the Ethernet channel and parsing it into a JTAG timing request signal, the message is sent to the FPGA. The system receives the JTAG timing acknowledgment signal returned by the FPGA, converts it into an XVC protocol reply message, and returns it to the computer via the Ethernet path.

[0036] According to some embodiments of the present invention, the internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After obtaining Ethernet data packets from the computer to poll for the online status of the digital subarray via the Ethernet channel, the periodic communication with the FPGA is interrupted, and the online status of the digital subarray is reported to the computer via the Ethernet channel. The system obtains single-board query or polling query commands from the computer through the Ethernet channel, and repeatedly or sequentially reports the working status information of the digital subarray to the computer through the Ethernet channel.

[0037] According to some embodiments of the present invention, the internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After receiving the broadcast programming request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted, and an erase command is sent to the internal flash memory. Once the internal flash memory has completed the erase operation, an erase completion flag is sent back to the computer via the Ethernet path. The programming data stream is obtained from the computer through the Ethernet channel, parsed, and then written into the internal Ethernet physical layer chip. The write completion flag is sent back to the computer via the Ethernet channel.

[0038] The digital subarray remote control method according to the present invention will now be described in detail with reference to the accompanying drawings and a specific embodiment. It is to be understood that the following description is merely exemplary and should not be construed as a specific limitation of the invention.

[0039] This invention aims to more efficiently and conveniently complete the software debugging, updating, and maintenance of digital subarrays, as well as the monitoring, management, and troubleshooting of hardware status, reducing manpower and time costs. It constructs an Ethernet path from multiple digital subarrays to the computer through a three-level cascade of the Ethernet physical layer chip, array network allocation, and network switches within the digital subarray, along with multiple IP address lines provided by the array allocation. Inside the digital subarray, the MCU bridges the Ethernet physical layer chip and the FPGA's JTAG port, enabling remote debugging of the digital subarray via the XVC protocol. Furthermore, the MCU bridges the Ethernet physical layer chip and the internal FLASH of the digital subarray. When the host computer sends a broadcast programming command, the programming data stream is distributed via Ethernet to the MCUs of each digital subarray, and the MCUs then use the SPI bus to program the external FLASH of the FPGA inside the digital subarray. Meanwhile, each component within the digital subarray has a communication interface with the FPGA. Status information from transceiver modules, frequency converters, power supplies, and ADCs / DACs can be aggregated by the FPGA and sent to the MCU. The MCU then transmits this information via Ethernet to a computer interface for display, enabling health monitoring and fault alarms for the digital subarray's hardware status. This design method is reasonable and practical, and has been successfully applied in real-world engineering projects.

[0040] The digital subarray remote control method of this invention is based on the digital subarray remote control system.

[0041] Reference Figure 1 As shown, the digital subarray remote control system includes multiple digital subarrays, array network allocation, network switches, and computers.

[0042] The main components of the array network allocation include four microcontrollers (MCUs), four flash memories (FLASH), four Ethernet switching chips, 52 Ethernet physical layer chips, and 52 network transformers. The default configuration information for each Ethernet switching chip is stored in the FLASH memory, and the MCU configures the switching chip via the SPI bus. Ethernet switching chip-1 and Ethernet switching chip-3 each connect 17 Ethernet physical layer chips and 17 network transformers to achieve 17-port Ethernet switching. Ethernet switching chip-2 and Ethernet switching chip-4 each connect 9 Ethernet physical layer chips and 9 network transformers to achieve 9-port Ethernet switching. Specifically, port 1 of Ethernet switching chip-1 and Ethernet switching chip-3 connects to a network switch, ports 2-16 each connect to 15 digital subarrays, port 17 is cascaded with port 1 of Ethernet switching chip-2 and Ethernet switching chip-4, and ports 2-9 of Ethernet switching chip-2 and Ethernet switching chip-4 each connect to 8 digital subarrays. At the same time, the array network allocation provides multiple different IP address lines to the digital subarrays, allowing multiple digital subarrays to be configured with different IP addresses.

[0043] The internal hardware architecture of the digital subarray is as follows Figure 2 As shown, the array includes multiple antenna units, transceiver components, frequency conversion modules, power supplies, a main control unit FPGA, an MCU, an ADC, a DAC, a FLASH chip, an Ethernet physical layer chip, and a network transformer. The MCU, Ethernet physical layer chip, and network transformer are used to construct a 100Mbps Ethernet path to the array network. The JTAG port connection between the MCU and the FPGA establishes a remote debugging path for the main control unit FPGA. The MCU, FPGA, and FLASH are connected via a multi-master, one-slave connection to establish a remote loading path for the main control unit FPGA. The main control unit FPGA connects to the transceiver components, frequency conversion modules, power supplies, ADCs, and DACs to collect status information from each component and send it to the MCU for uploading, thus constructing a health monitoring path for the digital subarray's status information.

[0044] It should be noted that since the array network allocation also uses MCU, FLASH, Ethernet physical layer chip and network transformer, the word "internal" can be added before the relevant devices inside the digital subarray for differentiation.

[0045] This invention presents a method that constructs an Ethernet data hardware path from multiple digital subarrays to a computer at the physical layer by using a three-level cascade of Ethernet physical layer chips, array network allocation, and network switches, combined with the IP address lines provided by the array network allocation.

[0046] The remote control method for digital subarrays in this invention includes remote debugging, health monitoring, and broadcast recording.

[0047] like Figure 3 As shown, after power-on initialization, the MCU in the array network allocation first reads the program stored in the FLASH memory, and then configures the Ethernet switching chip via the SPI bus. Simultaneously, the internal MCU in the digital subarray detects the IP address line provided by the array network allocation and uses it as the subarray's IP address to initialize and configure the internal Ethernet physical layer chip. Once the network status configuration is complete, the internal MCU in the digital subarray enters a communication loop with the FPGA. Every 2 seconds, the internal MCU initiates a data request to the FPGA, and upon receiving the request, the FPGA immediately sends back the status information of each component within the digital subarray.

[0048] At this point, if the host computer interface initiates a request message, the message will be transmitted to the network switch via the network cable. The network switch will then transmit it to the array network distribution unit, and finally distribute it to multiple digital subarrays through devices such as the Ethernet switching chip, Ethernet physical layer chip, and network transformer in the array network distribution unit. Inside the digital subarray, the message also passes through the internal network transformer and internal Ethernet physical layer chip to reach the internal MCU. The internal MCU determines the type of request message. If a remote debugging request is received, the internal MCU enters the remote debugging process; if a health monitoring request is received, the internal MCU enters the health monitoring process; if a broadcast loading request is received, the internal MCU enters the broadcast loading data stream process.

[0049] This invention utilizes a computer-based host computer interface to initiate operation commands and display status, employs an MCU to forward, convert, and transmit Ethernet data, and utilizes an FPGA to collect and transmit status information of various components in the digital subarray. This enables remote debugging, broadcast loading, status display, and fault alarms for digital subarrays in inaccessible locations such as when the phased array radar antenna array is mounted at a high elevation. It solves the problems of low efficiency and excessive manpower and time costs in debugging, updating, and maintaining software, and monitoring, managing, and troubleshooting hardware for digital subarrays.

[0050] Specifically, the remote debugging process for digital subarrays is as follows: Figure 4 As shown, after the digital subarray, array network allocation, and network switch complete the power-on initialization configuration, the internal MCU and FPGA in each digital subarray communicate every 2 seconds via the Universal Asynchronous Receiver / Transmitter (UART) protocol. The main purpose of this communication is to provide the internal MCU with the real-time status information of the transceiver components, power supply, frequency converter module, ADC, DAC, and the FPGA itself collected by the FPGA.

[0051] If, at this moment, the MCU inside a digital subarray receives a remote debugging request message transmitted from the host computer interface through a link consisting of a network switch, an Ethernet switching chip in the array network allocation, an Ethernet physical layer chip, a network transformer, an internal network transformer in the digital subarray, and an internal Ethernet physical layer chip, then the MCU inside the digital subarray will exit the UART communication process with the FPGA and begin receiving XVC protocol Ethernet messages sent by the host computer. It will then parse the XVC protocol and generate corresponding JTAG timing signals such as Test Data Input (TDI), Test Clock (TCK), and Test Mode Select (TMS), which will be transmitted to the FPGA through general-purpose input / output (GPIO) ports. The FPGA itself provides the function of parsing TDI, TCK, TMS and returning test data output (TDO) and other JTAG timing signals. When the internal MCU receives the JTAG timing signals returned by the FPGA, it converts them into XVC protocol and returns them to the computer through the link of the internal Ethernet physical layer chip in the digital subarray, the internal network transformer, the network transformer in the array network distribution, the Ethernet physical layer chip, the Ethernet switching chip, and the network switch, thereby realizing remote debugging of the digital subarray FPGA.

[0052] Digital subarray health monitoring process as follows Figure 5As shown, the host computer on the computer side sequentially sends Ethernet data packets to the digital subarrays within the range of the starting IP to the ending IP via a link consisting of a network switch, an Ethernet switching chip in the array network allocation, an Ethernet physical layer chip, a network transformer, an internal network transformer in the digital subarray, and an internal Ethernet physical layer chip, polling for the online status of the digital subarrays. When the internal MCU in the i-th digital subarray receives the Ethernet data packet, it exits the communication process with the FPGA and begins communicating with the host computer on the computer side via the link consisting of the internal Ethernet physical layer chip in the digital subarray, the internal network transformer, the network transformer in the array network allocation, the Ethernet physical layer chip, the Ethernet switching chip, and the network switch, replying to the current online status of the digital subarray. At this time, the internal MCU has also obtained and stored the current status information of each component of the digital subarray provided by the FPGA. After the polling for the online status is completed, the host computer sends a single-board query or polling query command. During single-board query, the computer sends request commands to a fixed IP address in a loop. The internal MCU of the digital subarray of that IP address replies with the status information of the digital subarray in a loop. After receiving the status information, the computer judges and displays it. During polling query, the computer first sends a request command to the j-th online IP address. When it receives the status information returned by the j-th digital subarray, it judges and displays it, and then sends a request command to the next online IP address, and so on in a loop.

[0053] Digital subarray broadcast loading process as follows Figure 6 As shown, after the Ethernet path configuration is completed and the host computer has queried the online status of all digital subarrays, the host computer interface still sends programming requests to the MCUs in all digital subarrays sequentially through the link of network switch, Ethernet switching chip in array network allocation, Ethernet physical layer chip, network transformer, internal network transformer in digital subarray, and internal Ethernet physical layer chip. Then it enters the waiting for feedback state. At the same time, after receiving the programming request, the internal MCU of the digital subarray sends an erase command to the internal FLASH in the digital subarray. After the internal FLASH is erased, the internal MCU sends back the erase completion flag to the host computer through the link of internal Ethernet physical layer chip in digital subarray, internal network transformer, network transformer in array network allocation, Ethernet physical layer chip, Ethernet switching chip, and network switch.

[0054] If the host computer does not receive the erase FLASH completion information from the internal MCUs of all digital subarrays within a certain time, it triggers the failure retransmission mechanism, retransmits the writing request to the problematic digital subarray, and then enters the waiting state. The failure retransmission mechanism can be triggered a maximum of two times. If it still fails after two retransmissions, the computer prints out the IP address of the corresponding failed digital subarray and enters the next state.

[0055] Once the computer receives notifications that all internal MCUs of the digital subarrays have completed erasing the FLASH, it enters the next state, whereby the computer sequentially sends the first 2KB programming data stream to all digital subarrays. Simultaneously, the internal MCU of the digital subarray that received the programming data Ethernet message parses the message and writes it into the FLASH via the SPI bus. After writing, it sends a completion message back to the computer. If the computer does not receive a completion flag from all digital subarrays within a certain time, it triggers a retransmission mechanism, retransmitting the first programming data Ethernet message to the problematic digital subarray, and then enters the waiting state. Similarly, the retransmission mechanism is only triggered twice. If the computer receives a completion flag from all digital subarrays, it sends the second 2KB programming data, and so on, until all programming data is written to the FLASH.

[0056] Although the host computer communicates serially with each digital subarray via Ethernet, its data rate is 100Mbps. Meanwhile, the internal MCU of each digital subarray uses an SPI bus at a rate of 10Mbps to operate the FLASH memory. Therefore, this method can be considered as parallel remote loading of multiple digital subarrays. Furthermore, the added failure retransmission mechanism ensures stable operation even in the complex network environment of the radar system, demonstrating strong robustness. In practical engineering applications, when the file to be burned is 27.4MB, remote loading of 48 digital subarrays takes only about 15 minutes.

[0057] This invention constructs a hardware path for Ethernet data from multiple digital subarrays to a computer through a three-tiered cascade of Ethernet physical layer chips, array network allocation, and network switches. Operation commands and status displays are initiated via a host computer interface. An MCU handles the forwarding, conversion, and transmission of Ethernet data, while an FPGA collects and transmits status information from each component within the digital subarray. This enables remote debugging, broadcast loading, and health management of the digital subarrays. Furthermore, a retransmission mechanism is incorporated into the parallel broadcast loading process to ensure stability during program loading across multiple digital subarrays in complex network environments.

[0058] Compared with traditional phased array radar digital subarray design methods, this invention solves the problem of difficult software debugging of digital subarrays under the condition of high-altitude phased array radar antenna array by implementing remote debugging function; the implemented broadcast loading and failure retransmission mechanism improves loading efficiency from several hours to about 15 minutes, and has high stability; the implemented health management function can monitor and manage hardware status in real time, which greatly facilitates radar system hardware management and fault diagnosis, and saves manpower and time costs.

[0059] The method of this invention has the following advantages: 1. Health management of digital subarrays in phased array radar facilitates hardware maintenance, fault location, and troubleshooting of the radar system. 2. Broadcast loading of digital subarrays in phased array radar reduces the manpower and time costs of software debugging, updating, and maintenance of the radar system. 3. The retransmission mechanism for broadcast loading failure improves the robustness of the system in complex network environments.

[0060] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0061] It should be noted that the contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A remote control system for a digital subarray, characterized in that, include: Computers, network switches, array network distribution, digital subarrays; The network switch is communicatively connected to the computer; The array network allocation includes multiple microcontrollers, each of which is connected to a flash memory and an Ethernet switching chip via a serial peripheral interface (SPI) bus; the flash memory is used to store the configuration information of the microcontroller; the microcontroller is used to configure the Ethernet switching chip according to the configuration information; Each of the Ethernet switching chips is equipped with multiple Ethernet physical layer chips, and each Ethernet physical layer chip is connected to a network transformer. At least one of the Ethernet switching chips is connected to the network switch via a network transformer attached to it, and the remaining Ethernet switching chips are all connected to a network transformer of one of the at least one Ethernet switching chips via a network transformer attached to them; that is, all the remaining network transformers that are not connected to the network switch and are not connected to the network transformer are connected to one of the digital subarrays. The internal microcontroller unit, internal Ethernet physical layer chip, and internal network transformer of the digital subarray form an Ethernet path with the array network allocation, the network switch, and the computer. The internal microcontroller unit is used to detect the Internet Protocol IP address provided by the array network and to initialize and configure the internal Ethernet physical layer chip. The computer controls the digital subarray via the Ethernet path.

2. The system as described in claim 1, characterized in that, The internal microcontroller unit is used for: After initialization and configuration are completed, the system periodically communicates with the main control unit (FPGA) inside the digital subarray via a Universal Asynchronous Receiver / Transmitter Protocol (PART) to obtain the real-time status of the functional modules inside the digital subarray from the FPGA.

3. The system as described in claim 2, characterized in that, The internal microcontroller unit is used for: After obtaining a remote debugging request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted. The Xilinx Virtual Cable XVC Protocol Request message is obtained from the computer via the Ethernet channel, parsed into a Joint Working Test Group JTAG Timing Request signal, and then sent to the FPGA. The system receives the JTAG timing acknowledgment signal returned by the FPGA, converts it into an XVC protocol reply message, and returns it to the computer via the Ethernet path.

4. The system as described in claim 2, characterized in that, The internal microcontroller unit is used for: After obtaining Ethernet data packets from the computer to poll for the online status of the digital subarray via the Ethernet channel, the periodic communication with the FPGA is interrupted, and the online status of the digital subarray is reported to the computer via the Ethernet channel. The system obtains single-board query or polling query commands from the computer through the Ethernet channel, and reports the working status information of the digital subarray to the computer through the Ethernet channel.

5. The system as described in claim 2, characterized in that, The internal microcontroller unit is used for: After receiving the programming request message broadcast by the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted, and an erase command is sent to the internal flash memory of the digital subarray. Once the internal flash memory has completed the erase operation, an erase completion flag is sent back to the computer via the Ethernet path. The programming data stream is obtained from the computer via the Ethernet channel, parsed, and then written into the internal flash memory. The write completion flag is sent back to the computer via the Ethernet channel.

6. The system as described in claim 5, characterized in that, The computer is used for: If no erase completion flag or write completion flag is received from an internal microcontroller unit within a preset time period, the program will repeatedly send a program request message or program data stream to that internal microcontroller unit.

7. A method for remote control of a digital subarray, characterized in that, The digital subarray remote control method is implemented based on the digital subarray remote control system. The remote control system for the digital subarray includes: a computer, a network switch, an array network distribution system, and a digital subarray; the network switch is communicatively connected to the computer. The array network allocation includes multiple microcontrollers, each of which is connected to a flash memory and an Ethernet switching chip via a serial peripheral interface (SPI) bus; each Ethernet switching chip is connected to multiple Ethernet physical layer chips, and each Ethernet physical layer chip is connected to a network transformer. At least one of the Ethernet switching chips is connected to the network switch via a network transformer attached to it, and the remaining Ethernet switching chips are all connected to a network transformer of one of the at least one Ethernet switching chips via a network transformer attached to them; that is, all the remaining network transformers that are not connected to the network switch and are not connected to the network transformer are connected to one of the digital subarrays. The internal microcontroller unit, internal Ethernet physical layer chip, and internal network transformer of the digital subarray form an Ethernet path with the array network allocation, the network switch, and the computer. The method includes: The microcontroller obtains configuration information from the flash memory to configure the Ethernet switching chip; The internal microcontroller unit detects the Internet Protocol (IP) address provided by the array network and initializes the internal Ethernet physical layer chip. The internal microcontroller unit communicates periodically with the main control unit (FPGA) inside the digital subarray via a universal asynchronous transceiver protocol to obtain the real-time status of the functional modules inside the digital subarray from the FPGA. The internal microcontroller receives control information from the computer via the Ethernet channel, interrupts periodic communication with the FPGA, and completes corresponding actions.

8. The method as described in claim 7, characterized in that, The internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After obtaining a remote debugging request message from the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted. The Xilinx Virtual Cable XVC Protocol Request message is obtained from the computer via the Ethernet channel, parsed into a Joint Working Test Group JTAG Timing Request signal, and then sent to the FPGA. The system receives the JTAG timing acknowledgment signal returned by the FPGA, converts it into an XVC protocol reply message, and returns it to the computer via the Ethernet path.

9. The method as described in claim 7, characterized in that, The internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After obtaining Ethernet data packets from the computer to poll for the online status of the digital subarray via the Ethernet channel, the periodic communication with the FPGA is interrupted, and the online status of the digital subarray is reported to the computer via the Ethernet channel. The system obtains single-board query or polling query commands from the computer through the Ethernet channel, and reports the working status information of the digital subarray to the computer through the Ethernet channel.

10. The method as described in claim 7, characterized in that, The internal microcontroller receives control information from the computer via the Ethernet path, interrupts periodic communication with the FPGA, and completes corresponding actions, including: After receiving the programming request message broadcast by the computer via the Ethernet channel, the periodic communication with the FPGA is interrupted, and an erase command is sent to the internal flash memory of the digital subarray. Once the internal flash memory has completed the erase operation, an erase completion flag is sent back to the computer via the Ethernet path. The programming data stream is obtained from the computer via the Ethernet channel, parsed, and then written into the internal flash memory. The write completion flag is sent back to the computer via the Ethernet channel.

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